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* mistral: Fix MLAB clusteringgatecat2021-10-112-2/+9
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatgatecat2021-10-112-29/+42
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #843 from Ravenslofty/lofty/mistral-basic-timinggatecat2021-10-113-21/+256
|\ | | | | mistral: very basic timing info
| * mistral: very basic timing infoLofty2021-10-104-22/+257
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* | Merge pull request #844 from pepijndevos/patch-2gatecat2021-10-101-2/+2
|\ \ | | | | | | Gowin: more clearly mark dummy pips
| * | Gowin: more clearly mark dummy pipsPepijn de Vos2021-10-101-2/+2
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* | Merge pull request #842 from yrabbit/delaysgatecat2021-10-093-12/+40
|\ \ | | | | | | gowin: Replace the zero delays with reasonable values.
| * \ Merge branch 'master' into delaysYRabbit2021-10-091-18/+6
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| * | | gowin: Replace the zero delays with reasonable values.YRabbit2021-10-093-12/+40
| | |/ | |/| | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | | router2: Disable criticality sorting towards end of routinggatecat2021-10-091-1/+1
| |/ |/| | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #841 from Ravenslofty/lofty/mistral-cleanupgatecat2021-10-081-18/+6
|\ \ | |/ |/| mistral: clean up bel init slightly
| * mistral: clean up bel init slightlyLofty2021-10-081-18/+6
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* hashlib: Support for std::array keysgatecat2021-10-071-0/+13
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #839 from yrabbit/wide-lutsgatecat2021-10-077-9/+434
|\ | | | | gowin: add support for wide LUTs.
| * gowin: add support for wide LUTs.YRabbit2021-10-077-9/+434
|/ | | | | | | | | * A hardwired MUX within each logical cell is used. * The delay is equal 0. * No user placement constraints. * The output route contains dummy PIPs. They are ignored by gowin_pack, but it may be worth removing them. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #837 from YosysHQ/gatecat/mistral-mlab-2gatecat2021-10-058-21/+235
|\ | | | | mistral: Adding support for MLABs as memory
| * mistral: Adding support for MLABs as memorygatecat2021-10-058-21/+235
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #836 from YosysHQ/gatecat/mistral-mlabgatecat2021-10-032-19/+38
|\| | | | | mistral: Add bel pins for MLAB write port
| * mistral: Add bel pins for MLAB write portgatecat2021-10-032-19/+38
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #834 from YosysHQ/gatecat/cygwingatecat2021-10-011-1/+1
|\ | | | | Fix Cygwin build
| * Fix Cygwin buildgatecat2021-10-011-1/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #833 from antmicro/interchange-fix-uninitialized-memory-buggatecat2021-10-011-1/+1
|\ \ | |/ |/| interchange: fix uninitialized memory bug in cluster placement
| * interchange: fix uninitialized memory bug in cluster placementAlessandro Comodi2021-10-011-1/+1
|/ | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Merge pull request #828 from YosysHQ/gatecat/interchange-warn-fixgatecat2021-09-303-7/+10
|\ | | | | interchange: Enable Werror on CI and fix some compile warnings
| * interchange: Fix compile warningsgatecat2021-09-282-6/+9
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * ci: Enable -Werror for interchange archgatecat2021-09-281-1/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #810 from antmicro/write-timing-reportgatecat2021-09-297-158/+539
|\ \ | | | | | | Timing report in JSON format
| * | Code formattingMaciej Kurc2021-09-294-119/+87
| | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * | Brought back printout of critical path source file references, added ↵Maciej Kurc2021-09-293-28/+74
| | | | | | | | | | | | | | | | | | clk-to-q, source and setup segment types Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * | Shifted moving of data containers after printingMaciej Kurc2021-09-281-11/+11
| | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * | Added a commandline option controlled writeout of per-net timing detailsMaciej Kurc2021-09-284-9/+22
| | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * | Added description of the JSON report structure.Maciej Kurc2021-09-281-1/+73
| | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * | Moved timing result report storage to the context, added its writeout to the ↵Maciej Kurc2021-09-286-282/+279
| | | | | | | | | | | | | | | | | | current utilization and fmax report Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * | Added reporting critical paths in JSON formatMaciej Kurc2021-09-281-25/+49
| | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * | Decoupled critical path report generation from its printingMaciej Kurc2021-09-281-134/+264
| | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * | Switched to JSON format for timing analysis reportMaciej Kurc2021-09-281-33/+81
| | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * | Added writing a CSV report with timing analysis of each net branchMaciej Kurc2021-09-284-6/+89
| |/ | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | Merge pull request #830 from yrabbit/mistypegatecat2021-09-291-1/+1
|\ \ | |/ |/| Fix mistype.
| * Fix mistype.YRabbit2021-09-291-1/+1
|/ | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #827 from YosysHQ/gatecat/idstring-ingatecat2021-09-271-0/+10
|\ | | | | idstring: Add 'in' function from Yosys
| * idstring: Add 'in' functiongatecat2021-09-271-0/+10
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #812 from antmicro/MacroCellsgatecat2021-09-277-22/+572
|\ | | | | Convert macros to clusters for better placement
| * Fix small isses and code formattingMaciej Dudek2021-09-275-148/+150
| | | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
| * Break up macro_cluster_placement into smaller functionsMaciej Dudek2021-09-241-20/+33
| | | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
| * Update python-fpga-interchange to v0.0.20Maciej Dudek2021-09-231-1/+1
| | | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
| * Fix AC-3 algorithmMaciej Dudek2021-09-231-9/+17
| | | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
| * Improve macro cluster placementMaciej Dudek2021-09-231-235/+41
| | | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
| * Change Cluster placement algorithmMaciej Dudek2021-09-233-123/+133
| | | | | | | | | | | | | | Use physical placement from device DB It should reduce runtime Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
| * Adding MacroCell placementMaciej Dudek2021-09-234-21/+353
| | | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
| * Adding support for MacroCellsMaciej Dudek2021-09-235-6/+385
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