| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | clangformat | Clifford Wolf | 2018-07-23 | 2 | -20/+26 | |
| * | Add fallback to estimateDelay() in getNetinfoRouteDelay() | Clifford Wolf | 2018-07-23 | 1 | -1/+6 | |
| * | Add getGridDimX(), getGridDimY(), getTileDimZ() API | Clifford Wolf | 2018-07-23 | 3 | -1/+31 | |
| * | ecp5: Implement new Grid APIs | David Shah | 2018-07-23 | 2 | -0/+50 | |
| * | ecp5: Remove obsolete db entries, add Bel z-position | David Shah | 2018-07-23 | 2 | -19/+2 | |
| * | Bugfix in iCE40 chipdb.py | Clifford Wolf | 2018-07-23 | 1 | -3/+0 | |
| * | Added Bel port info to GUI | Miodrag Milanovic | 2018-07-22 | 1 | -0/+8 | |
| * | Move to new API and remove deprecated | Miodrag Milanovic | 2018-07-22 | 6 | -94/+40 | |
| * | Move to new api | Miodrag Milanovic | 2018-07-22 | 1 | -12/+3 | |
| * | ecp5: Adding new Bel pin API | David Shah | 2018-07-22 | 3 | -3/+63 | |
| * | ecp5: Fix regression following router update | David Shah | 2018-07-22 | 2 | -2/+2 | |
| * | Add Arch::getBelPins() to generic and iCE40 archs | Clifford Wolf | 2018-07-22 | 4 | -0/+25 | |
| * | Add Arch::getBelPinType() and Arch::getWireBelPins() in iCE40 arch | Clifford Wolf | 2018-07-22 | 3 | -4/+57 | |
| * | Add Arch::getBelPinType() and Arch::getWireBelPins() in generic arch | Clifford Wolf | 2018-07-22 | 2 | -2/+12 | |
| * | Rename getWireBelPin to getBelPinWire | Clifford Wolf | 2018-07-22 | 12 | -26/+26 | |
| * | Move common patterns from router1 to Context API | Clifford Wolf | 2018-07-22 | 3 | -150/+124 | |
| * | clangformat | Clifford Wolf | 2018-07-22 | 5 | -39/+30 | |
| * | QTimer::start(std::chrono::duration -> int) | Sergiusz Bazanski | 2018-07-21 | 2 | -3/+3 | |
| * | Merge branch 'q3k/lock-2-electric-boogaloo' into 'master' | Clifford Wolf | 2018-07-21 | 7 | -161/+397 | |
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| | * | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/lock-2-elec... | Sergiusz Bazanski | 2018-07-21 | 22 | -682/+1466 | |
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| | * | | Re-enable drawing Pips. | Sergiusz Bazanski | 2018-07-20 | 1 | -3/+3 | |
| | * | | Use UI lock for yielding | Sergiusz Bazanski | 2018-07-20 | 4 | -14/+40 | |
| | * | | clang-format | Sergiusz Bazanski | 2018-07-20 | 1 | -1/+1 | |
| | * | | Nuke IdStringDB | Sergiusz Bazanski | 2018-07-20 | 5 | -50/+41 | |
| | * | | Remove dead code. | Sergiusz Bazanski | 2018-07-20 | 1 | -2/+0 | |
| | * | | clang-format and uncomment debug | Sergiusz Bazanski | 2018-07-20 | 4 | -45/+39 | |
| | * | | Move pthread yield hack into BaseCtx | Sergiusz Bazanski | 2018-07-20 | 3 | -10/+14 | |
| | * | | Mix-in Deterministic RNG at Context instead of BaseCtx | Sergiusz Bazanski | 2018-07-20 | 1 | -2/+2 | |
| | * | | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/lock-2-elec... | Sergiusz Bazanski | 2018-07-20 | 48 | -825/+754 | |
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| | * | | | Refactor renderer thread | Sergiusz Bazanski | 2018-07-20 | 2 | -27/+64 | |
| | * | | | WIP. | Serge Bazanski | 2018-07-17 | 7 | -96/+227 | |
| | * | | | Add basic external locking, lock from P&R | Serge Bazanski | 2018-07-17 | 3 | -0/+40 | |
| | * | | | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/lock-2-elec... | Serge Bazanski | 2018-07-17 | 25 | -395/+1211 | |
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| | * \ \ \ | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/lock-2-elec... | Serge Bazanski | 2018-07-15 | 16 | -313/+810 | |
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| | * | | | | | Refactor RNG out to separate DeterministicRNG class | Serge Bazanski | 2018-07-14 | 1 | -57/+67 | |
| | * | | | | | Refactor IdString functionality into IdStringDB | Serge Bazanski | 2018-07-14 | 5 | -27/+33 | |
| * | | | | | | Add Loc constructors | Clifford Wolf | 2018-07-21 | 4 | -17/+10 | |
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| * | | | | | Added driver and users for nets | Miodrag Milanovic | 2018-07-21 | 1 | -0/+8 | |
| * | | | | | Merge branch 'router1ng' into 'master' | Clifford Wolf | 2018-07-21 | 2 | -87/+341 | |
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| | * | | | | | Bugfix in router1: Also bind src_wire | Clifford Wolf | 2018-07-21 | 1 | -0/+2 | |
| | * | | | | | Add final sanity check in router1 | Clifford Wolf | 2018-07-21 | 1 | -0/+19 | |
| | * | | | | | Refactoring of router1 | Clifford Wolf | 2018-07-21 | 2 | -87/+320 | |
| * | | | | | | Map ports to nets | Miodrag Milanovic | 2018-07-21 | 1 | -0/+14 | |
| * | | | | | | create io cells out of asc | Miodrag Milanovic | 2018-07-21 | 1 | -0/+27 | |
| * | | | | | | add cells that are in default state or no configuration | Miodrag Milanovic | 2018-07-21 | 1 | -0/+40 | |
| * | | | | | | Add used cells and attach them to bels | Miodrag Milanovic | 2018-07-21 | 1 | -0/+39 | |
| * | | | | | | Fix placement bug with VexRiscV reported by John McMaster | David Shah | 2018-07-21 | 1 | -2/+3 | |
| * | | | | | | Assign proper pips | Miodrag Milanovic | 2018-07-21 | 1 | -9/+27 | |
| * | | | | | | add only missing net | Miodrag Milanovic | 2018-07-21 | 1 | -3/+6 | |
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| * | | | | | Fix minor issue in GUI Wire properties | Clifford Wolf | 2018-07-21 | 1 | -2/+2 | |
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index : iCE40/nextpnr | |
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