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-rw-r--r--ice40/arch.h23
-rw-r--r--ice40/arch_pybindings.cc6
-rw-r--r--ice40/bitstream.cc74
3 files changed, 40 insertions, 63 deletions
diff --git a/ice40/arch.h b/ice40/arch.h
index 2e2018fb..3ae6ce65 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -471,29 +471,6 @@ struct Arch : BaseCtx
WireId getBelPinWire(BelId bel, PortPin pin) const;
PortType getBelPinType(BelId bel, PortPin pin) const;
-
- BelPin getBelPinUphill(WireId wire) const NPNR_DEPRECATED
- {
- BelPin ret;
- NPNR_ASSERT(wire != WireId());
-
- if (chip_info->wire_data[wire.index].bel_uphill.bel_index >= 0) {
- ret.bel.index = chip_info->wire_data[wire.index].bel_uphill.bel_index;
- ret.pin = chip_info->wire_data[wire.index].bel_uphill.port;
- }
-
- return ret;
- }
-
- BelPinRange getBelPinsDownhill(WireId wire) const NPNR_DEPRECATED
- {
- BelPinRange range;
- NPNR_ASSERT(wire != WireId());
- range.b.ptr = chip_info->wire_data[wire.index].bels_downhill.get();
- range.e.ptr = range.b.ptr + chip_info->wire_data[wire.index].num_bels_downhill;
- return range;
- }
-
std::vector<PortPin> getBelPins(BelId bel) const;
// -------------------------------------------------
diff --git a/ice40/arch_pybindings.cc b/ice40/arch_pybindings.cc
index a1ce9f5b..246d0f57 100644
--- a/ice40/arch_pybindings.cc
+++ b/ice40/arch_pybindings.cc
@@ -84,10 +84,8 @@ void arch_wrap_python()
fn_wrapper_2a<Context, decltype(&Context::getBelPinWire), &Context::getBelPinWire, conv_to_str<WireId>,
conv_from_str<BelId>, conv_from_str<PortPin>>::def_wrap(ctx_cls, "getBelPinWire");
- fn_wrapper_1a<Context, decltype(&Context::getBelPinUphill), &Context::getBelPinUphill, wrap_context<BelPin>,
- conv_from_str<WireId>>::def_wrap(ctx_cls, "getBelPinUphill");
- fn_wrapper_1a<Context, decltype(&Context::getBelPinsDownhill), &Context::getBelPinsDownhill,
- wrap_context<BelPinRange>, conv_from_str<WireId>>::def_wrap(ctx_cls, "getBelPinsDownhill");
+ fn_wrapper_1a<Context, decltype(&Context::getWireBelPins), &Context::getWireBelPins, wrap_context<BelPinRange>,
+ conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireBelPins");
fn_wrapper_1a<Context, decltype(&Context::getWireChecksum), &Context::getWireChecksum, pass_through<uint32_t>,
conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireChecksum");
diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index 9f5d1f66..5559c2ce 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -717,42 +717,44 @@ bool read_asc(Context *ctx, std::istream &in)
for (auto w : net.second->wires) {
if (w.second.pip == PipId()) {
WireId wire = w.first;
- BelPin belpin = ctx->getBelPinUphill(wire);
- if (ctx->checkBelAvail(belpin.bel)) {
- if (ctx->getBelType(belpin.bel) == TYPE_ICESTORM_LC) {
- std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("ICESTORM_LC"));
- IdString name = created->name;
- ctx->cells[name] = std::move(created);
- ctx->bindBel(belpin.bel, name, STRENGTH_WEAK);
- // TODO: Add port mapping to nets
- }
- if (ctx->getBelType(belpin.bel) == TYPE_SB_IO) {
- std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("SB_IO"));
- IdString name = created->name;
- ctx->cells[name] = std::move(created);
- ctx->bindBel(belpin.bel, name, STRENGTH_WEAK);
- // TODO: Add port mapping to nets
- }
- if (ctx->getBelType(belpin.bel) == TYPE_SB_GB) {
- std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("SB_GB"));
- IdString name = created->name;
- ctx->cells[name] = std::move(created);
- ctx->bindBel(belpin.bel, name, STRENGTH_WEAK);
- // TODO: Add port mapping to nets
- }
- if (ctx->getBelType(belpin.bel) == TYPE_SB_WARMBOOT) {
- std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("SB_WARMBOOT"));
- IdString name = created->name;
- ctx->cells[name] = std::move(created);
- ctx->bindBel(belpin.bel, name, STRENGTH_WEAK);
- // TODO: Add port mapping to nets
- }
- if (ctx->getBelType(belpin.bel) == TYPE_ICESTORM_LFOSC) {
- std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("ICESTORM_LFOSC"));
- IdString name = created->name;
- ctx->cells[name] = std::move(created);
- ctx->bindBel(belpin.bel, name, STRENGTH_WEAK);
- // TODO: Add port mapping to nets
+ for (auto belpin : ctx->getWireBelPins(wire)) {
+
+ if (ctx->checkBelAvail(belpin.bel)) {
+ if (ctx->getBelType(belpin.bel) == TYPE_ICESTORM_LC) {
+ std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("ICESTORM_LC"));
+ IdString name = created->name;
+ ctx->cells[name] = std::move(created);
+ ctx->bindBel(belpin.bel, name, STRENGTH_WEAK);
+ // TODO: Add port mapping to nets
+ }
+ if (ctx->getBelType(belpin.bel) == TYPE_SB_IO) {
+ std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("SB_IO"));
+ IdString name = created->name;
+ ctx->cells[name] = std::move(created);
+ ctx->bindBel(belpin.bel, name, STRENGTH_WEAK);
+ // TODO: Add port mapping to nets
+ }
+ if (ctx->getBelType(belpin.bel) == TYPE_SB_GB) {
+ std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("SB_GB"));
+ IdString name = created->name;
+ ctx->cells[name] = std::move(created);
+ ctx->bindBel(belpin.bel, name, STRENGTH_WEAK);
+ // TODO: Add port mapping to nets
+ }
+ if (ctx->getBelType(belpin.bel) == TYPE_SB_WARMBOOT) {
+ std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("SB_WARMBOOT"));
+ IdString name = created->name;
+ ctx->cells[name] = std::move(created);
+ ctx->bindBel(belpin.bel, name, STRENGTH_WEAK);
+ // TODO: Add port mapping to nets
+ }
+ if (ctx->getBelType(belpin.bel) == TYPE_ICESTORM_LFOSC) {
+ std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("ICESTORM_LFOSC"));
+ IdString name = created->name;
+ ctx->cells[name] = std::move(created);
+ ctx->bindBel(belpin.bel, name, STRENGTH_WEAK);
+ // TODO: Add port mapping to nets
+ }
}
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-31 09:39:24 +0000