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-rw-r--r--ice40/bitstream.cc2
-rw-r--r--ice40/cells.h2
-rw-r--r--ice40/main.cc2
3 files changed, 3 insertions, 3 deletions
diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index 918eb01b..9309a7da 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -398,7 +398,7 @@ void write_asc(const Design &design, std::ostream &out)
for (auto wire : chip.getWires()) {
IdString net = chip.getWireNet(wire, false);
if (net != IdString())
- out << ".sym " << wire.index << " net_" << net << std::endl;
+ out << ".sym " << wire.index << " " << net << std::endl;
}
}
diff --git a/ice40/cells.h b/ice40/cells.h
index 82d9f60e..45e81fd1 100644
--- a/ice40/cells.h
+++ b/ice40/cells.h
@@ -3,7 +3,7 @@
*
* Copyright (C) 2018 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2018 David Shah <david@symbioticeda.com>
- *
+ *
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
diff --git a/ice40/main.cc b/ice40/main.cc
index 3cd97f48..eb92d92f 100644
--- a/ice40/main.cc
+++ b/ice40/main.cc
@@ -25,6 +25,7 @@
#include <fstream>
#include <iostream>
#include "bitstream.h"
+#include "design_utils.h"
#include "jsonparse.h"
#include "log.h"
#include "mainwindow.h"
@@ -35,7 +36,6 @@
#include "pybindings.h"
#include "route.h"
#include "version.h"
-#include "design_utils.h"
void svg_dump_el(const GraphicElement &el)
{