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-rw-r--r--fpga_interchange/arch.cc7
1 files changed, 7 insertions, 0 deletions
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index 901725d4..33720e98 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -813,6 +813,10 @@ bool Arch::place()
getCtx()->attrs[getCtx()->id("step")] = std::string("place");
archInfoToAttributes();
+ // Print site LUT mapping caching stats
+ log_info("Site LUT mapping cache miss ratio: %.1f%%\n",
+ getCtx()->site_lut_mapping_cache.getMissRatio() * 100.0f);
+
getCtx()->check();
return true;
@@ -836,6 +840,9 @@ static void prepare_sites_for_routing(Context *ctx)
// pins to ensure a routeable pin choice.
ctx->site_routing_cache.clear();
+ // Clear the LUT mapping cache
+ ctx->site_lut_mapping_cache.clear();
+
// Have site router bind site routing (via bindPip and bindWire).
// This is important so that the pseudo pips are correctly blocked prior
// to handing the design to the generalized router algorithms.