diff options
Diffstat (limited to 'ecp5')
| -rw-r--r-- | ecp5/arch.cc | 132 | ||||
| -rw-r--r-- | ecp5/arch.h | 56 | ||||
| -rw-r--r-- | ecp5/arch_place.cc | 24 | ||||
| -rw-r--r-- | ecp5/archdefs.h | 4 | ||||
| -rw-r--r-- | ecp5/pack.cc | 24 | ||||
| -rwxr-xr-x | ecp5/trellis_import.py | 46 |
6 files changed, 244 insertions, 42 deletions
diff --git a/ecp5/arch.cc b/ecp5/arch.cc index 4358fdaf..82ebfba1 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -46,7 +46,9 @@ static std::tuple<int, int, std::string> split_identifier_name(const std::string void IdString::initialize_arch(const BaseCtx *ctx) { #define X(t) initialize_add(ctx, #t, ID_##t); + #include "constids.inc" + #undef X } @@ -92,6 +94,8 @@ Arch::Arch(ArchArgs args) : args(args) if (!package_info) log_error("Unsupported package '%s' for '%s'.\n", args.package.c_str(), getChipName().c_str()); + + bel_to_cell.resize(chip_info->height * chip_info->width * max_loc_bels, nullptr); } // ----------------------------------------------------------------------- @@ -367,7 +371,7 @@ BelId Arch::getBelByLocation(Loc loc) const delay_t Arch::estimateDelay(WireId src, WireId dst) const { - return 200 * (abs(src.location.x - dst.location.x) + abs(src.location.y - dst.location.y)); + return 100 * (abs(src.location.x - dst.location.x) + abs(src.location.y - dst.location.y)); } delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const @@ -376,20 +380,16 @@ delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const auto driver_loc = getBelLocation(driver.cell->bel); auto sink_loc = getBelLocation(sink.cell->bel); - return 200 * (abs(driver_loc.x - sink_loc.x) + abs(driver_loc.y - sink_loc.y)); + return 100 * (abs(driver_loc.x - sink_loc.x) + abs(driver_loc.y - sink_loc.y)); } bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; } // ----------------------------------------------------------------------- -bool Arch::place() { return placer1(getCtx(), Placer1Cfg()); } +bool Arch::place() { return placer1(getCtx(), Placer1Cfg(getCtx())); } -bool Arch::route() -{ - Router1Cfg cfg; - return router1(getCtx(), cfg); -} +bool Arch::route() { return router1(getCtx(), Router1Cfg(getCtx())); } // ----------------------------------------------------------------------- @@ -436,7 +436,7 @@ DecalXY Arch::getBelDecal(BelId bel) const decalxy.decal.type = DecalId::TYPE_BEL; decalxy.decal.location = bel.location; decalxy.decal.z = bel.index; - decalxy.decal.active = bel_to_cell.count(bel) && (bel_to_cell.at(bel) != nullptr); + decalxy.decal.active = (bel_to_cell.at(getBelFlatIndex(bel)) != nullptr); return decalxy; } @@ -450,12 +450,122 @@ DecalXY Arch::getGroupDecal(GroupId pip) const { return {}; }; bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const { - return false; + // Data for -8 grade + if (cell->type == id_TRELLIS_SLICE) { + bool has_carry = str_or_default(cell->params, id("MODE"), "LOGIC") == "CCU2"; + if (fromPort == id_A0 || fromPort == id_B0 || fromPort == id_C0 || fromPort == id_D0) { + if (toPort == id_F0) { + delay.delay = 180; + return true; + } else if (has_carry && toPort == id_F1) { + delay.delay = 500; + return true; + } else if (has_carry && toPort == id_FCO) { + delay.delay = 355; + return true; + } else if (toPort == id_OFX0) { + delay.delay = 306; + return true; + } + } + + if (fromPort == id_A1 || fromPort == id_B1 || fromPort == id_C1 || fromPort == id_D1) { + if (toPort == id_F1) { + delay.delay = 180; + return true; + } else if (has_carry && toPort == id_FCO) { + delay.delay = 355; + return true; + } else if (toPort == id_OFX0) { + delay.delay = 306; + return true; + } + } + + if (has_carry && fromPort == id_FCI) { + if (toPort == id_F0) { + delay.delay = 328; + return true; + } else if (toPort == id_F1) { + delay.delay = 349; + return true; + } else if (toPort == id_FCO) { + delay.delay = 56; + return true; + } + } + + if (fromPort == id_CLK && (toPort == id_Q0 || toPort == id_Q1)) { + delay.delay = 395; + return true; + } + + if (fromPort == id_M0 && toPort == id_OFX0) { + delay.delay = 193; + return true; + } + + if (fromPort == id_WCK && (toPort == id_F0 || toPort == id_F1)) { + delay.delay = 717; + return true; + } + + if ((fromPort == id_A0 && toPort == id_WADO3) || (fromPort == id_A1 && toPort == id_WDO1) || + (fromPort == id_B0 && toPort == id_WADO1) || (fromPort == id_B1 && toPort == id_WDO3) || + (fromPort == id_C0 && toPort == id_WADO2) || (fromPort == id_C1 && toPort == id_WDO0) || + (fromPort == id_D0 && toPort == id_WADO0) || (fromPort == id_D1 && toPort == id_WDO2)) { + delay.delay = 0; + return true; + } + return false; + } else { + return false; + } } TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockPort) const { - return TMG_IGNORE; + if (cell->type == id_TRELLIS_SLICE) { + int sd0 = int_or_default(cell->params, id("REG0_SD"), 0), sd1 = int_or_default(cell->params, id("REG1_SD"), 0); + if (port == id_CLK || port == id_WCK) + return TMG_CLOCK_INPUT; + if (port == id_A0 || port == id_A1 || port == id_B0 || port == id_B1 || port == id_C0 || port == id_C1 || + port == id_D0 || port == id_D1 || port == id_FCI || port == id_FXA || port == id_FXB) + return TMG_COMB_INPUT; + if (port == id_F0 || port == id_F1 || port == id_FCO || port == id_OFX0 || port == id_OFX1) + return TMG_COMB_OUTPUT; + if (port == id_DI0 || port == id_DI1 || port == id_CE || port == id_LSR || (sd0 == 1 && port == id_M0) || + (sd1 == 1 && port == id_M1)) { + clockPort = id_CLK; + return TMG_REGISTER_INPUT; + } + if (port == id_M0 || port == id_M1) + return TMG_COMB_INPUT; + if (port == id_Q0 || port == id_Q1) { + clockPort = id_CLK; + return TMG_REGISTER_OUTPUT; + } + + if (port == id_WDO0 || port == id_WDO1 || port == id_WDO2 || port == id_WDO3 || port == id_WADO0 || + port == id_WADO1 || port == id_WADO2 || port == id_WADO3) + return TMG_COMB_OUTPUT; + + if (port == id_WD0 || port == id_WD1 || port == id_WAD0 || port == id_WAD1 || port == id_WAD2 || + port == id_WAD3 || port == id_WRE) { + clockPort = id_WCK; + return TMG_REGISTER_INPUT; + } + + NPNR_ASSERT_FALSE_STR("no timing type for slice port '" + port.str(this) + "'"); + } else if (cell->type == id_TRELLIS_IO) { + if (port == id_T || port == id_I) + return TMG_ENDPOINT; + if (port == id_O) + return TMG_STARTPOINT; + return TMG_IGNORE; + } else { + NPNR_ASSERT_FALSE_STR("no timing data for cell type '" + cell->type.str(this) + "'"); + } } std::vector<std::pair<std::string, std::string>> Arch::getTilesAtLocation(int row, int col) diff --git a/ecp5/arch.h b/ecp5/arch.h index 36792625..da86d4e2 100644 --- a/ecp5/arch.h +++ b/ecp5/arch.h @@ -404,7 +404,7 @@ struct Arch : BaseCtx mutable std::unordered_map<IdString, WireId> wire_by_name; mutable std::unordered_map<IdString, PipId> pip_by_name; - std::unordered_map<BelId, CellInfo *> bel_to_cell; + std::vector<CellInfo *> bel_to_cell; std::unordered_map<WireId, NetInfo *> wire_to_net; std::unordered_map<PipId, NetInfo *> pip_to_net; @@ -443,11 +443,18 @@ struct Arch : BaseCtx uint32_t getBelChecksum(BelId bel) const { return bel.index; } + const int max_loc_bels = 20; + int getBelFlatIndex(BelId bel) const + { + return (bel.location.y * chip_info->width + bel.location.x) * max_loc_bels + bel.index; + } + void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength) { NPNR_ASSERT(bel != BelId()); - NPNR_ASSERT(bel_to_cell[bel] == nullptr); - bel_to_cell[bel] = cell; + int idx = getBelFlatIndex(bel); + NPNR_ASSERT(bel_to_cell.at(idx) == nullptr); + bel_to_cell[idx] = cell; cell->bel = bel; cell->belStrength = strength; refreshUiBel(bel); @@ -456,10 +463,11 @@ struct Arch : BaseCtx void unbindBel(BelId bel) { NPNR_ASSERT(bel != BelId()); - NPNR_ASSERT(bel_to_cell[bel] != nullptr); - bel_to_cell[bel]->bel = BelId(); - bel_to_cell[bel]->belStrength = STRENGTH_NONE; - bel_to_cell[bel] = nullptr; + int idx = getBelFlatIndex(bel); + NPNR_ASSERT(bel_to_cell.at(idx) != nullptr); + bel_to_cell[idx]->bel = BelId(); + bel_to_cell[idx]->belStrength = STRENGTH_NONE; + bel_to_cell[idx] = nullptr; refreshUiBel(bel); } @@ -480,25 +488,19 @@ struct Arch : BaseCtx bool checkBelAvail(BelId bel) const { NPNR_ASSERT(bel != BelId()); - return bel_to_cell.find(bel) == bel_to_cell.end() || bel_to_cell.at(bel) == nullptr; + return bel_to_cell[getBelFlatIndex(bel)] == nullptr; } CellInfo *getBoundBelCell(BelId bel) const { NPNR_ASSERT(bel != BelId()); - if (bel_to_cell.find(bel) == bel_to_cell.end()) - return nullptr; - else - return bel_to_cell.at(bel); + return bel_to_cell[getBelFlatIndex(bel)]; } CellInfo *getConflictingBelCell(BelId bel) const { NPNR_ASSERT(bel != BelId()); - if (bel_to_cell.find(bel) == bel_to_cell.end()) - return nullptr; - else - return bel_to_cell.at(bel); + return bel_to_cell[getBelFlatIndex(bel)]; } BelRange getBels() const @@ -522,6 +524,12 @@ struct Arch : BaseCtx return id; } + std::vector<std::pair<IdString, std::string>> getBelAttrs(BelId) const + { + std::vector<std::pair<IdString, std::string>> ret; + return ret; + } + WireId getBelPinWire(BelId bel, IdString pin) const; BelPinRange getWireBelPins(WireId wire) const @@ -553,6 +561,12 @@ struct Arch : BaseCtx IdString getWireType(WireId wire) const { return IdString(); } + std::vector<std::pair<IdString, std::string>> getWireAttrs(WireId) const + { + std::vector<std::pair<IdString, std::string>> ret; + return ret; + } + uint32_t getWireChecksum(WireId wire) const { return wire.index; } void bindWire(WireId wire, NetInfo *net, PlaceStrength strength) @@ -633,6 +647,12 @@ struct Arch : BaseCtx IdString getPipType(PipId pip) const { return IdString(); } + std::vector<std::pair<IdString, std::string>> getPipAttrs(PipId) const + { + std::vector<std::pair<IdString, std::string>> ret; + return ret; + } + uint32_t getPipChecksum(PipId pip) const { return pip.index; } void bindPip(PipId pip, NetInfo *net, PlaceStrength strength) @@ -725,7 +745,7 @@ struct Arch : BaseCtx { DelayInfo delay; NPNR_ASSERT(pip != PipId()); - delay.delay = locInfo(pip)->pip_data[pip.index].delay * 100; + delay.delay = locInfo(pip)->pip_data[pip.index].delay; return delay; } @@ -848,6 +868,8 @@ struct Arch : BaseCtx // Helper function for above bool slicesCompatible(const std::vector<const CellInfo *> &cells) const; + void assignArchInfo(); + std::vector<std::pair<std::string, std::string>> getTilesAtLocation(int row, int col); std::string getTileByTypeAndLocation(int row, int col, std::string type) const { diff --git a/ecp5/arch_place.cc b/ecp5/arch_place.cc index 83af6b5a..55fff73d 100644 --- a/ecp5/arch_place.cc +++ b/ecp5/arch_place.cc @@ -35,26 +35,26 @@ bool Arch::slicesCompatible(const std::vector<const CellInfo *> &cells) const { // TODO: allow different LSR/CLK and MUX/SRMODE settings once // routing details are worked out - NetInfo *clk_sig = nullptr, *lsr_sig = nullptr; - std::string CLKMUX, LSRMUX, SRMODE; + IdString clk_sig, lsr_sig; + IdString CLKMUX, LSRMUX, SRMODE; bool first = true; for (auto cell : cells) { if (first) { - clk_sig = port_or_nullptr(cell, id_CLK); - lsr_sig = port_or_nullptr(cell, id_LSR); - CLKMUX = str_or_default(cell->params, id_CLKMUX, "CLK"); - LSRMUX = str_or_default(cell->params, id_LSRMUX, "LSR"); - SRMODE = str_or_default(cell->params, id_SRMODE, "CE_OVER_LSR"); + clk_sig = cell->sliceInfo.clk_sig; + lsr_sig = cell->sliceInfo.lsr_sig; + CLKMUX = cell->sliceInfo.clkmux; + LSRMUX = cell->sliceInfo.lsrmux; + SRMODE = cell->sliceInfo.srmode; } else { - if (port_or_nullptr(cell, id_CLK) != clk_sig) + if (cell->sliceInfo.clk_sig != clk_sig) return false; - if (port_or_nullptr(cell, id_LSR) != lsr_sig) + if (cell->sliceInfo.lsr_sig != lsr_sig) return false; - if (str_or_default(cell->params, id_CLKMUX, "CLK") != CLKMUX) + if (cell->sliceInfo.clkmux != CLKMUX) return false; - if (str_or_default(cell->params, id_LSRMUX, "LSR") != LSRMUX) + if (cell->sliceInfo.lsrmux != LSRMUX) return false; - if (str_or_default(cell->params, id_SRMODE, "CE_OVER_LSR") != SRMODE) + if (cell->sliceInfo.srmode != SRMODE) return false; } first = false; diff --git a/ecp5/archdefs.h b/ecp5/archdefs.h index 1493c691..c4e1413f 100644 --- a/ecp5/archdefs.h +++ b/ecp5/archdefs.h @@ -139,6 +139,10 @@ struct ArchNetInfo }; struct ArchCellInfo { + struct + { + IdString clk_sig, lsr_sig, clkmux, lsrmux, srmode; + } sliceInfo; }; NEXTPNR_NAMESPACE_END diff --git a/ecp5/pack.cc b/ecp5/pack.cc index 786f543e..a2077204 100644 --- a/ecp5/pack.cc +++ b/ecp5/pack.cc @@ -536,10 +536,34 @@ bool Arch::pack() log_break(); Ecp5Packer(ctx).pack(); log_info("Checksum: 0x%08x\n", ctx->checksum()); + assignArchInfo(); return true; } catch (log_execution_error_exception) { + assignArchInfo(); return false; } } +void Arch::assignArchInfo() +{ + for (auto cell : sorted(cells)) { + CellInfo *ci = cell.second; + if (ci->type == id_TRELLIS_SLICE) { + if (ci->ports.count(id_CLK) && ci->ports[id_CLK].net != nullptr) + ci->sliceInfo.clk_sig = ci->ports[id_CLK].net->name; + else + ci->sliceInfo.clk_sig = IdString(); + + if (ci->ports.count(id_LSR) && ci->ports[id_LSR].net != nullptr) + ci->sliceInfo.lsr_sig = ci->ports[id_LSR].net->name; + else + ci->sliceInfo.lsr_sig = IdString(); + + ci->sliceInfo.clkmux = id(str_or_default(ci->params, id_CLKMUX, "CLK")); + ci->sliceInfo.lsrmux = id(str_or_default(ci->params, id_LSRMUX, "LSR")); + ci->sliceInfo.srmode = id(str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE")); + } + } +} + NEXTPNR_NAMESPACE_END diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py index 7c7c9e15..de8e9958 100755 --- a/ecp5/trellis_import.py +++ b/ecp5/trellis_import.py @@ -130,11 +130,54 @@ def process_loc_globals(chip): tapdrv = chip.global_data.get_tap_driver(y, x) global_data[x, y] = (quadrants.index(quad), int(tapdrv.dir), tapdrv.col) +def get_wire_type(name): + if "H00" in name or "V00" in name: + return "X0" + if "H01" in name or "V01" in name: + return "X1" + if "H02" in name or "V02" in name: + return "X2" + if "H06" in name or "V06" in name: + return "X6" + if "_SLICE" in name or "_EBR" in name: + return "SLICE" + return "LOCAL" + +def get_pip_delay(wire_from, wire_to): + # ECP5 timings WIP!!! + type_from = get_wire_type(wire_from) + type_to = get_wire_type(wire_to) + if type_from == "X2" and type_to == "X2": + return 170 + if type_from == "SLICE" or type_to == "SLICE": + return 205 + if type_from in ("LOCAL", "X0") and type_to in ("X1", "X2", "X6"): + return 90 + if type_from == "X6" or type_to == "X6": + return 200 + if type_from in ("X1", "X2", "X6") and type_to in ("LOCAL", "X0"): + return 90 + return 100 + + + def write_database(dev_name, chip, ddrg, endianness): def write_loc(loc, sym_name): bba.u16(loc.x, "%s.x" % sym_name) bba.u16(loc.y, "%s.y" % sym_name) + loctypes = list([_.key() for _ in ddrg.locationTypes]) + loc_with_type = {} + for y in range(0, max_row+1): + for x in range(0, max_col+1): + loc_with_type[loctypes.index(ddrg.typeAtLocation[pytrellis.Location(x, y)])] = (x, y) + + def get_wire_name(arc_loctype, rel, idx): + loc = loc_with_type[arc_loctype] + lt = ddrg.typeAtLocation[pytrellis.Location(loc[0] + rel.x, loc[1] + rel.y)] + wire = ddrg.locationTypes[lt].wires[idx] + return ddrg.to_str(wire.name) + bba = BinaryBlobAssembler() bba.pre('#include "nextpnr.h"') bba.pre('NEXTPNR_NAMESPACE_BEGIN') @@ -142,7 +185,6 @@ def write_database(dev_name, chip, ddrg, endianness): bba.push("chipdb_blob_%s" % dev_name) bba.r("chip_info", "chip_info") - loctypes = list([_.key() for _ in ddrg.locationTypes]) for idx in range(len(loctypes)): loctype = ddrg.locationTypes[loctypes[idx]] @@ -153,7 +195,7 @@ def write_database(dev_name, chip, ddrg, endianness): write_loc(arc.sinkWire.rel, "dst") bba.u32(arc.srcWire.id, "src_idx") bba.u32(arc.sinkWire.id, "dst_idx") - bba.u32(arc.delay, "delay") # TODO:delay + bba.u32(get_pip_delay(get_wire_name(idx, arc.srcWire.rel, arc.srcWire.id), get_wire_name(idx, arc.sinkWire.rel, arc.sinkWire.id)), "delay") # TODO:delay bba.u16(get_tiletype_index(ddrg.to_str(arc.tiletype)), "tile_type") bba.u8(int(arc.cls), "pip_type") bba.u8(0, "padding") |