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-rw-r--r--ecp5/arch.cc2
-rw-r--r--ecp5/arch.h5
-rw-r--r--ecp5/bitstream.cc139
-rw-r--r--ecp5/cells.cc42
-rw-r--r--ecp5/cells.h4
-rw-r--r--ecp5/constids.inc23
-rw-r--r--ecp5/globals.cc128
-rw-r--r--ecp5/globals.h1
-rw-r--r--ecp5/lpf.cc106
-rw-r--r--ecp5/main.cc16
-rw-r--r--ecp5/pack.cc12
11 files changed, 436 insertions, 42 deletions
diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index ab3e15c0..4a0b31b5 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -651,6 +651,8 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id
return TMG_IGNORE; // FIXME
} else if (cell->type == id_ALU54B) {
return TMG_IGNORE; // FIXME
+ } else if (cell->type == id_EHXPLLL) {
+ return TMG_IGNORE;
} else {
NPNR_ASSERT_FALSE_STR("no timing data for cell type '" + cell->type.str(this) + "'");
}
diff --git a/ecp5/arch.h b/ecp5/arch.h
index 35c8df19..583d539f 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -491,7 +491,7 @@ struct Arch : BaseCtx
BelId getBelByLocation(Loc loc) const;
BelRange getBelsByTile(int x, int y) const;
- bool getBelGlobalBuf(BelId bel) const { return false; }
+ bool getBelGlobalBuf(BelId bel) const { return getBelType(bel) == id_DCCA; }
bool checkBelAvail(BelId bel) const
{
@@ -917,6 +917,9 @@ struct Arch : BaseCtx
GlobalInfoPOD globalInfoAtLoc(Location loc);
+ // Apply LPF constraints to the context
+ bool applyLPF(std::string filename, std::istream &in);
+
IdString id_trellis_slice;
IdString id_clk, id_lsr;
IdString id_clkmux, id_lsrmux;
diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc
index c7b5d562..95256732 100644
--- a/ecp5/bitstream.cc
+++ b/ecp5/bitstream.cc
@@ -378,6 +378,32 @@ std::vector<std::string> get_dsp_tiles(Context *ctx, BelId bel)
}
return tiles;
}
+
+// Get the list of tiles corresponding to a PLL
+std::vector<std::string> get_pll_tiles(Context *ctx, BelId bel)
+{
+ std::string name = ctx->locInfo(bel)->bel_data[bel.index].name.get();
+ std::vector<std::string> tiles;
+ Loc loc = ctx->getBelLocation(bel);
+
+ if (name == "EHXPLL_UL") {
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 1, "PLL0_UL"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y + 1, loc.x - 1, "PLL1_UL"));
+ } else if (name == "EHXPLL_LL") {
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y + 1, loc.x, "PLL0_LL"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y + 1, loc.x + 1, "BANKREF8"));
+ } else if (name == "EHXPLL_LR") {
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y + 1, loc.x, "PLL0_LR"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y + 1, loc.x - 1, "PLL1_LR"));
+ } else if (name == "EHXPLL_UR") {
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x - 1, "PLL0_UR"));
+ tiles.push_back(ctx->getTileByTypeAndLocation(loc.y + 1, loc.x - 1, "PLL1_UR"));
+ } else {
+ NPNR_ASSERT_FALSE_STR("bad PLL loc " + name);
+ }
+ return tiles;
+}
+
void fix_tile_names(Context *ctx, ChipConfig &cc)
{
// Remove the V prefix/suffix on certain tiles if device is a SERDES variant
@@ -390,7 +416,7 @@ void fix_tile_names(Context *ctx, ChipConfig &cc)
auto vcib = tile.first.find("VCIB");
if (vcib != std::string::npos) {
// Remove the V
- newname.erase(vcib);
+ newname.erase(vcib, 1);
tiletype_xform[tile.first] = newname;
} else if (tile.first.back() == 'V') {
// BMID_0V or BMID_2V
@@ -429,6 +455,14 @@ void tieoff_dsp_ports(Context *ctx, ChipConfig &cc, CellInfo *ci)
}
}
+static void set_pip(Context *ctx, ChipConfig &cc, PipId pip)
+{
+ std::string tile = ctx->getPipTilename(pip);
+ std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip));
+ std::string sink = get_trellis_wirename(ctx, pip.location, ctx->getPipDstWire(pip));
+ cc.tiles[tile].add_arc(sink, source);
+}
+
void write_bitstream(Context *ctx, std::string base_config_file, std::string text_config_file)
{
ChipConfig cc;
@@ -450,10 +484,16 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
for (auto pip : ctx->getPips()) {
if (ctx->getBoundPipNet(pip) != nullptr) {
if (ctx->getPipClass(pip) == 0) { // ignore fixed pips
- std::string tile = ctx->getPipTilename(pip);
std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip));
- std::string sink = get_trellis_wirename(ctx, pip.location, ctx->getPipDstWire(pip));
- cc.tiles[tile].add_arc(sink, source);
+ if (source.find("CLKI_PLL") != std::string::npos) {
+ // Special case - must set pip in all relevant tiles
+ for (auto equiv_pip : ctx->getPipsUphill(ctx->getPipDstWire(pip))) {
+ if (ctx->getPipSrcWire(equiv_pip) == ctx->getPipSrcWire(pip))
+ set_pip(ctx, cc, equiv_pip);
+ }
+ } else {
+ set_pip(ctx, cc, pip);
+ }
}
}
}
@@ -624,6 +664,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
if (dir == "INPUT" && !is_differential(ioType_from_str(iotype))) {
cc.tiles[pio_tile].add_enum(pio + ".HYSTERESIS", "ON");
}
+ if (ci->attrs.count(ctx->id("SLEWRATE")))
+ cc.tiles[pio_tile].add_enum(pio + ".SLEWRATE", str_or_default(ci->attrs, ctx->id("SLEWRATE"), "SLOW"));
} else if (ci->type == ctx->id("DCCA")) {
// Nothing to do
} else if (ci->type == ctx->id("DP16KD")) {
@@ -867,7 +909,96 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
}
tieoff_dsp_ports(ctx, cc, ci);
cc.tilegroups.push_back(tg);
+ } else if (ci->type == id_EHXPLLL) {
+ TileGroup tg;
+ tg.tiles = get_pll_tiles(ctx, ci->bel);
+
+ tg.config.add_enum("MODE", "EHXPLLL");
+
+ tg.config.add_word("CLKI_DIV", int_to_bitvector(int_or_default(ci->params, ctx->id("CLKI_DIV"), 1) - 1, 7));
+ tg.config.add_word("CLKFB_DIV",
+ int_to_bitvector(int_or_default(ci->params, ctx->id("CLKFB_DIV"), 1) - 1, 7));
+
+ tg.config.add_enum("CLKOP_ENABLE", str_or_default(ci->params, ctx->id("CLKOP_ENABLE"), "ENABLED"));
+ tg.config.add_enum("CLKOS_ENABLE", str_or_default(ci->params, ctx->id("CLKOS_ENABLE"), "ENABLED"));
+ tg.config.add_enum("CLKOS2_ENABLE", str_or_default(ci->params, ctx->id("CLKOS2_ENABLE"), "ENABLED"));
+ tg.config.add_enum("CLKOS3_ENABLE", str_or_default(ci->params, ctx->id("CLKOS3_ENABLE"), "ENABLED"));
+
+ for (std::string out : {"CLKOP", "CLKOS", "CLKOS2", "CLKOS3"}) {
+ tg.config.add_word(out + "_DIV",
+ int_to_bitvector(int_or_default(ci->params, ctx->id(out + "_DIV"), 8) - 1, 7));
+ tg.config.add_word(out + "_CPHASE",
+ int_to_bitvector(int_or_default(ci->params, ctx->id(out + "_CPHASE"), 0), 7));
+ tg.config.add_word(out + "_FPHASE",
+ int_to_bitvector(int_or_default(ci->params, ctx->id(out + "_FPHASE"), 0), 3));
+ }
+ tg.config.add_enum("FEEDBK_PATH", str_or_default(ci->params, ctx->id("FEEDBK_PATH"), "CLKOP"));
+ tg.config.add_enum("CLKOP_TRIM_POL", str_or_default(ci->params, ctx->id("CLKOP_TRIM_POL"), "RISING"));
+ tg.config.add_enum("CLKOP_TRIM_DELAY", str_or_default(ci->params, ctx->id("CLKOP_TRIM_DELAY"), "0"));
+ tg.config.add_enum("CLKOS_TRIM_POL", str_or_default(ci->params, ctx->id("CLKOS_TRIM_POL"), "RISING"));
+ tg.config.add_enum("CLKOS_TRIM_DELAY", str_or_default(ci->params, ctx->id("CLKOS_TRIM_DELAY"), "0"));
+
+ tg.config.add_enum("OUTDIVIDER_MUXA", str_or_default(ci->params, ctx->id("OUTDIVIDER_MUXA"),
+ get_net_or_empty(ci, id_CLKOP) ? "DIVA" : "REFCLK"));
+ tg.config.add_enum("OUTDIVIDER_MUXB", str_or_default(ci->params, ctx->id("OUTDIVIDER_MUXB"),
+ get_net_or_empty(ci, id_CLKOP) ? "DIVB" : "REFCLK"));
+ tg.config.add_enum("OUTDIVIDER_MUXC", str_or_default(ci->params, ctx->id("OUTDIVIDER_MUXC"),
+ get_net_or_empty(ci, id_CLKOP) ? "DIVC" : "REFCLK"));
+ tg.config.add_enum("OUTDIVIDER_MUXD", str_or_default(ci->params, ctx->id("OUTDIVIDER_MUXD"),
+ get_net_or_empty(ci, id_CLKOP) ? "DIVD" : "REFCLK"));
+
+ tg.config.add_word("PLL_LOCK_MODE",
+ int_to_bitvector(int_or_default(ci->params, ctx->id("PLL_LOCK_MODE"), 0), 3));
+
+ tg.config.add_enum("STDBY_ENABLE", str_or_default(ci->params, ctx->id("STDBY_ENABLE"), "DISABLED"));
+ tg.config.add_enum("REFIN_RESET", str_or_default(ci->params, ctx->id("REFIN_RESET"), "DISABLED"));
+ tg.config.add_enum("SYNC_ENABLE", str_or_default(ci->params, ctx->id("SYNC_ENABLE"), "DISABLED"));
+ tg.config.add_enum("INT_LOCK_STICKY", str_or_default(ci->params, ctx->id("INT_LOCK_STICKY"), "ENABLED"));
+ tg.config.add_enum("DPHASE_SOURCE", str_or_default(ci->params, ctx->id("DPHASE_SOURCE"), "DISABLED"));
+ tg.config.add_enum("PLLRST_ENA", str_or_default(ci->params, ctx->id("PLLRST_ENA"), "DISABLED"));
+ tg.config.add_enum("INTFB_WAKE", str_or_default(ci->params, ctx->id("INTFB_WAKE"), "DISABLED"));
+
+ tg.config.add_word("KVCO", int_to_bitvector(int_or_default(ci->attrs, ctx->id("KVCO"), 0), 3));
+ tg.config.add_word("LPF_CAPACITOR",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("LPF_CAPACITOR"), 0), 2));
+ tg.config.add_word("LPF_RESISTOR",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("LPF_RESISTOR"), 0), 7));
+ tg.config.add_word("ICP_CURRENT",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("ICP_CURRENT"), 0), 5));
+ tg.config.add_word("FREQ_LOCK_ACCURACY",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("FREQ_LOCK_ACCURACY"), 0), 2));
+
+ tg.config.add_word("MFG_GMC_GAIN",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMC_GAIN"), 0), 3));
+ tg.config.add_word("MFG_GMC_TEST",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMC_TEST"), 14), 4));
+ tg.config.add_word("MFG1_TEST", int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG1_TEST"), 0), 3));
+ tg.config.add_word("MFG2_TEST", int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG2_TEST"), 0), 3));
+
+ tg.config.add_word("MFG_FORCE_VFILTER",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_FORCE_VFILTER"), 0), 1));
+ tg.config.add_word("MFG_ICP_TEST",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_ICP_TEST"), 0), 1));
+ tg.config.add_word("MFG_EN_UP", int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_EN_UP"), 0), 1));
+ tg.config.add_word("MFG_FLOAT_ICP",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_FLOAT_ICP"), 0), 1));
+ tg.config.add_word("MFG_GMC_PRESET",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMC_PRESET"), 0), 1));
+ tg.config.add_word("MFG_LF_PRESET",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_LF_PRESET"), 0), 1));
+ tg.config.add_word("MFG_GMC_RESET",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMC_RESET"), 0), 1));
+ tg.config.add_word("MFG_LF_RESET",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_LF_RESET"), 0), 1));
+ tg.config.add_word("MFG_LF_RESGRND",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_LF_RESGRND"), 0), 1));
+ tg.config.add_word("MFG_GMCREF_SEL",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMCREF_SEL"), 0), 2));
+ tg.config.add_word("MFG_ENABLE_FILTEROPAMP",
+ int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_ENABLE_FILTEROPAMP"), 0), 1));
+
+ cc.tilegroups.push_back(tg);
} else {
NPNR_ASSERT_FALSE("unsupported cell type");
}
diff --git a/ecp5/cells.cc b/ecp5/cells.cc
index a728104d..31839ee4 100644
--- a/ecp5/cells.cc
+++ b/ecp5/cells.cc
@@ -343,4 +343,46 @@ void dram_to_ram_slice(Context *ctx, CellInfo *ram, CellInfo *lc, CellInfo *ramw
}
}
+void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::unique_ptr<CellInfo>> &created_cells,
+ std::unordered_set<IdString> &todelete_cells)
+{
+ if (nxio->type == ctx->id("$nextpnr_ibuf")) {
+ trio->params[ctx->id("DIR")] = "INPUT";
+ replace_port(nxio, ctx->id("O"), trio, ctx->id("O"));
+ } else if (nxio->type == ctx->id("$nextpnr_obuf")) {
+ trio->params[ctx->id("DIR")] = "OUTPUT";
+ replace_port(nxio, ctx->id("I"), trio, ctx->id("I"));
+ } else if (nxio->type == ctx->id("$nextpnr_iobuf")) {
+ // N.B. tristate will be dealt with below
+ trio->params[ctx->id("DIR")] = "BIDIR";
+ replace_port(nxio, ctx->id("I"), trio, ctx->id("I"));
+ replace_port(nxio, ctx->id("O"), trio, ctx->id("O"));
+ } else {
+ NPNR_ASSERT(false);
+ }
+ NetInfo *donet = trio->ports.at(ctx->id("I")).net;
+ CellInfo *tbuf = net_driven_by(
+ ctx, donet, [](const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("$_TBUF_"); },
+ ctx->id("Y"));
+ if (tbuf) {
+ replace_port(tbuf, ctx->id("I"), trio, ctx->id("I"));
+ // Need to invert E to form T
+ std::unique_ptr<CellInfo> inv_lut = create_ecp5_cell(ctx, ctx->id("LUT4"), trio->name.str(ctx) + "$invert_T");
+ replace_port(tbuf, ctx->id("E"), inv_lut.get(), ctx->id("A"));
+ inv_lut->params[ctx->id("INIT")] = "21845";
+ connect_ports(ctx, inv_lut.get(), ctx->id("Z"), trio, ctx->id("T"));
+ created_cells.push_back(std::move(inv_lut));
+
+ if (donet->users.size() > 1) {
+ for (auto user : donet->users)
+ log_info(" remaining tristate user: %s.%s\n", user.cell->name.c_str(ctx), user.port.c_str(ctx));
+ log_error("unsupported tristate IO pattern for IO buffer '%s', "
+ "instantiate SB_IO manually to ensure correct behaviour\n",
+ nxio->name.c_str(ctx));
+ }
+ ctx->nets.erase(donet->name);
+ todelete_cells.insert(tbuf->name);
+ }
+}
+
NEXTPNR_NAMESPACE_END
diff --git a/ecp5/cells.h b/ecp5/cells.h
index a5229fe0..9c2ff3cf 100644
--- a/ecp5/cells.h
+++ b/ecp5/cells.h
@@ -52,6 +52,10 @@ void ccu2c_to_slice(Context *ctx, CellInfo *ccu, CellInfo *lc);
void dram_to_ramw(Context *ctx, CellInfo *ram, CellInfo *lc);
void dram_to_ram_slice(Context *ctx, CellInfo *ram, CellInfo *lc, CellInfo *ramw, int index);
+// Convert a nextpnr IO buffer to a TRELLIS_IO
+void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::unique_ptr<CellInfo>> &created_cells,
+ std::unordered_set<IdString> &todelete_cells);
+
NEXTPNR_NAMESPACE_END
#endif
diff --git a/ecp5/constids.inc b/ecp5/constids.inc
index e3bfec6e..bdcbc1ea 100644
--- a/ecp5/constids.inc
+++ b/ecp5/constids.inc
@@ -787,3 +787,26 @@ X(OVER)
X(UNDER)
X(OVERUNDER)
X(SIGNEDR)
+
+X(EHXPLLL)
+X(CLKFB)
+X(PHASESEL1)
+X(PHASESEL0)
+X(PHASEDIR)
+X(PHASESTEP)
+X(PHASELOADREG)
+X(STDBY)
+X(PLLWAKESYNC)
+X(RST)
+X(ENCLKOP)
+X(ENCLKOS)
+X(ENCLKOS2)
+X(ENCLKOS3)
+X(CLKOP)
+X(CLKOS)
+X(CLKOS2)
+X(CLKOS3)
+X(LOCK)
+X(INTLOCK)
+X(REFCLK)
+X(CLKINTFB)
diff --git a/ecp5/globals.cc b/ecp5/globals.cc
index 5e5a2a01..06412fef 100644
--- a/ecp5/globals.cc
+++ b/ecp5/globals.cc
@@ -25,6 +25,7 @@
#include "log.h"
#include "nextpnr.h"
#include "place_common.h"
+#include "util.h"
#define fmt_str(x) (static_cast<const std::ostringstream &>(std::ostringstream() << x).str())
NEXTPNR_NAMESPACE_BEGIN
@@ -257,6 +258,45 @@ class Ecp5GlobalRouter
return true;
}
+ // Get DCC wirelength based on source
+ wirelen_t get_dcc_wirelen(CellInfo *dcc)
+ {
+ NetInfo *clki = dcc->ports.at(id_CLKI).net;
+ BelId drv_bel;
+ const PortRef &drv = clki->driver;
+ if (drv.cell == nullptr) {
+ return 0;
+ } else if (drv.cell->attrs.count(ctx->id("BEL"))) {
+ drv_bel = ctx->getBelByName(ctx->id(drv.cell->attrs.at(ctx->id("BEL"))));
+ } else {
+ // Check if driver is a singleton
+ BelId last_bel;
+ bool singleton = true;
+ for (auto bel : ctx->getBels()) {
+ if (ctx->getBelType(bel) == drv.cell->type) {
+ if (last_bel != BelId()) {
+ singleton = false;
+ break;
+ }
+ last_bel = bel;
+ }
+ }
+ if (singleton && last_bel != BelId()) {
+ drv_bel = last_bel;
+ }
+ }
+ if (drv_bel == BelId()) {
+ // Driver is not locked. Use standard metric
+ float tns;
+ return get_net_metric(ctx, clki, MetricType::WIRELENGTH, tns);
+ } else {
+ // Driver is locked
+ Loc dcc_loc = ctx->getBelLocation(dcc->bel);
+ Loc drv_loc = ctx->getBelLocation(drv_bel);
+ return std::abs(dcc_loc.x - drv_loc.x) + std::abs(dcc_loc.y - drv_loc.y);
+ }
+ }
+
// Attempt to place a DCC
void place_dcc(CellInfo *dcc)
{
@@ -266,8 +306,7 @@ class Ecp5GlobalRouter
if (ctx->getBelType(bel) == id_DCCA && ctx->checkBelAvail(bel)) {
if (ctx->isValidBelForCell(dcc, bel)) {
ctx->bindBel(bel, dcc, STRENGTH_LOCKED);
- float tns;
- wirelen_t wirelen = get_net_metric(ctx, dcc->ports.at(id_CLKI).net, MetricType::WIRELENGTH, tns);
+ wirelen_t wirelen = get_dcc_wirelen(dcc);
if (wirelen < best_wirelen) {
best_bel = bel;
best_wirelen = wirelen;
@@ -292,11 +331,16 @@ class Ecp5GlobalRouter
glbnet->is_global = true;
dcc->ports[id_CLKO].net = glbnet.get();
- glbnet->users = net->users;
+ std::vector<PortRef> keep_users;
for (auto user : net->users) {
- user.cell->ports.at(user.port).net = glbnet.get();
+ if (user.port == id_CLKFB) {
+ keep_users.push_back(user);
+ } else {
+ glbnet->users.push_back(user);
+ user.cell->ports.at(user.port).net = glbnet.get();
+ }
}
- net->users.clear();
+ net->users = keep_users;
dcc->ports[id_CLKI].net = net;
PortRef clki_pr;
@@ -322,47 +366,61 @@ class Ecp5GlobalRouter
Context *ctx;
public:
- void promote_and_route_globals()
+ void promote_globals()
{
- log_info("Promoting and routing globals...\n");
+ log_info("Promoting globals...\n");
auto clocks = get_clocks();
+ for (auto clock : clocks) {
+ log_info(" promoting clock net %s to global network\n", clock->name.c_str(ctx));
+ insert_dcc(clock);
+ }
+ }
+
+ void route_globals()
+ {
+ log_info("Routing globals...\n");
std::set<int> all_globals, fab_globals;
for (int i = 0; i < 16; i++) {
all_globals.insert(i);
if (i < 8)
fab_globals.insert(i);
}
- for (auto clock : clocks) {
- bool drives_fabric = std::any_of(clock->users.begin(), clock->users.end(),
- [this](const PortRef &port) { return !is_clock_port(port); });
- int glbid;
- if (drives_fabric) {
- if (fab_globals.empty())
- continue;
- glbid = *(fab_globals.begin());
- } else {
- glbid = *(all_globals.begin());
- }
- all_globals.erase(glbid);
- fab_globals.erase(glbid);
- log_info(" promoting clock net %s to global %d\n", clock->name.c_str(ctx), glbid);
- auto old_users = clock->users;
- NetInfo *global = insert_dcc(clock);
- bool routed = route_onto_global(global, glbid);
- NPNR_ASSERT(routed);
-
- // WCK must have routing priority
- auto sorted_users = global->users;
- std::sort(sorted_users.begin(), sorted_users.end(), [this](const PortRef &a, const PortRef &b) {
- return global_route_priority(a) < global_route_priority(b);
- });
- for (const auto &user : sorted_users) {
- route_logic_tile_global(global, glbid, user);
+ for (auto cell : sorted(ctx->cells)) {
+ CellInfo *ci = cell.second;
+ if (ci->type == id_DCCA) {
+ NetInfo *clock = ci->ports.at(id_CLKO).net;
+ NPNR_ASSERT(clock != nullptr);
+ bool drives_fabric = std::any_of(clock->users.begin(), clock->users.end(),
+ [this](const PortRef &port) { return !is_clock_port(port); });
+
+ int glbid;
+ if (drives_fabric) {
+ if (fab_globals.empty())
+ continue;
+ glbid = *(fab_globals.begin());
+ } else {
+ glbid = *(all_globals.begin());
+ }
+ all_globals.erase(glbid);
+ fab_globals.erase(glbid);
+
+ log_info(" routing clock net %s using global %d\n", clock->name.c_str(ctx), glbid);
+ bool routed = route_onto_global(clock, glbid);
+ NPNR_ASSERT(routed);
+
+ // WCK must have routing priority
+ auto sorted_users = clock->users;
+ std::sort(sorted_users.begin(), sorted_users.end(), [this](const PortRef &a, const PortRef &b) {
+ return global_route_priority(a) < global_route_priority(b);
+ });
+ for (const auto &user : sorted_users) {
+ route_logic_tile_global(clock, glbid, user);
+ }
}
}
}
};
-
-void route_ecp5_globals(Context *ctx) { Ecp5GlobalRouter(ctx).promote_and_route_globals(); }
+void promote_ecp5_globals(Context *ctx) { Ecp5GlobalRouter(ctx).promote_globals(); }
+void route_ecp5_globals(Context *ctx) { Ecp5GlobalRouter(ctx).route_globals(); }
NEXTPNR_NAMESPACE_END
diff --git a/ecp5/globals.h b/ecp5/globals.h
index 23e25c8d..cc7cf98e 100644
--- a/ecp5/globals.h
+++ b/ecp5/globals.h
@@ -21,6 +21,7 @@
NEXTPNR_NAMESPACE_BEGIN
+void promote_ecp5_globals(Context *ctx);
void route_ecp5_globals(Context *ctx);
NEXTPNR_NAMESPACE_END \ No newline at end of file
diff --git a/ecp5/lpf.cc b/ecp5/lpf.cc
new file mode 100644
index 00000000..4bde660e
--- /dev/null
+++ b/ecp5/lpf.cc
@@ -0,0 +1,106 @@
+/*
+ * nextpnr -- Next Generation Place and Route
+ *
+ * Copyright (C) 2018 David Shah <david@symbioticeda.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <sstream>
+#include "log.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+bool Arch::applyLPF(std::string filename, std::istream &in)
+{
+ auto isempty = [](const std::string &str) {
+ return std::all_of(str.begin(), str.end(), [](char c) { return isblank(c); });
+ };
+ auto strip_quotes = [](const std::string &str) {
+ if (str.at(0) == '"') {
+ NPNR_ASSERT(str.back() == '"');
+ return str.substr(1, str.size() - 2);
+ } else {
+ return str;
+ }
+ };
+
+ try {
+ if (!in)
+ log_error("failed to open LPF file\n");
+ std::string line;
+ std::string linebuf;
+ while (std::getline(in, line)) {
+ size_t cstart = line.find('#');
+ if (cstart != std::string::npos)
+ line = line.substr(0, cstart);
+ if (isempty(line))
+ continue;
+ linebuf += line;
+ // Look for a command up to a semicolon
+ size_t scpos = linebuf.find(';');
+ while (scpos != std::string::npos) {
+ std::string command = linebuf.substr(0, scpos);
+ // Split command into words
+ std::stringstream ss(command);
+ std::vector<std::string> words;
+ std::string tmp;
+ while (ss >> tmp)
+ words.push_back(tmp);
+ if (words.size() >= 0) {
+ std::string verb = words.at(0);
+ if (verb == "BLOCK" || verb == "SYSCONFIG" || verb == "FREQUENCY") {
+ log_warning(" ignoring unsupported LPF command '%s'\n", command.c_str());
+ } else if (verb == "LOCATE") {
+ NPNR_ASSERT(words.at(1) == "COMP");
+ std::string cell = strip_quotes(words.at(2));
+ NPNR_ASSERT(words.at(3) == "SITE");
+ auto fnd_cell = cells.find(id(cell));
+ if (fnd_cell == cells.end()) {
+ log_warning("unmatched LPF 'LOCATE COMP' '%s'\n", cell.c_str());
+ } else {
+ fnd_cell->second->attrs[id("LOC")] = strip_quotes(words.at(4));
+ }
+ } else if (verb == "IOBUF") {
+ NPNR_ASSERT(words.at(1) == "PORT");
+ std::string cell = strip_quotes(words.at(2));
+ auto fnd_cell = cells.find(id(cell));
+ if (fnd_cell == cells.end()) {
+ log_warning("unmatched LPF 'IOBUF PORT' '%s'\n", cell.c_str());
+ } else {
+ for (size_t i = 3; i < words.size(); i++) {
+ std::string setting = words.at(i);
+ size_t eqpos = setting.find('=');
+ NPNR_ASSERT(eqpos != std::string::npos);
+ std::string key = setting.substr(0, eqpos), value = setting.substr(eqpos + 1);
+ fnd_cell->second->attrs[id(key)] = value;
+ }
+ }
+ }
+ }
+
+ linebuf = linebuf.substr(scpos + 1);
+ scpos = linebuf.find(';');
+ }
+ }
+ if (!isempty(linebuf))
+ log_error("unexpected end of LPF file\n");
+ settings.emplace(id("input/lpf"), filename);
+ return true;
+ } catch (log_execution_error_exception) {
+ return false;
+ }
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/ecp5/main.cc b/ecp5/main.cc
index e71b0983..c444f96f 100644
--- a/ecp5/main.cc
+++ b/ecp5/main.cc
@@ -35,6 +35,7 @@ class ECP5CommandHandler : public CommandHandler
virtual ~ECP5CommandHandler(){};
std::unique_ptr<Context> createContext() override;
void setupArchContext(Context *ctx) override{};
+ void customAfterLoad(Context *ctx) override;
void validate() override;
void customBitstream(Context *ctx) override;
@@ -56,9 +57,13 @@ po::options_description ECP5CommandHandler::getArchOptions()
specific.add_options()("um5g-25k", "set device type to LFE5UM5G-25F");
specific.add_options()("um5g-45k", "set device type to LFE5UM5G-45F");
specific.add_options()("um5g-85k", "set device type to LFE5UM5G-85F");
+
specific.add_options()("package", po::value<std::string>(), "select device package (defaults to CABGA381)");
specific.add_options()("basecfg", po::value<std::string>(), "base chip configuration in Trellis text format");
specific.add_options()("textcfg", po::value<std::string>(), "textual configuration in Trellis format to write");
+
+ specific.add_options()("lpf", po::value<std::vector<std::string>>(), "LPF pin constraint file(s)");
+
return specific;
}
void ECP5CommandHandler::validate()
@@ -111,6 +116,17 @@ std::unique_ptr<Context> ECP5CommandHandler::createContext()
return std::unique_ptr<Context>(new Context(chipArgs));
}
+void ECP5CommandHandler::customAfterLoad(Context *ctx)
+{
+ if (vm.count("lpf")) {
+ std::vector<std::string> files = vm["lpf"].as<std::vector<std::string>>();
+ for (const auto &filename : files) {
+ std::ifstream in(filename);
+ ctx->applyLPF(filename, in);
+ }
+ }
+}
+
int main(int argc, char *argv[])
{
ECP5CommandHandler handler(argc, argv);
diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index 18debb74..73e15609 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -24,6 +24,7 @@
#include "cells.h"
#include "chain_utils.h"
#include "design_utils.h"
+#include "globals.h"
#include "log.h"
#include "util.h"
NEXTPNR_NAMESPACE_BEGIN
@@ -266,11 +267,17 @@ class Ecp5Packer
}
}
} else {
- log_error("TRELLIS_IO required on all top level IOs...\n");
+ // Create a TRELLIS_IO buffer
+ std::unique_ptr<CellInfo> tr_cell =
+ create_ecp5_cell(ctx, ctx->id("TRELLIS_IO"), ci->name.str(ctx) + "$tr_io");
+ nxio_to_tr(ctx, ci, tr_cell.get(), new_cells, packed_cells);
+ new_cells.push_back(std::move(tr_cell));
+ trio = new_cells.back().get();
}
packed_cells.insert(ci->name);
- std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(trio->attrs, trio->attrs.begin()));
+ for (const auto &attr : ci->attrs)
+ trio->attrs[attr.first] = attr.second;
auto loc_attr = trio->attrs.find(ctx->id("LOC"));
if (loc_attr != trio->attrs.end()) {
@@ -1041,6 +1048,7 @@ class Ecp5Packer
pack_lut_pairs();
pack_remaining_luts();
pack_remaining_ffs();
+ promote_ecp5_globals(ctx);
ctx->check();
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-11 17:50:54 +0000