diff options
| -rw-r--r-- | docs/generic.md | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/docs/generic.md b/docs/generic.md index 5ea4804d..5c079a7b 100644 --- a/docs/generic.md +++ b/docs/generic.md @@ -28,9 +28,9 @@ Adds a pip (programmable connection between two named wires). Pip delays that co Loc is constructed using `Loc(x, y, z)`. 'z' for pips is only important if region constraints (e.g. for partial reconfiguration regions) are used. -### void addBel(IdString name, IdString type, Loc loc, bool gb); +### void addBel(IdString name, IdString type, Loc loc, bool gb, bool hidden); -Adds a bel to the FPGA description. Bel type should match the type of cells in the netlist that are placed at this bel (see below for information on special bel types supported by the packer). Loc is constructed using `Loc(x, y, z)` and must be unique. +Adds a bel to the FPGA description. Bel type should match the type of cells in the netlist that are placed at this bel (see below for information on special bel types supported by the packer). Loc is constructed using `Loc(x, y, z)` and must be unique. If `hidden` is true, then the bel will not be included in utilisation reports (e.g. for routing/internal use bels). ### void addBelInput(IdString bel, IdString name, IdString wire); ### void addBelOutput(IdString bel, IdString name, IdString wire); @@ -90,6 +90,14 @@ Specify setup and hold timings for a port of a cell, and set the timing class of Specify clock-to-out time for a port of a cell, and set the timing class of that port as register output. +### void clearCellBelPinMap(IdString cell, IdString cell_pin); + +Remove all bel pin mappings from a given cell pin. + +### addCellBelPinMapping(IdString cell, IdString cell_pin, IdString bel_pin); + +Add a bel pin to the list of bel pins a cell pin maps to. Note that if no mappings are set up (the usual case), cell pins are assumed to map to an identically named bel pin. + ## Generic Packer The generic packer combines K-input LUTs (`LUT` cells) and simple D-type flip flops (`DFF` cells) (posedge clock only, no set/reset or enable) into a `GENERIC_SLICE` cell. It also inserts `GENERIC_IOB`s onto any top level IO pins without an IO buffer. Constrained IOBs can be implemented by instantiating `GENERIC_IOB` and setting the `BEL` attribute to an IO location. |