@@ -640,6 +640,30 @@ struct CriticalPath
typedef dict<ClockPair, CriticalPath> CriticalPathMap;
+struct CriticalPathSegment
+{
+ enum class Type {
+ LOGIC,
+ ROUTING
+ };
+
+ std::pair<CellInfo*,IdString> from;
+ std::pair<CellInfo*,IdString> to;
+ Type type;
+ const NetInfo* net;
+ delay_t delay;
+ delay_t budget;
+};
+typedef std::vector<CriticalPathSegment> CriticalPathSegments;
+
+struct CriticalPathReport
+{
+ ClockPair clock_pair;
+ CriticalPathSegments segments;
+ delay_t period;
+};
+typedef dict<ClockPair, CriticalPathReport> CriticalPathReportMap;
+
struct NetSinkTiming
{
ClockPair clock_pair;
@@ -1141,9 +1165,101 @@ void assign_budget(Context *ctx, bool quiet)
void write_timing_report(
Context* ctx,
const std::string& file_name,
+ const std::map<IdString, CriticalPathReport> clock_reports,
+ const std::vector<CriticalPathReport> xclock_reports,
const DetailedNetTimings& detailed_net_timings
);
+CriticalPathReport build_critical_path_report(Context* ctx, ClockPair &clocks, const PortRefVector &crit_path) {
+
+ CriticalPathReport report;
+ report.clock_pair = clocks;
+
+ auto &front = crit_path.front();
+ auto &front_port = front->cell->ports.at(front->port);
+ auto &front_driver = front_port.net->driver;
+
+ int port_clocks;
+ auto portClass = ctx->getPortTimingClass(front_driver.cell, front_driver.port, port_clocks);
+
+ const CellInfo* last_cell = front->cell;
+ IdString last_port = front_driver.port;
+
+ int clock_start = -1;
+ if (portClass == TMG_REGISTER_OUTPUT) {
+ for (int i = 0; i < port_clocks; i++) {
+ TimingClockingInfo clockInfo = ctx->getPortClockingInfo(front_driver.cell, front_driver.port, i);
+ const NetInfo *clknet = get_net_or_empty(front_driver.cell, clockInfo.clock_port);
+ if (clknet != nullptr && clknet->name == clocks.start.clock &&
+ clockInfo.edge == clocks.start.edge) {
+ last_port = clockInfo.clock_port;
+ clock_start = i;
+ break;
+ }
+ }
+ }
+
+ for (auto sink : crit_path) {
+ auto sink_cell = sink->cell;
+ auto &port = sink_cell->ports.at(sink->port);
+ auto net = port.net;
+ auto &driver = net->driver;
+ auto driver_cell = driver.cell;
+ DelayQuad comb_delay;
+ if (clock_start != -1) {
+ auto clockInfo = ctx->getPortClockingInfo(driver_cell, driver.port, clock_start);
+ comb_delay = clockInfo.clockToQ;
+ clock_start = -1;
+ } else if (last_port == driver.port) {
+ // Case where we start with a STARTPOINT etc
+ comb_delay = DelayQuad(0);
+ } else {
+ ctx->getCellDelay(driver_cell, last_port, driver.port, comb_delay);
+ }
+
+ CriticalPathSegment seg_logic;
+ seg_logic.type = CriticalPathSegment::Type::LOGIC;
+ seg_logic.delay = comb_delay.maxDelay();
+ seg_logic.budget = 0;
+ seg_logic.from = std::make_pair(const_cast<CellInfo*>(last_cell), last_port);
+ seg_logic.to = std::make_pair(driver_cell, driver.port);
+ seg_logic.net = nullptr;
+ report.segments.push_back(seg_logic);
+
+ auto net_delay = ctx->getNetinfoRouteDelay(net, *sink);
+
+ CriticalPathSegment seg_route;
+ seg_route.type = CriticalPathSegment::Type::ROUTING;
+ seg_route.delay = net_delay;
+ seg_route.budget = sink->budget;
+ seg_route.from = std::make_pair(driver_cell, driver.port);
+ seg_route.to = std::make_pair(sink_cell, sink->port);
+ seg_route.net = net;
+ report.segments.push_back(seg_route);
+
+ last_cell = sink_cell;
+ last_port = sink->port;
+ }
+
+ int clockCount = 0;
+ auto sinkClass = ctx->getPortTimingClass(crit_path.back()->cell, crit_path.back()->port, clockCount);
+ if (sinkClass == TMG_REGISTER_INPUT && clockCount > 0) {
+ auto sinkClockInfo = ctx->getPortClockingInfo(crit_path.back()->cell, crit_path.back()->port, 0);
+ delay_t setup = sinkClockInfo.setup.maxDelay();
+
+ CriticalPathSegment seg_logic;
+ seg_logic.type = CriticalPathSegment::Type::LOGIC;
+ seg_logic.delay = setup;
+ seg_logic.budget = 0;
+ seg_logic.from = std::make_pair(nullptr, IdString());
+ seg_logic.to = std::make_pair(const_cast<CellInfo*>(last_cell), last_port);
+ seg_logic.net = nullptr;
+ report.segments.push_back(seg_logic);
+ }
+
+ return report;
+}
+
void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool print_path, bool warn_on_failure, bool write_report)
{
auto format_event = [ctx](const ClockEvent &e, int field_width = 0) {
@@ -1164,11 +1280,17 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
Timing timing(ctx, true /* net_delays */, false /* update */, (print_path || print_fmax) ? &crit_paths : nullptr,
print_histogram ? &slack_histogram : nullptr, write_report ? &detailed_net_timings : nullptr);
timing.walk_paths();
- std::map<IdString, std::pair<ClockPair, CriticalPath>> clock_reports;
+
+ bool report_critical_paths = print_path || print_fmax || write_report;
+
+ std::map<IdString, CriticalPathReport> clock_reports;
+ std::vector<CriticalPathReport> xclock_reports;
+
std::map<IdString, double> clock_fmax;
- std::vector<ClockPair> xclock_paths;
std::set<IdString> empty_clocks; // set of clocks with no interior paths
- if (print_path || print_fmax) {
