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-rw-r--r--.cirrus.yml1
-rw-r--r--.cirrus/Dockerfile.ubuntu16.044
-rw-r--r--common/command.cc5
-rw-r--r--common/design_utils.cc4
-rw-r--r--common/timing.cc13
-rw-r--r--ecp5/arch.cc161
-rw-r--r--ecp5/arch.h10
-rw-r--r--ecp5/arch_place.cc74
-rw-r--r--ecp5/archdefs.h2
-rw-r--r--ecp5/bitstream.cc144
-rw-r--r--ecp5/cells.cc3
-rw-r--r--ecp5/cells.h11
-rw-r--r--ecp5/constids.inc2
-rw-r--r--ecp5/docs/primitives.md47
-rw-r--r--ecp5/globals.cc19
-rw-r--r--ecp5/lpf.cc63
-rw-r--r--ecp5/main.cc23
-rw-r--r--ecp5/pack.cc854
-rwxr-xr-xecp5/trellis_import.py27
-rw-r--r--gui/fpgaviewwidget.cc21
-rw-r--r--ice40/arch.cc16
-rw-r--r--ice40/arch.h5
-rw-r--r--ice40/arch_pybindings.cc1
-rw-r--r--ice40/bitstream.cc12
-rw-r--r--ice40/chipdb.py23
-rw-r--r--ice40/constids.inc6
-rw-r--r--ice40/delay.cc2
-rw-r--r--ice40/family.cmake16
-rw-r--r--ice40/main.cc8
-rw-r--r--ice40/project.cc3
-rw-r--r--ice40/resource/chipdb.rc1
-rw-r--r--ice40/resource/embed.cc4
-rw-r--r--ice40/resource/resource.h1
m---------tests0
34 files changed, 1498 insertions, 88 deletions
diff --git a/.cirrus.yml b/.cirrus.yml
index 2347b502..c97b521c 100644
--- a/.cirrus.yml
+++ b/.cirrus.yml
@@ -12,3 +12,4 @@ task:
smoketest_ice40_script: export NEXTPNR=$(pwd)/build/nextpnr-ice40 && cd ice40/smoketest/attosoc && ./smoketest.sh
test_ecp5_script: cd build && ./nextpnr-ecp5-test
regressiontest_ice40_script: make -j $(nproc) -C tests/ice40/regressions NPNR=$(pwd)/build/nextpnr-ice40
+ regressiontest_ecp5_script: make -j $(nproc) -C tests/ecp5/regressions NPNR=$(pwd)/build/nextpnr-ecp5
diff --git a/.cirrus/Dockerfile.ubuntu16.04 b/.cirrus/Dockerfile.ubuntu16.04
index fb140d8d..1b93cfb8 100644
--- a/.cirrus/Dockerfile.ubuntu16.04
+++ b/.cirrus/Dockerfile.ubuntu16.04
@@ -27,7 +27,7 @@ RUN set -e -x ;\
cd /usr/local/src ;\
git clone --recursive https://github.com/cliffordwolf/icestorm.git ;\
cd icestorm ;\
- git reset --hard 9671b760f84ca4006f0ef101a3e3b201df4eabb5 ;\
+ git reset --hard 3a2bfee5cbc0558641668114260d3f644d6b7c83 ;\
make -j $(nproc) ;\
make install
@@ -51,5 +51,3 @@ RUN set -e -x ;\
cmake -DCMAKE_INSTALL_PREFIX=/usr . ;\
make -j $(nproc) ;\
make install
-
-
diff --git a/common/command.cc b/common/command.cc
index 8f18f54d..1399efdb 100644
--- a/common/command.cc
+++ b/common/command.cc
@@ -129,6 +129,7 @@ po::options_description CommandHandler::getGeneralOptions()
general.add_options()("version,V", "show version");
general.add_options()("test", "check architecture database integrity");
general.add_options()("freq", po::value<double>(), "set target frequency for design in MHz");
+ general.add_options()("timing-allow-fail", "allow timing to fail in design");
general.add_options()("no-tmdriv", "disable timing-driven placement");
general.add_options()("save", po::value<std::string>(), "project file to write");
general.add_options()("load", po::value<std::string>(), "project file to read");
@@ -178,6 +179,10 @@ void CommandHandler::setupContext(Context *ctx)
settings->set("timing/ignoreLoops", true);
}
+ if (vm.count("timing-allow-fail")) {
+ settings->set("timing/allowFail", true);
+ }
+
if (vm.count("cstrweight")) {
settings->set("placer1/constraintWeight", vm["cstrweight"].as<float>());
}
diff --git a/common/design_utils.cc b/common/design_utils.cc
index a0b87764..da170030 100644
--- a/common/design_utils.cc
+++ b/common/design_utils.cc
@@ -27,6 +27,8 @@ NEXTPNR_NAMESPACE_BEGIN
void replace_port(CellInfo *old_cell, IdString old_name, CellInfo *rep_cell, IdString rep_name)
{
+ if (!old_cell->ports.count(old_name))
+ return;
PortInfo &old = old_cell->ports.at(old_name);
PortInfo &rep = rep_cell->ports.at(rep_name);
NPNR_ASSERT(old.type == rep.type);
@@ -107,6 +109,8 @@ void disconnect_port(const Context *ctx, CellInfo *cell, IdString port_name)
return user.cell == cell && user.port == port_name;
}),
port.net->users.end());
+ if (port.net->driver.cell == cell && port.net->driver.port == port_name)
+ port.net->driver.cell = nullptr;
}
}
diff --git a/common/timing.cc b/common/timing.cc
index 64dcdf71..2a0af874 100644
--- a/common/timing.cc
+++ b/common/timing.cc
@@ -611,8 +611,9 @@ struct Timing
continue;
delay_t dmax = crit_path->at(ClockPair{startdomain.first, startdomain.first}).path_delay;
for (size_t i = 0; i < net->users.size(); i++) {
- float criticality = 1.0f - (float(nc.slack.at(i) - worst_slack.at(startdomain.first)) / dmax);
- nc.criticality.at(i) = criticality;
+ float criticality =
+ 1.0f - ((float(nc.slack.at(i)) - float(worst_slack.at(startdomain.first))) / dmax);
+ nc.criticality.at(i) = std::min<double>(1.0, std::max<double>(0.0, criticality));
}
nc.max_path_length = nd.max_path_length;
nc.cd_worst_slack = worst_slack.at(startdomain.first);
@@ -837,6 +838,10 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
auto cursor = sink_wire;
delay_t delay;
while (driver_wire != cursor) {
+#ifdef ARCH_ECP5
+ if (net->is_global)
+ break;
+#endif
auto it = net->wires.find(cursor);
assert(it != net->wires.end());
auto pip = it->second.pip;
@@ -900,6 +905,10 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
log_info("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
clock_name.c_str(), clock_fmax[clock.first], passed ? "PASS" : "FAIL", target);
else
+ if (bool_or_default(ctx->settings, ctx->id("timing/allowFail"), false))
+ log_warning("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
+ clock_name.c_str(), clock_fmax[clock.first], passed ? "PASS" : "FAIL", target);
+ else
log_nonfatal_error("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
clock_name.c_str(), clock_fmax[clock.first], passed ? "PASS" : "FAIL", target);
}
diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index 23cdea3b..da0f7b1a 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -427,44 +427,90 @@ BelId Arch::getBelByLocation(Loc loc) const
delay_t Arch::estimateDelay(WireId src, WireId dst) const
{
- auto est_location = [&](WireId w) -> std::pair<int16_t, int16_t> {
- if (w.location.x == 0 && w.location.y == 0) {
- // Global wires
- const auto &wire = locInfo(w)->wire_data[w.index];
- // Use location of first downhill bel or pip, if available
- if (wire.num_bel_pins > 0) {
- return std::make_pair(wire.bel_pins[0].rel_bel_loc.x, wire.bel_pins[0].rel_bel_loc.y);
- } else if (wire.num_downhill > 0) {
- return std::make_pair(wire.pips_downhill[0].rel_loc.x, wire.pips_downhill[0].rel_loc.y);
- } else if (wire.num_uphill > 0) {
- return std::make_pair(wire.pips_uphill[0].rel_loc.x, wire.pips_uphill[0].rel_loc.y);
- } else {
- return std::make_pair<int16_t, int16_t>(0, 0);
- }
+ WireId cursor = dst;
+
+ int num_uh = locInfo(dst)->wire_data[dst.index].num_uphill;
+ if (num_uh < 6) {
+ for (auto uh : getPipsUphill(dst)) {
+ if (getPipSrcWire(uh) == src)
+ return getPipDelay(uh).maxDelay();
+ }
+ }
+
+ auto est_location = [&](WireId w) -> std::pair<int, int> {
+ const auto &wire = locInfo(w)->wire_data[w.index];
+ if (wire.num_bel_pins > 0) {
+ return std::make_pair(w.location.x + wire.bel_pins[0].rel_bel_loc.x,
+ w.location.y + wire.bel_pins[0].rel_bel_loc.y);
+ } else if (wire.num_downhill > 0) {
+ return std::make_pair(w.location.x + wire.pips_downhill[0].rel_loc.x,
+ w.location.y + wire.pips_downhill[0].rel_loc.y);
+ } else if (wire.num_uphill > 0) {
+ return std::make_pair(w.location.x + wire.pips_uphill[0].rel_loc.x,
+ w.location.y + wire.pips_uphill[0].rel_loc.y);
} else {
- return std::make_pair(w.location.x, w.location.y);
+ return std::make_pair(int(w.location.x), int(w.location.y));
}
};
auto src_loc = est_location(src), dst_loc = est_location(dst);
- return (240 - 20 * args.speed) * (abs(src_loc.first - dst_loc.first) + abs(src_loc.second - dst_loc.second));
+ int dx = abs(src_loc.first - dst_loc.first), dy = abs(src_loc.second - dst_loc.second);
+ return (130 - 25 * args.speed) *
+ (6 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5)));
}
delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
{
const auto &driver = net_info->driver;
+ if ((driver.port == id_FCO && sink.port == id_FCI) || sink.port == id_FXA || sink.port == id_FXB)
+ return 0;
auto driver_loc = getBelLocation(driver.cell->bel);
auto sink_loc = getBelLocation(sink.cell->bel);
- return (240 - 20 * args.speed) * (abs(driver_loc.x - sink_loc.x) + abs(driver_loc.y - sink_loc.y));
+ // Encourage use of direct interconnect
+ if (driver_loc.x == sink_loc.x && driver_loc.y == sink_loc.y) {
+ if ((sink.port == id_A0 || sink.port == id_A1) && (driver.port == id_F1) &&
+ (driver_loc.z == 2 || driver_loc.z == 3))
+ return 0;
+ if ((sink.port == id_B0 || sink.port == id_B1) && (driver.port == id_F1) &&
+ (driver_loc.z == 0 || driver_loc.z == 1))
+ return 0;
+ if ((sink.port == id_C0 || sink.port == id_C1) && (driver.port == id_F0) &&
+ (driver_loc.z == 2 || driver_loc.z == 3))
+ return 0;
+ if ((sink.port == id_D0 || sink.port == id_D1) && (driver.port == id_F0) &&
+ (driver_loc.z == 0 || driver_loc.z == 1))
+ return 0;
+ }
+
+ int dx = abs(driver_loc.x - sink_loc.x), dy = abs(driver_loc.y - sink_loc.y);
+ return (130 - 25 * args.speed) *
+ (6 + std::max(dx - 5, 0) + std::max(dy - 5, 0) + 2 * (std::min(dx, 5) + std::min(dy, 5)));
}
-bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; }
+bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const
+{
+ if (net_info->driver.port == id_FCO && sink.port == id_FCI) {
+ budget = 0;
+ return true;
+ } else if (sink.port == id_FXA || sink.port == id_FXB) {
+ budget = 0;
+ return true;
+ } else {
+ return false;
+ }
+}
// -----------------------------------------------------------------------
-bool Arch::place() { return placer1(getCtx(), Placer1Cfg(getCtx())); }
+bool Arch::place()
+{
+ bool result = placer1(getCtx(), Placer1Cfg(getCtx()));
+ if (result)
+ permute_luts();
+ return result;
+}
bool Arch::route()
{
@@ -602,7 +648,7 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
// Data for -8 grade
if (cell->type == id_TRELLIS_SLICE) {
- bool has_carry = str_or_default(cell->params, id("MODE"), "LOGIC") == "CCU2";
+ bool has_carry = cell->sliceInfo.is_carry;
if (fromPort == id_A0 || fromPort == id_B0 || fromPort == id_C0 || fromPort == id_D0 || fromPort == id_A1 ||
fromPort == id_B1 || fromPort == id_C1 || fromPort == id_D1 || fromPort == id_M0 || fromPort == id_M1 ||
fromPort == id_FXA || fromPort == id_FXB || fromPort == id_FCI) {
@@ -639,7 +685,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
auto disconnected = [cell](IdString p) { return !cell->ports.count(p) || cell->ports.at(p).net == nullptr; };
clockInfoCount = 0;
if (cell->type == id_TRELLIS_SLICE) {
- int sd0 = int_or_default(cell->params, id("REG0_SD"), 0), sd1 = int_or_default(cell->params, id("REG1_SD"), 0);
+ int sd0 = cell->sliceInfo.sd0, sd1 = cell->sliceInfo.sd1;
if (port == id_CLK || port == id_WCK)
return TMG_CLOCK_INPUT;
if (port == id_A0 || port == id_A1 || port == id_B0 || port == id_B1 || port == id_C0 || port == id_C1 ||
@@ -746,6 +792,29 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
return TMG_GEN_CLOCK;
else
NPNR_ASSERT_FALSE("bad clkdiv port");
+ } else if (cell->type == id_DQSBUFM) {
+ if (port == id_READ0 || port == id_READ1) {
+ clockInfoCount = 1;
+ return TMG_REGISTER_INPUT;
+ } else if (port == id_DATAVALID) {
+ clockInfoCount = 1;
+ return TMG_REGISTER_OUTPUT;
+ } else if (port == id_SCLK || port == id_ECLK || port == id_DQSI) {
+ return TMG_CLOCK_INPUT;
+ } else if (port == id_DQSR90 || port == id_DQSW || port == id_DQSW270) {
+ return TMG_GEN_CLOCK;
+ }
+ return (cell->ports.at(port).type == PORT_OUT) ? TMG_STARTPOINT : TMG_ENDPOINT;
+ } else if (cell->type == id_DDRDLL) {
+ if (port == id_CLK)
+ return TMG_CLOCK_INPUT;
+ return (cell->ports.at(port).type == PORT_OUT) ? TMG_STARTPOINT : TMG_ENDPOINT;
+ } else if (cell->type == id_TRELLIS_ECLKBUF) {
+ return (cell->ports.at(port).type == PORT_OUT) ? TMG_COMB_OUTPUT : TMG_COMB_INPUT;
+ } else if (cell->type == id_ECLKSYNCB) {
+ if (cell->ports.at(port).name == id_STOP)
+ return TMG_ENDPOINT;
+ return (cell->ports.at(port).type == PORT_OUT) ? TMG_COMB_OUTPUT : TMG_COMB_INPUT;
} else {
log_error("cell type '%s' is unsupported (instantiated as '%s')\n", cell->type.c_str(this),
cell->name.c_str(this));
@@ -759,8 +828,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
info.hold = getDelayFromNS(0);
info.clockToQ = getDelayFromNS(0);
if (cell->type == id_TRELLIS_SLICE) {
- int sd0 = int_or_default(cell->params, id("REG0_SD"), 0), sd1 = int_or_default(cell->params, id("REG1_SD"), 0);
-
+ int sd0 = cell->sliceInfo.sd0, sd1 = cell->sliceInfo.sd1;
if (port == id_WD0 || port == id_WD1 || port == id_WAD0 || port == id_WAD1 || port == id_WAD2 ||
port == id_WAD3 || port == id_WRE) {
info.edge = RISING_EDGE;
@@ -829,6 +897,16 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
info.setup = getDelayFromNS(0.1);
info.hold = getDelayFromNS(0);
}
+ } else if (cell->type == id_DQSBUFM) {
+ info.clock_port = id_SCLK;
+ if (port == id_DATAVALID) {
+ info.clockToQ = getDelayFromNS(0.2);
+ } else if (port == id_READ0 || port == id_READ1) {
+ info.setup = getDelayFromNS(0.5);
+ info.hold = getDelayFromNS(-0.4);
+ } else {
+ NPNR_ASSERT_FALSE("unknown DQSBUFM register port");
+ }
}
return info;
}
@@ -850,4 +928,41 @@ GlobalInfoPOD Arch::globalInfoAtLoc(Location loc)
return chip_info->location_glbinfo[locidx];
}
+bool Arch::getPIODQSGroup(BelId pio, bool &dqsright, int &dqsrow)
+{
+ for (int i = 0; i < chip_info->num_pios; i++) {
+ if (Location(chip_info->pio_info[i].abs_loc) == pio.location && chip_info->pio_info[i].bel_index == pio.index) {
+ int dqs = chip_info->pio_info[i].dqsgroup;
+ if (dqs == -1)
+ return false;
+ else {
+ dqsright = (dqs & 2048) != 0;
+ dqsrow = dqs & 0x1FF;
+ return true;
+ }
+ }
+ }
+ NPNR_ASSERT_FALSE("failed to find PIO");
+}
+
+BelId Arch::getDQSBUF(bool dqsright, int dqsrow)
+{
+ BelId bel;
+ bel.location.y = dqsrow;
+ bel.location.x = (dqsright ? (chip_info->width - 1) : 0);
+ for (int i = 0; i < locInfo(bel)->num_bels; i++) {
+ auto &bd = locInfo(bel)->bel_data[i];
+ if (bd.type == id_DQSBUFM.index) {
+ bel.index = i;
+ return bel;
+ }
+ }
+ NPNR_ASSERT_FALSE("failed to find DQSBUF");
+}
+
+WireId Arch::getBankECLK(int bank, int eclk)
+{
+ return getWireByLocAndBasename(Location(0, 0), "G_BANK" + std::to_string(bank) + "ECLK" + std::to_string(eclk));
+}
+
NEXTPNR_NAMESPACE_END
diff --git a/ecp5/arch.h b/ecp5/arch.h
index 713c320e..ab4a4e00 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -103,7 +103,7 @@ NPNR_PACKED_STRUCT(struct PIOInfoPOD {
int32_t bel_index;
RelPtr<char> function_name;
int16_t bank;
- int16_t padding;
+ int16_t dqsgroup;
});
NPNR_PACKED_STRUCT(struct PackagePinPOD {
@@ -918,7 +918,7 @@ struct Arch : BaseCtx
delay_t estimateDelay(WireId src, WireId dst) const;
delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const;
delay_t getDelayEpsilon() const { return 20; }
- delay_t getRipupDelayPenalty() const { return 200; }
+ delay_t getRipupDelayPenalty() const { return 400; }
float getDelayNS(delay_t v) const { return v * 0.001; }
DelayInfo getDelayFromNS(float ns) const
{
@@ -971,6 +971,8 @@ struct Arch : BaseCtx
void assignArchInfo();
+ void permute_luts();
+
std::vector<std::pair<std::string, std::string>> getTilesAtLocation(int row, int col);
std::string getTileByTypeAndLocation(int row, int col, std::string type) const
{
@@ -1006,6 +1008,10 @@ struct Arch : BaseCtx
GlobalInfoPOD globalInfoAtLoc(Location loc);
+ bool getPIODQSGroup(BelId pio, bool &dqsright, int &dqsrow);
+ BelId getDQSBUF(bool dqsright, int dqsrow);
+ WireId getBankECLK(int bank, int eclk);
+
// Apply LPF constraints to the context
bool applyLPF(std::string filename, std::istream &in);
diff --git a/ecp5/arch_place.cc b/ecp5/arch_place.cc
index ff70bb5a..e5c9b31f 100644
--- a/ecp5/arch_place.cc
+++ b/ecp5/arch_place.cc
@@ -18,8 +18,10 @@
*/
#include "cells.h"
+#include "design_utils.h"
#include "log.h"
#include "nextpnr.h"
+#include "timing.h"
#include "util.h"
NEXTPNR_NAMESPACE_BEGIN
@@ -115,4 +117,76 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
}
}
+void Arch::permute_luts()
+{
+ NetCriticalityMap nc;
+ get_criticalities(getCtx(), &nc);
+
+ std::unordered_map<PortInfo *, size_t> port_to_user;
+ for (auto net : sorted(nets)) {
+ NetInfo *ni = net.second;
+ for (size_t i = 0; i < ni->users.size(); i++) {
+ auto &usr = ni->users.at(i);
+ port_to_user[&(usr.cell->ports.at(usr.port))] = i;
+ }
+ }
+
+ auto proc_lut = [&](CellInfo *ci, int lut) {
+ std::vector<IdString> port_names;
+ for (int i = 0; i < 4; i++)
+ port_names.push_back(id(std::string("ABCD").substr(i, 1) + std::to_string(lut)));
+
+ std::vector<std::pair<float, int>> inputs;
+ std::vector<NetInfo *> orig_nets;
+
+ for (int i = 0; i < 4; i++) {
+ auto &port = ci->ports.at(port_names.at(i));
+ float crit = 0;
+ if (port.net != nullptr && nc.count(port.net->name)) {
+ auto &n = nc.at(port.net->name);
+ size_t usr = port_to_user.at(&port);
+ if (usr < n.criticality.size())
+ crit = n.criticality.at(usr);
+ }
+ orig_nets.push_back(port.net);
+ inputs.emplace_back(crit, i);
+ }
+ // Least critical first (A input is slowest)
+ std::sort(inputs.begin(), inputs.end());
+ for (int i = 0; i < 4; i++) {
+ IdString p = port_names.at(i);
+ // log_info("%s %s %f\n", p.c_str(ctx), port_names.at(inputs.at(i).second).c_str(ctx), inputs.at(i).first);
+ disconnect_port(getCtx(), ci, p);
+ ci->ports.at(p).net = nullptr;
+ if (orig_nets.at(inputs.at(i).second) != nullptr) {
+ connect_port(getCtx(), orig_nets.at(inputs.at(i).second), ci, p);
+ ci->params[id(p.str(this) + "MUX")] = p.str(this);
+ } else {
+ ci->params[id(p.str(this) + "MUX")] = "1";
+ }
+ }
+ // Rewrite function
+ int old_init = int_or_default(ci->params, id("LUT" + std::to_string(lut) + "_INITVAL"), 0);
+ int new_init = 0;
+ for (int i = 0; i < 16; i++) {
+ int old_index = 0;
+ for (int k = 0; k < 4; k++) {
+ if (i & (1 << k))
+ old_index |= (1 << inputs.at(k).second);
+ }
+ if (old_init & (1 << old_index))
+ new_init |= (1 << i);
+ }
+ ci->params[id("LUT" + std::to_string(lut) + "_INITVAL")] = std::to_string(new_init);
+ };
+
+ for (auto cell : sorted(cells)) {
+ CellInfo *ci = cell.second;
+ if (ci->type == id_TRELLIS_SLICE && str_or_default(ci->params, id("MODE"), "LOGIC") == "LOGIC") {
+ proc_lut(ci, 0);
+ proc_lut(ci, 1);
+ }
+ }
+}
+
NEXTPNR_NAMESPACE_END
diff --git a/ecp5/archdefs.h b/ecp5/archdefs.h
index bfc5769b..d7ea0a8e 100644
--- a/ecp5/archdefs.h
+++ b/ecp5/archdefs.h
@@ -159,7 +159,9 @@ struct ArchCellInfo
{
bool using_dff;
bool has_l6mux;
+ bool is_carry;
IdString clk_sig, lsr_sig, clkmux, lsrmux, srmode;
+ int sd0, sd1;
} sliceInfo;
};
diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc
index ccaafdb6..a9c82524 100644
--- a/ecp5/bitstream.cc
+++ b/ecp5/bitstream.cc
@@ -619,7 +619,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
}
// Find bank voltages
std::unordered_map<int, IOVoltage> bankVcc;
- std::unordered_map<int, bool> bankLvds;
+ std::unordered_map<int, bool> bankLvds, bankVref;
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
@@ -628,7 +628,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
std::string dir = str_or_default(ci->params, ctx->id("DIR"), "INPUT");
std::string iotype = str_or_default(ci->attrs, ctx->id("IO_TYPE"), "LVCMOS33");
- if (dir != "INPUT") {
+ if (dir != "INPUT" || is_referenced(ioType_from_str(iotype))) {
IOVoltage vcc = get_vccio(ioType_from_str(iotype));
if (bankVcc.find(bank) != bankVcc.end()) {
// TODO: strong and weak constraints
@@ -644,6 +644,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
if (iotype == "LVDS")
bankLvds[bank] = true;
+ if ((dir == "INPUT" || dir == "BIDIR") && is_referenced(ioType_from_str(iotype)))
+ bankVref[bank] = true;
}
}
@@ -655,17 +657,67 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
std::string type = tile.second;
if (type.find("BANKREF") != std::string::npos && type != "BANKREF8") {
int bank = std::stoi(type.substr(7));
- if (bankVcc.find(bank) != bankVcc.end())
- cc.tiles[tile.first].add_enum("BANK.VCCIO", iovoltage_to_str(bankVcc[bank]));
+ if (bankVcc.find(bank) != bankVcc.end()) {
+ if (bankVcc[bank] == IOVoltage::VCC_1V35)
+ cc.tiles[tile.first].add_enum("BANK.VCCIO", "1V2");
+ else
+ cc.tiles[tile.first].add_enum("BANK.VCCIO", iovoltage_to_str(bankVcc[bank]));
+ }
if (bankLvds[bank]) {
cc.tiles[tile.first].add_enum("BANK.DIFF_REF", "ON");
cc.tiles[tile.first].add_enum("BANK.LVDSO", "ON");
}
+ if (bankVref[bank]) {
+ cc.tiles[tile.first].add_enum("BANK.DIFF_REF", "ON");
+ cc.tiles[tile.first].add_enum("BANK.VREF", "ON");
+ }
}
}
}
}
+ // Create dummy outputs used as Vref input buffer for banks where Vref is used
+ for (auto bv : bankVref) {
+ if (!bv.second)
+ continue;
+ BelId vrefIO = ctx->getPioByFunctionName(fmt_str("VREF1_" << bv.first));
+ if (vrefIO == BelId())
+ log_error("unable to find VREF input for bank %d\n", bv.first);
+ if (!ctx->checkBelAvail(vrefIO)) {
+ CellInfo *bound = ctx->getBoundBelCell(vrefIO);
+ if (bound != nullptr)
+ log_error("VREF pin %s of bank %d is occupied by IO '%s'\n", ctx->getBelPackagePin(vrefIO).c_str(),
+ bv.first, bound->name.c_str(ctx));
+ else
+ log_error("VREF pin %s of bank %d is unavailable\n", ctx->getBelPackagePin(vrefIO).c_str(), bv.first);
+ }
+ log_info("Using pin %s as VREF for bank %d\n", ctx->getBelPackagePin(vrefIO).c_str(), bv.first);
+ std::string pio_tile = get_pio_tile(ctx, vrefIO);
+
+ std::string iotype;
+ switch (bankVcc[bv.first]) {
+ case IOVoltage::VCC_1V2:
+ iotype = "HSUL12";
+ break;
+ case IOVoltage::VCC_1V35:
+ iotype = "SSTL18_I";
+ break;
+ case IOVoltage::VCC_1V5:
+ iotype = "SSTL18_I";
+ break;
+ case IOVoltage::VCC_1V8:
+ iotype = "SSTL18_I";
+ break;
+ default:
+ log_error("Referenced inputs are not supported with bank VccIO of %s.\n",
+ iovoltage_to_str(bankVcc[bv.first]).c_str());
+ }
+
+ std::string pio = ctx->locInfo(vrefIO)->bel_data[vrefIO.index].name.get();
+ cc.tiles[pio_tile].add_enum(pio + ".BASE_TYPE", "OUTPUT_" + iotype);
+ cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE");
+ }
+
// Configure slices
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
@@ -768,9 +820,13 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
// cc.tiles[pic_tile].add_enum(other + ".BASE_TYPE", "_NONE_");
cc.tiles[pio_tile].add_enum(other + ".PULLMODE", "NONE");
cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE");
+ } else if (is_referenced(ioType_from_str(iotype))) {
+ cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE");
}
if (dir != "INPUT" &&
- (ci->ports.find(ctx->id("T")) == ci->ports.end() || ci->ports.at(ctx->id("T")).net == nullptr)) {
+ (ci->ports.find(ctx->id("T")) == ci->ports.end() || ci->ports.at(ctx->id("T")).net == nullptr) &&
+ (ci->ports.find(ctx->id("IOLTO")) == ci->ports.end() ||
+ ci->ports.at(ctx->id("IOLTO")).net == nullptr)) {
// Tie tristate low if unconnected for outputs or bidir
std::string jpt = fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/JPADDT" << pio.back());
WireId jpt_wire = ctx->getWireByName(ctx->id(jpt));
@@ -781,13 +837,37 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
std::string cib_wirename = ctx->locInfo(cib_wire)->wire_data[cib_wire.index].name.get();
cc.tiles[cib_tile].add_enum("CIB." + cib_wirename + "MUX", "0");
}
- if (dir == "INPUT" && !is_differential(ioType_from_str(iotype))) {
+ if (dir == "INPUT" && !is_differential(ioType_from_str(iotype)) &&
+ !is_referenced(ioType_from_str(iotype))) {
cc.tiles[pio_tile].add_enum(pio + ".HYSTERESIS", "ON");
}
- if (ci->attrs.count(ctx->id("SLEWRATE")))
+ if (ci->attrs.count(ctx->id("SLEWRATE")) && !is_referenced(ioType_from_str(iotype)))
cc.tiles[pio_tile].add_enum(pio + ".SLEWRATE", str_or_default(ci->attrs, ctx->id("SLEWRATE"), "SLOW"));
if (ci->attrs.count(ctx->id("PULLMODE")))
cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", str_or_default(ci->attrs, ctx->id("PULLMODE"), "NONE"));
+ if (ci->attrs.count(ctx->id("DIFFRESISTOR")))
+ cc.tiles[pio_tile].add_enum(pio + ".DIFFRESISTOR",
+ str_or_default(ci->attrs, ctx->id("DIFFRESISTOR"), "OFF"));
+ if (ci->attrs.count(ctx->id("TERMINATION"))) {
+ auto vccio = get_vccio(ioType_from_str(iotype));
+ switch (vccio) {
+ case IOVoltage::VCC_1V8:
+ cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V8",
+ str_or_default(ci->attrs, ctx->id("TERMINATION"), "OFF"));
+ break;
+ case IOVoltage::VCC_1V5:
+ cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V5",
+ str_or_default(ci->attrs, ctx->id("TERMINATION"), "OFF"));
+ break;
+ case IOVoltage::VCC_1V35:
+ cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V35",
+ str_or_default(ci->attrs, ctx->id("TERMINATION"), "OFF"));
+ break;
+ default:
+ log_error("TERMINATION is not supported with Vcc = %s (on PIO %s)\n",
+ iovoltage_to_str(vccio).c_str(), ci->name.c_str(ctx));
+ }
+ }
std::string datamux_oddr = str_or_default(ci->params, ctx->id("DATAMUX_ODDR"), "PADDO");
if (datamux_oddr != "PADDO")
cc.tiles[pic_tile].add_enum(pio + ".DATAMUX_ODDR", datamux_oddr);
@@ -1190,6 +1270,56 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
std::string tile = ctx->getTileByType(std::string("ECLK_") + (r ? "R" : "L"));
cc.tiles[tile].add_enum(clkdiv + ".DIV", str_or_default(ci->params, ctx->id("DIV"), "2.0"));
cc.tiles[tile].add_enum(clkdiv + ".GSR", str_or_default(ci->params, ctx->id("GSR"), "DISABLED"));
+ } else if (ci->type == id_TRELLIS_ECLKBUF) {
+ } else if (ci->type == id_DQSBUFM) {
+ Loc loc = ctx->getBelLocation(ci->bel);
+ bool l = loc.x < 10;
+ std::string pic = l ? "PICL" : "PICR";
+ TileGroup tg;
+ tg.tiles.push_back(ctx->getTileByTypeAndLocation(loc.y - 2, loc.x, pic + "1_DQS0"));
+ tg.tiles.push_back(ctx->getTileByTypeAndLocation(loc.y - 1, loc.x, pic + "2_DQS1"));
+ tg.tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, pic + "0_DQS2"));
+ tg.tiles.push_back(ctx->getTileByTypeAndLocation(loc.y + 1, loc.x, pic + "1_DQS3"));
+ tg.config.add_enum("DQS.MODE", "DQSBUFM");
+ tg.config.add_enum("DQS.DQS_LI_DEL_ADJ", str_or_default(ci->params, ctx->id("DQS_LI_DEL_ADJ"), "PLUS"));
+ tg.config.add_enum("DQS.DQS_LO_DEL_ADJ", str_or_default(ci->params, ctx->id("DQS_LO_DEL_ADJ"), "PLUS"));
+ int li_del_value = int_or_default(ci->params, ctx->id("DQS_LI_DEL_VAL"), 0);
+ if (str_or_default(ci->params, ctx->id("DQS_LI_DEL_ADJ"), "PLUS") == "MINUS")
+ li_del_value = (256 - li_del_value) & 0xFF;
+ int lo_del_value = int_or_default(ci->params, ctx->id("DQS_LO_DEL_VAL"), 0);
+ if (str_or_default(ci->params, ctx->id("DQS_LO_DEL_ADJ"), "PLUS") == "MINUS")
+ lo_del_value = (256 - lo_del_value) & 0xFF;
+ tg.config.add_word("DQS.DQS_LI_DEL_VAL", int_to_bitvector(li_del_value, 8));
+ tg.config.add_word("DQS.DQS_LO_DEL_VAL", int_to_bitvector(lo_del_value, 8));
+ tg.config.add_enum("DQS.WRLOADN_USED", get_net_or_empty(ci, id_WRLOADN) != nullptr ? "YES" : "NO");
+ tg.config.add_enum("DQS.RDLOADN_USED", get_net_or_empty(ci, id_RDLOADN) != nullptr ? "YES" : "NO");
+ tg.config.add_enum("DQS.PAUSE_USED", get_net_or_empty(ci, id_PAUSE) != nullptr ? "YES" : "NO");
+ tg.config.add_enum("DQS.READ_USED",
+ (get_net_or_empty(ci, id_READ0) != nullptr || get_net_or_empty(ci, id_READ1) != nullptr)
+ ? "YES"
+ : "NO");
+ tg.config.add_enum("DQS.DDRDEL", get_net_or_empty(ci, id_DDRDEL) != nullptr ? "DDRDEL" : "0");
+ tg.config.add_enum("DQS.GSR", str_or_default(ci->params, ctx->id("GSR"), "DISABLED"));
+ cc.tilegroups.push_back(tg);
+ } else if (ci->type == id_ECLKSYNCB) {
+ Loc loc = ctx->getBelLocation(ci->bel);
+ bool r = loc.x > 5;
+ std::string eclksync = ctx->locInfo(bel)->bel_data[bel.index].name.get();
+ std::string tile = ctx->getTileByType(std::string("ECLK_") + (r ? "R" : "L"));
+ if (get_net_or_empty(ci, id_STOP) != nullptr)
+ cc.tiles[tile].add_enum(eclksync + ".MODE", "ECLKSYNCB");
+ } else if (ci->type == id_DDRDLL) {
+ Loc loc = ctx->getBelLocation(ci->bel);
+ bool u = loc.y<15, r = loc.x> 15;
+ std::string tiletype = fmt_str("DDRDLL_" << (u ? 'U' : 'L') << (r ? 'R' : 'L'));
+ if (ctx->args.type == ArchArgs::LFE5U_25F || ctx->args.type == ArchArgs::LFE5UM_25F ||
+ ctx->args.type == ArchArgs::LFE5UM5G_25F)
+ tiletype += "A";
+ std::string tile = ctx->getTileByType(tiletype);
+ cc.tiles[tile].add_enum("DDRDLL.MODE", "DDRDLLA");
+ cc.tiles[tile].add_enum("DDRDLL.GSR", str_or_default(ci->params, ctx->id("GSR"), "DISABLED"));
+ cc.tiles[tile].add_enum("DDRDLL.FORCE_MAX_DELAY",
+ str_or_default(ci->params, ctx->id("FORCE_MAX_DELAY"), "NO"));
} else {
NPNR_ASSERT_FALSE("unsupported cell type");
}
diff --git a/ecp5/cells.cc b/ecp5/cells.cc
index a8e92083..38bcc17c 100644
--- a/ecp5/cells.cc
+++ b/ecp5/cells.cc
@@ -201,6 +201,9 @@ std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::str
}
// Just copy ports from the Bel
copy_bel_ports();
+ } else if (type == id_TRELLIS_ECLKBUF) {
+ add_port(ctx, new_cell.get(), "ECLKI", PORT_IN);
+ add_port(ctx, new_cell.get(), "ECLKO", PORT_OUT);
} else {
log_error("unable to create ECP5 cell of type %s", type.c_str(ctx));
}
diff --git a/ecp5/cells.h b/ecp5/cells.h
index dcef99e3..e66f8f21 100644
--- a/ecp5/cells.h
+++ b/ecp5/cells.h
@@ -46,6 +46,17 @@ inline bool is_pfumx(const BaseCtx *ctx, const CellInfo *cell) { return cell->ty
inline bool is_l6mux(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("L6MUX21"); }
+inline bool is_iologic_input_cell(const BaseCtx *ctx, const CellInfo *cell)
+{
+ return cell->type == ctx->id("IDDRX1F") || cell->type == ctx->id("IDDRX2F") || cell->type == ctx->id("IDDR71B") ||
+ cell->type == ctx->id("IDDRX2DQA");
+}
+inline bool is_iologic_output_cell(const BaseCtx *ctx, const CellInfo *cell)
+{
+ return cell->type == ctx->id("ODDRX1F") || cell->type == ctx->id("ODDRX2F") || cell->type == ctx->id("ODDR71B") ||
+ cell->type == ctx->id("ODDRX2DQA") || cell->type == ctx->id("ODDRX2DQSB") || cell->type == ctx->id("OSHX2A");
+}
+
void ff_to_slice(Context *ctx, CellInfo *ff, CellInfo *lc, int index, bool driven_by_lut);
void lut_to_slice(Context *ctx, CellInfo *lut, CellInfo *lc, int index);
void ccu2c_to_slice(Context *ctx, CellInfo *ccu, CellInfo *lc);
diff --git a/ecp5/constids.inc b/ecp5/constids.inc
index 6ba453c7..8a3179b6 100644
--- a/ecp5/constids.inc
+++ b/ecp5/constids.inc
@@ -1280,3 +1280,5 @@ X(BURSTDET)
X(RDCFLAG)
X(WRCFLAG)
X(SCLK)
+
+X(TRELLIS_ECLKBUF) \ No newline at end of file
diff --git a/ecp5/docs/primitives.md b/ecp5/docs/primitives.md
new file mode 100644
index 00000000..aa37f3e5
--- /dev/null
+++ b/ecp5/docs/primitives.md
@@ -0,0 +1,47 @@
+# nextpnr-ecp5 Primitive Support List
+
+nextpnr-ecp5 currently supports the following primitives:
+
+ - **ALU54B** (limited support, must be manually placed)
+ - **CCU2C**
+ - **CLKDIVF**
+ - **DCUA**
+ - **DDRDLLA**
+ - **DELAYF**
+ - **DELAYG**
+ - **DP16KD**
+ - **DQSBUFM**
+ - **DTR**
+ - **ECLKSYNCB**
+ - **EHXPLLL**
+ - **EXTREFB**
+ - **GSR**
+ - **IDDR71B**
+ - **IDDRX1F**
+ - **IDDRX2DQA**
+ - **IDDRX2F**
+ - **IOLOGIC**
+ - **JTAGG** (untested)
+ - **L6MUX21**
+ - **LUT4**
+ - **MULT18X18D** (cascade functionality not supported)
+ - **ODDR71B**
+ - **ODDRX1F**
+ - **ODDRX2DQA**
+ - **ODDRX2DQSB**
+ - **ODDRX2F**
+ - **OSCG**
+ - **OSHX2A**
+ - **PCSCLKDIV**
+ - **PFUMX**
+ - **SEDGA** (untested)
+ - **SIOLOGIC**
+ - **TRELLIS_DPR16X4**
+ - **TRELLIS_ECLKBUF**
+ - **TRELLIS_FF**
+ - **TRELLIS_IO**
+ - **TRELLIS_SLICE**
+ - **TSHX2DQA**
+ - **TSHX2DQSA**
+ - **USRMCLK** (untested)
+
diff --git a/ecp5/globals.cc b/ecp5/globals.cc
index 49947b20..fae2c683 100644
--- a/ecp5/globals.cc
+++ b/ecp5/globals.cc
@@ -448,6 +448,8 @@ class Ecp5GlobalRouter
if (i < 8)
fab_globals.insert(i);
}
+ std::vector<std::pair<PortRef *, int>> toroute;
+ std::unordered_map<int, NetInfo *> clocks;
for (auto cell : sorted(ctx->cells)) {
CellInfo *ci = cell.second;
if (ci->type == id_DCCA) {
@@ -472,15 +474,18 @@ class Ecp5GlobalRouter
NPNR_ASSERT(routed);
// WCK must have routing priority
- auto sorted_users = clock->users;
- std::sort(sorted_users.begin(), sorted_users.end(), [this](const PortRef &a, const PortRef &b) {
- return global_route_priority(a) < global_route_priority(b);
- });
- for (const auto &user : sorted_users) {
- route_logic_tile_global(clock, glbid, user);
- }
+ for (auto &user : clock->users)
+ toroute.emplace_back(&user, glbid);
+ clocks[glbid] = clock;
}
}
+ std::sort(toroute.begin(), toroute.end(),
+ [this](const std::pair<PortRef *, int> &a, const std::pair<PortRef *, int> &b) {
+ return global_route_priority(*a.first) < global_route_priority(*b.first);
+ });
+ for (const auto &user : toroute) {
+ route_logic_tile_global(clocks.at(user.second), user.second, *user.first);
+ }
}
};
void promote_ecp5_globals(Context *ctx) { Ecp5GlobalRouter(ctx).promote_globals(); }
diff --git a/ecp5/lpf.cc b/ecp5/lpf.cc
index 4bde660e..4ac70fc9 100644
--- a/ecp5/lpf.cc
+++ b/ecp5/lpf.cc
@@ -17,6 +17,7 @@
*
*/
+#include <boost/algorithm/string.hpp>
#include <sstream>
#include "log.h"
@@ -25,7 +26,7 @@ NEXTPNR_NAMESPACE_BEGIN
bool Arch::applyLPF(std::string filename, std::istream &in)
{
auto isempty = [](const std::string &str) {
- return std::all_of(str.begin(), str.end(), [](char c) { return isblank(c); });
+ return std::all_of(str.begin(), str.end(), [](char c) { return isblank(c) || c == '\r' || c == '\n'; });
};
auto strip_quotes = [](const std::string &str) {
if (str.at(0) == '"') {
@@ -41,7 +42,9 @@ bool Arch::applyLPF(std::string filename, std::istream &in)
log_error("failed to open LPF file\n");
std::string line;
std::string linebuf;
+ int lineno = 0;
while (std::getline(in, line)) {
+ ++lineno;
size_t cstart = line.find('#');
if (cstart != std::string::npos)
line = line.substr(0, cstart);
@@ -60,29 +63,63 @@ bool Arch::applyLPF(std::string filename, std::istream &in)
words.push_back(tmp);
if (words.size() >= 0) {
std::string verb = words.at(0);
- if (verb == "BLOCK" || verb == "SYSCONFIG" || verb == "FREQUENCY") {
- log_warning(" ignoring unsupported LPF command '%s'\n", command.c_str());
+ if (verb == "BLOCK" || verb == "SYSCONFIG") {
+ if (words.size() != 2 || (words.at(1) != "ASYNCPATHS" && words.at(1) != "RESETPATHS"))
+ log_warning(" ignoring unsupported LPF command '%s' (on line %d)\n", command.c_str(),
+ lineno);
+ } else if (verb == "FREQUENCY") {
+ if (words.size() < 2)
+ log_error("expected object type after FREQUENCY (on line %d)\n", lineno);
+ std::string etype = words.at(1);
+ if (etype == "PORT" || etype == "NET") {
+ if (words.size() < 4)
+ log_error("expected frequency value and unit after 'FREQUENCY %s' (on line %d)\n",
+ etype.c_str(), lineno);
+ std::string target = strip_quotes(words.at(2));
+ float freq = std::stof(words.at(3));
+ std::string unit = words.at(4);
+ boost::algorithm::to_upper(unit);
+ if (unit == "MHZ")
+ ;
+ else if (unit == "KHZ")
+ freq /= 1.0e3;
+ else if (unit == "HZ")
+ freq /= 1.0e6;
+ else
+ log_error("unsupported frequency unit '%s' (on line %d)\n", unit.c_str(), lineno);
+ addClock(id(target), freq);
+ } else {
+ log_warning(" ignoring unsupported LPF command '%s %s' (on line %d)\n", command.c_str(),
+ etype.c_str(), lineno);
+ }
} else if (verb == "LOCATE") {
- NPNR_ASSERT(words.at(1) == "COMP");
+ if (words.size() < 5)
+ log_error("expected syntax 'LOCATE COMP <port name> SITE <pin>' (on line %d)\n", lineno);
+ if (words.at(1) != "COMP")
+ log_error("expected 'COMP' after 'LOCATE' (on line %d)\n", lineno);
std::string cell = strip_quotes(words.at(2));
- NPNR_ASSERT(words.at(3) == "SITE");
+ if (words.at(3) != "SITE")
+ log_error("expected 'SITE' after 'LOCATE COMP %s' (on line %d)\n", cell.c_str(), lineno);
auto fnd_cell = cells.find(id(cell));
- if (fnd_cell == cells.end()) {
- log_warning("unmatched LPF 'LOCATE COMP' '%s'\n", cell.c_str());
- } else {
+ if (fnd_cell != cells.end()) {
fnd_cell->second->attrs[id("LOC")] = strip_quotes(words.at(4));
}
} else if (verb == "IOBUF") {
- NPNR_ASSERT(words.at(1) == "PORT");
+ if (words.size() < 3)
+ log_error("expected syntax 'IOBUF PORT <port name> <attr>=<value>...' (on line %d)\n",
+ lineno);
+ if (words.at(1) != "PORT")
+ log_error("expected 'PORT' after 'IOBUF' (on line %d)\n", lineno);
std::string cell = strip_quotes(words.at(2));
auto fnd_cell = cells.find(id(cell));
- if (fnd_cell == cells.end()) {
- log_warning("unmatched LPF 'IOBUF PORT' '%s'\n", cell.c_str());
- } else {
+ if (fnd_cell != cells.end()) {
for (size_t i = 3; i < words.size(); i++) {
std::string setting = words.at(i);
size_t eqpos = setting.find('=');
- NPNR_ASSERT(eqpos != std::string::npos);
+ if (eqpos == std::string::npos)
+ log_error(
+ "expected syntax 'IOBUF PORT <port name> <attr>=<value>...' (on line %d)\n",
+ lineno);
std::string key = setting.substr(0, eqpos), value = setting.substr(eqpos + 1);
fnd_cell->second->attrs[id(key)] = value;
}
diff --git a/ecp5/main.cc b/ecp5/main.cc
index 4f9ac3da..15027a5a 100644
--- a/ecp5/main.cc
+++ b/ecp5/main.cc
@@ -25,6 +25,7 @@
#include "design_utils.h"
#include "log.h"
#include "timing.h"
+#include "util.h"
USING_NEXTPNR_NAMESPACE
@@ -68,6 +69,7 @@ po::options_description ECP5CommandHandler::getArchOptions()
specific.add_options()("textcfg", po::value<std::string>(), "textual configuration in Trellis format to write");
specific.add_options()("lpf", po::value<std::vector<std::string>>(), "LPF pin constraint file(s)");
+ specific.add_options()("lpf-allow-unconstrained", "don't require LPF file(s) to constrain all IO");
return specific;
}
@@ -157,7 +159,26 @@ void ECP5CommandHandler::customAfterLoad(Context *ctx)
std::vector<std::string> files = vm["lpf"].as<std::vector<std::string>>();
for (const auto &filename : files) {
std::ifstream in(filename);
- ctx->applyLPF(filename, in);
+ if (!in)
+ log_error("failed to open LPF file '%s'\n", filename.c_str());
+ if (!ctx->applyLPF(filename, in))
+ log_error("failed to parse LPF file '%s'\n", filename.c_str());
+ }
+
+ for (auto cell : sorted(ctx->cells)) {
+ CellInfo *ci = cell.second;
+ if (ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_obuf") ||
+ ci->type == ctx->id("$nextpnr_iobuf")) {
+ if (!ci->attrs.count(ctx->id("LOC"))) {
+ if (vm.count("lpf-allow-unconstrained"))
+ log_warning("IO '%s' is unconstrained in LPF and will be automatically placed\n",
+ cell.first.c_str(ctx));
+ else
+ log_error("IO '%s' is unconstrained in LPF (override this error with "
+ "--lpf-allow-unconstrained)\n",
+ cell.first.c_str(ctx));
+ }
+ }
}
}
}
diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index 84fce1c7..1b07c2ae 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -20,12 +20,14 @@
#include <algorithm>
#include <boost/optional.hpp>
#include <iterator>
+#include <queue>
#include <unordered_set>
#include "cells.h"
#include "chain_utils.h"
#include "design_utils.h"
#include "globals.h"
#include "log.h"
+#include "timing.h"
#include "util.h"
NEXTPNR_NAMESPACE_BEGIN
@@ -163,6 +165,7 @@ class Ecp5Packer
CellInfo *ci = cell.second;
if (is_lut(ctx, ci) && procdLuts.find(cell.first) == procdLuts.end()) {
NetInfo *znet = ci->ports.at(ctx->id("Z")).net;
+ std::vector<NetInfo *> inpnets;
if (znet != nullptr) {
for (auto user : znet->users) {
if (is_lut(ctx, user.cell) && user.cell != ci &&
@@ -227,12 +230,67 @@ class Ecp5Packer
}
}
}
+
+ // Pack LUTs feeding the same CCU2, RAM or DFF into a SLICE
+ if (znet != nullptr && znet->users.size() < 10) {
+ for (auto user : znet->users) {
+ if (is_lc(ctx, user.cell) || user.cell->type == ctx->id("DP16KD") || is_ff(ctx, user.cell)) {
+ for (auto port : user.cell->ports) {
+ if (port.second.type != PORT_IN || port.second.net == nullptr ||
+ port.second.net == znet)
+ continue;
+ if (port.second.net->users.size() > 10)
+ continue;
+ CellInfo *drv = port.second.net->driver.cell;
+ if (drv == nullptr)
+ continue;
+ if (is_lut(ctx, drv) && !procdLuts.count(drv->name) &&
+ can_pack_lutff(ci->name, drv->name)) {
+ procdLuts.insert(ci->name);
+ procdLuts.insert(drv->name);
+ lutPairs[ci->name] = drv->name;
+ goto paired_inlut;
+ }
+ }
+ }
+ }
+ }
+
+ // Pack LUTs sharing an input with a simple fanout-based heuristic
+ for (const char *inp : {"A", "B", "C", "D"}) {
+ NetInfo *innet = ci->ports.at(ctx->id(inp)).net;
+ if (innet != nullptr && innet->users.size() < 5 && innet->users.size() > 1)
+ inpnets.push_back(innet);
+ }
+ std::sort(inpnets.begin(), inpnets.end(),
+ [&](const NetInfo *a, const NetInfo *b) { return a->users.size() < b->users.size(); });
+ for (auto inet : inpnets) {
+ for (auto &user : inet->users) {
+ if (user.cell == nullptr || user.cell == ci || !is_lut(ctx, user.cell))
+ continue;
+ if (procdLuts.count(user.cell->name))
+ continue;
+ if (can_pack_lutff(ci->name, user.cell->name)) {
+ procdLuts.insert(ci->name);
+ procdLuts.insert(user.cell->name);
+ lutPairs[ci->name] = user.cell->name;
+ goto paired_inlut;
+ }
+ }
+ }
+
if (false) {
paired_inlut:
continue;
}
}
}
+ if (ctx->debug) {
+ log_info("Singleton LUTs (packer QoR debug): \n");
+ for (auto cell : sorted(ctx->cells))
+ if (is_lut(ctx, cell.second) && !procdLuts.count(cell.first))
+ log_info(" %s\n", cell.first.c_str(ctx));
+ }
}
// Return true if an port is a top level port that provides its own IOBUF
@@ -939,11 +997,11 @@ class Ecp5Packer
if (is_lut(ctx, ci)) {
std::unique_ptr<CellInfo> slice =
create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "_SLICE");
- lut_to_slice(ctx, ci, slice.get(), 0);
+ lut_to_slice(ctx, ci, slice.get(), 1);
auto ff = lutffPairs.find(ci->name);
if (ff != lutffPairs.end()) {
- ff_to_slice(ctx, ctx->cells.at(ff->second).get(), slice.get(), 0, true);
+ ff_to_slice(ctx, ctx->cells.at(ff->second).get(), slice.get(), 1, true);
packed_cells.insert(ff->second);
fflutPairs.erase(ff->second);
lutffPairs.erase(ci->name);
@@ -1396,6 +1454,233 @@ class Ecp5Packer
return a->driver.cell->type == b->driver.cell->type;
}
+ struct EdgeClockInfo
+ {
+ CellInfo *buffer = nullptr;
+ NetInfo *unbuf = nullptr;
+ NetInfo *buf = nullptr;
+ };
+
+ std::map<std::pair<int, int>, EdgeClockInfo> eclks;
+
+ void make_eclk(PortInfo &usr_port, CellInfo *usr_cell, BelId usr_bel, int bank)
+ {
+ NetInfo *ecknet = usr_port.net;
+ if (ecknet == nullptr)
+ log_error("Input '%s' of cell '%s' cannot be disconnected\n", usr_port.name.c_str(ctx),
+ usr_cell->name.c_str(ctx));
+ int found_eclk = -1, free_eclk = -1;
+ for (int i = 0; i < 2; i++) {
+ if (eclks.count(std::make_pair(bank, i))) {
+ if (eclks.at(std::make_pair(bank, i)).unbuf == ecknet) {
+ found_eclk = i;
+ break;
+ }
+ } else if (free_eclk == -1) {
+ free_eclk = i;
+ }
+ }
+ if (found_eclk == -1) {
+ if (free_eclk == -1) {
+ log_error("Unable to promote edge clock '%s' for bank %d. 2/2 edge clocks already used by '%s' and "
+ "'%s'.\n",
+ ecknet->name.c_str(ctx), bank, eclks.at(std::make_pair(bank, 0)).unbuf->name.c_str(ctx),
+ eclks.at(std::make_pair(bank, 1)).unbuf->name.c_str(ctx));
+ } else {
+ log_info("Promoted '%s' to bank %d ECLK%d.\n", ecknet->name.c_str(ctx), bank, free_eclk);
+ auto &eclk = eclks[std::make_pair(bank, free_eclk)];
+ eclk.unbuf = ecknet;
+ IdString eckname = ctx->id(ecknet->name.str(ctx) + "$eclk" + std::to_string(bank) + "_" +
+ std::to_string(free_eclk));
+
+ std::unique_ptr<NetInfo> promoted_ecknet(new NetInfo);
+ promoted_ecknet->name = eckname;
+ promoted_ecknet->is_global = true; // Prevents router etc touching this special net
+ eclk.buf = promoted_ecknet.get();
+ NPNR_ASSERT(!ctx->nets.count(eckname));
+ ctx->nets[eckname] = std::move(promoted_ecknet);
+
+ // Insert TRELLIS_ECLKBUF to isolate edge clock from general routing
+ std::unique_ptr<CellInfo> eclkbuf =
+ create_ecp5_cell(ctx, id_TRELLIS_ECLKBUF, eckname.str(ctx) + "$buffer");
+ BelId target_bel;
+ // Find the correct Bel for the ECLKBUF
+ IdString eclkname = ctx->id("G_BANK" + std::to_string(bank) + "ECLK" + std::to_string(free_eclk));
+ for (auto bel : ctx->getBels()) {
+ if (ctx->getBelType(bel) != id_TRELLIS_ECLKBUF)
+ continue;
+ if (ctx->getWireBasename(ctx->getBelPinWire(bel, id_ECLKO)) != eclkname)
+ continue;
+ target_bel = bel;
+ break;
+ }
+ NPNR_ASSERT(target_bel != BelId());
+
+ eclkbuf->attrs[ctx->id("BEL")] = ctx->getBelName(target_bel).str(ctx);
+
+ connect_port(ctx, ecknet, eclkbuf.get(), id_ECLKI);
+ connect_port(ctx, eclk.buf, eclkbuf.get(), id_ECLKO);
+ found_eclk = free_eclk;
+ eclk.buffer = eclkbuf.get();
+ new_cells.push_back(std::move(eclkbuf));
+ }
+ }
+
+ auto &eclk = eclks[std::make_pair(bank, found_eclk)];
+ disconnect_port(ctx, usr_cell, usr_port.name);
+ usr_port.net = nullptr;
+ connect_port(ctx, eclk.buf, usr_cell, usr_port.name);
+
+ // Simple ECLK router
+ WireId userWire = ctx->getBelPinWire(usr_bel, usr_port.name);
+ IdString bnke_name = ctx->id("BNK_ECLK" + std::to_string(found_eclk));
+ IdString global_name = ctx->id("G_BANK" + std::to_string(bank) + "ECLK" + std::to_string(found_eclk));
+
+ std::queue<WireId> upstream;
+ std::unordered_map<WireId, PipId> backtrace;
+ upstream.push(userWire);
+ WireId next;
+ while (true) {
+ if (upstream.empty() || upstream.size() > 30000)
+ log_error("failed to route bank %d ECLK%d to %s.%s\n", bank, found_eclk,
+ ctx->getBelName(usr_bel).c_str(ctx), usr_port.name.c_str(ctx));
+ next = upstream.front();
+ upstream.pop();
+ if (ctx->debug)
+ log_info(" visited %s\n", ctx->getWireName(next).c_str(ctx));
+ IdString basename = ctx->getWireBasename(next);
+ if (basename == bnke_name || basename == global_name) {
+ break;
+ }
+ if (ctx->checkWireAvail(next)) {
+ for (auto pip : ctx->getPipsUphill(next)) {
+ WireId src = ctx->getPipSrcWire(pip);
+ backtrace[src] = pip;
+ upstream.push(src);
+ }
+ }
+ }
+ // Set all the pips we found along the way
+ WireId cursor = next;
+ while (true) {
+ auto fnd = backtrace.find(cursor);
+ if (fnd == backtrace.end())
+ break;
+ ctx->bindPip(fnd->second, eclk.buf, STRENGTH_LOCKED);
+ cursor = ctx->getPipDstWire(fnd->second);
+ }
+ }
+
+ void tie_zero(CellInfo *ci, IdString port)
+ {
+
+ if (!ci->ports.count(port)) {
+ ci->ports[port].name = port;
+ ci->ports[port].type = PORT_IN;
+ }
+
+ std::unique_ptr<CellInfo> zero_cell{new CellInfo};
+ std::unique_ptr<NetInfo> zero_net{new NetInfo};
+ IdString name = ctx->id(ci->name.str(ctx) + "$zero$" + port.str(ctx));
+ zero_cell->type = ctx->id("GND");
+ zero_cell->name = name;
+ zero_net->name = name;
+ zero_cell->ports[ctx->id("GND")].type = PORT_OUT;
+ connect_port(ctx, zero_net.get(), zero_cell.get(), ctx->id("GND"));
+ connect_port(ctx, zero_net.get(), ci, port);
+ ctx->nets[name] = std::move(zero_net);
+ new_cells.push_back(std::move(zero_cell));
+ }
+
+ std::unordered_map<IdString, std::pair<bool, int>> dqsbuf_dqsg;
+ // Pack DQSBUFs
+ void pack_dqsbuf()
+ {
+ for (auto cell : sorted(ctx->cells)) {
+ CellInfo *ci = cell.second;
+ if (ci->type == id_DQSBUFM) {
+ CellInfo *pio = net_driven_by(ctx, ci->ports.at(ctx->id("DQSI")).net, is_trellis_io, id_O);
+ if (pio == nullptr || ci->ports.at(ctx->id("DQSI")).net->users.size() > 1)
+ log_error("DQSBUFM '%s' DQSI input must be connected only to a top level input\n",
+ ci->name.c_str(ctx));
+ if (!pio->attrs.count(ctx->id("BEL")))
+ log_error("DQSBUFM can only be used with a pin-constrained PIO connected to its DQSI input"
+ "(while processing '%s').\n",
+ ci->name.c_str(ctx));
+ BelId pio_bel = ctx->getBelByName(ctx->id(pio->attrs.at(ctx->id("BEL"))));
+ NPNR_ASSERT(pio_bel != BelId());
+ Loc pio_loc = ctx->getBelLocation(pio_bel);
+ if (pio_loc.z != 0)
+ log_error("PIO '%s' does not appear to be a DQS site (expecting an 'A' pin).\n",
+ ctx->getBelName(pio_bel).c_str(ctx));
+ pio_loc.z = 8;
+ BelId dqsbuf = ctx->getBelByLocation(pio_loc);
+ if (dqsbuf == BelId() || ctx->getBelType(dqsbuf) != id_DQSBUFM)
+ log_error("PIO '%s' does not appear to be a DQS site (didn't find a DQSBUFM).\n",
+ ctx->getBelName(pio_bel).c_str(ctx));
+ ci->attrs[ctx->id("BEL")] = ctx->getBelName(dqsbuf).str(ctx);
+ bool got_dqsg = ctx->getPIODQSGroup(pio_bel, dqsbuf_dqsg[ci->name].first, dqsbuf_dqsg[ci->name].second);
+ NPNR_ASSERT(got_dqsg);
+ log_info("Constrained DQSBUFM '%s' to %cDQS%d\n", ci->name.c_str(ctx),
+ dqsbuf_dqsg[ci->name].first ? 'R' : 'L', dqsbuf_dqsg[ci->name].second);
+
+ // Set all special ports, if used as 'globals' that the router won't touch
+ for (auto port : {id_DQSR90, id_RDPNTR0, id_RDPNTR1, id_RDPNTR2, id_WRPNTR0, id_WRPNTR1, id_WRPNTR2,
+ id_DQSW270, id_DQSW}) {
+ if (!ci->ports.count(port))
+ continue;
+ NetInfo *pn = ci->ports.at(port).net;
+ if (pn == nullptr)
+ continue;
+ for (auto &usr : pn->users) {
+ if (usr.port != port ||
+ (usr.cell->type != ctx->id("ODDRX2DQA") && usr.cell->type != ctx->id("ODDRX2DQSB") &&
+ usr.cell->type != ctx->id("TSHX2DQSA") && usr.cell->type != ctx->id("IDDRX2DQA") &&
+ usr.cell->type != ctx->id("TSHX2DQA") && usr.cell->type != id_IOLOGIC))
+ log_error("Port '%s' of DQSBUFM '%s' cannot drive port '%s' of cell '%s'.\n",
+ port.c_str(ctx), ci->name.c_str(ctx), usr.port.c_str(ctx),
+ usr.cell->name.c_str(ctx));
+ }
+ pn->is_global = true;
+ }
+
+ for (auto zport :
+ {id_RDMOVE, id_RDDIRECTION, id_WRMOVE, id_WRDIRECTION, id_READ0, id_READ1, id_READCLKSEL0,
+ id_READCLKSEL1, id_READCLKSEL2, id_DYNDELAY0, id_DYNDELAY1, id_DYNDELAY2, id_DYNDELAY3,
+ id_DYNDELAY4, id_DYNDELAY5, id_DYNDELAY6, id_DYNDELAY7}) {
+ if (net_or_nullptr(ci, zport) == nullptr)
+ tie_zero(ci, zport);
+ }
+ }
+ }
+ }
+
+ int lookup_delay(const std::string &del_mode)
+ {
+ if (del_mode == "USER_DEFINED")
+ return 0;
+ else if (del_mode == "DQS_ALIGNED_X2")
+ return 6;
+ else if (del_mode == "DQS_CMD_CLK")
+ return 9;
+ else if (del_mode == "ECLK_ALIGNED")
+ return 21;
+ else if (del_mode == "ECLK_CENTERED")
+ return 11;
+ else if (del_mode == "ECLKBRIDGE_ALIGNED")
+ return 39;
+ else if (del_mode == "ECLKBRIDGE_CENTERED")
+ return 29;
+ else if (del_mode == "SCLK_ALIGNED")
+ return 50;
+ else if (del_mode == "SCLK_CENTERED")
+ return 39;
+ else if (del_mode == "SCLK_ZEROHOLD")
+ return 59;
+ else
+ log_error("Unsupported DEL_MODE '%s'\n", del_mode.c_str());
+ }
+
// Pack IOLOGIC
void pack_iologic()
{
@@ -1421,6 +1706,24 @@ class Ecp5Packer
disconnect_port(ctx, prim, port);
};
+ auto set_iologic_eclk = [&](CellInfo *iol, CellInfo *prim, IdString port) {
+ NetInfo *eclk = nullptr;
+ if (prim->ports.count(port))
+ eclk = prim->ports[port].net;
+ if (eclk == nullptr)
+ log_error("%s '%s' cannot have disconnected ECLK", prim->type.c_str(ctx), prim->name.c_str(ctx));
+
+ if (iol->ports[id_ECLK].net != nullptr) {
+ if (iol->ports[id_ECLK].net != eclk)
+ log_error("IOLOGIC '%s' has conflicting ECLKs '%s' and '%s'\n", iol->name.c_str(ctx),
+ iol->ports[id_ECLK].net->name.c_str(ctx), eclk->name.c_str(ctx));
+ } else {
+ connect_port(ctx, eclk, iol, id_ECLK);
+ }
+ if (prim->ports.count(port))
+ disconnect_port(ctx, prim, port);
+ };
+
auto set_iologic_lsr = [&](CellInfo *iol, CellInfo *prim, IdString port, bool input) {
NetInfo *lsr = nullptr;
if (prim->ports.count(port))
@@ -1433,7 +1736,7 @@ class Ecp5Packer
if (iol->ports[id_LSR].net != lsr)
log_error("IOLOGIC '%s' has conflicting LSR signals '%s' and '%s'\n", iol->name.c_str(ctx),
iol->ports[id_LSR].net->name.c_str(ctx), lsr->name.c_str(ctx));
- } else {
+ } else if (iol->ports[id_LSR].net == nullptr) {
connect_port(ctx, lsr, iol, id_LSR);
}
}
@@ -1443,19 +1746,27 @@ class Ecp5Packer
auto set_iologic_mode = [&](CellInfo *iol, std::string mode) {
auto &curr_mode = iol->params[ctx->id("MODE")];
- if (curr_mode != "NONE" && curr_mode != mode)
+ if (curr_mode != "NONE" && curr_mode != "IREG_OREG" && curr_mode != mode)
log_error("IOLOGIC '%s' has conflicting modes '%s' and '%s'\n", iol->name.c_str(ctx), curr_mode.c_str(),
mode.c_str());
+ if (iol->type == id_SIOLOGIC && mode != "IREG_OREG" && mode != "IDDRX1_ODDRX1" && mode != "NONE")
+ log_error("IOLOGIC '%s' is set to mode '%s', but this is only supported for left and right IO\n",
+ iol->name.c_str(ctx), mode.c_str());
curr_mode = mode;
};
- auto create_pio_iologic = [&](CellInfo *pio, CellInfo *curr) {
+ auto get_pio_bel = [&](CellInfo *pio, CellInfo *curr) {
if (!pio->attrs.count(ctx->id("BEL")))
log_error("IOLOGIC functionality (DDR, DELAY, DQS, etc) can only be used with pin-constrained PIO "
"(while processing '%s').\n",
curr->name.c_str(ctx));
BelId bel = ctx->getBelByName(ctx->id(pio->attrs.at(ctx->id("BEL"))));
NPNR_ASSERT(bel != BelId());
+ return bel;
+ };
+
+ auto create_pio_iologic = [&](CellInfo *pio, CellInfo *curr) {
+ BelId bel = get_pio_bel(pio, curr);
log_info("IOLOGIC component %s connected to PIO Bel %s\n", curr->name.c_str(ctx),
ctx->getBelName(bel).c_str(ctx));
Loc loc = ctx->getBelLocation(bel);
@@ -1474,6 +1785,123 @@ class Ecp5Packer
return iol_ptr;
};
+ auto process_dqs_port = [&](CellInfo *prim, CellInfo *pio, CellInfo *iol, IdString port) {
+ NetInfo *sig = nullptr;
+ if (prim->ports.count(port))
+ sig = prim->ports[port].net;
+ if (sig == nullptr || sig->driver.cell == nullptr)
+ log_error("Port %s of cell '%s' cannot be disconnected, it must be driven by a DQSBUFM\n",
+ port.c_str(ctx), prim->name.c_str(ctx));
+ if (iol->ports.at(port).net != nullptr) {
+ if (iol->ports.at(port).net != sig) {
+ log_error("IOLOGIC '%s' has conflicting %s signals '%s' and '%s'\n", iol->name.c_str(ctx),
+ port.c_str(ctx), iol->ports[port].net->name.c_str(ctx), sig->name.c_str(ctx));
+ }
+ disconnect_port(ctx, prim, port);
+ } else {
+ bool dqsr;
+ int dqsgroup;
+ bool has_dqs = ctx->getPIODQSGroup(get_pio_bel(pio, prim), dqsr, dqsgroup);
+ if (!has_dqs)
+ log_error("Primitive '%s' cannot be connected to top level port '%s' as the associated pin is not "
+ "in any DQS group",
+ prim->name.c_str(ctx), pio->name.c_str(ctx));
+ if (sig->driver.cell->type != id_DQSBUFM || sig->driver.port != port)
+ log_error("Port %s of cell '%s' must be driven by port %s of a DQSBUFM", port.c_str(ctx),
+ prim->name.c_str(ctx), port.c_str(ctx));
+ auto &driver_group = dqsbuf_dqsg.at(sig->driver.cell->name);
+ if (driver_group.first != dqsr || driver_group.second != dqsgroup)
+ log_error("DQS group mismatch, port %s of '%s' in group %cDQ%d is driven by DQSBUFM '%s' in group "
+ "%cDQ%d\n",
+ port.c_str(ctx), prim->name.c_str(ctx), dqsr ? 'R' : 'L', dqsgroup,
+ sig->driver.cell->name.c_str(ctx), driver_group.first ? 'R' : 'L', driver_group.second);
+ replace_port(prim, port, iol, port);
+ }
+ };
+
+ for (auto cell : sorted(ctx->cells)) {
+ CellInfo *ci = cell.second;
+ if (ci->type == ctx->id("DELAYF") || ci->type == ctx->id("DELAYG")) {
+ CellInfo *i_pio = net_driven_by(ctx, ci->ports.at(ctx->id("A")).net, is_trellis_io, id_O);
+ CellInfo *o_pio = net_only_drives(ctx, ci->ports.at(ctx->id("Z")).net, is_trellis_io, id_I, true);
+ CellInfo *iol = nullptr;
+ if (i_pio != nullptr && ci->ports.at(ctx->id("A")).net->users.size() == 1) {
+ iol = create_pio_iologic(i_pio, ci);
+ set_iologic_mode(iol, "IREG_OREG");
+ bool drives_iologic = false;
+ for (auto user : ci->ports.at(ctx->id("Z")).net->users)
+ if (is_iologic_input_cell(ctx, user.cell) && user.port == ctx->id("D"))
+ drives_iologic = true;
+ if (drives_iologic) {
+ // Reconnect to PIO which the packer expects later on
+ NetInfo *input_net = ci->ports.at(ctx->id("A")).net, *dly_net = ci->ports.at(ctx->id("Z")).net;
+ disconnect_port(ctx, i_pio, id_O);
+ i_pio->ports.at(id_O).net = nullptr;
+ disconnect_port(ctx, ci, id_A);
+ ci->ports.at(id_A).net = nullptr;
+ disconnect_port(ctx, ci, id_Z);
+ ci->ports.at(id_Z).net = nullptr;
+ connect_port(ctx, dly_net, i_pio, id_O);
+ connect_port(ctx, input_net, iol, id_INDD);
+ connect_port(ctx, input_net, iol, id_DI);
+ } else {
+ replace_port(ci, id_A, iol, id_PADDI);
+ replace_port(ci, id_Z, iol, id_INDD);
+ }
+ packed_cells.insert(cell.first);
+ } else if (o_pio != nullptr) {
+ iol = create_pio_iologic(o_pio, ci);
+ iol->params[ctx->id("DELAY.OUTDEL")] = "ENABLED";
+ bool driven_by_iol = false;
+ NetInfo *input_net = ci->ports.at(ctx->id("A")).net, *dly_net = ci->ports.at(ctx->id("Z")).net;
+ if (input_net->driver.cell != nullptr && is_iologic_output_cell(ctx, input_net->driver.cell) &&
+ input_net->driver.port == ctx->id("Q"))
+ driven_by_iol = true;
+ if (driven_by_iol) {
+ disconnect_port(ctx, o_pio, id_I);
+ o_pio->ports.at(id_I).net = nullptr;
+ disconnect_port(ctx, ci, id_A);
+ ci->ports.at(id_A).net = nullptr;
+ disconnect_port(ctx, ci, id_Z);
+ ci->ports.at(id_Z).net = nullptr;
+ connect_port(ctx, input_net, o_pio, id_I);
+ ctx->nets.erase(dly_net->name);
+ } else {
+ replace_port(ci, ctx->id("A"), iol, id_TXDATA0);
+ replace_port(ci, ctx->id("Z"), iol, id_IOLDO);
+ if (!o_pio->ports.count(id_IOLDO)) {
+ o_pio->ports[id_IOLDO].name = id_IOLDO;
+ o_pio->ports[id_IOLDO].type = PORT_IN;
+ }
+ replace_port(o_pio, id_I, o_pio, id_IOLDO);
+ }
+ packed_cells.insert(cell.first);
+ } else {
+ log_error("%s '%s' must be connected directly to top level input or output\n", ci->type.c_str(ctx),
+ ci->name.c_str(ctx));
+ }
+ iol->params[ctx->id("DELAY.DEL_VALUE")] =
+ std::to_string(lookup_delay(str_or_default(ci->params, ctx->id("DEL_MODE"), "USER_DEFINED")));
+ if (ci->params.count(ctx->id("DEL_VALUE")) &&
+ ci->params.at(ctx->id("DEL_VALUE")).substr(0, 5) != "DELAY")
+ iol->params[ctx->id("DELAY.DEL_VALUE")] = ci->params.at(ctx->id("DEL_VALUE"));
+ if (ci->ports.count(id_LOADN))
+ replace_port(ci, id_LOADN, iol, id_LOADN);
+ else
+ tie_zero(ci, id_LOADN);
+ if (ci->ports.count(id_MOVE))
+ replace_port(ci, id_MOVE, iol, id_MOVE);
+ else
+ tie_zero(ci, id_MOVE);
+ if (ci->ports.count(id_DIRECTION))
+ replace_port(ci, id_DIRECTION, iol, id_DIRECTION);
+ else
+ tie_zero(ci, id_DIRECTION);
+ if (ci->ports.count(id_CFLAG))
+ replace_port(ci, id_CFLAG, iol, id_CFLAG);
+ }
+ }
+
for (auto cell : sorted(ctx->cells)) {
CellInfo *ci = cell.second;
if (ci->type == ctx->id("IDDRX1F")) {
@@ -1518,15 +1946,427 @@ class Ecp5Packer
replace_port(ci, ctx->id("D1"), iol, id_TXDATA1);
iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
packed_cells.insert(cell.first);
+ } else if (ci->type == ctx->id("ODDRX2F")) {
+ CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true);
+ if (pio == nullptr)
+ log_error("ODDRX2F '%s' Q output must be connected only to a top level output\n",
+ ci->name.c_str(ctx));
+ CellInfo *iol;
+ if (pio_iologic.count(pio->name))
+ iol = pio_iologic.at(pio->name);
+ else
+ iol = create_pio_iologic(pio, ci);
+ set_iologic_mode(iol, "ODDRXN");
+ replace_port(ci, ctx->id("Q"), iol, id_IOLDO);
+ if (!pio->ports.count(id_IOLDO)) {
+ pio->ports[id_IOLDO].name = id_IOLDO;
+ pio->ports[id_IOLDO].type = PORT_IN;
+ }
+ replace_port(pio, id_I, pio, id_IOLDO);
+ set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
+ set_iologic_sclk(iol, ci, ctx->id("SCLK"), true);
+ set_iologic_eclk(iol, ci, id_ECLK);
+ set_iologic_lsr(iol, ci, ctx->id("RST"), false);
+ set_iologic_lsr(iol, ci, ctx->id("RST"), true);
+ replace_port(ci, ctx->id("D0"), iol, id_TXDATA0);
+ replace_port(ci, ctx->id("D1"), iol, id_TXDATA1);
+ replace_port(ci, ctx->id("D2"), iol, id_TXDATA2);
+ replace_port(ci, ctx->id("D3"), iol, id_TXDATA3);
+ iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+ iol->params[ctx->id("ODDRXN.MODE")] = "ODDRX2";
+ pio->params[ctx->id("DATAMUX_ODDR")] = "IOLDO";
+ packed_cells.insert(cell.first);
+ } else if (ci->type == ctx->id("IDDRX2F")) {
+ CellInfo *pio = net_driven_by(ctx, ci->ports.at(ctx->id("D")).net, is_trellis_io, id_O);
+ if (pio == nullptr || ci->ports.at(ctx->id("D")).net->users.size() > 1)
+ log_error("IDDRX2F '%s' D input must be connected only to a top level input\n",
+ ci->name.c_str(ctx));
+ CellInfo *iol;
+ if (pio_iologic.count(pio->name))
+ iol = pio_iologic.at(pio->name);
+ else
+ iol = create_pio_iologic(pio, ci);
+ set_iologic_mode(iol, "IDDRXN");
+ replace_port(ci, ctx->id("D"), iol, id_PADDI);
+ set_iologic_sclk(iol, ci, ctx->id("SCLK"), true);
+ set_iologic_eclk(iol, ci, id_ECLK);
+ set_iologic_lsr(iol, ci, ctx->id("RST"), true);
+ replace_port(ci, ctx->id("Q0"), iol, id_RXDATA0);
+ replace_port(ci, ctx->id("Q1"), iol, id_RXDATA1);
+ replace_port(ci, ctx->id("Q2"), iol, id_RXDATA2);
+ replace_port(ci, ctx->id("Q3"), iol, id_RXDATA3);
+ iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+ iol->params[ctx->id("IDDRXN.MODE")] = "IDDRX2";
+ packed_cells.insert(cell.first);
+ } else if (ci->type == ctx->id("OSHX2A")) {
+ CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true);
+ if (pio == nullptr)
+ log_error("OSHX2A '%s' Q output must be connected only to a top level output\n",
+ ci->name.c_str(ctx));
+ CellInfo *iol;
+ if (pio_iologic.count(pio->name))
+ iol = pio_iologic.at(pio->name);
+ else
+ iol = create_pio_iologic(pio, ci);
+ set_iologic_mode(iol, "MIDDRX_MODDRX");
+ replace_port(ci, ctx->id("Q"), iol, id_IOLDO);
+ if (!pio->ports.count(id_IOLDO)) {
+ pio->ports[id_IOLDO].name = id_IOLDO;
+ pio->ports[id_IOLDO].type = PORT_IN;
+ }
+ replace_port(pio, id_I, pio, id_IOLDO);
+ set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
+ set_iologic_eclk(iol, ci, id_ECLK);
+ set_iologic_lsr(iol, ci, ctx->id("RST"), false);
+ set_iologic_lsr(iol, ci, ctx->id("RST"), true);
+ replace_port(ci, ctx->id("D0"), iol, id_TXDATA0);
+ replace_port(ci, ctx->id("D1"), iol, id_TXDATA2);
+ iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+ iol->params[ctx->id("MODDRX.MODE")] = "MOSHX2";
+ pio->params[ctx->id("DATAMUX_MDDR")] = "IOLDO";
+ packed_cells.insert(cell.first);
+ } else if (ci->type == ctx->id("ODDRX2DQA") || ci->type == ctx->id("ODDRX2DQSB")) {
+ CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true);
+ if (pio == nullptr)
+ log_error("%s '%s' Q output must be connected only to a top level output\n", ci->type.c_str(ctx),
+ ci->name.c_str(ctx));
+ CellInfo *iol;
+ if (pio_iologic.count(pio->name))
+ iol = pio_iologic.at(pio->name);
+ else
+ iol = create_pio_iologic(pio, ci);
+ set_iologic_mode(iol, "MIDDRX_MODDRX");
+ replace_port(ci, ctx->id("Q"), iol, id_IOLDO);
+ if (!pio->ports.count(id_IOLDO)) {
+ pio->ports[id_IOLDO].name = id_IOLDO;
+ pio->ports[id_IOLDO].type = PORT_IN;
+ }
+ replace_port(pio, id_I, pio, id_IOLDO);
+ set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
+ set_iologic_eclk(iol, ci, id_ECLK);
+ set_iologic_lsr(iol, ci, ctx->id("RST"), false);
+ set_iologic_lsr(iol, ci, ctx->id("RST"), true);
+ replace_port(ci, ctx->id("D0"), iol, id_TXDATA0);
+ replace_port(ci, ctx->id("D1"), iol, id_TXDATA1);
+ replace_port(ci, ctx->id("D2"), iol, id_TXDATA2);
+ replace_port(ci, ctx->id("D3"), iol, id_TXDATA3);
+ iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+ iol->params[ctx->id("MODDRX.MODE")] = "MODDRX2";
+ iol->params[ctx->id("MIDDRX_MODDRX.WRCLKMUX")] = ci->type == ctx->id("ODDRX2DQSB") ? "DQSW" : "DQSW270";
+ process_dqs_port(ci, pio, iol, ci->type == ctx->id("ODDRX2DQSB") ? id_DQSW : id_DQSW270);
+ pio->params[ctx->id("DATAMUX_MDDR")] = "IOLDO";
+ packed_cells.insert(cell.first);
+ } else if (ci->type == ctx->id("IDDRX2DQA")) {
+ CellInfo *pio = net_driven_by(ctx, ci->ports.at(ctx->id("D")).net, is_trellis_io, id_O);
+ if (pio == nullptr || ci->ports.at(ctx->id("D")).net->users.size() > 1)
+ log_error("IDDRX2DQA '%s' D input must be connected only to a top level input\n",
+ ci->name.c_str(ctx));
+ CellInfo *iol;
+ if (pio_iologic.count(pio->name))
+ iol = pio_iologic.at(pio->name);
+ else
+ iol = create_pio_iologic(pio, ci);
+ set_iologic_mode(iol, "MIDDRX_MODDRX");
+ replace_port(ci, ctx->id("D"), iol, id_PADDI);
+ set_iologic_sclk(iol, ci, ctx->id("SCLK"), true);
+ set_iologic_eclk(iol, ci, id_ECLK);
+ set_iologic_lsr(iol, ci, ctx->id("RST"), true);
+ replace_port(ci, ctx->id("Q0"), iol, id_RXDATA0);
+ replace_port(ci, ctx->id("Q1"), iol, id_RXDATA1);
+ replace_port(ci, ctx->id("Q2"), iol, id_RXDATA2);
+ replace_port(ci, ctx->id("Q3"), iol, id_RXDATA3);
+ replace_port(ci, ctx->id("QWL"), iol, id_INFF);
+ iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+ iol->params[ctx->id("MIDDRX.MODE")] = "MIDDRX2";
+ process_dqs_port(ci, pio, iol, id_DQSR90);
+ process_dqs_port(ci, pio, iol, id_RDPNTR2);
+ process_dqs_port(ci, pio, iol, id_RDPNTR1);
+ process_dqs_port(ci, pio, iol, id_RDPNTR0);
+ process_dqs_port(ci, pio, iol, id_WRPNTR2);
+ process_dqs_port(ci, pio, iol, id_WRPNTR1);
+ process_dqs_port(ci, pio, iol, id_WRPNTR0);
+ packed_cells.insert(cell.first);
+ } else if (ci->type == ctx->id("TSHX2DQA") || ci->type == ctx->id("TSHX2DQSA")) {
+ CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_T, true);
+ if (pio == nullptr)
+ log_error("%s '%s' Q output must be connected only to a top level tristate\n", ci->type.c_str(ctx),
+ ci->name.c_str(ctx));
+ CellInfo *iol;
+ if (pio_iologic.count(pio->name))
+ iol = pio_iologic.at(pio->name);
+ else
+ iol = create_pio_iologic(pio, ci);
+ set_iologic_mode(iol, "MIDDRX_MODDRX");
+ replace_port(ci, ctx->id("Q"), iol, id_IOLTO);
+ if (!pio->ports.count(id_IOLTO)) {
+ pio->ports[id_IOLTO].name = id_IOLTO;
+ pio->ports[id_IOLTO].type = PORT_IN;
+ }
+ replace_port(pio, id_T, pio, id_IOLTO);
+ set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
+ set_iologic_eclk(iol, ci, id_ECLK);
+ set_iologic_lsr(iol, ci, ctx->id("RST"), false);
+ replace_port(ci, ctx->id("T0"), iol, id_TSDATA0);
+ replace_port(ci, ctx->id("T1"), iol, id_TSDATA1);
+ process_dqs_port(ci, pio, iol, ci->type == ctx->id("TSHX2DQSA") ? id_DQSW : id_DQSW270);
+ iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+ iol->params[ctx->id("MTDDRX.MODE")] = "MTSHX2";
+ iol->params[ctx->id("MTDDRX.REGSET")] = "SET";
+ iol->params[ctx->id("MTDDRX.DQSW_INVERT")] = ci->type == ctx->id("TSHX2DQSA") ? "ENABLED" : "DISABLED";
+ iol->params[ctx->id("MIDDRX_MODDRX.WRCLKMUX")] = ci->type == ctx->id("TSHX2DQSA") ? "DQSW" : "DQSW270";
+ iol->params[ctx->id("IOLTOMUX")] = "TDDR";
+ packed_cells.insert(cell.first);
}
}
flush_cells();
+ // Promote/route edge clocks
+ for (auto cell : sorted(ctx->cells)) {
+ CellInfo *ci = cell.second;
+ if (ci->type == id_IOLOGIC || ci->type == id_DQSBUFM) {
+ if (!ci->ports.count(id_ECLK) || ci->ports.at(id_ECLK).net == nullptr)
+ continue;
+ BelId bel = ctx->getBelByName(ctx->id(str_or_default(ci->attrs, ctx->id("BEL"))));
+ NPNR_ASSERT(bel != BelId());
+ Loc pioLoc = ctx->getBelLocation(bel);
+ if (ci->type == id_DQSBUFM)
+ pioLoc.z -= 8;
+ else
+ pioLoc.z -= 4;
+ BelId pioBel = ctx->getBelByLocation(pioLoc);
+ NPNR_ASSERT(pioBel != BelId());
+ int bank = ctx->getPioBelBank(pioBel);
+ make_eclk(ci->ports.at(id_ECLK), ci, bel, bank);
+ }
+ }
+ flush_cells();
+ // Constrain ECLK-related cells
+ for (auto cell : sorted(ctx->cells)) {
+ CellInfo *ci = cell.second;
+ if (ci->type == id_CLKDIVF) {
+ const NetInfo *clki = net_or_nullptr(ci, id_CLKI);
+ for (auto &eclk : eclks) {
+ if (eclk.second.unbuf == clki) {
+ for (auto bel : ctx->getBels()) {
+ if (ctx->getBelType(bel) != id_CLKDIVF)
+ continue;
+ Loc loc = ctx->getBelLocation(bel);
+ // CLKDIVF for bank 6/7 on the left; for bank 2/3 on the right
+ if (loc.x < 10 && eclk.first.first != 6 && eclk.first.first != 7)
+ continue;
+ // z-index of CLKDIVF must match index of ECLK
+ if (loc.z != eclk.first.second)
+ continue;
+ ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
+ make_eclk(ci->ports.at(id_CLKI), ci, bel, eclk.first.first);
+ goto clkdiv_done;
+ }
+ }
+ }
+ clkdiv_done:
+ continue;
+ } else if (ci->type == id_ECLKSYNCB) {
+ const NetInfo *eclko = net_or_nullptr(ci, id_ECLKO);
+ if (eclko == nullptr)
+ log_error("ECLKSYNCB '%s' has disconnected port ECLKO\n", ci->name.c_str(ctx));
+ for (auto user : eclko->users) {
+ if (user.cell->type == id_TRELLIS_ECLKBUF) {
+ Loc eckbuf_loc =
+ ctx->getBelLocation(ctx->getBelByName(ctx->id(user.cell->attrs.at(ctx->id("BEL")))));
+ for (auto bel : ctx->getBels()) {
+ if (ctx->getBelType(bel) != id_ECLKSYNCB)
+ continue;
+ Loc loc = ctx->getBelLocation(bel);
+ if (loc.x == eckbuf_loc.x && loc.y == eckbuf_loc.y && loc.z == eckbuf_loc.z - 2) {
+ ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
+ goto eclksync_done;
+ }
+ }
+ }
+ }
+ eclksync_done:
+ continue;
+ } else if (ci->type == ctx->id("DDRDLLA")) {
+ ci->type = id_DDRDLL; // transform from Verilog to Bel name
+ const NetInfo *clk = net_or_nullptr(ci, id_CLK);
+ if (clk == nullptr)
+ log_error("DDRDLLA '%s' has disconnected port CLK\n", ci->name.c_str(ctx));
+ for (auto &eclk : eclks) {
+ if (eclk.second.unbuf == clk) {
+ for (auto bel : ctx->getBels()) {
+ if (ctx->getBelType(bel) != id_DDRDLL)
+ continue;
+ Loc loc = ctx->getBelLocation(bel);
+ int ddrdll_bank = -1;
+ if (loc.x < 15 && loc.y < 15)
+ ddrdll_bank = 7;
+ else if (loc.x < 15 && loc.y > 15)
+ ddrdll_bank = 6;
+ else if (loc.x > 15 && loc.y < 15)
+ ddrdll_bank = 2;
+ else if (loc.x > 15 && loc.y > 15)
+ ddrdll_bank = 3;
+ if (eclk.first.first != ddrdll_bank)
+ continue;
+ ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
+ make_eclk(ci->ports.at(id_CLK), ci, bel, eclk.first.first);
+ goto ddrdll_done;
+ }
+ }
+ }
+ ddrdll_done:
+ continue;
+ }
+ }
+
+ flush_cells();
};
+ void generate_constraints()
+ {
+ log_info("Generating derived timing constraints...\n");
+ auto MHz = [&](delay_t a) { return 1000.0 / ctx->getDelayNS(a); };
+
+ auto equals_epsilon = [](delay_t a, delay_t b) { return (std::abs(a - b) / std::max(double(b), 1.0)) < 1e-3; };
+
+ std::unordered_set<IdString> user_constrained, changed_nets;
+ for (auto &net : ctx->nets) {
+ if (net.second->clkconstr != nullptr)
+ user_constrained.insert(net.first);
+ changed_nets.insert(net.first);
+ }
+ auto get_period = [&](CellInfo *ci, IdString port, delay_t &period) {
+ if (!ci->ports.count(port))
+ return false;
+ NetInfo *from = ci->ports.at(port).net;
+ if (from == nullptr || from->clkconstr == nullptr)
+ return false;
+ period = from->clkconstr->period.min_delay;
+ return true;
+ };
+
+ auto set_period = [&](CellInfo *ci, IdString port, delay_t period) {
+ if (!ci->ports.count(port))
+ return;
+ NetInfo *to = ci->ports.at(port).net;
+ if (to == nullptr)
+ return;
+ if (to->clkconstr != nullptr) {
+ if (!equals_epsilon(to->clkconstr->period.min_delay, period) && user_constrained.count(to->name))
+ log_warning(
+ " Overriding derived constraint of %.1f MHz on net %s with user-specified constraint of "
+ "%.1f MHz.\n",
+ MHz(to->clkconstr->period.min_delay), to->name.c_str(ctx), MHz(period));
+ return;
+ }
+ to->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
+ to->clkconstr->low.min_delay = period / 2;
+ to->clkconstr->low.max_delay = period / 2;
+ to->clkconstr->high.min_delay = period / 2;
+ to->clkconstr->high.max_delay = period / 2;
+ to->clkconstr->period.min_delay = period;
+ to->clkconstr->period.max_delay = period;
+ log_info(" Derived frequency constraint of %.1f MHz for net %s\n", MHz(to->clkconstr->period.min_delay),
+ to->name.c_str(ctx));
+ changed_nets.insert(to->name);
+ };
+
+ auto copy_constraint = [&](CellInfo *ci, IdString fromPort, IdString toPort, double ratio = 1.0) {
+ if (!ci->ports.count(fromPort) || !ci->ports.count(toPort))
+ return;
+ NetInfo *from = ci->ports.at(fromPort).net, *to = ci->ports.at(toPort).net;
+ if (from == nullptr || from->clkconstr == nullptr || to == nullptr)
+ return;
+ if (to->clkconstr != nullptr) {
+ if (!equals_epsilon(to->clkconstr->period.min_delay,
+ delay_t(from->clkconstr->period.min_delay / ratio)) &&
+ user_constrained.count(to->name))
+ log_warning(
+ " Overriding derived constraint of %.1f MHz on net %s with user-specified constraint of "
+ "%.1f MHz.\n",
+ MHz(to->clkconstr->period.min_delay), to->name.c_str(ctx),
+ MHz(delay_t(from->clkconstr->period.min_delay / ratio)));
+ return;
+ }
+ to->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
+ to->clkconstr->low = ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->low.min_delay) / ratio);
+ to->clkconstr->high = ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->high.min_delay) / ratio);
+ to->clkconstr->period = ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->period.min_delay) / ratio);
+ log_info(" Derived frequency constraint of %.1f MHz for net %s\n", MHz(to->clkconstr->period.min_delay),
+ to->name.c_str(ctx));
+ changed_nets.insert(to->name);
+ };
+
+ // Run in a loop while constraints are changing to deal with dependencies
+ // Iteration limit avoids hanging in crazy loopback situation (self-fed PLLs or dividers, etc)
+ int iter = 0;
+ const int itermax = 5000;
+ while (!changed_nets.empty() && iter < itermax) {
+ ++iter;
+ std::unordered_set<IdString> changed_cells;
+ for (auto net : changed_nets)
+ for (auto &user : ctx->nets.at(net)->users)
+ if (user.port == id_CLKI || user.port == id_ECLKI)
+ changed_cells.insert(user.cell->name);
+ changed_nets.clear();
+ for (auto cell : sorted(changed_cells)) {
+ CellInfo *ci = ctx->cells.at(cell).get();
+ if (ci->type == id_CLKDIVF) {
+ std::string div = str_or_default(ci->params, ctx->id("DIV"), "2.0");
+ double ratio;
+ if (div == "2.0")
+ ratio = 1 / 2.0;
+ else if (div == "3.5")
+ ratio = 1 / 3.5;
+ else
+ log_error("Unsupported divider ratio '%s' on CLKDIVF '%s'\n", div.c_str(), ci->name.c_str(ctx));
+ copy_constraint(ci, id_CLKI, id_CDIVX, ratio);
+ } else if (ci->type == id_ECLKSYNCB || ci->type == id_TRELLIS_ECLKBUF) {
+ copy_constraint(ci, id_ECLKI, id_ECLKO, 1);
+ } else if (ci->type == id_EHXPLLL) {
+ delay_t period_in;
+ if (!get_period(ci, id_CLKI, period_in))
+ continue;
+ log_info(" Input frequency of PLL '%s' is constrained to %.1f MHz\n", ci->name.c_str(ctx),
+ MHz(period_in));
+ double period_in_div = period_in * int_or_default(ci->params, ctx->id("CLKI_DIV"), 1);
+ std::string path = str_or_default(ci->params, ctx->id("FEEDBK_PATH"), "CLKOP");
+ int feedback_div = int_or_default(ci->params, ctx->id("CLKFB_DIV"), 1);
+ if (path == "CLKOP" || path == "INT_OP")
+ feedback_div *= int_or_default(ci->params, ctx->id("CLKOP_DIV"), 1);
+ else if (path == "CLKOS" || path == "INT_OS")
+ feedback_div *= int_or_default(ci->params, ctx->id("CLKOS_DIV"), 1);
+ else if (path == "CLKOS2" || path == "INT_OS2")
+ feedback_div *= int_or_default(ci->params, ctx->id("CLKOS2_DIV"), 1);
+ else if (path == "CLKOS3" || path == "INT_OS3")
+ feedback_div *= int_or_default(ci->params, ctx->id("CLKOS3_DIV"), 1);
+ else {
+ log_info(" Unable to determine output frequencies for PLL '%s' with FEEDBK_PATH=%s\n",
+ ci->name.c_str(ctx), path.c_str());
+ continue;
+ }
+ double vco_period = period_in_div / feedback_div;
+ double vco_freq = MHz(vco_period);
+ if (vco_freq < 400 || vco_freq > 800)
+ log_info(" Derived VCO frequency %.1f MHz of PLL '%s' is out of legal range [400MHz, "
+ "800MHz]\n",
+ vco_freq, ci->name.c_str(ctx));
+ set_period(ci, id_CLKOP, vco_period * int_or_default(ci->params, ctx->id("CLKOP_DIV"), 1));
+ set_period(ci, id_CLKOS, vco_period * int_or_default(ci->params, ctx->id("CLKOS_DIV"), 1));
+ set_period(ci, id_CLKOS2, vco_period * int_or_default(ci->params, ctx->id("CLKOS2_DIV"), 1));
+ set_period(ci, id_CLKOS3, vco_period * int_or_default(ci->params, ctx->id("CLKOS3_DIV"), 1));
+ } else if (ci->type == id_OSCG) {
+ int div = int_or_default(ci->params, ctx->id("DIV"), 128);
+ set_period(ci, id_OSC, delay_t((1.0e6 / (2.0 * 155)) * div));
+ }
+ }
+ }
+ }
+
public:
void pack()
{
pack_io();
+ pack_dqsbuf();
pack_iologic();
pack_ebr();
pack_dsps();
@@ -1541,6 +2381,7 @@ class Ecp5Packer
pack_lut_pairs();
pack_remaining_luts();
pack_remaining_ffs();
+ generate_constraints();
promote_ecp5_globals(ctx);
ctx->check();
}
@@ -1605,6 +2446,9 @@ void Arch::assignArchInfo()
ci->sliceInfo.clkmux = id(str_or_default(ci->params, id_CLKMUX, "CLK"));
ci->sliceInfo.lsrmux = id(str_or_default(ci->params, id_LSRMUX, "LSR"));
ci->sliceInfo.srmode = id(str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE"));
+ ci->sliceInfo.is_carry = str_or_default(ci->params, id("MODE"), "LOGIC") == "CCU2";
+ ci->sliceInfo.sd0 = int_or_default(ci->params, id("REG0_SD"), 0);
+ ci->sliceInfo.sd1 = int_or_default(ci->params, id("REG1_SD"), 0);
ci->sliceInfo.has_l6mux = false;
if (ci->ports.count(id_FXA) && ci->ports[id_FXA].net != nullptr &&
ci->ports[id_FXA].net->driver.port == id_OFX0)
diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py
index cdd3bd06..610bd331 100755
--- a/ecp5/trellis_import.py
+++ b/ecp5/trellis_import.py
@@ -119,9 +119,20 @@ def process_pio_db(ddrg, device):
pinfunc = metaitem["function"]
else:
pinfunc = None
+ dqs = -1
+ if "dqs" in metaitem:
+ tdqs = metaitem["dqs"]
+ if tdqs[0] == "L":
+ dqs = 0
+ elif tdqs[0] == "R":
+ dqs = 2048
+ suffix_size = 0
+ while tdqs[-(suffix_size+1)].isdigit():
+ suffix_size += 1
+ dqs |= int(tdqs[-suffix_size:])
bel_idx = get_bel_index(ddrg, loc, pio)
if bel_idx is not None:
- pindata.append((loc, bel_idx, bank, pinfunc))
+ pindata.append((loc, bel_idx, bank, pinfunc, dqs))
global_data = {}
quadrants = ["UL", "UR", "LL", "LR"]
@@ -142,7 +153,7 @@ speed_grade_names = ["6", "7", "8", "8_5G"]
speed_grade_cells = {}
speed_grade_pips = {}
-pip_class_to_idx = {"default": 0}
+pip_class_to_idx = {"default": 0, "zero": 1}
timing_port_xform = {
"RAD0": "D0",
@@ -188,7 +199,7 @@ def process_timing_data():
pip_class_delays = []
for i in range(len(pip_class_to_idx)):
pip_class_delays.append((50, 50, 0, 0))
-
+ pip_class_delays[pip_class_to_idx["zero"]] = (0, 0, 0, 0)
with open(timing_dbs.interconnect_db_path("ECP5", grade)) as f:
interconn_data = json.load(f)
for pipclass, pipdata in sorted(interconn_data.items()):
@@ -208,6 +219,12 @@ def process_timing_data():
def get_pip_class(wire_from, wire_to):
+
+ if "FCO" in wire_from or "FCI" in wire_to:
+ return pip_class_to_idx["zero"]
+ if "F5" in wire_from or "FX" in wire_from or "FXA" in wire_to or "FXB" in wire_to:
+ return pip_class_to_idx["zero"]
+
class_name = pip_classes.get_pip_class(wire_from, wire_to)
if class_name is None or class_name not in pip_class_to_idx:
class_name = "default"
@@ -360,7 +377,7 @@ def write_database(dev_name, chip, ddrg, endianness):
bba.l("pio_info", "PIOInfoPOD")
for pin in pindata:
- loc, bel_idx, bank, func = pin
+ loc, bel_idx, bank, func, dqs = pin
write_loc(loc, "abs_loc")
bba.u32(bel_idx, "bel_index")
if func is not None:
@@ -368,7 +385,7 @@ def write_database(dev_name, chip, ddrg, endianness):
else:
bba.r(None, "function_name")
bba.u16(bank, "bank")
- bba.u16(0, "padding")
+ bba.u16(dqs, "dqsgroup")
bba.l("tiletype_names", "RelPtr<char>")
for tt, idx in sorted(tiletype_names.items(), key=lambda x: x[1]):
diff --git a/gui/fpgaviewwidget.cc b/gui/fpgaviewwidget.cc
index 0ad90527..c932c3e7 100644
--- a/gui/fpgaviewwidget.cc
+++ b/gui/fpgaviewwidget.cc
@@ -114,7 +114,7 @@ void FPGAViewWidget::initializeGL()
initializeOpenGLFunctions();
QtImGui::initialize(this);
glClearColor(colors_.background.red() / 255, colors_.background.green() / 255, colors_.background.blue() / 255,
- 0.0);
+ 1.0);
}
float FPGAViewWidget::PickedElement::distance(Context *ctx, float wx, float wy) const
@@ -644,12 +644,16 @@ void FPGAViewWidget::mousePressEvent(QMouseEvent *event)
if (io.WantCaptureMouse)
return;
- if (event->buttons() & Qt::RightButton || event->buttons() & Qt::MidButton) {
+ bool shift = QApplication::keyboardModifiers().testFlag(Qt::ShiftModifier);
+ bool ctrl = QApplication::keyboardModifiers().testFlag(Qt::ControlModifier);
+ bool btn_right = event->buttons() & Qt::RightButton;
+ bool btn_mid = event->buttons() & Qt::MidButton;
+ bool btn_left = event->buttons() & Qt::LeftButton;
+
+ if (btn_right || btn_mid || (btn_left && shift)) {
lastDragPos_ = event->pos();
}
- if (event->buttons() & Qt::LeftButton) {
- bool ctrl = QApplication::keyboardModifiers().testFlag(Qt::ControlModifier);
-
+ if (btn_left && !shift) {
auto world = mouseToWorldCoordinates(event->x(), event->y());
auto closestOr = pickElement(world.x(), world.y());
if (!closestOr) {
@@ -681,7 +685,12 @@ void FPGAViewWidget::mouseMoveEvent(QMouseEvent *event)
if (io.WantCaptureMouse)
return;
- if (event->buttons() & Qt::RightButton || event->buttons() & Qt::MidButton) {
+ bool shift = QApplication::keyboardModifiers().testFlag(Qt::ShiftModifier);
+ bool btn_right = event->buttons() & Qt::RightButton;
+ bool btn_mid = event->buttons() & Qt::MidButton;
+ bool btn_left = event->buttons() & Qt::LeftButton;
+
+ if (btn_right || btn_mid || (btn_left && shift)) {
const int dx = event->x() - lastDragPos_.x();
const int dy = event->y() - lastDragPos_.y();
lastDragPos_ = event->pos();
diff --git a/ice40/arch.cc b/ice40/arch.cc
index 23a2130c..c822d5c4 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -53,6 +53,7 @@ void load_chipdb();
const char *chipdb_blob_384 = nullptr;
const char *chipdb_blob_1k = nullptr;
const char *chipdb_blob_5k = nullptr;
+const char *chipdb_blob_u4k = nullptr;
const char *chipdb_blob_8k = nullptr;
boost::iostreams::mapped_file_source blob_files[4];
@@ -74,6 +75,7 @@ void load_chipdb()
chipdb_blob_384 = mmap_file(0, EXTERNAL_CHIPDB_ROOT "/ice40/chipdb-384.bin");
chipdb_blob_1k = mmap_file(1, EXTERNAL_CHIPDB_ROOT "/ice40/chipdb-1k.bin");
chipdb_blob_5k = mmap_file(2, EXTERNAL_CHIPDB_ROOT "/ice40/chipdb-5k.bin");
+ chipdb_blob_u4k = mmap_file(2, EXTERNAL_CHIPDB_ROOT "/ice40/chipdb-u4k.bin");
chipdb_blob_8k = mmap_file(3, EXTERNAL_CHIPDB_ROOT "/ice40/chipdb-8k.bin");
}
#endif
@@ -100,6 +102,9 @@ Arch::Arch(ArchArgs args) : args(args)
} else if (args.type == ArchArgs::UP5K) {
fast_part = false;
chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_5k));
+ } else if (args.type == ArchArgs::U4K) {
+ fast_part = false;
+ chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_u4k));
} else if (args.type == ArchArgs::LP8K || args.type == ArchArgs::HX8K) {
fast_part = args.type == ArchArgs::HX8K;
chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_8k));
@@ -144,6 +149,8 @@ std::string Arch::getChipName() const
return "Lattice HX1K";
} else if (args.type == ArchArgs::UP5K) {
return "Lattice UP5K";
+ } else if (args.type == ArchArgs::U4K) {
+ return "Lattice U4K";
} else if (args.type == ArchArgs::LP8K) {
return "Lattice LP8K";
} else if (args.type == ArchArgs::HX8K) {
@@ -166,6 +173,8 @@ IdString Arch::archArgsToId(ArchArgs args) const
return id("hx1k");
if (args.type == ArchArgs::UP5K)
return id("up5k");
+ if (args.type == ArchArgs::U4K)
+ return id("u4k");
if (args.type == ArchArgs::LP8K)
return id("lp8k");
if (args.type == ArchArgs::HX8K)
@@ -645,6 +654,7 @@ bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay
budget = cin ? 290 : (same_y ? 380 : 670);
break;
case ArchArgs::UP5K:
+ case ArchArgs::U4K:
budget = cin ? 560 : (same_y ? 660 : 1220);
break;
#endif
@@ -1021,7 +1031,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
return TMG_IGNORE;
} else if (cell->type == id_SB_GB) {
if (port == id_GLOBAL_BUFFER_OUTPUT)
- return TMG_COMB_OUTPUT;
+ return cell->gbInfo.forPadIn ? TMG_GEN_CLOCK : TMG_COMB_OUTPUT;
return TMG_COMB_INPUT;
} else if (cell->type == id_SB_WARMBOOT) {
return TMG_ENDPOINT;
@@ -1053,7 +1063,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
NPNR_ASSERT(has_ld);
if (args.type == ArchArgs::LP1K || args.type == ArchArgs::LP8K || args.type == ArchArgs::LP384) {
info.setup.delay = 30 + dlut.delay;
- } else if (args.type == ArchArgs::UP5K) {
+ } else if (args.type == ArchArgs::UP5K || args.type == ArchArgs::U4K) { // XXX verify u4k
info.setup.delay = dlut.delay - 50;
} else {
info.setup.delay = 20 + dlut.delay;
@@ -1083,7 +1093,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
if (args.type == ArchArgs::LP1K || args.type == ArchArgs::LP8K || args.type == ArchArgs::LP384) {
io_setup = 115;
io_clktoq = 210;
- } else if (args.type == ArchArgs::UP5K) {
+ } else if (args.type == ArchArgs::UP5K || args.type == ArchArgs::U4K) {
io_setup = 205;
io_clktoq = 1005;
}
diff --git a/ice40/arch.h b/ice40/arch.h
index b25e3aee..706043b2 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -248,11 +248,13 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD {
extern const char *chipdb_blob_384;
extern const char *chipdb_blob_1k;
extern const char *chipdb_blob_5k;
+extern const char *chipdb_blob_u4k;
extern const char *chipdb_blob_8k;
#else
extern const char chipdb_blob_384[];
extern const char chipdb_blob_1k[];
extern const char chipdb_blob_5k[];
+extern const char chipdb_blob_u4k[];
extern const char chipdb_blob_8k[];
#endif
@@ -400,7 +402,8 @@ struct ArchArgs
LP8K,
HX1K,
HX8K,
- UP5K
+ UP5K,
+ U4K
} type = NONE;
std::string package;
};
diff --git a/ice40/arch_pybindings.cc b/ice40/arch_pybindings.cc
index 3fafb1f6..f0ca584b 100644
--- a/ice40/arch_pybindings.cc
+++ b/ice40/arch_pybindings.cc
@@ -39,6 +39,7 @@ void arch_wrap_python()
.value("HX1K", ArchArgs::HX1K)
.value("HX8K", ArchArgs::HX8K)
.value("UP5K", ArchArgs::UP5K)
+ .value("U4K", ArchArgs::U4K)
.export_values();
class_<BelId>("BelId").def_readwrite("index", &BelId::index);
diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index 141c218b..fe0d592d 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -297,6 +297,9 @@ void write_asc(const Context *ctx, std::ostream &out)
case ArchArgs::UP5K:
out << ".device 5k" << std::endl;
break;
+ case ArchArgs::U4K:
+ out << ".device u4k" << std::endl;
+ break;
default:
NPNR_ASSERT_FALSE("unsupported device type\n");
}
@@ -660,7 +663,9 @@ void write_asc(const Context *ctx, std::ostream &out)
{"B_SIGNED", 1}};
configure_extra_cell(config, ctx, cell.second.get(), mac16_params, false, std::string("IpConfig."));
} else if (cell.second->type == ctx->id("ICESTORM_HFOSC")) {
- const std::vector<std::pair<std::string, int>> hfosc_params = {{"CLKHF_DIV", 2}, {"TRIM_EN", 1}};
+ std::vector<std::pair<std::string, int>> hfosc_params = {{"CLKHF_DIV", 2}};
+ if (ctx->args.type != ArchArgs::U4K)
+ hfosc_params.push_back(std::pair<std::string, int>("TRIM_EN", 1));
configure_extra_cell(config, ctx, cell.second.get(), hfosc_params, true, std::string("IpConfig."));
} else if (cell.second->type == ctx->id("ICESTORM_PLL")) {
@@ -753,6 +758,8 @@ void write_asc(const Context *ctx, std::ostream &out)
setColBufCtrl = (y == 8 || y == 9 || y == 24 || y == 25);
} else if (ctx->args.type == ArchArgs::UP5K) {
setColBufCtrl = (y == 4 || y == 5 || y == 14 || y == 15 || y == 26 || y == 27);
+ } else if (ctx->args.type == ArchArgs::U4K) {
+ setColBufCtrl = (y == 4 || y == 5 || y == 16 || y == 17);
} else if (ctx->args.type == ArchArgs::LP384) {
setColBufCtrl = false;
}
@@ -884,6 +891,9 @@ void read_config(Context *ctx, std::istream &in, chipconfig_t &config)
case ArchArgs::UP5K:
expected = "5k";
break;
+ case ArchArgs::U4K:
+ expected = "u4k";
+ break;
default:
log_error("unsupported device type\n");
}
diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index 96231b26..42ca6ac1 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -492,7 +492,7 @@ def wiredelay(wire_idx, db):
def init_tiletypes(device):
global num_tile_types, tile_sizes, tile_bits
- if device == "5k":
+ if device in ["5k", "u4k"]:
num_tile_types = 10
else:
num_tile_types = 5
@@ -954,6 +954,27 @@ def add_bel_ec(ec):
add_pll_clock_output(bel, ec, entry)
else:
extra_cell_config[bel].append(entry)
+ if ectype == "MAC16":
+ if y == 5:
+ last_dsp_y = 0 # dummy, but the wire is needed
+ elif y == 10:
+ last_dsp_y = 5
+ elif y == 13:
+ last_dsp_y = 5
+ elif y == 15:
+ last_dsp_y = 10
+ elif y == 23:
+ last_dsp_y = 23
+ else:
+ assert False, "unknown DSP y " + str(y)
+ wire_signextin = add_wire(x, last_dsp_y, "dsp/signextout")
+ wire_signextout = add_wire(x, y, "dsp/signextout")
+ wire_accumci = add_wire(x, last_dsp_y, "dsp/accumco")
+ wire_accumco = add_wire(x, y, "dsp/accumco")
+ add_bel_input(bel, wire_signextin, "SIGNEXTIN")
+ add_bel_output(bel, wire_signextout, "SIGNEXTOUT")
+ add_bel_input(bel, wire_accumci, "ACCUMCI")
+ add_bel_output(bel, wire_accumco, "ACCUMCO")
cell_timings = {}
tmport_to_constids = {
diff --git a/ice40/constids.inc b/ice40/constids.inc
index e1c4992e..366a3a9d 100644
--- a/ice40/constids.inc
+++ b/ice40/constids.inc
@@ -247,6 +247,11 @@ X(O_6)
X(O_7)
X(O_8)
X(O_9)
+X(SIGNEXTIN)
+X(SIGNEXTOUT)
+X(ACCUMCI)
+X(ACCUMCO)
+
X(CLKHF)
X(CLKHFEN)
@@ -426,6 +431,7 @@ X(SB_WARMBOOT)
X(ICESTORM_DSP)
X(ICESTORM_HFOSC)
X(ICESTORM_LFOSC)
+X(SMCCLK)
X(SB_I2C)
X(SB_SPI)
X(IO_I3C)
diff --git a/ice40/delay.cc b/ice40/delay.cc
index 54905551..707208d8 100644
--- a/ice40/delay.cc
+++ b/ice40/delay.cc
@@ -138,7 +138,7 @@ struct model_params_t
if (args.type == ArchArgs::LP384 || args.type == ArchArgs::LP1K || args.type == ArchArgs::LP8K)
return model_lp8k;
- if (args.type == ArchArgs::UP5K)
+ if (args.type == ArchArgs::UP5K || args.type == ArchArgs::U4K)
return model_up5k;
NPNR_ASSERT(0);
diff --git a/ice40/family.cmake b/ice40/family.cmake
index 877b27ee..e1fcec16 100644
--- a/ice40/family.cmake
+++ b/ice40/family.cmake
@@ -5,7 +5,7 @@ if (NOT EXTERNAL_CHIPDB)
target_compile_definitions(${target} PRIVATE ICE40_HX1K_ONLY=1)
endforeach (target)
else()
- set(devices 384 1k 5k 8k)
+ set(devices 384 1k 5k u4k 8k)
endif()
set(DB_PY ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdb.py)
@@ -20,10 +20,13 @@ if (NOT EXTERNAL_CHIPDB)
target_sources(ice40_chipdb PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/ice40/resource/embed.cc)
set_source_files_properties(${CMAKE_CURRENT_SOURCE_DIR}/ice40/resources/chipdb.rc PROPERTIES LANGUAGE RC)
foreach (dev ${devices})
- if (dev EQUAL "5k")
+ if (dev STREQUAL "5k")
set(OPT_FAST "")
set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_up5k.txt)
- elseif(dev EQUAL "384")
+ elseif (dev STREQUAL "u4k")
+ set(OPT_FAST "")
+ set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_u4k.txt)
+ elseif(dev STREQUAL "384")
set(OPT_FAST "")
set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_lp384.txt)
else()
@@ -52,10 +55,13 @@ if (NOT EXTERNAL_CHIPDB)
else()
target_compile_options(ice40_chipdb PRIVATE -g0 -O0 -w)
foreach (dev ${devices})
- if (dev EQUAL "5k")
+ if (dev STREQUAL "5k")
set(OPT_FAST "")
set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_up5k.txt)
- elseif(dev EQUAL "384")
+ elseif (dev STREQUAL "u4k")
+ set(OPT_FAST "")
+ set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_u4k.txt)
+ elseif(dev STREQUAL "384")
set(OPT_FAST "")
set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_lp384.txt)
else()
diff --git a/ice40/main.cc b/ice40/main.cc
index 286f68db..2313c2ae 100644
--- a/ice40/main.cc
+++ b/ice40/main.cc
@@ -60,6 +60,7 @@ po::options_description Ice40CommandHandler::getArchOptions()
specific.add_options()("hx1k", "set device type to iCE40HX1K");
specific.add_options()("hx8k", "set device type to iCE40HX8K");
specific.add_options()("up5k", "set device type to iCE40UP5K");
+ specific.add_options()("u4k", "set device type to iCE5LP4K");
#endif
specific.add_options()("package", po::value<std::string>(), "set device package");
specific.add_options()("pcf", po::value<std::string>(), "PCF constraints file to ingest");
@@ -78,7 +79,7 @@ void Ice40CommandHandler::validate()
{
conflicting_options(vm, "read", "json");
if ((vm.count("lp384") + vm.count("lp1k") + vm.count("lp8k") + vm.count("hx1k") + vm.count("hx8k") +
- vm.count("up5k")) > 1)
+ vm.count("up5k") + vm.count("u4k")) > 1)
log_error("Only one device type can be set\n");
}
@@ -147,6 +148,11 @@ std::unique_ptr<Context> Ice40CommandHandler::createContext()
chipArgs.package = "sg48";
}
+ if (vm.count("u4k")) {
+ chipArgs.type = ArchArgs::U4K;
+ chipArgs.package = "sg48";
+ }
+
if (chipArgs.type == ArchArgs::NONE) {
chipArgs.type = ArchArgs::HX1K;
chipArgs.package = "tq144";
diff --git a/ice40/project.cc b/ice40/project.cc
index 47c0903d..bbd82fd7 100644
--- a/ice40/project.cc
+++ b/ice40/project.cc
@@ -56,6 +56,9 @@ std::unique_ptr<Context> ProjectHandler::createContext(pt::ptree &root)
if (arch_type == "up5k") {
chipArgs.type = ArchArgs::UP5K;
}
+ if (arch_type == "u4k") {
+ chipArgs.type = ArchArgs::U4K;
+ }
chipArgs.package = root.get<std::string>("project.arch.package");
return std::unique_ptr<Context>(new Context(chipArgs));
diff --git a/ice40/resource/chipdb.rc b/ice40/resource/chipdb.rc
index a6f2dbe8..46459538 100644
--- a/ice40/resource/chipdb.rc
+++ b/ice40/resource/chipdb.rc
@@ -3,4 +3,5 @@
IDR_CHIPDB_384 BINARYFILE "..\chipdbs\chipdb-384.bin"
IDR_CHIPDB_1K BINARYFILE "..\chipdbs\chipdb-1k.bin"
IDR_CHIPDB_5K BINARYFILE "..\chipdbs\chipdb-5k.bin"
+IDR_CHIPDB_U4K BINARYFILE "..\chipdbs\chipdb-u4k.bin"
IDR_CHIPDB_8K BINARYFILE "..\chipdbs\chipdb-8k.bin"
diff --git a/ice40/resource/embed.cc b/ice40/resource/embed.cc
index 74f2eee9..048ac474 100644
--- a/ice40/resource/embed.cc
+++ b/ice40/resource/embed.cc
@@ -8,6 +8,7 @@ NEXTPNR_NAMESPACE_BEGIN
const char *chipdb_blob_384;
const char *chipdb_blob_1k;
const char *chipdb_blob_5k;
+const char *chipdb_blob_u4k;
const char *chipdb_blob_8k;
const char *LoadFileInResource(int name, int type, DWORD &size)
@@ -24,7 +25,8 @@ void load_chipdb()
chipdb_blob_384 = LoadFileInResource(IDR_CHIPDB_384, BINARYFILE, size);
chipdb_blob_1k = LoadFileInResource(IDR_CHIPDB_1K, BINARYFILE, size);
chipdb_blob_5k = LoadFileInResource(IDR_CHIPDB_5K, BINARYFILE, size);
+ chipdb_blob_u4k = LoadFileInResource(IDR_CHIPDB_U4K, BINARYFILE, size);
chipdb_blob_8k = LoadFileInResource(IDR_CHIPDB_8K, BINARYFILE, size);
}
-NEXTPNR_NAMESPACE_END \ No newline at end of file
+NEXTPNR_NAMESPACE_END
diff --git a/ice40/resource/resource.h b/ice40/resource/resource.h
index 46997ae5..4dacbf61 100644
--- a/ice40/resource/resource.h
+++ b/ice40/resource/resource.h
@@ -3,3 +3,4 @@
#define IDR_CHIPDB_1K 102
#define IDR_CHIPDB_5K 103
#define IDR_CHIPDB_8K 104
+#define IDR_CHIPDB_U4K 105
diff --git a/tests b/tests
-Subproject 691dfb8204131bec7f1c5e139764bf418640f94
+Subproject ee3ff3c4bdce20c47bd6c35a2f7430497b28380
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-28 01:17:16 +0000