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-rw-r--r--ice40/bitstream.cc2
-rw-r--r--ice40/chip.cc14
-rw-r--r--ice40/chip.h84
-rw-r--r--ice40/chipdb.py364
4 files changed, 350 insertions, 114 deletions
diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index 9309a7da..2913303c 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -31,7 +31,7 @@ const ConfigEntryPOD &find_config(const TileInfoPOD &tile,
const std::string &name)
{
for (int i = 0; i < tile.num_config_entries; i++) {
- if (std::string(tile.entries[i].name) == name) {
+ if (std::string(tile.entries[i].name.get()) == name) {
return tile.entries[i];
}
}
diff --git a/ice40/chip.cc b/ice40/chip.cc
index 1255dfc8..7b1afd2e 100644
--- a/ice40/chip.cc
+++ b/ice40/chip.cc
@@ -153,7 +153,7 @@ BelId Chip::getBelByName(IdString name) const
if (bel_by_name.empty()) {
for (int i = 0; i < chip_info.num_bels; i++)
- bel_by_name[chip_info.bel_data[i].name] = i;
+ bel_by_name[chip_info.bel_data[i].name.get()] = i;
}
auto it = bel_by_name.find(name);
@@ -190,7 +190,7 @@ WireId Chip::getWireBelPin(BelId bel, PortPin pin) const
assert(bel != BelId());
int num_bel_wires = chip_info.bel_data[bel.index].num_bel_wires;
- BelWirePOD *bel_wires = chip_info.bel_data[bel.index].bel_wires;
+ const BelWirePOD *bel_wires = chip_info.bel_data[bel.index].bel_wires.get();
for (int i = 0; i < num_bel_wires; i++)
if (bel_wires[i].port == pin) {
@@ -209,7 +209,7 @@ WireId Chip::getWireByName(IdString name) const
if (wire_by_name.empty()) {
for (int i = 0; i < chip_info.num_wires; i++)
- wire_by_name[chip_info.wire_data[i].name] = i;
+ wire_by_name[chip_info.wire_data[i].name.get()] = i;
}
auto it = wire_by_name.find(name);
@@ -248,11 +248,11 @@ IdString Chip::getPipName(PipId pip) const
int y = chip_info.pip_data[pip.index].y;
std::string src_name =
- chip_info.wire_data[chip_info.pip_data[pip.index].src].name;
+ chip_info.wire_data[chip_info.pip_data[pip.index].src].name.get();
std::replace(src_name.begin(), src_name.end(), '/', '.');
std::string dst_name =
- chip_info.wire_data[chip_info.pip_data[pip.index].dst].name;
+ chip_info.wire_data[chip_info.pip_data[pip.index].dst].name.get();
std::replace(dst_name.begin(), dst_name.end(), '/', '.');
return "X" + std::to_string(x) + "/Y" + std::to_string(y) + "/" + src_name +
@@ -264,7 +264,7 @@ IdString Chip::getPipName(PipId pip) const
BelId Chip::getPackagePinBel(const std::string &pin) const
{
for (int i = 0; i < package_info->num_pins; i++) {
- if (package_info->pins[i].name == pin) {
+ if (package_info->pins[i].name.get() == pin) {
BelId id;
id.index = package_info->pins[i].bel_index;
return id;
@@ -277,7 +277,7 @@ std::string Chip::getBelPackagePin(BelId bel) const
{
for (int i = 0; i < package_info->num_pins; i++) {
if (package_info->pins[i].bel_index == bel.index) {
- return std::string(package_info->pins[i].name);
+ return std::string(package_info->pins[i].name.get());
}
}
return "";
diff --git a/ice40/chip.h b/ice40/chip.h
index 5eeca5e9..9f15bf60 100644
--- a/ice40/chip.h
+++ b/ice40/chip.h
@@ -72,31 +72,38 @@ PortPin portPinFromId(IdString id);
// -----------------------------------------------------------------------
-#if 0
+/**** Everything in this section must be kept in sync with chipdb.py ****/
+
template <typename T>
struct RelPtr {
- int offset;
+ int32_t offset;
- // RelPtr(T *ptr) : offset(reinterpret_cast<const char*>(ptr) -
- // reinterpret_cast<const char*>(this)) {}
+ // void set(const T *ptr) {
+ // offset = reinterpret_cast<const char*>(ptr) - reinterpret_cast<const char*>(this);
+ // }
+
+ const T*get() const {
+ return reinterpret_cast<const T*>(reinterpret_cast<const char*>(this) + offset);
+ }
- T&operator*() {
- return *reinterpret_cast<T*>(reinterpret_cast<char*>(this) + offset);
+ const T&operator[](size_t index) const {
+ return get()[index];
}
- T*operator->() {
- return reinterpret_cast<T*>(reinterpret_cast<char*>(this) + offset);
+ const T&operator*() const {
+ return *(get());
+ }
+
+ const T*operator->() const {
+ return get();
}
};
-#else
-template <typename T> using RelPtr = T *;
-#endif
struct BelWirePOD
{
int32_t wire_index;
PortPin port;
-};
+} __attribute__((packed));
struct BelInfoPOD
{
@@ -105,13 +112,14 @@ struct BelInfoPOD
int32_t num_bel_wires;
RelPtr<BelWirePOD> bel_wires;
int8_t x, y, z;
-};
+ int8_t padding_0;
+} __attribute__((packed));
struct BelPortPOD
{
int32_t bel_index;
PortPin port;
-};
+} __attribute__((packed));
struct PipInfoPOD
{
@@ -120,7 +128,7 @@ struct PipInfoPOD
int8_t x, y;
int16_t switch_mask;
int32_t switch_index;
-};
+} __attribute__((packed));
struct WireInfoPOD
{
@@ -132,21 +140,21 @@ struct WireInfoPOD
BelPortPOD bel_uphill;
RelPtr<BelPortPOD> bels_downhill;
- int8_t x, y;
-};
+ int16_t x, y;
+} __attribute__((packed));
struct PackagePinPOD
{
- const char *name;
+ RelPtr<char> name;
int32_t bel_index;
-};
+} __attribute__((packed));
struct PackageInfoPOD
{
const char *name;
int num_pins;
PackagePinPOD *pins;
-};
+} __attribute__((packed));
enum TileType
{
@@ -160,21 +168,21 @@ enum TileType
struct ConfigBitPOD
{
int8_t row, col;
-};
+} __attribute__((packed));
struct ConfigEntryPOD
{
- const char *name;
- int num_bits;
- ConfigBitPOD *bits;
-};
+ RelPtr<char> name;
+ int32_t num_bits;
+ RelPtr<ConfigBitPOD> bits;
+} __attribute__((packed));
struct TileInfoPOD
{
int8_t cols, rows;
int num_config_entries;
ConfigEntryPOD *entries;
-};
+} __attribute__((packed));
static const int max_switch_bits = 5;
@@ -183,13 +191,13 @@ struct SwitchInfoPOD
int8_t x, y;
int num_bits;
ConfigBitPOD cbits[max_switch_bits];
-};
+} __attribute__((packed));
struct IerenInfoPOD
{
int8_t iox, ioy, ioz;
int8_t ierx, iery, ierz;
-};
+} __attribute__((packed));
struct BitstreamInfoPOD
{
@@ -197,7 +205,7 @@ struct BitstreamInfoPOD
TileInfoPOD *tiles_nonrouting;
SwitchInfoPOD *switches;
IerenInfoPOD *ierens;
-};
+} __attribute__((packed));
struct ChipInfoPOD
{
@@ -210,13 +218,15 @@ struct ChipInfoPOD
TileType *tile_grid;
BitstreamInfoPOD *bits_info;
PackageInfoPOD *packages_data;
-};
+} __attribute__((packed));
extern ChipInfoPOD chip_info_384;
extern ChipInfoPOD chip_info_1k;
extern ChipInfoPOD chip_info_5k;
extern ChipInfoPOD chip_info_8k;
+/************************ End of chipdb section. ************************/
+
// -----------------------------------------------------------------------
struct BelId
@@ -329,7 +339,7 @@ struct BelRange
struct BelPinIterator
{
- BelPortPOD *ptr = nullptr;
+ const BelPortPOD *ptr = nullptr;
void operator++() { ptr++; }
bool operator!=(const BelPinIterator &other) const
@@ -411,7 +421,7 @@ struct AllPipRange
struct PipIterator
{
- int *cursor = nullptr;
+ const int *cursor = nullptr;
void operator++() { cursor++; }
bool operator!=(const PipIterator &other) const
@@ -476,7 +486,7 @@ struct Chip
IdString getBelName(BelId bel) const
{
assert(bel != BelId());
- return chip_info.bel_data[bel.index].name;
+ return chip_info.bel_data[bel.index].name.get();
}
void bindBel(BelId bel, IdString cell)
@@ -555,7 +565,7 @@ struct Chip
{
BelPinRange range;
assert(wire != WireId());
- range.b.ptr = chip_info.wire_data[wire.index].bels_downhill;
+ range.b.ptr = chip_info.wire_data[wire.index].bels_downhill.get();
range.e.ptr =
range.b.ptr + chip_info.wire_data[wire.index].num_bels_downhill;
return range;
@@ -568,7 +578,7 @@ struct Chip
IdString getWireName(WireId wire) const
{
assert(wire != WireId());
- return chip_info.wire_data[wire.index].name;
+ return chip_info.wire_data[wire.index].name.get();
}
void bindWire(WireId wire, IdString net)
@@ -687,7 +697,7 @@ struct Chip
{
PipRange range;
assert(wire != WireId());
- range.b.cursor = chip_info.wire_data[wire.index].pips_downhill;
+ range.b.cursor = chip_info.wire_data[wire.index].pips_downhill.get();
range.e.cursor =
range.b.cursor + chip_info.wire_data[wire.index].num_downhill;
return range;
@@ -697,7 +707,7 @@ struct Chip
{
PipRange range;
assert(wire != WireId());
- range.b.cursor = chip_info.wire_data[wire.index].pips_uphill;
+ range.b.cursor = chip_info.wire_data[wire.index].pips_uphill.get();
range.e.cursor =
range.b.cursor + chip_info.wire_data[wire.index].num_uphill;
return range;
diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index f8fe8b5d..73787ca3 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -4,6 +4,9 @@ import sys
import re
import textwrap
+endianness = "le"
+compact_output = True
+
dev_name = None
dev_width = None
dev_height = None
@@ -39,6 +42,25 @@ tile_bits = [[] for _ in range(num_tile_types)]
cbit_re = re.compile(r'B(\d+)\[(\d+)\]')
+portpins = dict()
+beltypes = dict()
+
+with open("ice40/portpins.inc") as f:
+ for line in f:
+ line = line.replace("(", " ")
+ line = line.replace(")", " ")
+ line = line.split()
+ if len(line) == 0:
+ continue
+ assert len(line) == 2
+ assert line[0] == "X"
+ idx = len(portpins) + 1
+ portpins[line[1]] = idx
+
+beltypes["ICESTORM_LC"] = 1
+beltypes["ICESTORM_RAM"] = 2
+beltypes["SB_IO"] = 3
+beltypes["SB_GB"] = 4
def maj_wire_name(name):
if re.match(r"lutff_\d/(in|out)", name[2]):
@@ -344,83 +366,271 @@ elif dev_name == "384":
add_bel_gb( 3, 0, 5)
add_bel_gb( 3, 9, 4)
+class BinaryBlobAssembler:
+ def __init__(self, cname, endianness, ctype = "unsigned char"):
+ assert endianness in ["le", "be"]
+ self.cname = cname
+ self.ctype = ctype
+ self.endianness = endianness
+ self.finalized = False
+ self.data = bytearray()
+ self.comments = dict()
+ self.labels = dict()
+ self.exports = set()
+ self.labels_byaddr = dict()
+ self.ltypes_byaddr = dict()
+ self.strings = dict()
+ self.refs = dict()
+
+ def l(self, name, ltype = None, export = False):
+ assert not self.finalized
+ assert name not in self.labels
+ assert len(self.data) not in self.labels_byaddr
+ self.labels[name] = len(self.data)
+ if ltype is not None:
+ self.ltypes_byaddr[len(self.data)] = ltype
+ self.labels_byaddr[len(self.data)] = name
+ if export:
+ assert ltype is not None
+ self.exports.add(len(self.data))
+
+ def r(self, name, comment):
+ assert not self.finalized
+ assert len(self.data) % 4 == 0
+ assert len(self.data) not in self.refs
+ if name is not None:
+ self.refs[len(self.data)] = (name, comment)
+ self.data.append(0)
+ self.data.append(0)
+ self.data.append(0)
+ self.data.append(0)
+ if (name is None) and (comment is not None):
+ self.comments[len(self.data)] = comment + " (null reference)"
+
+ def s(self, s, comment):
+ assert not self.finalized
+ if s not in self.strings:
+ index = len(self.strings)
+ self.strings[s] = index
+ else:
+ index = self.strings[s]
+ self.r("str%d" % index, '%s: "%s"' % (comment, s))
+
+ def u8(self, v, comment):
+ assert not self.finalized
+ self.data.append(v)
+ if comment is not None:
+ self.comments[len(self.data)] = comment
+
+ def u16(self, v, comment):
+ assert not self.finalized
+ assert len(self.data) % 2 == 0
+ if self.endianness == "le":
+ self.data.append(v & 255)
+ self.data.append((v >> 8) & 255)
+ elif self.endianness == "be":
+ self.data.append((v >> 8) & 255)
+ self.data.append(v & 255)
+ else:
+ assert 0
+ if comment is not None:
+ self.comments[len(self.data)] = comment
+
+ def u32(self, v, comment):
+ assert not self.finalized
+ assert len(self.data) % 4 == 0
+ if self.endianness == "le":
+ self.data.append(v & 255)
+ self.data.append((v >> 8) & 255)
+ self.data.append((v >> 16) & 255)
+ self.data.append((v >> 24) & 255)
+ elif self.endianness == "be":
+ self.data.append((v >> 24) & 255)
+ self.data.append((v >> 16) & 255)
+ self.data.append((v >> 8) & 255)
+ self.data.append(v & 255)
+ else:
+ assert 0
+ if comment is not None:
+ self.comments[len(self.data)] = comment
+
+ def finalize(self):
+ assert not self.finalized
+ for s, index in self.strings.items():
+ self.l("str%d" % index, "char")
+ for c in s:
+ self.data.append(ord(c))
+ self.data.append(0)
+ self.finalized = True
+ cursor = 0
+ while cursor < len(self.data):
+ if cursor in self.refs:
+ v = self.labels[self.refs[cursor][0]] - cursor
+ if self.endianness == "le":
+ self.data[cursor+0] = (v & 255)
+ self.data[cursor+1] = ((v >> 8) & 255)
+ self.data[cursor+2] = ((v >> 16) & 255)
+ self.data[cursor+3] = ((v >> 24) & 255)
+ elif self.endianness == "be":
+ self.data[cursor+0] = ((v >> 24) & 255)
+ self.data[cursor+1] = ((v >> 16) & 255)
+ self.data[cursor+2] = ((v >> 8) & 255)
+ self.data[cursor+3] = (v & 255)
+ else:
+ assert 0
+ cursor += 4
+ else:
+ cursor += 1
+
+ def write_verbose_c(self, f):
+ assert self.finalized
+ print("%s %s[%d] = {" % (self.ctype, self.cname, len(self.data)), file=f)
+ cursor = 0
+ bytecnt = 0
+ while cursor < len(self.data):
+ if cursor in self.comments:
+ if bytecnt == 0:
+ print(" ", end="", file=f)
+ print(" // %s" % self.comments[cursor], file=f)
+ bytecnt = 0
+ if cursor in self.labels_byaddr:
+ if bytecnt != 0:
+ print(file=f)
+ if cursor in self.exports:
+ print("#define %s ((%s*)(%s+%d))" % (self.labels_byaddr[cursor], self.ltypes_byaddr[cursor], self.cname, cursor), file=f)
+ else:
+ print(" // [%d] %s" % (cursor, self.labels_byaddr[cursor]), file=f)
+ bytecnt = 0
+ if cursor in self.refs:
+ if bytecnt != 0:
+ print(file=f)
+ print(" ", end="", file=f)
+ print(" %-4s" % ("%d," % self.data[cursor+0]), end="", file=f)
+ print(" %-4s" % ("%d," % self.data[cursor+1]), end="", file=f)
+ print(" %-4s" % ("%d," % self.data[cursor+2]), end="", file=f)
+ print(" %-4s" % ("%d," % self.data[cursor+3]), end="", file=f)
+ print(" // [%d] %s (reference to %s)" % (cursor, self.refs[cursor][1], self.refs[cursor][0]), file=f)
+ bytecnt = 0
+ cursor += 4
+ else:
+ if bytecnt == 0:
+ print(" ", end="", file=f)
+ print(" %-4s" % ("%d," % self.data[cursor]), end=("" if bytecnt < 15 else "\n"), file=f)
+ bytecnt = (bytecnt + 1) & 15
+ cursor += 1
+ if bytecnt != 0:
+ print(file=f)
+ print("};", file=f)
+
+ def write_compact_c(self, f):
+ assert self.finalized
+ print("%s %s[%d] = {" % (self.ctype, self.cname, len(self.data)), file=f)
+ column = 0
+ for v in self.data:
+ if column == 0:
+ print(" ", end="", file=f)
+ column += 2
+ s = "%d," % v
+ print(s, end="", file=f)
+ column += len(s)
+ if column > 75:
+ print(file=f)
+ column = 0
+ if column != 0:
+ print(file=f)
+ for cursor in self.exports:
+ print("#define %s ((%s*)(%s+%d))" % (self.labels_byaddr[cursor], self.ltypes_byaddr[cursor], self.cname, cursor), file=f)
+ print("};", file=f)
+
+bba = BinaryBlobAssembler("binblob_%s" % dev_name, endianness, "static uint8_t")
+
print('#include "nextpnr.h"')
print('namespace {')
print('USING_NEXTPNR_NAMESPACE')
index = 0
-print("static BelWirePOD bel_wires[] = {")
for bel in range(len(bel_name)):
- print("#define bel_wires_%d (bel_wires+%d)" % (bel, index))
+ bba.l("bel_wires_%d" % bel, "BelWirePOD")
for i in range(len(bel_wires[bel])):
- print(" {%d, PIN_%s}," % bel_wires[bel][i])
+ bba.u32(bel_wires[bel][i][0], "wire_index")
+ bba.u32(portpins[bel_wires[bel][i][1]], "port")
index += 1
-print("};")
-print("static BelInfoPOD bel_data_%s[%d] = {" % (dev_name, len(bel_name)))
+bba.l("bel_data", "BelInfoPOD", export=True)
for bel in range(len(bel_name)):
- print(" {\"%s\", TYPE_%s, %d, bel_wires_%d, %d, %d, %d}%s" % (bel_name[bel], bel_type[bel],
- len(bel_wires[bel]), bel, bel_pos[bel][0], bel_pos[bel][1], bel_pos[bel][2],
- "," if bel+1 < len(bel_name) else ""))
-print("};")
+ bba.s(bel_name[bel], "name")
+ bba.u32(beltypes[bel_type[bel]], "type")
+ bba.u32(len(bel_wires[bel]), "num_bel_wires")
+ bba.r("bel_wires_%d" % bel, "bel_wires")
+ bba.u8(bel_pos[bel][0], "x")
+ bba.u8(bel_pos[bel][1], "y")
+ bba.u8(bel_pos[bel][2], "z")
+ bba.u8(0, "padding")
wireinfo = list()
pipinfo = list()
pipcache = dict()
-uppips_array = list()
-downpips_array = list()
-downbels_array = list()
-
for wire in range(num_wires):
if wire in wire_uphill:
pips = list()
for src in wire_uphill[wire]:
if (src, wire) not in pipcache:
pipcache[(src, wire)] = len(pipinfo)
- pipinfo.append(" {%d, %d, 1.0, %d, %d, %d, %d}" % (src, wire, pip_xy[(src, wire)][0], pip_xy[(src, wire)][1], pip_xy[(src, wire)][2], pip_xy[(src, wire)][3]))
- pips.append("%d" % pipcache[(src, wire)])
+ pipinfo.append(" {%d, %d, 1, %d, %d, %d, %d}" % (src, wire, pip_xy[(src, wire)][0], pip_xy[(src, wire)][1], pip_xy[(src, wire)][2], pip_xy[(src, wire)][3]))
+ pips.append(pipcache[(src, wire)])
num_uphill = len(pips)
list_uphill = "wire%d_uppips" % wire
- print("#define wire%d_uppips (wire_uppips+%d)" % (wire, len(uppips_array)))
- uppips_array += pips
+ bba.l(list_uphill, "int32_t")
+ for p in pips:
+ bba.u32(p, None)
else:
num_uphill = 0
- list_uphill = "nullptr"
+ list_uphill = None
if wire in wire_downhill:
pips = list()
for dst in wire_downhill[wire]:
if (wire, dst) not in pipcache:
pipcache[(wire, dst)] = len(pipinfo)
- pipinfo.append(" {%d, %d, 1.0, %d, %d, %d, %d}" % (wire, dst, pip_xy[(wire, dst)][0], pip_xy[(wire, dst)][1], pip_xy[(wire, dst)][2], pip_xy[(wire, dst)][3]))
- pips.append("%d" % pipcache[(wire, dst)])
+ pipinfo.append(" {%d, %d, 1, %d, %d, %d, %d}" % (wire, dst, pip_xy[(wire, dst)][0], pip_xy[(wire, dst)][1], pip_xy[(wire, dst)][2], pip_xy[(wire, dst)][3]))
+ pips.append(pipcache[(wire, dst)])
num_downhill = len(pips)
list_downhill = "wire%d_downpips" % wire
- print("#define wire%d_downpips (wire_downpips+%d)" % (wire, len(downpips_array)))
- downpips_array += pips
+ bba.l(list_downhill, "int32_t")
+ for p in pips:
+ bba.u32(p, None)
else:
num_downhill = 0
- list_downhill = "nullptr"
+ list_downhill = None
if wire in wire_downhill_belports:
num_bels_downhill = len(wire_downhill_belports[wire])
-
- print("#define wire%d_downbels (wire_downbels+%d)" % (wire, len(downbels_array)))
- downbels_array += ["{%d, PIN_%s}" % it for it in wire_downhill_belports[wire]]
+ bba.l("wire%d_downbels" % wire, "BelPortPOD")
+ for belport in wire_downhill_belports[wire]:
+ bba.u32(belport[0], "bel_index")
+ bba.u32(portpins[belport[1]], "port")
else:
num_bels_downhill = 0
- info = " {"
- info += "\"X%d/Y%d/%s\", " % wire_names_r[wire]
- info += "%d, %d, %s, %s, %d, " % (num_uphill, num_downhill, list_uphill, list_downhill, num_bels_downhill)
+ info = dict()
+ info["name"] = "X%d/Y%d/%s" % wire_names_r[wire]
+
+ info["num_uphill"] = num_uphill
+ info["list_uphill"] = list_uphill
+
+ info["num_downhill"] = num_downhill
+ info["list_downhill"] = list_downhill
+
+ info["num_bels_downhill"] = num_bels_downhill
+ info["list_bels_downhill"] = ("wire%d_downbels" % wire) if num_bels_downhill > 0 else None
if wire in wire_uphill_belport:
- info += "{%d, PIN_%s}, " % wire_uphill_belport[wire]
+ info["uphill_bel"] = wire_uphill_belport[wire][0]
+ info["uphill_pin"] = portpins[wire_uphill_belport[wire][1]]
else:
- info += "{-1, PIN_NONE}, "
-
- info += ("wire%d_downbels, " % wire) if num_bels_downhill > 0 else "nullptr, "
+ info["uphill_bel"] = -1
+ info["uphill_pin"] = 0
avg_x, avg_y = 0, 0
if wire in wire_xy:
@@ -430,22 +640,11 @@ for wire in range(num_wires):
avg_x /= len(wire_xy[wire])
avg_y /= len(wire_xy[wire])
- info += "%d, %d}" % (round(avg_x), round(avg_y))
+ info["x"] = int(round(avg_x))
+ info["y"] = int(round(avg_y))
wireinfo.append(info)
-print("static int wire_uppips[] = {")
-print(" " + "\n ".join(textwrap.wrap(", ".join(uppips_array))))
-print("};");
-
-print("static int wire_downpips[] = {")
-print(" " + "\n ".join(textwrap.wrap(", ".join(downpips_array))))
-print("};");
-
-print("static BelPortPOD wire_downbels[] = {")
-print(" " + "\n ".join(textwrap.wrap(", ".join(downbels_array))))
-print("};");
-
packageinfo = []
for package in packages:
@@ -456,10 +655,11 @@ for package in packages:
pinname, x, y, z = pin
pin_bel = "X%d/Y%d/io%d" % (x, y, z)
bel_idx = bel_name.index(pin_bel)
- pins_info.append('{"%s", %d}' % (pinname, bel_idx))
- print("static PackagePinPOD package_%s_pins[%d] = {" % (safename, len(pins_info)))
- print(" " + ",\n ".join(pins_info))
- print("};")
+ pins_info.append((pinname, bel_idx))
+ bba.l("package_%s_pins" % safename, "PackagePinPOD", export=True)
+ for pi in pins_info:
+ bba.s(pi[0], "name")
+ bba.u32(pi[1], "bel_index")
packageinfo.append('{"%s", %d, package_%s_pins}' % (name, len(pins_info), safename))
tilegrid = []
@@ -476,14 +676,48 @@ for t in range(num_tile_types):
for cb in tile_bits[t]:
name, bits = cb
safename = re.sub("[^A-Za-z0-9]", "_", name)
- bits_list = ["{%d, %d}" % _ for _ in bits]
- print("static ConfigBitPOD tile%d_%s_bits[%d] = {%s};" % (t, safename, len(bits_list), ", ".join(bits_list)))
- centries_info.append('{"%s", %d, tile%d_%s_bits}' % (name, len(bits_list), t, safename))
- print("static ConfigEntryPOD tile%d_config[%d] = {" % (t, len(centries_info)))
- print(" " + ",\n ".join(centries_info))
- print("};")
+ bba.l("tile%d_%s_bits" % (t, safename), "ConfigBitPOD")
+ for row, col in bits:
+ bba.u8(row, "row")
+ bba.u8(col, "col")
+ if len(bits) == 0:
+ bba.u32(0, "padding")
+ elif len(bits) % 2 == 1:
+ bba.u16(0, "padding")
+ centries_info.append((name, len(bits), t, safename))
+ bba.l("tile%d_config" % t, "ConfigEntryPOD", export=True)
+ for name, num_bits, t, safename in centries_info:
+ bba.s(name, "name")
+ bba.u32(num_bits, "num_bits")
+ bba.r("tile%d_%s_bits" % (t, safename), "num_bits")
+ if len(centries_info) == 0:
+ bba.u32(0, "padding")
tileinfo.append("{%d, %d, %d, tile%d_config}" % (tile_sizes[t][0], tile_sizes[t][1], len(centries_info), t))
+bba.l("wire_data_%s" % dev_name, "WireInfoPOD", export=True)
+for info in wireinfo:
+ bba.s(info["name"], "name")
+ bba.u32(info["num_uphill"], "num_uphill")
+ bba.u32(info["num_downhill"], "num_downhill")
+ bba.r(info["list_uphill"], "pips_uphill")
+ bba.r(info["list_downhill"], "pips_downhill")
+ bba.u32(info["num_bels_downhill"], "num_bels_downhill")
+ bba.u32(info["uphill_bel"], "bel_uphill.bel_index")
+ bba.u32(info["uphill_pin"], "bel_uphill.port")
+ bba.r(info["list_bels_downhill"], "bels_downhill")
+ bba.u16(info["x"], "x")
+ bba.u16(info["y"], "y")
+
+bba.finalize()
+if compact_output:
+ bba.write_compact_c(sys.stdout)
+else:
+ bba.write_verbose_c(sys.stdout)
+
+print("static PipInfoPOD pip_data_%s[%d] = {" % (dev_name, len(pipinfo)))
+print(" " + ",\n ".join(pipinfo))
+print("};")
+
switchinfo = []
switchid = 0
for switch in switches:
@@ -497,18 +731,6 @@ for switch in switches:
switchinfo.append("{%d, %d, %d, {%s}}" % (x, y, len(bits), cbits))
switchid += 1
-iereninfo = []
-for ieren in ierens:
- iereninfo.append("{%d, %d, %d, %d, %d, %d}" % ieren)
-
-print("static WireInfoPOD wire_data_%s[%d] = {" % (dev_name, num_wires))
-print(" " + ",\n ".join(wireinfo))
-print("};")
-
-print("static PipInfoPOD pip_data_%s[%d] = {" % (dev_name, len(pipinfo)))
-print(" " + ",\n ".join(pipinfo))
-print("};")
-
print("static SwitchInfoPOD switch_data_%s[%d] = {" % (dev_name, len(switchinfo)))
print(" " + ",\n ".join(switchinfo))
print("};")
@@ -517,6 +739,10 @@ print("static TileInfoPOD tile_data_%s[%d] = {" % (dev_name, num_tile_types))
print(" " + ",\n ".join(tileinfo))
print("};")
+iereninfo = []
+for ieren in ierens:
+ iereninfo.append("{%d, %d, %d, %d, %d, %d}" % ieren)
+
print("static IerenInfoPOD ieren_data_%s[%d] = {" % (dev_name, len(iereninfo)))
print(" " + ",\n ".join(iereninfo))
print("};")
@@ -540,7 +766,7 @@ print('NEXTPNR_NAMESPACE_BEGIN')
print("ChipInfoPOD chip_info_%s = {" % dev_name)
print(" %d, %d, %d, %d, %d, %d, %d," % (dev_width, dev_height, len(bel_name), num_wires, len(pipinfo), len(switchinfo), len(packageinfo)))
-print(" bel_data_%s, wire_data_%s, pip_data_%s," % (dev_name, dev_name, dev_name))
+print(" bel_data, wire_data_%s, pip_data_%s," % (dev_name, dev_name))
print(" tile_grid_%s, &bits_info_%s, package_info_%s" % (dev_name, dev_name, dev_name))
print("};")
generated by cgit v1.2.3 (git 2.25.1) at 2025-05-07 08:12:53 +0000