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-rw-r--r--gowin/arch.cc6
1 files changed, 6 insertions, 0 deletions
diff --git a/gowin/arch.cc b/gowin/arch.cc
index a924f000..f43cc00a 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -2169,11 +2169,17 @@ void Arch::fix_pll_nets(Context *ctx)
ci->setParam(id_FBSEL, Property("UNKNOWN"));
continue;
}
+ // XXX Redesign for chips other than N-1 and NS-4
if (net_driven_by(ctx, net, is_RPLL_T_FB_iob, id_O) != nullptr) {
ci->disconnectPort(id_CLKFB);
ci->setParam(id_FBSEL, Property("CLKFB2"));
break;
}
+ if (net_driven_by(ctx, net, is_LPLL_T_FB_iob, id_O) != nullptr) {
+ ci->disconnectPort(id_CLKFB);
+ ci->setParam(id_FBSEL, Property("CLKFB2"));
+ break;
+ }
// XXX do special bels (HCLK etc)
// This is general routing through CLK2 pip
ci->setParam(id_FBSEL, Property("CLKFB0"));