diff options
| -rw-r--r-- | ice40/bitstream.cc | 36 |
1 files changed, 21 insertions, 15 deletions
diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 2e1a6d4e..c8ad93d8 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -829,24 +829,30 @@ void write_asc(const Context *ctx, std::ostream &out) // Weird UltraPlus bits if (tile == TILE_DSP0 || tile == TILE_DSP1 || tile == TILE_DSP2 || tile == TILE_DSP3 || tile == TILE_IPCON) { + auto set_ipcon = [&](int lc_idx) { + static const std::vector<int> ip_dsp_lut_perm = { + 4, 14, 15, 5, 6, 16, 17, 7, 3, 13, 12, 2, 1, 11, 10, 0, + }; + for (int i = 0; i < 16; i++) + set_config(ti, config.at(y).at(x), "LC_" + std::to_string(lc_idx), ((i % 8) >= 4), + ip_dsp_lut_perm.at(i)); + if (tile == TILE_IPCON) + set_config(ti, config.at(y).at(x), "Cascade.IPCON_LC0" + std::to_string(lc_idx) + "_inmux02_5", + true); + else + set_config(ti, config.at(y).at(x), + "Cascade.MULT" + std::to_string(int(tile - TILE_DSP0)) + "_LC0" + + std::to_string(lc_idx) + "_inmux02_5", + true); + }; if ((ctx->args.type == ArchArgs::UP5K || ctx->args.type == ArchArgs::UP3K) && x == 25 && y == 14) { - // Mystery bits not set in this one tile + // Mystery bits not set in this one tile, other than to route through the DSP carry out if used + if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(25, 10, 0)))) { + set_ipcon(0); + } } else { for (int lc_idx = 0; lc_idx < 8; lc_idx++) { - static const std::vector<int> ip_dsp_lut_perm = { - 4, 14, 15, 5, 6, 16, 17, 7, 3, 13, 12, 2, 1, 11, 10, 0, - }; - for (int i = 0; i < 16; i++) - set_config(ti, config.at(y).at(x), "LC_" + std::to_string(lc_idx), ((i % 8) >= 4), - ip_dsp_lut_perm.at(i)); - if (tile == TILE_IPCON) - set_config(ti, config.at(y).at(x), - "Cascade.IPCON_LC0" + std::to_string(lc_idx) + "_inmux02_5", true); - else - set_config(ti, config.at(y).at(x), - "Cascade.MULT" + std::to_string(int(tile - TILE_DSP0)) + "_LC0" + - std::to_string(lc_idx) + "_inmux02_5", - true); + set_ipcon(lc_idx); } } } |