diff options
| -rw-r--r-- | README.md | 16 | ||||
| -rw-r--r-- | docs/faq.md | 33 | ||||
| -rw-r--r-- | docs/generic.md | 8 | ||||
| -rw-r--r-- | ecp5/synth/.gitignore | 3 | ||||
| -rw-r--r-- | ecp5/synth/blinky.v | 77 | ||||
| -rw-r--r-- | ecp5/synth/blinky.ys | 2 | ||||
| -rw-r--r-- | ecp5/synth/ulx3s_empty.config | 439 |
7 files changed, 21 insertions, 557 deletions
@@ -6,13 +6,10 @@ tool. Currently nextpnr supports: * Lattice iCE40 devices supported by [Project IceStorm](http://www.clifford.at/icestorm/) - * *(experimental)* Lattice ECP5 devices supported by [Project Trellis](https://github.com/SymbiFlow/prjtrellis) + * Lattice ECP5 devices supported by [Project Trellis](https://github.com/SymbiFlow/prjtrellis) * *(experimental)* a "generic" back-end for user-defined architectures -We hope to see Xilinx 7 Series thanks to -[Project X-Ray](https://github.com/SymbiFlow/prjxray) and even more FPGA families -supported in the future. We would love your help in developing this -awesome new project! +There is some work in progress towards [support for Xilinx devices](https://github.com/daveshah1/nextpnr-xilinx/) but it is not upstream and not intended for end users at the present time. We hope to see more FPGA families supported in the future. We would love your help in developing this awesome new project! A brief (academic) paper describing the Yosys+nextpnr flow can be found on [arXiv](https://arxiv.org/abs/1903.10407). @@ -106,12 +103,7 @@ make -j$(nproc) sudo make install ``` - - For an ECP5 blinky on the 45k ULX3S board, first synthesise using `yosys blinky.ys` in `ecp5/synth`. - - Then run ECP5 place-and route using `./nextpnr-ecp5 --json ecp5/synth/blinky.json --basecfg ecp5/synth/ulx3s_empty.config --textcfg ecp5/synth/ulx3s_out.config` - - Create a bitstream using `ecppack ulx3s_out.config ulx3s.bit` - - Note that `ulx3s_empty.config` contains fixed/unknown bits to be copied to the output bitstream - - - More examples of the ECP5 flow for a range of boards can be found in the [Project Trellis Examples](https://github.com/SymbiFlow/prjtrellis/tree/master/examples). + - Examples of the ECP5 flow for a range of boards can be found in the [Project Trellis Examples](https://github.com/SymbiFlow/prjtrellis/tree/master/examples). ### nextpnr-generic @@ -124,7 +116,7 @@ make -j$(nproc) sudo make install ``` -TBD: Getting started example for generic target. +An example of how to use the generic flow is in [generic/examples](generic/examples). See also the [Generic Architecture docs](docs/generic.md). Additional notes for building nextpnr ------------------------------------- diff --git a/docs/faq.md b/docs/faq.md index 7b358187..fe0c7231 100644 --- a/docs/faq.md +++ b/docs/faq.md @@ -132,9 +132,8 @@ Nextpnr and other tools ### Which toolchain should I use and why? - * If you wish to do new **research** into FPGA architectures, place and route - algorithms or other similar topics, we suggest you look at using - [Verilog to Routing](https://verilogtorouting.org). + * If you wish to do new **research** into FPGA architectures, or other similar topics, we suggest you look at using + [Verilog to Routing](https://verilogtorouting.org). If you want to use nextpnr, you might also be able to use the [Generic Arch](generic.md). * If you are developing FPGA code in **Verilog** for a **Lattice iCE40** and need an open source toolchain, we suggest you use [Yosys](http://www.clifford.at/yosys/) and nextpnr. @@ -144,14 +143,9 @@ Nextpnr and other tools migrating to nextpnr. * If you are developing Verilog FPGA code targeted at the Lattice ECP5 and - need an open source toolchain, you may consider the **extremely - experimental** ECP5 support in Yosys and nextpnr. + need an open source toolchain, there is also stable ECP5 support in Yosys and nextpnr. - * If you are developing FPGA code in **VHDL** you will need to use either a - version of [Yosys with Verific support](https://github.com/YosysHQ/yosys/tree/master/frontends/verific) or the vendor provided tools due - to the lack of useful open source VHDL support in Yosys. You could also look at developing - one of the experimental open source VHDL frontends, such as [yavhdl](https://github.com/rqou/yavhdl) - or [ghdlsynth-beta](https://github.com/tgingold/ghdlsynth-beta), further. + * If you are developing FPGA code in **VHDL** you may wish to look at the [ghdlsynth-beta](https://github.com/tgingold/ghdlsynth-beta) experimental VHDL frontend for Yosys. ### Why didn't you just improve [arachne-pnr](https://github.com/cseed/arachne-pnr)? @@ -162,11 +156,9 @@ that actually produced valid bitstreams. For its original purpose, it has served the community extremely well. However, it was never designed to support multiple different FPGA families, nor more -complicated timing driven placement and routing used by most commercial place and route -tools. +complicated timing driven placement and routing used by most commercial place and route tools. -It felt like extending arachne-pnr was not going to be the best path forward, so -it was decided to build nextpnr as replacement. +It felt like extending arachne-pnr was not going to be the best path forward, so it was decided to build nextpnr as replacement. ### arachne-pnr does X better! @@ -174,7 +166,8 @@ If you have a use case which prevents you from switching to nextpnr from arachne, we want to hear about it! Please create an issue and we will do our best to solve the problem! We want nextpnr to be a suitable replacement for anyone who is currently a user -of arachne-pnr. +of arachne-pnr, and it is important to bear in mind that arachne-pnr is no +longer in active development. ### Why are you not just contributing to [Verilog to Routing](https://verilogtorouting.org)? @@ -191,8 +184,7 @@ for current FPGAs. We also believe that support for real architectures will enable interesting new research. nextpnr (like all place and route tools) depends heavily on -research groups like the VtR developers to investigate and push forward FPGA placement and routing -algorithms in new and exciting ways. +research groups like the VtR developers to investigate and push forward FPGA placement and routing algorithms in new and exciting ways. #### What is VPR? @@ -220,15 +212,14 @@ enable support for creation of bitstreams for these parts. the bitstream format for the Xilinx Series 7 series of FPGAs. It also includes tooling around bitstream generation for these parts. -While nextpnr currently does **not** support these Xilinx parts, we expect it -will soon be using Project X-Ray in a similar manner to Project Trellis. +While upstream nextpnr currently does **not** support these Xilinx parts, we expect it might soon be using Project X-Ray in a similar manner to Project Trellis. ### What is [Project IceStorm](http://www.clifford.at/icestorm/)? [Project IceStorm](http://www.clifford.at/icestorm/) is both a project to document the bitstream for the Lattice iCE40 series of parts **and** a full -flow including Yosys and arachne-pnr for converting Verilog into a bitstream for -these parts. +flow including Yosys and arachne-pnr for converting Verilog into a bitstream +for these parts. As the open source community now has support for multiple different FPGA parts, in the nextpnr documentation we generally use Project IceStorm to mean the database and diff --git a/docs/generic.md b/docs/generic.md index d6ddbfb6..a635f98c 100644 --- a/docs/generic.md +++ b/docs/generic.md @@ -72,7 +72,7 @@ Sets the number of input pins a LUT in the architecture has. Only affects the ge ### void setDelayScaling(double scale, double offset); -Set the linear scaling vs distance and fixed offset (both values in nanoseconds) for routing delay estimates. +Set the linear scaling vs distance and fixed offset (both values in nanoseconds) for routing delay estimates. Delay estimates that correlate to pip delays, even if they have no bearing to reality, are important for reasonable routing runtime. ### void addCellTimingClock(IdString cell, IdString port); @@ -96,17 +96,19 @@ Specify clock-to-out time for a port of a cell, and set the timing class of that ## Generic Packer -The generic packer combines K-input LUTs (`LUT` cells) and simple D-type flip flops (`DFF` cells) (posedge clock only, no set/reset or enable) into a `GENERIC_SLICE` cell. It also inserts `GENERIC_IOB`s onto any top level IO pins without an IO buffer. +The generic packer combines K-input LUTs (`LUT` cells) and simple D-type flip flops (`DFF` cells) (posedge clock only, no set/reset or enable) into a `GENERIC_SLICE` cell. It also inserts `GENERIC_IOB`s onto any top level IO pins without an IO buffer. Constrained IOBs can be implemented by instantiating `GENERIC_IOB` and setting the `BEL` attribute to an IO location. Thus, the architecture should provide bels with the following ports in order to use the generic packer: - - `GENERIC_SLICE` bels with `CLK` input, `I[0]` .. `I[K-1]` LUT inputs and `Q` LUT/FF output (N.B. both LUT and FF outputs are not available at the same time) + - `GENERIC_SLICE` bels with `CLK` input, `I[0]` .. `I[K-1]` LUT inputs, `F` LUT output and `Q` FF output (N.B. both LUT and FF outputs are not available at the same time, to represent the constraints of some FPGAs). - `GENERIC_IOB` bels with `I` output buffer input, `EN` output enable input, and `O` input buffer output. See [prims.v](../generic/synth/prims.v) for Verilog simulation models for all these cells. [synth_generic.tcl](../generic/synth/synth_generic.tcl) can be used with Yosys to perform synthesis to the generic `LUT` and `DFF` cells which the generic packer supports. Invoke it using `tcl synth_generic.tcl K out.json` where _K_ is the number of LUT inputs and _out.json_ the name of the JSON file to write. +The generic packer in its current state is intended for experimentation and proof-of-concept tests. It is _not_ intended to make use of all FPGA features or support complex designs. In these cases a proper [Arch API](archapi.md) implementation is strongly recommended. + ## Validity Checks The following constraints are enforced by the generic architecture during placement. diff --git a/ecp5/synth/.gitignore b/ecp5/synth/.gitignore deleted file mode 100644 index f4dfa215..00000000 --- a/ecp5/synth/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -*.bit -*_out.config - diff --git a/ecp5/synth/blinky.v b/ecp5/synth/blinky.v deleted file mode 100644 index 9c6b187b..00000000 --- a/ecp5/synth/blinky.v +++ /dev/null @@ -1,77 +0,0 @@ -module top(input clk_pin, input btn_pin, output [7:0] led_pin, output gpio0_pin); - - wire clk; - wire [7:0] led; - wire btn; - wire gpio0; - - (* LOC="G2" *) (* IO_TYPE="LVCMOS33" *) - TRELLIS_IO #(.DIR("INPUT")) clk_buf (.B(clk_pin), .O(clk)); - - (* LOC="R1" *) (* IO_TYPE="LVCMOS33" *) - TRELLIS_IO #(.DIR("INPUT")) btn_buf (.B(btn_pin), .O(btn)); - - (* LOC="B2" *) (* IO_TYPE="LVCMOS33" *) - TRELLIS_IO #(.DIR("OUTPUT")) led_buf_0 (.B(led_pin[0]), .I(led[0])); - (* LOC="C2" *) (* IO_TYPE="LVCMOS33" *) - TRELLIS_IO #(.DIR("OUTPUT")) led_buf_1 (.B(led_pin[1]), .I(led[1])); - (* LOC="C1" *) (* IO_TYPE="LVCMOS33" *) - TRELLIS_IO #(.DIR("OUTPUT")) led_buf_2 (.B(led_pin[2]), .I(led[2])); - (* LOC="D2" *) (* IO_TYPE="LVCMOS33" *) - TRELLIS_IO #(.DIR("OUTPUT")) led_buf_3 (.B(led_pin[3]), .I(led[3])); - - (* LOC="D1" *) (* IO_TYPE="LVCMOS33" *) - TRELLIS_IO #(.DIR("OUTPUT")) led_buf_4 (.B(led_pin[4]), .I(led[4])); - (* LOC="E2" *) (* IO_TYPE="LVCMOS33" *) - TRELLIS_IO #(.DIR("OUTPUT")) led_buf_5 (.B(led_pin[5]), .I(led[5])); - (* LOC="E1" *) (* IO_TYPE="LVCMOS33" *) - TRELLIS_IO #(.DIR("OUTPUT")) led_buf_6 (.B(led_pin[6]), .I(led[6])); - (* LOC="H3" *) (* IO_TYPE="LVCMOS33" *) - TRELLIS_IO #(.DIR("OUTPUT")) led_buf_7 (.B(led_pin[7]), .I(led[7])); - - - (* LOC="L2" *) (* IO_TYPE="LVCMOS33" *) - TRELLIS_IO #(.DIR("OUTPUT")) gpio0_buf (.B(gpio0_pin), .I(gpio0)); - - localparam ctr_width = 24; - localparam ctr_max = 2**ctr_width - 1; - reg [ctr_width-1:0] ctr = 0; - reg [9:0] pwm_ctr = 0; - reg dir = 0; - - always@(posedge clk) begin - ctr <= btn ? ctr : (dir ? ctr - 1'b1 : ctr + 1'b1); - if (ctr[ctr_width-1 : ctr_width-3] == 0 && dir == 1) - dir <= 1'b0; - else if (ctr[ctr_width-1 : ctr_width-3] == 7 && dir == 0) - dir <= 1'b1; - pwm_ctr <= pwm_ctr + 1'b1; - end - - reg [9:0] brightness [0:7]; - localparam bright_max = 2**10 - 1; - reg [7:0] led_reg; - - genvar i; - generate - for (i = 0; i < 8; i=i+1) begin - always @ (posedge clk) begin - if (ctr[ctr_width-1 : ctr_width-3] == i) - brightness[i] <= bright_max; - else if (ctr[ctr_width-1 : ctr_width-3] == (i - 1)) - brightness[i] <= ctr[ctr_width-4:ctr_width-13]; - else if (ctr[ctr_width-1 : ctr_width-3] == (i + 1)) - brightness[i] <= bright_max - ctr[ctr_width-4:ctr_width-13]; - else - brightness[i] <= 0; - led_reg[i] <= pwm_ctr < brightness[i]; - end - end - endgenerate - - assign led = led_reg; - - // Tie GPIO0, keep board from rebooting - assign gpio0 = 1'b1; - -endmodule diff --git a/ecp5/synth/blinky.ys b/ecp5/synth/blinky.ys deleted file mode 100644 index fb359380..00000000 --- a/ecp5/synth/blinky.ys +++ /dev/null @@ -1,2 +0,0 @@ -read_verilog blinky.v -synth_ecp5 -noccu2 -nomux -nodram -json blinky.json diff --git a/ecp5/synth/ulx3s_empty.config b/ecp5/synth/ulx3s_empty.config deleted file mode 100644 index 815e7f0d..00000000 --- a/ecp5/synth/ulx3s_empty.config +++ /dev/null @@ -1,439 +0,0 @@ -.device LFE5U-45F - -.tile CIB_R10C3:PVT_COUNT2 -unknown: F2B0 -unknown: F3B0 -unknown: F5B0 -unknown: F11B0 -unknown: F13B0 - -.tile CIB_R5C1:CIB_PLL1 -enum: CIB.JA3MUX 0 -enum: CIB.JB3MUX 0 - - -.tile CIB_R5C89:CIB_PLL1 -enum: CIB.JA3MUX 0 -enum: CIB.JB3MUX 0 - - -.tile CIB_R70C3:CIB_PLL3 -enum: CIB.JA3MUX 0 -enum: CIB.JB3MUX 0 - - -.tile CIB_R70C42:VCIB_DCU0 -enum: CIB.JA1MUX 0 -enum: CIB.JA3MUX 0 -enum: CIB.JA5MUX 0 -enum: CIB.JA7MUX 0 -enum: CIB.JB1MUX 0 -enum: CIB.JB3MUX 0 -enum: CIB.JB5MUX 0 -enum: CIB.JB7MUX 0 -enum: CIB.JC0MUX 0 -enum: CIB.JC2MUX 0 -enum: CIB.JC4MUX 0 -enum: CIB.JC6MUX 0 -enum: CIB.JD0MUX 0 -enum: CIB.JD2MUX 0 -enum: CIB.JD4MUX 0 -enum: CIB.JD6MUX 0 - - -.tile CIB_R70C43:VCIB_DCUA -enum: CIB.JA1MUX 0 -enum: CIB.JA3MUX 0 -enum: CIB.JA5MUX 0 -enum: CIB.JA7MUX 0 -enum: CIB.JB1MUX 0 -enum: CIB.JB3MUX 0 -enum: CIB.JB5MUX 0 -enum: CIB.JB7MUX 0 -enum: CIB.JC0MUX 0 -enum: CIB.JC2MUX 0 -enum: CIB.JC4MUX 0 -enum: CIB.JC6MUX 0 -enum: CIB.JD0MUX 0 -enum: CIB.JD2MUX 0 -enum: CIB.JD4MUX 0 -enum: CIB.JD6MUX 0 - - -.tile CIB_R70C44:VCIB_DCUB -enum: CIB.JA1MUX 0 -enum: CIB.JA3MUX 0 -enum: CIB.JA5MUX 0 -enum: CIB.JA7MUX 0 -enum: CIB.JB1MUX 0 -enum: CIB.JB3MUX 0 -enum: CIB.JB5MUX 0 -enum: CIB.JB7MUX 0 -enum: CIB.JC0MUX 0 -enum: CIB.JC2MUX 0 -enum: CIB.JC4MUX 0 -enum: CIB.JC6MUX 0 -enum: CIB.JD0MUX 0 -enum: CIB.JD2MUX 0 -enum: CIB.JD4MUX 0 -enum: CIB.JD6MUX 0 - - -.tile CIB_R70C45:VCIB_DCUC -enum: CIB.JA1MUX 0 -enum: CIB.JA3MUX 0 -enum: CIB.JA5MUX 0 -enum: CIB.JA7MUX 0 -enum: CIB.JB1MUX 0 -enum: CIB.JB3MUX 0 -enum: CIB.JB5MUX 0 -enum: CIB.JB7MUX 0 -enum: CIB.JC0MUX 0 -enum: CIB.JC2MUX 0 -enum: CIB.JC4MUX 0 -enum: CIB.JC6MUX 0 -enum: CIB.JD0MUX 0 -enum: CIB.JD2MUX 0 -enum: CIB.JD4MUX 0 -enum: CIB.JD6MUX 0 - - -.tile CIB_R70C46:VCIB_DCUD -enum: CIB.JA1MUX 0 -enum: CIB.JA5MUX 0 -enum: CIB.JA7MUX 0 -enum: CIB.JB1MUX 0 -enum: CIB.JB3MUX 0 -enum: CIB.JB5MUX 0 -enum: CIB.JB7MUX 0 -enum: CIB.JC0MUX 0 -enum: CIB.JC2MUX 0 -enum: CIB.JC4MUX 0 -enum: CIB.JC6MUX 0 -enum: CIB.JD0MUX 0 -enum: CIB.JD2MUX 0 -enum: CIB.JD4MUX 0 -enum: CIB.JD6MUX 0 - - -.tile CIB_R70C47:VCIB_DCUF -enum: CIB.JA1MUX 0 -enum: CIB.JA3MUX 0 -enum: CIB.JA5MUX 0 -enum: CIB.JA7MUX 0 -enum: CIB.JB1MUX 0 -enum: CIB.JB3MUX 0 -enum: CIB.JB5MUX 0 -enum: CIB.JB7MUX 0 -enum: CIB.JC0MUX 0 -enum: CIB.JC2MUX 0 -enum: CIB.JC4MUX 0 -enum: CIB.JC6MUX 0 -enum: CIB.JD0MUX 0 -enum: CIB.JD2MUX 0 -enum: CIB.JD4MUX 0 -enum: CIB.JD6MUX 0 - - -.tile CIB_R70C48:VCIB_DCU3 -enum: CIB.JA5MUX 0 -enum: CIB.JA7MUX 0 -enum: CIB.JB1MUX 0 -enum: CIB.JB3MUX 0 -enum: CIB.JB5MUX 0 -enum: CIB.JB7MUX 0 -enum: CIB.JC0MUX 0 -enum: CIB.JC4MUX 0 -enum: CIB.JC6MUX 0 -enum: CIB.JD0MUX 0 -enum: CIB.JD2MUX 0 -enum: CIB.JD4MUX 0 -enum: CIB.JD6MUX 0 - - -.tile CIB_R70C49:VCIB_DCU2 -enum: CIB.JB1MUX 0 -enum: CIB.JB3MUX 0 -enum: CIB.JB5MUX 0 -enum: CIB.JB7MUX 0 -enum: CIB.JD0MUX 0 -enum: CIB.JD2MUX 0 -enum: CIB.JD4MUX 0 -enum: CIB.JD6MUX 0 - - -.tile CIB_R70C50:VCIB_DCUG -enum: CIB.JB1MUX 0 -enum: CIB.JB3MUX 0 -enum: CIB.JB5MUX 0 -enum: CIB.JB7MUX 0 -enum: CIB.JD0MUX 0 -enum: CIB.JD2MUX 0 -enum: CIB.JD4MUX 0 -enum: CIB.JD6MUX 0 - - -.tile CIB_R70C51:VCIB_DCUH -enum: CIB.JB1MUX 0 -enum: CIB.JB3MUX 0 -enum: CIB.JB5MUX 0 -enum: CIB.JB7MUX 0 -enum: CIB.JD0MUX 0 -enum: CIB.JD2MUX 0 -enum: CIB.JD4MUX 0 -enum: CIB.JD6MUX 0 - - -.tile CIB_R70C52:VCIB_DCUI -enum: CIB.JB1MUX 0 -enum: CIB.JB3MUX 0 -enum: CIB.JB5MUX 0 -enum: CIB.JB7MUX 0 -enum: CIB.JD0MUX 0 -enum: CIB.JD2MUX 0 -enum: CIB.JD4MUX 0 -enum: CIB.JD6MUX 0 - - -.tile CIB_R70C53:VCIB_DCU1 -enum: CIB.JB1MUX 0 -enum: CIB.JB3MUX 0 -enum: CIB.JB5MUX 0 -enum: CIB.JD0MUX 0 -enum: CIB.JD2MUX 0 - - -.tile CIB_R70C69:VCIB_DCU0 -enum: CIB.JA1MUX 0 -enum: CIB.JA3MUX 0 -enum: CIB.JA5MUX 0 -enum: CIB.JA7MUX 0 -enum: CIB.JB1MUX 0 -enum: CIB.JB3MUX 0 -enum: CIB.JB5MUX 0 -enum: CIB.JB7MUX 0 -enum: CIB.JC0MUX 0 -enum: CIB.JC2MUX 0 -enum: CIB.JC4MUX 0 -enum: CIB.JC6MUX 0 -enum: CIB.JD0MUX 0 -enum: CIB.JD2MUX 0 -enum: CIB.JD4MUX 0 -enum: CIB.JD6MUX 0 - - -.tile CIB_R70C6:CIB_EFB0 -enum: CIB.JB3MUX 0 -enum: CIB.JC6MUX 0 -enum: CIB.JD6MUX 0 - - -.tile CIB_R70C70:VCIB_DCUA -enum: CIB.JA1MUX 0 -enum: CIB.JA3MUX 0 -enum: CIB.JA5MUX 0 -enum: CIB.JA7MUX 0 -enum: CIB.JB1MUX 0 -enum: CIB.JB3MUX 0 -enum: CIB.JB5MUX 0 -enum: CIB.JB7MUX 0 -enum: CIB.JC0MUX 0 -enum: CIB.JC2MUX 0 -enum: CIB.JC4MUX 0 -enum: CIB.JC6MUX 0 -enum: CIB.JD0MUX 0 -enum: CIB.JD2MUX 0 -enum: CIB.JD4MUX 0 -enum: CIB.JD6MUX 0 - - -.tile CIB_R70C71:VCIB_DCUB -enum: CIB.JA1MUX 0 -enum: CIB.JA3MUX 0 -enum: CIB.JA5MUX 0 -enum: CIB.JA7MUX 0 -enum: CIB.JB1MUX 0 -enum: CIB.JB3MUX 0 -enum: CIB.JB5MUX 0 -enum: CIB.JB7MUX 0 -enum: CIB.JC0MUX 0 -enum: CIB.JC2MUX 0 -enum: CIB.JC4MUX 0 -enum: CIB.JC6MUX 0 -enum: CIB.JD0MUX 0 -enum: CIB.JD2MUX 0 -enum: CIB.JD4MUX 0 -enum: CIB.JD6MUX 0 - - -.tile CIB_R70C72:VCIB_DCUC -enum: CIB.JA1MUX 0 -enum: CIB.JA3MUX 0 -enum: CIB.JA5MUX 0 -enum: CIB.JA7MUX 0 -enum: CIB.JB1MUX 0 -enum: CIB.JB3MUX 0 -enum: CIB.JB5MUX 0 -enum: CIB.JB7MUX 0 -enum: CIB.JC0MUX 0 -enum: CIB.JC2MUX 0 -enum: CIB.JC4MUX 0 -enum: CIB.JC6MUX 0 -enum: CIB.JD0MUX 0 -enum: CIB.JD2MUX 0 -enum: CIB.JD4MUX 0 -enum: CIB.JD6MUX 0 - - -.tile CIB_R70C73:VCIB_DCUD -enum: CIB.JA1MUX 0 -enum: CIB.JA5MUX 0 -enum: CIB.JA7MUX 0 -enum: CIB.JB1MUX 0 -enum: CIB.JB3MUX 0 -enum: CIB.JB5MUX 0 -enum: CIB.JB7MUX 0 -enum: CIB.JC0MUX 0 -enum: CIB.JC2MUX 0 -enum: CIB.JC4MUX 0 -enum: CIB.JC6MUX 0 -enum: CIB.JD0MUX 0 -enum: CIB.JD2MUX 0 -enum: CIB.JD4MUX 0 -enum: CIB.JD6MUX 0 - - -.tile CIB_R70C74:VCIB_DCUF -enum: CIB.JA1MUX 0 -enum: CIB.JA3MUX 0 -enum: CIB.JA5MUX 0 -enum: CIB.JA7MUX 0 -enum: CIB.JB1MUX 0 -enum: CIB.JB3MUX 0 -enum: CIB.JB5MUX 0 -enum: CIB.JB7MUX 0 -enum: CIB.JC0MUX 0 -enum: CIB.JC2MUX 0 -enum: CIB.JC4MUX 0 -enum: CIB.JC6MUX 0 -enum: CIB.JD0MUX 0 -enum: CIB.JD2MUX 0 -enum: CIB.JD4MUX 0 -enum: CIB.JD6MUX 0 - - -.tile CIB_R70C75:VCIB_DCU3 -enum: CIB.JA5MUX 0 -enum: CIB.JA7MUX 0 -enum: CIB.JB1MUX 0 -enum: CIB.JB3MUX 0 -enum: CIB.JB5MUX 0 -enum: CIB.JB7MUX 0 -enum: CIB.JC0MUX 0 -enum: CIB.JC4MUX 0 -enum: CIB.JC6MUX 0 -enum: CIB.JD0MUX 0 -enum: CIB.JD2MUX 0 -enum: CIB.JD4MUX 0 -enum: CIB.JD6MUX 0 - - -.tile CIB_R70C76:VCIB_DCU2 -enum: CIB.JB1MUX 0 -enum: CIB.JB3MUX 0 -enum: CIB.JB5MUX 0 -enum: CIB.JB7MUX 0 -enum: CIB.JD0MUX 0 -enum: CIB.JD2MUX 0 -enum: CIB.JD4MUX 0 -enum: CIB.JD6MUX 0 - - -.tile CIB_R70C77:VCIB_DCUG -enum: CIB.JB1MUX 0 -enum: CIB.JB3MUX 0 -enum: CIB.JB5MUX 0 -enum: CIB.JB7MUX 0 -enum: CIB.JD0MUX 0 -enum: CIB.JD2MUX 0 -enum: CIB.JD4MUX 0 -enum: CIB.JD6MUX 0 - - -.tile CIB_R70C78:VCIB_DCUH -enum: CIB.JB1MUX 0 -enum: CIB.JB3MUX 0 -enum: CIB.JB5MUX 0 -enum: CIB.JB7MUX 0 -enum: CIB.JD0MUX 0 -enum: CIB.JD2MUX 0 -enum: CIB.JD4MUX 0 -enum: CIB.JD6MUX 0 - - -.tile CIB_R70C79:VCIB_DCUI -enum: CIB.JB1MUX 0 -enum: CIB.JB3MUX 0 -enum: CIB.JB5MUX 0 -enum: CIB.JB7MUX 0 -enum: CIB.JD0MUX 0 -enum: CIB.JD2MUX 0 -enum: CIB.JD4MUX 0 -enum: CIB.JD6MUX 0 - - -.tile CIB_R70C7:CIB_EFB1 -enum: CIB.JA3MUX 0 -enum: CIB.JA4MUX 0 -enum: CIB.JA5MUX 0 -enum: CIB.JA6MUX 0 -enum: CIB.JB3MUX 0 -enum: CIB.JB4MUX 0 -enum: CIB.JB5MUX 0 -enum: CIB.JB6MUX 0 -enum: CIB.JC3MUX 0 -enum: CIB.JC4MUX 0 -enum: CIB.JC5MUX 0 -enum: CIB.JD3MUX 0 -enum: CIB.JD4MUX 0 -enum: CIB.JD5MUX 0 - - -.tile CIB_R70C80:VCIB_DCU1 -enum: CIB.JB1MUX 0 -enum: CIB.JB3MUX 0 -enum: CIB.JB5MUX 0 -enum: CIB.JD0MUX 0 -enum: CIB.JD2MUX 0 - - -.tile CIB_R70C87:CIB_PLL3 -enum: CIB.JA3MUX 0 -enum: CIB.JB3MUX 0 - - -.tile MIB_R10C40:CMUX_UL_0 -arc: G_DCS0CLK0 G_VPFN0000 - - -.tile MIB_R10C41:CMUX_UR_0 -arc: G_DCS0CLK1 G_VPFN0000 - - -.tile MIB_R58C40:CMUX_LL_0 -arc: G_DCS1CLK0 G_VPFN0000 - - -.tile MIB_R58C41:CMUX_LR_0 -arc: G_DCS1CLK1 G_VPFN0000 - - -.tile MIB_R71C4:EFB0_PICB0 -unknown: F54B1 -unknown: F56B1 -unknown: F82B1 -unknown: F94B1 - -.tile MIB_R71C3:BANKREF8 -unknown: F18B0 - |