1 files changed, 33 insertions, 0 deletions
diff --git a/ice40/regressions/issue0186/pll.v b/ice40/regressions/issue0186/pll.v
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+++ b/ice40/regressions/issue0186/pll.v
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+/**
+ * PLL configuration
+ *
+ * This Verilog module was generated automatically
+ * using the icepll tool from the IceStorm project.
+ * Use at your own risk.
+ *
+ * Given input frequency:       100.000 MHz
+ * Requested output frequency:  120.000 MHz
+ * Achieved output frequency:   120.000 MHz
+ */
+
+module pll(
+	input  clock_in,
+	output clock_out,
+	output locked
+	);
+
+SB_PLL40_CORE #(
+		.FEEDBACK_PATH("SIMPLE"),
+		.DIVR(4'b0100),		// DIVR =  4
+		.DIVF(7'b0101111),	// DIVF = 47
+		.DIVQ(3'b011),		// DIVQ =  3
+		.FILTER_RANGE(3'b010)	// FILTER_RANGE = 2
+	) uut (
+		.LOCK(locked),
+		.RESETB(1'b1),
+		.BYPASS(1'b0),
+		.REFERENCECLK(clock_in),
+		.PLLOUTCORE(clock_out)
+		);
+
+endmodule