Project IceStorm – UltraPlus Features Documentation

Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files. This is work in progress.

The ice40 UltraPlus devices have a number of new features compared to the older LP/HX series devices, in particular:

• Internal DSP units, capable of 16-bit multiply and 32-bit accumulate.
• 1Mbit of extra single-ported RAM, in addition to the usual BRAM
• Internal hard IP cores for I2C and SPI
• 2 internal oscillators, 48MHz (with divider) and 10kHz
• 24mA constant current LED ouputs and PWM hard IP

DSP Tiles

Each MAC16 DSP comprises of 4 DSP tiles, all of which perform part of the DSP function and have different routing bit configurations. Structually they are similar to logic tiles, but with the DSP function wired into where the LUTs and DFFs would be. The four types of DSP tiles will be referred to as DSP0 through DSP3, with DSP0 at the lowest y-position. One signal CO, is also routed through the IPConnect tile above the DSP tile, referred to as IPCON4 in this context. A work-in-progress effort to determine where signals and configuration bits are located is below:

Signal Assignments

Configuration Bits

The DSP configuration bits mostly follow the order stated in the ICE Technology Library document, where they are described asCBIT[24:0]. For most DSP tiles, these follow a logical order where CBIT[7:0] maps to DSP0 CBIT[7:0]; CBIT[15:8] to DSP1 CBIT[7:0], CBIT[23:16] to DSP2 CBIT[7:0] and CBIT[24] to DSP3 CBIT0.

However, there is one location where configuration bits are swapped between DSP tiles and IPConnect tiles. In DSP1 (0, 16) CBIT[4:1] are used for IP such as the internal oscillator, and the DSP configuration bits are then located in IPConnect tile (0, 19) CBIT[6:3].

The full list of configuration bits, including the changes for the DSP at (0, 15) are described in the table below.

Lattice document a limited number of supported configurations in the ICE Technology Library document, and Lattice's EDIF parser will reject designs not following a supported configuration. It is not yet known whether unsupported configurations (such as mixed signed and unsigned) function correctly or not.

Other Implementation Notes

All active DSP tiles, and all IPConnect tiles whether used or not, have some bits set which reflect their logic tile heritage. The LC_x bits which would be used to configure the logic cell, are set to the below pattern for each "logic cell" (interpreting them like a logic tile):

0000111100001111 0000

Coincidentally or not, this corresponds to a buffer passing through input 2 to the output. For each "cell" the cascade bit LC0x_inmux02_5 is also set, effectively creating one large chain, as this connects input 2 to the output of the previous LUT. It is not yet known if this serves any purpose, or is merely a remainder of Lattice's internal testing.

IPConnect Tiles

IPConnect tiles are used for connections to all of the other UltraPlus features, such as I2C/SPI, SPRAM, RGB and oscillators. Like DSP tiles, they are structually similar to logic tiles. The outputs of IP functions are connected to nets named slf_op_0 through slf_op_7, and the inputs use the LUT/FF inputs in the same way as DSP tiles.

Internal Oscillators

SB_HFOSC

The CLKHFPU input connects through IPConnect tile (0, 29) input lutff_0/in_1; and the CLKHFEN input connects through input lutff_7/in_3 of the same tile.
The CLKHF output of SB_HFOSC is connected to both IPConnect tile (0, 28) output slf_op_7 and to the padin of glb_netwk_4.

Configuration bit CLKHF_DIV[1] maps to DSP1 tile (0, 16) config bit CBIT_4, and CLKHF_DIV[0] maps to DSP1 tile (0, 16) config bit CBIT_3.

SB_LFOSC

The CLKLFPU input connects through IPConnect tile (25, 29) input lutff_0/in_1; and the CLKLFEN input connects through input lutff_7/in_3 of the same tile.
The CLKLF output of SB_LFOSC is connected to both IPConnect tile (25, 29) output slf_op_0 and to the padin of glb_netwk_5.

SB_LFOSC has no configuration bits.

SPRAM

The UltraPlus devices have 1Mbit of extra single-ported RAM, split into 4 256kbit blocks. The full list of connections for each SPRAM block in the 5k device is shown below, as well as the location of the 1 configuration bit which is set to enable use of that SPRAM block.