From c5862ab276bb061a43dc19a996eb3ab0726df23b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 21 Oct 2015 00:49:59 +0200
Subject: Progress in icetime

---
 icetime/cells.v    | 686 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 icetime/icetime.cc |  76 +++++-
 2 files changed, 751 insertions(+), 11 deletions(-)
 create mode 100644 icetime/cells.v

(limited to 'icetime')

diff --git a/icetime/cells.v b/icetime/cells.v
new file mode 100644
index 0000000..289c55e
--- /dev/null
+++ b/icetime/cells.v
@@ -0,0 +1,686 @@
+module AND2(A, B, O);
+  input A;
+  input B;
+  output O;
+endmodule
+
+module CEMux(I, O);
+  input I;
+  output O;
+endmodule
+
+module CascadeBuf(I, O);
+  input I;
+  output O;
+endmodule
+
+module CascadeMux(I, O);
+  input I;
+  output O;
+endmodule
+
+module ClkMux(I, O);
+  input I;
+  output O;
+endmodule
+
+module ColCtrlBuf(I, O);
+  input I;
+  output O;
+endmodule
+
+module DummyBuf(I, O);
+  input I;
+  output O;
+endmodule
+
+module Glb2LocalMux(I, O);
+  input I;
+  output O;
+endmodule
+
+module GlobalMux(I, O);
+  input I;
+  output O;
+endmodule
+
+module ICE_CARRY_IN_MUX(carryinitout, carryinitin);
+  input carryinitin;
+  output carryinitout;
+endmodule
+
+module ICE_GB(GLOBALBUFFEROUTPUT, USERSIGNALTOGLOBALBUFFER);
+  output GLOBALBUFFEROUTPUT;
+  input USERSIGNALTOGLOBALBUFFER;
+endmodule
+
+module ICE_GB_IO(PACKAGEPIN, LATCHINPUTVALUE, CLOCKENABLE, INPUTCLK, OUTPUTCLK, OUTPUTENABLE, DOUT1, DOUT0, DIN1, DIN0, GLOBALBUFFEROUTPUT);
+  input CLOCKENABLE;
+  output DIN0;
+  output DIN1;
+  input DOUT0;
+  input DOUT1;
+  output GLOBALBUFFEROUTPUT;
+  input INPUTCLK;
+  input LATCHINPUTVALUE;
+  input OUTPUTCLK;
+  input OUTPUTENABLE;
+  inout PACKAGEPIN;
+endmodule
+
+module ICE_IO(PACKAGEPIN, LATCHINPUTVALUE, CLOCKENABLE, INPUTCLK, OUTPUTCLK, OUTPUTENABLE, DOUT1, DOUT0, DIN1, DIN0);
+  input CLOCKENABLE;
+  output DIN0;
+  output DIN1;
+  input DOUT0;
+  input DOUT1;
+  input INPUTCLK;
+  input LATCHINPUTVALUE;
+  input OUTPUTCLK;
+  input OUTPUTENABLE;
+  inout PACKAGEPIN;
+endmodule
+
+module ICE_IO_DLY(PACKAGEPIN, LATCHINPUTVALUE, CLOCKENABLE, INPUTCLK, OUTPUTCLK, OUTPUTENABLE, DOUT1, DOUT0, DIN1, DIN0, SCLK, SDI, CRSEL, SDO);
+  input CLOCKENABLE;
+  input CRSEL;
+  output DIN0;
+  output DIN1;
+  input DOUT0;
+  input DOUT1;
+  input INPUTCLK;
+  input LATCHINPUTVALUE;
+  input OUTPUTCLK;
+  input OUTPUTENABLE;
+  inout PACKAGEPIN;
+  input SCLK;
+  input SDI;
+  output SDO;
+endmodule
+
+module ICE_IO_DS(PACKAGEPIN, PACKAGEPINB, LATCHINPUTVALUE, CLOCKENABLE, INPUTCLK, OUTPUTCLK, OUTPUTENABLE, DOUT1, DOUT0, DIN1, DIN0);
+  input CLOCKENABLE;
+  output DIN0;
+  output DIN1;
+  input DOUT0;
+  input DOUT1;
+  input INPUTCLK;
+  input LATCHINPUTVALUE;
+  input OUTPUTCLK;
+  input OUTPUTENABLE;
+  inout PACKAGEPIN;
+  inout PACKAGEPINB;
+endmodule
+
+module ICE_IO_OD(PACKAGEPIN, LATCHINPUTVALUE, CLOCKENABLE, INPUTCLK, OUTPUTCLK, OUTPUTENABLE, DOUT1, DOUT0, DIN1, DIN0);
+  input CLOCKENABLE;
+  output DIN0;
+  output DIN1;
+  input DOUT0;
+  input DOUT1;
+  input INPUTCLK;
+  input LATCHINPUTVALUE;
+  input OUTPUTCLK;
+  input OUTPUTENABLE;
+  inout PACKAGEPIN;
+endmodule
+
+module ICE_IR500_DRV(IRLEDEN, IRPWM, CURREN, IRLEDEN2, IRPWM2, IRLED1, IRLED2);
+  input CURREN;
+  output IRLED1;
+  output IRLED2;
+  input IRLEDEN;
+  input IRLEDEN2;
+  input IRPWM;
+  input IRPWM2;
+endmodule
+
+module INV(I, O);
+  input I;
+  output O;
+endmodule
+
+module IO_PAD(PACKAGEPIN, DOUT, DIN, OE);
+  input DIN;
+  output DOUT;
+  input OE;
+  inout PACKAGEPIN;
+endmodule
+
+module InMux(I, O);
+  input I;
+  output O;
+endmodule
+
+module IoInMux(I, O);
+  input I;
+  output O;
+endmodule
+
+module IoSpan4Mux(I, O);
+  input I;
+  output O;
+endmodule
+
+module IpInMux(I, O);
+  input I;
+  output O;
+endmodule
+
+module IpOutMux(I, O);
+  input I;
+  output O;
+endmodule
+
+module LocalMux(I, O);
+  input I;
+  output O;
+endmodule
+
+module LogicCell(carryout, lcout, carryin, clk, clkb, in0, in1, in2, in3, sr);
+  input carryin;
+  output carryout;
+  input clk;
+  input clkb;
+  input in0;
+  input in1;
+  input in2;
+  input in3;
+  output lcout;
+  input sr;
+endmodule
+
+module LogicCell2(carryout, lcout, carryin, clk, in0, in1, in2, in3, sr, ce);
+  input carryin;
+  output carryout;
+  input ce;
+  input clk;
+  input in0;
+  input in1;
+  input in2;
+  input in3;
+  output lcout;
+  input sr;
+endmodule
+
+module LogicCell40(carryout, lcout, ltout, carryin, clk, in0, in1, in2, in3, sr, ce);
+  input carryin;
+  output carryout;
+  input ce;
+  input clk;
+  input in0;
+  input in1;
+  input in2;
+  input in3;
+  output lcout;
+  output ltout;
+  input sr;
+endmodule
+
+module Odrv12(I, O);
+  input I;
+  output O;
+endmodule
+
+module Odrv4(I, O);
+  input I;
+  output O;
+endmodule
+
+module PAD_BANK0(PAD, PADIN, PADOUT, PADOEN);
+  inout PAD;
+  output PADIN;
+  input PADOEN;
+  input PADOUT;
+endmodule
+
+module PAD_BANK1(PAD, PADIN, PADOUT, PADOEN);
+  inout PAD;
+  output PADIN;
+  input PADOEN;
+  input PADOUT;
+endmodule
+
+module PAD_BANK2(PAD, PADIN, PADOUT, PADOEN);
+  inout PAD;
+  output PADIN;
+  input PADOEN;
+  input PADOUT;
+endmodule
+
+module PAD_BANK3(PAD, PADIN, PADOUT, PADOEN);
+  inout PAD;
+  output PADIN;
+  input PADOEN;
+  input PADOUT;
+endmodule
+
+module PLL40(PLLIN, PLLOUTCORE, PLLOUTGLOBAL, EXTFEEDBACK, DYNAMICDELAY, LOCK, BYPASS, RESETB, SDI, SDO, SCLK, LATCHINPUTVALUE);
+  input BYPASS;
+  input [7:0] DYNAMICDELAY;
+  input EXTFEEDBACK;
+  input LATCHINPUTVALUE;
+  output LOCK;
+  input PLLIN;
+  output PLLOUTCORE;
+  output PLLOUTGLOBAL;
+  input RESETB;
+  input SCLK;
+  input SDI;
+  output SDO;
+endmodule
+
+module PLL40_2(PLLIN, PLLOUTCOREA, PLLOUTGLOBALA, PLLOUTCOREB, PLLOUTGLOBALB, EXTFEEDBACK, DYNAMICDELAY, LOCK, BYPASS, RESETB, SDI, SDO, SCLK, LATCHINPUTVALUE);
+  input BYPASS;
+  input [7:0] DYNAMICDELAY;
+  input EXTFEEDBACK;
+  input LATCHINPUTVALUE;
+  output LOCK;
+  input PLLIN;
+  output PLLOUTCOREA;
+  output PLLOUTCOREB;
+  output PLLOUTGLOBALA;
+  output PLLOUTGLOBALB;
+  input RESETB;
+  input SCLK;
+  input SDI;
+  output SDO;
+endmodule
+
+module PLL40_2F(PLLIN, PLLOUTCOREA, PLLOUTGLOBALA, PLLOUTCOREB, PLLOUTGLOBALB, EXTFEEDBACK, DYNAMICDELAY, LOCK, BYPASS, RESETB, SDI, SDO, SCLK, LATCHINPUTVALUE);
+  input BYPASS;
+  input [7:0] DYNAMICDELAY;
+  input EXTFEEDBACK;
+  input LATCHINPUTVALUE;
+  output LOCK;
+  input PLLIN;
+  output PLLOUTCOREA;
+  output PLLOUTCOREB;
+  output PLLOUTGLOBALA;
+  output PLLOUTGLOBALB;
+  input RESETB;
+  input SCLK;
+  input SDI;
+  output SDO;
+endmodule
+
+module PREIO(PADIN, PADOUT, PADOEN, LATCHINPUTVALUE, CLOCKENABLE, INPUTCLK, OUTPUTCLK, OUTPUTENABLE, DOUT1, DOUT0, DIN1, DIN0);
+  input CLOCKENABLE;
+  output DIN0;
+  output DIN1;
+  input DOUT0;
+  input DOUT1;
+  input INPUTCLK;
+  input LATCHINPUTVALUE;
+  input OUTPUTCLK;
+  input OUTPUTENABLE;
+  input PADIN;
+  output PADOEN;
+  output PADOUT;
+endmodule
+
+module PRE_IO(PADIN, PADOUT, PADOEN, LATCHINPUTVALUE, CLOCKENABLE, INPUTCLK, OUTPUTCLK, OUTPUTENABLE, DOUT1, DOUT0, DIN1, DIN0);
+  input CLOCKENABLE;
+  output DIN0;
+  output DIN1;
+  input DOUT0;
+  input DOUT1;
+  input INPUTCLK;
+  input LATCHINPUTVALUE;
+  input OUTPUTCLK;
+  input OUTPUTENABLE;
+  input PADIN;
+  output PADOEN;
+  output PADOUT;
+endmodule
+
+module PRE_IO_GBUF(GLOBALBUFFEROUTPUT, PADSIGNALTOGLOBALBUFFER);
+  output GLOBALBUFFEROUTPUT;
+  input PADSIGNALTOGLOBALBUFFER;
+endmodule
+
+module QuadClkMux(I, O);
+  input I;
+  output O;
+endmodule
+
+module SB_G2TBuf(I, O);
+  input I;
+  output O;
+endmodule
+
+module SMCCLK(CLK);
+  output CLK;
+endmodule
+
+module SRMux(I, O);
+  input I;
+  output O;
+endmodule
+
+module Sp12to4(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span12Mux(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span12Mux_h(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span12Mux_s0_h(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span12Mux_s0_v(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span12Mux_s10_h(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span12Mux_s10_v(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span12Mux_s11_h(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span12Mux_s11_v(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span12Mux_s1_h(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span12Mux_s1_v(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span12Mux_s2_h(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span12Mux_s2_v(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span12Mux_s3_h(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span12Mux_s3_v(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span12Mux_s4_h(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span12Mux_s4_v(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span12Mux_s5_h(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span12Mux_s5_v(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span12Mux_s6_h(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span12Mux_s6_v(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span12Mux_s7_h(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span12Mux_s7_v(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span12Mux_s8_h(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span12Mux_s8_v(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span12Mux_s9_h(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span12Mux_s9_v(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span12Mux_v(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span4Mux(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span4Mux_h(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span4Mux_s0_h(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span4Mux_s0_v(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span4Mux_s1_h(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span4Mux_s1_v(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span4Mux_s2_h(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span4Mux_s2_v(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span4Mux_s3_h(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span4Mux_s3_v(I, O);
+  input I;
+  output O;
+endmodule
+
+module Span4Mux_v(I, O);
+  input I;
+  output O;
+endmodule
+
+module carry_logic(cout, carry_in, a, a_bar, b, b_bar, vg_en);
+  input a;
+  input a_bar;
+  input b;
+  input b_bar;
+  input carry_in;
+  output cout;
+  input vg_en;
+endmodule
+
+module clut4(lut4, in0, in1, in2, in3, in0b, in1b, in2b, in3b, cbit);
+  input [15:0] cbit;
+  input in0;
+  input in0b;
+  input in1;
+  input in1b;
+  input in2;
+  input in2b;
+  input in3;
+  input in3b;
+  output lut4;
+endmodule
+
+module coredffr(q, d, purst, S_R, cbit, clk, clkb);
+  input S_R;
+  input [1:0] cbit;
+  input clk;
+  input clkb;
+  input d;
+  input purst;
+  output q;
+endmodule
+
+module coredffr2(q, d, purst, S_R, cbit, clk, clkb, ce);
+  input S_R;
+  input [1:0] cbit;
+  input ce;
+  input clk;
+  input clkb;
+  input d;
+  input purst;
+  output q;
+endmodule
+
+module gio2CtrlBuf(I, O);
+  input I;
+  output O;
+endmodule
+
+module inv_hvt(Y, A);
+  input A;
+  output Y;
+endmodule
+
+module logic_cell(carry_out, lc_out, carry_in, cbit, clk, clkb, in0, in1, in2, in3, prog, purst, s_r);
+  input carry_in;
+  output carry_out;
+  input [20:0] cbit;
+  input clk;
+  input clkb;
+  input in0;
+  input in1;
+  input in2;
+  input in3;
+  output lc_out;
+  input prog;
+  input purst;
+  input s_r;
+endmodule
+
+module logic_cell2(carry_out, lc_out, carry_in, cbit, clk, clkb, in0, in1, in2, in3, prog, purst, s_r, ce);
+  input carry_in;
+  output carry_out;
+  input [20:0] cbit;
+  input ce;
+  input clk;
+  input clkb;
+  input in0;
+  input in1;
+  input in2;
+  input in3;
+  output lc_out;
+  input prog;
+  input purst;
+  input s_r;
+endmodule
+
+module logic_cell40(carry_out, lc_out, lt_out, carry_in, cbit, clk, clkb, in0, in1, in2, in3, prog, purst, s_r, ce);
+  input carry_in;
+  output carry_out;
+  input [20:0] cbit;
+  input ce;
+  input clk;
+  input clkb;
+  input in0;
+  input in1;
+  input in2;
+  input in3;
+  output lc_out;
+  output lt_out;
+  input prog;
+  input purst;
+  input s_r;
+endmodule
+
+module o_mux(O, in0, in1, cbit, prog);
+  output O;
+  input cbit;
+  input in0;
+  input in1;
+  input prog;
+endmodule
+
+module sync_clk_enable(D, NC, Q);
+  input D;
+  input NC;
+  output Q;
+endmodule
+
+module GND(Y);
+  output Y;
+endmodule
+
+module VCC(Y);
+  output Y;
+endmodule
+
+module INTERCONN(I, O);
+  input I;
+  output O;
+endmodule
diff --git a/icetime/icetime.cc b/icetime/icetime.cc
index 7e32295..9ba91a9 100644
--- a/icetime/icetime.cc
+++ b/icetime/icetime.cc
@@ -46,6 +46,7 @@ std::map<std::pair<int, int>, std::pair<int, int>> connection_pos;
 std::set<int> used_nets;
 
 std::set<net_segment_t> interconn_src, interconn_dst;
+std::set<int> no_interconn_net;
 
 // netlist_cells[cell_name][port_name] = port_expr
 std::map<std::string, std::map<std::string, std::string>> netlist_cells;
@@ -341,6 +342,29 @@ std::string make_seg_pre_io(int x, int y, int z)
 	return cell;
 }
 
+std::string make_lc40(int x, int y, int z)
+{
+	auto cell = stringf("lc40_%d_%d_%d", x, y, z);
+
+	if (netlist_cell_types.count(cell))
+		return cell;
+
+	netlist_cell_types[cell] = "LogicCell40";
+	netlist_cells[cell]["carryin"] = "";
+	netlist_cells[cell]["ce"] = "";
+	netlist_cells[cell]["clk"] = "";
+	netlist_cells[cell]["in0"] = "";
+	netlist_cells[cell]["in1"] = "";
+	netlist_cells[cell]["in2"] = "";
+	netlist_cells[cell]["in3"] = "";
+	netlist_cells[cell]["sr"] = "";
+	netlist_cells[cell]["carryout"] = "";
+	netlist_cells[cell]["lcout"] = "";
+	netlist_cells[cell]["ltout"] = "";
+
+	return cell;
+}
+
 void make_odrv(int x, int y, int src)
 {
 	for (int dst : net_buffers[src])
@@ -357,6 +381,11 @@ void make_odrv(int x, int y, int src)
 			if (seg.name.substr(0, 5) == "sp12_") is12 = true;
 		}
 
+		if (!is4 && !is12) {
+			register_interconn_src(x, y, src);
+			continue;
+		}
+
 		assert(is4 != is12);
 		netlist_cell_types[cell] = is4 ? "Odrv4" : "Odrv12";
 		netlist_cells[cell]["I"] = net_name(src);
@@ -378,12 +407,14 @@ void make_inmux(int x, int y, int dst)
 		netlist_cells[cell]["I"] = net_name(src);
 		netlist_cells[cell]["O"] = net_name(dst);
 		register_interconn_dst(x, y, src);
+		no_interconn_net.insert(dst);
 	}
 }
 
 void make_seg_cell(int net, const net_segment_t &seg)
 {
-	int a, b;
+	int a = -1, b = -1;
+	char c = 0;
 
 	if (sscanf(seg.name.c_str(), "io_%d/D_IN_%d", &a, &b) == 2) {
 		auto cell = make_seg_pre_io(seg.x, seg.y, a);
@@ -398,6 +429,20 @@ void make_seg_cell(int net, const net_segment_t &seg)
 		make_inmux(seg.x, seg.y, net);
 		return;
 	}
+
+	if (sscanf(seg.name.c_str(), "lutff_%d/in_%d", &a, &b) == 2) {
+		auto cell = make_lc40(seg.x, seg.y, a);
+		netlist_cells[cell][stringf("in%d", b)] = net_name(net);
+		make_inmux(seg.x, seg.y, net);
+		return;
+	}
+
+	if (sscanf(seg.name.c_str(), "lutff_%d/ou%c", &a, &c) == 2 && c == 't') {
+		auto cell = make_lc40(seg.x, seg.y, a);
+		netlist_cells[cell]["lcout"] = net_name(net);
+		make_odrv(seg.x, seg.y, net);
+		return;
+	}
 }
 
 struct make_interconn_worker_t
@@ -410,13 +455,13 @@ struct make_interconn_worker_t
 		auto &children = net_tree[src];
 
 		for (auto &other : net_buffers[src])
-			if (!net_tree.count(other)) {
+			if (!net_tree.count(other) && !no_interconn_net.count(other)) {
 				build_net_tree(other);
 				children.insert(other);
 			}
 
 		for (auto &other : net_routing[src])
-			if (!net_tree.count(other)) {
+			if (!net_tree.count(other) && !no_interconn_net.count(other)) {
 				build_net_tree(other);
 				children.insert(other);
 			}
@@ -506,18 +551,27 @@ void make_interconn(const net_segment_t &src)
 #if 1
 	printf("// INTERCONN %d %d %s %d\n", src.x, src.y, src.name.c_str(), src.net);
 	std::function<void(int,int)> print_net_tree = [&] (int net, int indent) {
-		printf("// %*sNET_TREE %d\n", 2*indent, "", net);
+		printf("// %*sNET_TREE %d\n", indent, "", net);
 		for (int child : worker.net_tree.at(net))
-			print_net_tree(child, indent+1);
+			print_net_tree(child, indent+2);
 	};
-	std::function<void(const net_segment_t&,int)> print_seg_tree = [&] (const net_segment_t &seg, int indent) {
-		printf("// %*sSEG_TREE %d %d %s %d\n", 2*indent, "", seg.x, seg.y, seg.name.c_str(), seg.net);
-		for (auto &child : worker.seg_tree.at(seg))
-			print_seg_tree(child, indent+1);
+	std::function<void(const net_segment_t&,int,bool)> print_seg_tree = [&] (const net_segment_t &seg, int indent, bool chain) {
+		printf("// %*sSEG_TREE %d %d %s %d\n", indent, chain ? "`" : "", seg.x, seg.y, seg.name.c_str(), seg.net);
+		auto &children = worker.seg_tree.at(seg);
+		bool child_chain = children.size() == 1;
+		for (auto &child : children)
+			print_seg_tree(child, child_chain ? (chain ? indent : indent+1) : indent+2, child_chain);
 	};
-	print_net_tree(src.net, 1);
-	print_seg_tree(src, 1);
+	print_net_tree(src.net, 2);
+	print_seg_tree(src, 2, false);
 #endif
+
+	// FIXME: interconnect cells
+	for (auto &it : worker.net_tree)
+	for (auto &dst : it.second)
+		if (declared_nets.count(dst))
+			extra_vlog.push_back(stringf("  INTERCONN conn_%d_%d (.I(%s), .O(%s));\n",
+					src.net, dst, net_name(src.net).c_str(), net_name(dst).c_str()));
 }
 
 void help(const char *cmd)
-- 
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