From dd00d41fb22f9b1f2715d1f8d93de43dc63ba88d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 2 Aug 2015 09:10:59 +0200
Subject: Added colbufs test case

---
 icefuzz/tests/colbufs.pcf |  8 ++++++++
 icefuzz/tests/colbufs.v   | 34 ++++++++++++++++++++++++++++++++++
 2 files changed, 42 insertions(+)
 create mode 100644 icefuzz/tests/colbufs.pcf
 create mode 100644 icefuzz/tests/colbufs.v

(limited to 'icefuzz')

diff --git a/icefuzz/tests/colbufs.pcf b/icefuzz/tests/colbufs.pcf
new file mode 100644
index 0000000..61c3d41
--- /dev/null
+++ b/icefuzz/tests/colbufs.pcf
@@ -0,0 +1,8 @@
+set_io clk[0] J3
+set_io clk[1] G1
+set_io clk[2] R9
+set_io clk[3] F7
+set_io clk[4] K9
+set_io clk[5] C8
+set_io clk[6] H11
+set_io clk[7] H16
diff --git a/icefuzz/tests/colbufs.v b/icefuzz/tests/colbufs.v
new file mode 100644
index 0000000..b84c189
--- /dev/null
+++ b/icefuzz/tests/colbufs.v
@@ -0,0 +1,34 @@
+module top #(
+	parameter NUM_BITS = 8
+) (
+	input [NUM_BITS-1:0] clk,
+	output reg [NUM_BITS-1:0] y
+);
+	wire [NUM_BITS-1:0] t1;
+	reg [NUM_BITS-1:0] t2;
+
+	genvar i;
+	generate for (i = 0; i < NUM_BITS; i = i+1) begin:bitslice
+		SB_RAM40_4K #(
+			.READ_MODE(0),
+			.WRITE_MODE(0)
+		) ram40 (
+			.WADDR(8'b0),
+			.RADDR(8'b0),
+			.MASK(~16'b0),
+			.WDATA(8'b0),
+			.RDATA(t1[i]),
+			.WE(1'b1),
+			.WCLKE(1'b1),
+			.WCLK(clk[i]),
+			.RE(1'b1),
+			.RCLKE(1'b1),
+			.RCLK(clk[i])
+		);
+
+		always @(posedge clk[i]) begin
+			t2[i] <= t1[i];
+			y[i] <= t2[i];
+		end
+	end endgenerate
+endmodule
-- 
cgit v1.2.3