From b00ffb1c091b65ed6c741dde74a4e7d5f709efd1 Mon Sep 17 00:00:00 2001 From: Scott Shawcroft Date: Sun, 2 Jul 2017 15:38:44 -0700 Subject: Introduce device class into fuxx workign directories and have glbcheck handle unsupported 5k tiles ok. --- icefuzz/Makefile | 42 +-- icefuzz/cached_ramb_5k.txt | 667 --------------------------------------------- icefuzz/cached_ramt_5k.txt | 630 ------------------------------------------ icefuzz/fuzzconfig.py | 9 + icefuzz/glbcheck.py | 17 +- icefuzz/make_aig.py | 19 +- icefuzz/make_binop.py | 19 +- icefuzz/make_cluster.py | 19 +- icefuzz/make_fanout.py | 19 +- icefuzz/make_fflogic.py | 17 +- icefuzz/make_gbio.py | 19 +- icefuzz/make_gbio2.py | 19 +- icefuzz/make_io.py | 19 +- icefuzz/make_iopack.py | 18 +- icefuzz/make_logic.py | 18 +- icefuzz/make_mem.py | 19 +- icefuzz/make_mesh.py | 20 +- icefuzz/make_pin2pin.py | 19 +- icefuzz/make_pll.py | 20 +- icefuzz/make_prim.py | 19 +- icefuzz/make_ram40.py | 19 +- 21 files changed, 198 insertions(+), 1469 deletions(-) (limited to 'icefuzz') diff --git a/icefuzz/Makefile b/icefuzz/Makefile index b3e3b95..2e42889 100644 --- a/icefuzz/Makefile +++ b/icefuzz/Makefile @@ -2,7 +2,7 @@ include ../config.mk export LC_ALL=C export ICE_SBTIMER_LP=1 -DEVICECLASS := 1k +DEVICECLASS = 1k ifeq ($(DEVICECLASS), 384) DEVICE := lp384-cm49 @@ -14,7 +14,7 @@ ifeq ($(DEVICECLASS), 1k) endif ifeq ($(DEVICECLASS), 5k) - DEVICE := up5k-sg48 + DEVICE := up5k-sg48 RAM_SUFFIX := _5k endif @@ -66,7 +66,7 @@ endif timings: ifeq ($(DEVICECLASS),8k) cp tmedges.txt tmedges.tmp - set -e; for f in work_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done + set -e; for f in work_$(DEVICECLASS)_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done sort -u tmedges.tmp > tmedges.txt && rm -f tmedges.tmp python3 timings.py -t timings_hx8k.txt work_*/*.sdf > timings_hx8k.new mv timings_hx8k.new timings_hx8k.txt @@ -75,13 +75,13 @@ ifeq ($(DEVICECLASS),8k) else ifeq ($(DEVICECLASS),384) cp tmedges.txt tmedges.tmp - set -e; for f in work_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done + set -e; for f in work_$(DEVICECLASS)_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done sort -u tmedges.tmp > tmedges.txt && rm -f tmedges.tmp python3 timings.py -t timings_lp384.txt work_*/*.slp > timings_lp384.new mv timings_lp384.new timings_lp384.txt else cp tmedges.txt tmedges.tmp - set -e; for f in work_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done + set -e; for f in work_$(DEVICECLASS)_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done sort -u tmedges.tmp > tmedges.txt && rm -f tmedges.tmp python3 timings.py -t timings_hx1k.txt work_*/*.sdf > timings_hx1k.new mv timings_hx1k.new timings_hx1k.txt @@ -104,16 +104,16 @@ data_cached.txt: cached_io.txt cached_logic.txt cached_ramb$(RAM_SUFFIX).txt cac gawk '{ print "ramt$(RAM_SUFFIX)", $$0; }' cached_ramt$(RAM_SUFFIX).txt >> data_cached.new mv data_cached.new data_cached.txt -bitdata_io.txt: data_cached.txt $(addprefix data_,$(addsuffix .txt,$(TESTS))) +bitdata_io.txt: data_cached.txt $(addprefix data_$(DEVICECLASS)_,$(addsuffix .txt,$(TESTS))) grep ^io $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ -bitdata_logic.txt: data_cached.txt $(addprefix data_,$(addsuffix .txt,$(TESTS))) +bitdata_logic.txt: data_cached.txt $(addprefix data_$(DEVICECLASS)_,$(addsuffix .txt,$(TESTS))) grep ^logic $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ -bitdata_ramb$(RAM_SUFFIX).txt: data_cached.txt $(addprefix data_,$(addsuffix .txt,$(TESTS))) +bitdata_ramb$(RAM_SUFFIX).txt: data_cached.txt $(addprefix data_$(DEVICECLASS)_,$(addsuffix .txt,$(TESTS))) grep ^ramb$(RAM_SUFFIX) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ -bitdata_ramt$(RAM_SUFFIX).txt: data_cached.txt $(addprefix data_,$(addsuffix .txt,$(TESTS))) +bitdata_ramt$(RAM_SUFFIX).txt: data_cached.txt $(addprefix data_$(DEVICECLASS)_,$(addsuffix .txt,$(TESTS))) grep ^ramt$(RAM_SUFFIX) $^ | tr -s ' ' | tr -d '\r' | cut -f2- -d' ' | sort -u > $@ datafiles: $(addprefix data_,$(addsuffix .txt,$(TESTS))) @@ -122,10 +122,10 @@ datafiles: $(addprefix data_,$(addsuffix .txt,$(TESTS))) $(MAKE) -C ../icepack define data_template -data_$(1).txt: make_$(1).py ../icepack/icepack +data_$(DEVICECLASS)_$(1).txt: make_$(1).py ../icepack/icepack ICEDEVICE=$(DEVICECLASS) python3 make_$(1).py - +ICEDEV=$(DEVICE) $(MAKE) -C work_$(1) - ICEDEVICE=$(DEVICECLASS) python3 extract.py work_$(1)/*.glb > $$@ + +ICEDEV=$(DEVICE) $(MAKE) -C work_$(DEVICECLASS)_$(1) + ICEDEVICE=$(DEVICECLASS) python3 extract.py work_$(DEVICECLASS)_$(1)/*.glb > $$@ endef $(foreach test,$(TESTS),$(eval $(call data_template,$(test)))) @@ -133,17 +133,17 @@ $(foreach test,$(TESTS),$(eval $(call data_template,$(test)))) %.ok: %.bin bash check.sh $< -check: $(addsuffix .ok,$(basename $(wildcard work_binop/*.bin))) -check: $(addsuffix .ok,$(basename $(wildcard work_pin2pin/*.bin))) -check: $(addsuffix .ok,$(basename $(wildcard work_mesh/*.bin))) -check: $(addsuffix .ok,$(basename $(wildcard work_fanout/*.bin))) -check: $(addsuffix .ok,$(basename $(wildcard work_logic/*.bin))) -check: $(addsuffix .ok,$(basename $(wildcard work_cluster/*.bin))) -check: $(addsuffix .ok,$(basename $(wildcard work_iopack/*.bin))) -check: $(addsuffix .ok,$(basename $(wildcard work_pll/*.bin))) +check: $(addsuffix .ok,$(basename $(wildcard work_$(DEVICECLASS)_binop/*.bin))) +check: $(addsuffix .ok,$(basename $(wildcard work_$(DEVICECLASS)_pin2pin/*.bin))) +check: $(addsuffix .ok,$(basename $(wildcard work_$(DEVICECLASS)_mesh/*.bin))) +check: $(addsuffix .ok,$(basename $(wildcard work_$(DEVICECLASS)_fanout/*.bin))) +check: $(addsuffix .ok,$(basename $(wildcard work_$(DEVICECLASS)_logic/*.bin))) +check: $(addsuffix .ok,$(basename $(wildcard work_$(DEVICECLASS)_cluster/*.bin))) +check: $(addsuffix .ok,$(basename $(wildcard work_$(DEVICECLASS)_iopack/*.bin))) +check: $(addsuffix .ok,$(basename $(wildcard work_$(DEVICECLASS)_pll/*.bin))) clean: - rm -rf work_* + rm -rf work_$(DEVICECLASS)_* rm -rf data_*.txt rm -rf bitdata_*.txt rm -rf database_*.txt diff --git a/icefuzz/cached_ramb_5k.txt b/icefuzz/cached_ramb_5k.txt index b19db9a..ad427d9 100644 --- a/icefuzz/cached_ramb_5k.txt +++ b/icefuzz/cached_ramb_5k.txt @@ -1,91 +1,39 @@ (0 0) Negative Clock bit -(0 10) routing glb_netwk_2 glb2local_2 -(0 10) routing glb_netwk_3 glb2local_2 (0 10) routing glb_netwk_6 glb2local_2 -(0 10) routing glb_netwk_7 glb2local_2 -(0 11) routing glb_netwk_1 glb2local_2 -(0 11) routing glb_netwk_3 glb2local_2 (0 11) routing glb_netwk_5 glb2local_2 -(0 11) routing glb_netwk_7 glb2local_2 -(0 12) routing glb_netwk_2 glb2local_3 -(0 12) routing glb_netwk_3 glb2local_3 (0 12) routing glb_netwk_6 glb2local_3 -(0 12) routing glb_netwk_7 glb2local_3 -(0 13) routing glb_netwk_1 glb2local_3 -(0 13) routing glb_netwk_3 glb2local_3 (0 13) routing glb_netwk_5 glb2local_3 -(0 13) routing glb_netwk_7 glb2local_3 -(0 14) routing glb_netwk_4 wire_bram/ram/RE (0 14) routing glb_netwk_6 wire_bram/ram/RE (0 14) routing lc_trk_g2_4 wire_bram/ram/RE (0 14) routing lc_trk_g3_5 wire_bram/ram/RE -(0 15) routing glb_netwk_2 wire_bram/ram/RE (0 15) routing glb_netwk_6 wire_bram/ram/RE (0 15) routing lc_trk_g1_5 wire_bram/ram/RE (0 15) routing lc_trk_g3_5 wire_bram/ram/RE (0 2) routing glb_netwk_2 wire_bram/ram/RCLK -(0 2) routing glb_netwk_3 wire_bram/ram/RCLK (0 2) routing glb_netwk_6 wire_bram/ram/RCLK (0 2) routing glb_netwk_7 wire_bram/ram/RCLK (0 2) routing lc_trk_g2_0 wire_bram/ram/RCLK (0 2) routing lc_trk_g3_1 wire_bram/ram/RCLK -(0 3) routing glb_netwk_1 wire_bram/ram/RCLK -(0 3) routing glb_netwk_3 wire_bram/ram/RCLK (0 3) routing glb_netwk_5 wire_bram/ram/RCLK (0 3) routing glb_netwk_7 wire_bram/ram/RCLK (0 3) routing lc_trk_g1_1 wire_bram/ram/RCLK (0 3) routing lc_trk_g3_1 wire_bram/ram/RCLK (0 4) routing glb_netwk_5 wire_bram/ram/RCLKE -(0 4) routing glb_netwk_7 wire_bram/ram/RCLKE (0 4) routing lc_trk_g2_2 wire_bram/ram/RCLKE (0 4) routing lc_trk_g3_3 wire_bram/ram/RCLKE -(0 5) routing glb_netwk_3 wire_bram/ram/RCLKE -(0 5) routing glb_netwk_7 wire_bram/ram/RCLKE (0 5) routing lc_trk_g1_3 wire_bram/ram/RCLKE (0 5) routing lc_trk_g3_3 wire_bram/ram/RCLKE -(0 6) routing glb_netwk_2 glb2local_0 (0 6) routing glb_netwk_3 glb2local_0 -(0 6) routing glb_netwk_6 glb2local_0 -(0 6) routing glb_netwk_7 glb2local_0 -(0 7) routing glb_netwk_1 glb2local_0 (0 7) routing glb_netwk_3 glb2local_0 (0 7) routing glb_netwk_5 glb2local_0 -(0 7) routing glb_netwk_7 glb2local_0 -(0 8) routing glb_netwk_2 glb2local_1 -(0 8) routing glb_netwk_3 glb2local_1 -(0 8) routing glb_netwk_6 glb2local_1 -(0 8) routing glb_netwk_7 glb2local_1 -(0 9) routing glb_netwk_1 glb2local_1 -(0 9) routing glb_netwk_3 glb2local_1 -(0 9) routing glb_netwk_5 glb2local_1 -(0 9) routing glb_netwk_7 glb2local_1 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_0 glb2local_2 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_2 glb2local_2 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2 -(1 11) routing glb_netwk_4 glb2local_2 (1 11) routing glb_netwk_5 glb2local_2 (1 11) routing glb_netwk_6 glb2local_2 -(1 11) routing glb_netwk_7 glb2local_2 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_0 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_2 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3 -(1 13) routing glb_netwk_4 glb2local_3 (1 13) routing glb_netwk_5 glb2local_3 (1 13) routing glb_netwk_6 glb2local_3 -(1 13) routing glb_netwk_7 glb2local_3 -(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_0 wire_bram/ram/RE -(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_bram/ram/RE -(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_bram/ram/RE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g1_5 wire_bram/ram/RE @@ -100,10 +48,7 @@ (1 2) routing glb_netwk_6 wire_bram/ram/RCLK (1 2) routing glb_netwk_7 wire_bram/ram/RCLK (1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_l_9 sp4_h_r_17 -(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_1 wire_bram/ram/RCLKE -(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_3 wire_bram/ram/RCLKE (1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_5 wire_bram/ram/RCLKE -(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_7 wire_bram/ram/RCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g0_2 wire_bram/ram/RCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g1_3 wire_bram/ram/RCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g2_2 wire_bram/ram/RCLKE @@ -112,39 +57,15 @@ (1 5) routing lc_trk_g1_3 wire_bram/ram/RCLKE (1 5) routing lc_trk_g2_2 wire_bram/ram/RCLKE (1 5) routing lc_trk_g3_3 wire_bram/ram/RCLKE -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_0 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_2 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0 -(1 7) routing glb_netwk_4 glb2local_0 (1 7) routing glb_netwk_5 glb2local_0 -(1 7) routing glb_netwk_6 glb2local_0 -(1 7) routing glb_netwk_7 glb2local_0 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_0 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_2 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_7 glb2local_1 -(1 9) routing glb_netwk_4 glb2local_1 -(1 9) routing glb_netwk_5 glb2local_1 -(1 9) routing glb_netwk_6 glb2local_1 -(1 9) routing glb_netwk_7 glb2local_1 (10 0) routing sp4_h_l_40 sp4_h_r_1 -(10 0) routing sp4_h_l_47 sp4_h_r_1 (10 0) routing sp4_v_b_7 sp4_h_r_1 (10 0) routing sp4_v_t_45 sp4_h_r_1 (10 1) routing sp4_h_l_42 sp4_v_b_1 -(10 1) routing sp4_h_r_8 sp4_v_b_1 (10 1) routing sp4_v_t_40 sp4_v_b_1 (10 1) routing sp4_v_t_47 sp4_v_b_1 -(10 10) routing sp4_h_r_11 sp4_h_l_42 (10 10) routing sp4_h_r_4 sp4_h_l_42 (10 10) routing sp4_v_b_2 sp4_h_l_42 (10 10) routing sp4_v_t_36 sp4_h_l_42 @@ -152,8 +73,6 @@ (10 11) routing sp4_h_r_1 sp4_v_t_42 (10 11) routing sp4_v_b_11 sp4_v_t_42 (10 11) routing sp4_v_b_4 sp4_v_t_42 -(10 12) routing sp4_h_l_39 sp4_h_r_10 -(10 12) routing sp4_h_l_42 sp4_h_r_10 (10 12) routing sp4_v_b_4 sp4_h_r_10 (10 12) routing sp4_v_t_40 sp4_h_r_10 (10 13) routing sp4_h_l_41 sp4_v_b_10 @@ -169,7 +88,6 @@ (10 15) routing sp4_v_b_2 sp4_v_t_47 (10 15) routing sp4_v_b_7 sp4_v_t_47 (10 2) routing sp4_h_r_10 sp4_h_l_36 -(10 2) routing sp4_h_r_5 sp4_h_l_36 (10 2) routing sp4_v_b_8 sp4_h_l_36 (10 2) routing sp4_v_t_42 sp4_h_l_36 (10 3) routing sp4_h_l_45 sp4_v_t_36 @@ -178,24 +96,16 @@ (10 3) routing sp4_v_b_5 sp4_v_t_36 (10 4) routing sp4_h_l_36 sp4_h_r_4 (10 4) routing sp4_h_l_45 sp4_h_r_4 -(10 4) routing sp4_v_b_10 sp4_h_r_4 (10 4) routing sp4_v_t_46 sp4_h_r_4 (10 5) routing sp4_h_l_47 sp4_v_b_4 (10 5) routing sp4_h_r_11 sp4_v_b_4 (10 5) routing sp4_v_t_36 sp4_v_b_4 (10 5) routing sp4_v_t_45 sp4_v_b_4 -(10 6) routing sp4_h_r_1 sp4_h_l_41 -(10 6) routing sp4_h_r_8 sp4_h_l_41 (10 6) routing sp4_v_b_11 sp4_h_l_41 (10 6) routing sp4_v_t_47 sp4_h_l_41 (10 7) routing sp4_h_l_46 sp4_v_t_41 -(10 7) routing sp4_h_r_10 sp4_v_t_41 (10 7) routing sp4_v_b_1 sp4_v_t_41 (10 7) routing sp4_v_b_8 sp4_v_t_41 -(10 8) routing sp4_h_l_41 sp4_h_r_7 -(10 8) routing sp4_h_l_46 sp4_h_r_7 -(10 8) routing sp4_v_b_1 sp4_h_r_7 -(10 8) routing sp4_v_t_39 sp4_h_r_7 (10 9) routing sp4_h_l_36 sp4_v_b_7 (10 9) routing sp4_h_r_2 sp4_v_b_7 (10 9) routing sp4_v_t_41 sp4_v_b_7 @@ -204,15 +114,11 @@ (11 0) routing sp4_h_r_9 sp4_v_b_2 (11 0) routing sp4_v_t_43 sp4_v_b_2 (11 0) routing sp4_v_t_46 sp4_v_b_2 -(11 1) routing sp4_h_l_39 sp4_h_r_2 -(11 1) routing sp4_h_l_43 sp4_h_r_2 (11 1) routing sp4_v_b_2 sp4_h_r_2 -(11 1) routing sp4_v_b_8 sp4_h_r_2 (11 10) routing sp4_h_l_38 sp4_v_t_45 (11 10) routing sp4_h_r_2 sp4_v_t_45 (11 10) routing sp4_v_b_0 sp4_v_t_45 (11 10) routing sp4_v_b_5 sp4_v_t_45 -(11 11) routing sp4_h_r_0 sp4_h_l_45 (11 11) routing sp4_h_r_8 sp4_h_l_45 (11 11) routing sp4_v_t_39 sp4_h_l_45 (11 11) routing sp4_v_t_45 sp4_h_l_45 @@ -220,8 +126,6 @@ (11 12) routing sp4_h_r_6 sp4_v_b_11 (11 12) routing sp4_v_t_38 sp4_v_b_11 (11 12) routing sp4_v_t_45 sp4_v_b_11 -(11 13) routing sp4_h_l_38 sp4_h_r_11 -(11 13) routing sp4_h_l_46 sp4_h_r_11 (11 13) routing sp4_v_b_11 sp4_h_r_11 (11 13) routing sp4_v_b_5 sp4_h_r_11 (11 14) routing sp4_h_l_43 sp4_v_t_46 @@ -231,48 +135,36 @@ (11 15) routing sp4_h_r_11 sp4_h_l_46 (11 15) routing sp4_h_r_3 sp4_h_l_46 (11 15) routing sp4_v_t_40 sp4_h_l_46 -(11 15) routing sp4_v_t_46 sp4_h_l_46 (11 2) routing sp4_h_l_44 sp4_v_t_39 (11 2) routing sp4_h_r_8 sp4_v_t_39 (11 2) routing sp4_v_b_11 sp4_v_t_39 (11 2) routing sp4_v_b_6 sp4_v_t_39 -(11 3) routing sp4_h_r_2 sp4_h_l_39 -(11 3) routing sp4_h_r_6 sp4_h_l_39 (11 3) routing sp4_v_t_39 sp4_h_l_39 (11 3) routing sp4_v_t_45 sp4_h_l_39 (11 4) routing sp4_h_l_46 sp4_v_b_5 (11 4) routing sp4_h_r_0 sp4_v_b_5 (11 4) routing sp4_v_t_39 sp4_v_b_5 (11 4) routing sp4_v_t_44 sp4_v_b_5 -(11 5) routing sp4_h_l_40 sp4_h_r_5 -(11 5) routing sp4_h_l_44 sp4_h_r_5 (11 5) routing sp4_v_b_11 sp4_h_r_5 (11 5) routing sp4_v_b_5 sp4_h_r_5 (11 6) routing sp4_h_l_37 sp4_v_t_40 (11 6) routing sp4_h_r_11 sp4_v_t_40 (11 6) routing sp4_v_b_2 sp4_v_t_40 (11 6) routing sp4_v_b_9 sp4_v_t_40 -(11 7) routing sp4_h_r_5 sp4_h_l_40 -(11 7) routing sp4_h_r_9 sp4_h_l_40 (11 7) routing sp4_v_t_40 sp4_h_l_40 (11 7) routing sp4_v_t_46 sp4_h_l_40 (11 8) routing sp4_h_l_39 sp4_v_b_8 (11 8) routing sp4_h_r_3 sp4_v_b_8 (11 8) routing sp4_v_t_37 sp4_v_b_8 (11 8) routing sp4_v_t_40 sp4_v_b_8 -(11 9) routing sp4_h_l_37 sp4_h_r_8 -(11 9) routing sp4_h_l_45 sp4_h_r_8 (11 9) routing sp4_v_b_2 sp4_h_r_8 (11 9) routing sp4_v_b_8 sp4_h_r_8 -(12 0) routing sp4_h_l_46 sp4_h_r_2 (12 0) routing sp4_v_b_2 sp4_h_r_2 -(12 0) routing sp4_v_b_8 sp4_h_r_2 (12 0) routing sp4_v_t_39 sp4_h_r_2 (12 1) routing sp4_h_l_39 sp4_v_b_2 (12 1) routing sp4_h_l_45 sp4_v_b_2 (12 1) routing sp4_h_r_2 sp4_v_b_2 (12 1) routing sp4_v_t_46 sp4_v_b_2 -(12 10) routing sp4_h_r_5 sp4_h_l_45 (12 10) routing sp4_v_b_8 sp4_h_l_45 (12 10) routing sp4_v_t_39 sp4_h_l_45 (12 10) routing sp4_v_t_45 sp4_h_l_45 @@ -280,7 +172,6 @@ (12 11) routing sp4_h_r_2 sp4_v_t_45 (12 11) routing sp4_h_r_8 sp4_v_t_45 (12 11) routing sp4_v_b_5 sp4_v_t_45 -(12 12) routing sp4_h_l_45 sp4_h_r_11 (12 12) routing sp4_v_b_11 sp4_h_r_11 (12 12) routing sp4_v_b_5 sp4_h_r_11 (12 12) routing sp4_v_t_46 sp4_h_r_11 @@ -288,15 +179,12 @@ (12 13) routing sp4_h_l_46 sp4_v_b_11 (12 13) routing sp4_h_r_11 sp4_v_b_11 (12 13) routing sp4_v_t_45 sp4_v_b_11 -(12 14) routing sp4_h_r_8 sp4_h_l_46 (12 14) routing sp4_v_b_11 sp4_h_l_46 (12 14) routing sp4_v_t_40 sp4_h_l_46 -(12 14) routing sp4_v_t_46 sp4_h_l_46 (12 15) routing sp4_h_l_46 sp4_v_t_46 (12 15) routing sp4_h_r_11 sp4_v_t_46 (12 15) routing sp4_h_r_5 sp4_v_t_46 (12 15) routing sp4_v_b_8 sp4_v_t_46 -(12 2) routing sp4_h_r_11 sp4_h_l_39 (12 2) routing sp4_v_b_2 sp4_h_l_39 (12 2) routing sp4_v_t_39 sp4_h_l_39 (12 2) routing sp4_v_t_45 sp4_h_l_39 @@ -304,7 +192,6 @@ (12 3) routing sp4_h_r_2 sp4_v_t_39 (12 3) routing sp4_h_r_8 sp4_v_t_39 (12 3) routing sp4_v_b_11 sp4_v_t_39 -(12 4) routing sp4_h_l_39 sp4_h_r_5 (12 4) routing sp4_v_b_11 sp4_h_r_5 (12 4) routing sp4_v_b_5 sp4_h_r_5 (12 4) routing sp4_v_t_40 sp4_h_r_5 @@ -320,36 +207,26 @@ (12 7) routing sp4_h_r_11 sp4_v_t_40 (12 7) routing sp4_h_r_5 sp4_v_t_40 (12 7) routing sp4_v_b_2 sp4_v_t_40 -(12 8) routing sp4_h_l_40 sp4_h_r_8 (12 8) routing sp4_v_b_2 sp4_h_r_8 (12 8) routing sp4_v_b_8 sp4_h_r_8 -(12 8) routing sp4_v_t_45 sp4_h_r_8 (12 9) routing sp4_h_l_39 sp4_v_b_8 (12 9) routing sp4_h_l_45 sp4_v_b_8 -(12 9) routing sp4_h_r_8 sp4_v_b_8 (12 9) routing sp4_v_t_40 sp4_v_b_8 (13 0) routing sp4_h_l_39 sp4_v_b_2 (13 0) routing sp4_h_l_45 sp4_v_b_2 (13 0) routing sp4_v_t_39 sp4_v_b_2 (13 0) routing sp4_v_t_43 sp4_v_b_2 -(13 1) routing sp4_h_l_43 sp4_h_r_2 -(13 1) routing sp4_h_l_46 sp4_h_r_2 -(13 1) routing sp4_v_b_8 sp4_h_r_2 (13 1) routing sp4_v_t_44 sp4_h_r_2 (13 10) routing sp4_h_r_2 sp4_v_t_45 (13 10) routing sp4_h_r_8 sp4_v_t_45 (13 10) routing sp4_v_b_0 sp4_v_t_45 (13 10) routing sp4_v_b_8 sp4_v_t_45 -(13 11) routing sp4_h_r_0 sp4_h_l_45 -(13 11) routing sp4_h_r_5 sp4_h_l_45 (13 11) routing sp4_v_b_3 sp4_h_l_45 (13 11) routing sp4_v_t_39 sp4_h_l_45 (13 12) routing sp4_h_l_40 sp4_v_b_11 (13 12) routing sp4_h_l_46 sp4_v_b_11 (13 12) routing sp4_v_t_38 sp4_v_b_11 (13 12) routing sp4_v_t_46 sp4_v_b_11 -(13 13) routing sp4_h_l_38 sp4_h_r_11 -(13 13) routing sp4_h_l_45 sp4_h_r_11 (13 13) routing sp4_v_b_5 sp4_h_r_11 (13 13) routing sp4_v_t_43 sp4_h_r_11 (13 14) routing sp4_h_r_11 sp4_v_t_46 @@ -357,23 +234,18 @@ (13 14) routing sp4_v_b_11 sp4_v_t_46 (13 14) routing sp4_v_b_3 sp4_v_t_46 (13 15) routing sp4_h_r_3 sp4_h_l_46 -(13 15) routing sp4_h_r_8 sp4_h_l_46 (13 15) routing sp4_v_b_6 sp4_h_l_46 (13 15) routing sp4_v_t_40 sp4_h_l_46 (13 2) routing sp4_h_r_2 sp4_v_t_39 (13 2) routing sp4_h_r_8 sp4_v_t_39 (13 2) routing sp4_v_b_2 sp4_v_t_39 (13 2) routing sp4_v_b_6 sp4_v_t_39 -(13 3) routing sp4_h_r_11 sp4_h_l_39 -(13 3) routing sp4_h_r_6 sp4_h_l_39 (13 3) routing sp4_v_b_9 sp4_h_l_39 (13 3) routing sp4_v_t_45 sp4_h_l_39 (13 4) routing sp4_h_l_40 sp4_v_b_5 (13 4) routing sp4_h_l_46 sp4_v_b_5 (13 4) routing sp4_v_t_40 sp4_v_b_5 (13 4) routing sp4_v_t_44 sp4_v_b_5 -(13 5) routing sp4_h_l_39 sp4_h_r_5 -(13 5) routing sp4_h_l_44 sp4_h_r_5 (13 5) routing sp4_v_b_11 sp4_h_r_5 (13 5) routing sp4_v_t_37 sp4_h_r_5 (13 6) routing sp4_h_r_11 sp4_v_t_40 @@ -381,25 +253,20 @@ (13 6) routing sp4_v_b_5 sp4_v_t_40 (13 6) routing sp4_v_b_9 sp4_v_t_40 (13 7) routing sp4_h_r_2 sp4_h_l_40 -(13 7) routing sp4_h_r_9 sp4_h_l_40 (13 7) routing sp4_v_b_0 sp4_h_l_40 (13 7) routing sp4_v_t_46 sp4_h_l_40 (13 8) routing sp4_h_l_39 sp4_v_b_8 (13 8) routing sp4_h_l_45 sp4_v_b_8 (13 8) routing sp4_v_t_37 sp4_v_b_8 (13 8) routing sp4_v_t_45 sp4_v_b_8 -(13 9) routing sp4_h_l_37 sp4_h_r_8 -(13 9) routing sp4_h_l_40 sp4_h_r_8 (13 9) routing sp4_v_b_2 sp4_h_r_8 (13 9) routing sp4_v_t_38 sp4_h_r_8 -(14 0) routing bnr_op_0 lc_trk_g0_0 (14 0) routing lft_op_0 lc_trk_g0_0 (14 0) routing sp12_h_r_0 lc_trk_g0_0 (14 0) routing sp4_h_r_16 lc_trk_g0_0 (14 0) routing sp4_h_r_8 lc_trk_g0_0 (14 0) routing sp4_v_b_0 lc_trk_g0_0 (14 0) routing sp4_v_b_8 lc_trk_g0_0 -(14 1) routing bnr_op_0 lc_trk_g0_0 (14 1) routing sp12_h_l_15 lc_trk_g0_0 (14 1) routing sp12_h_r_0 lc_trk_g0_0 (14 1) routing sp4_h_r_0 lc_trk_g0_0 @@ -424,14 +291,12 @@ (14 12) routing bnl_op_0 lc_trk_g3_0 (14 12) routing rgt_op_0 lc_trk_g3_0 (14 12) routing sp12_v_b_0 lc_trk_g3_0 -(14 12) routing sp4_h_r_32 lc_trk_g3_0 (14 12) routing sp4_h_r_40 lc_trk_g3_0 (14 12) routing sp4_v_b_32 lc_trk_g3_0 (14 12) routing sp4_v_t_13 lc_trk_g3_0 (14 13) routing bnl_op_0 lc_trk_g3_0 (14 13) routing sp12_v_b_0 lc_trk_g3_0 (14 13) routing sp12_v_b_16 lc_trk_g3_0 -(14 13) routing sp4_h_r_24 lc_trk_g3_0 (14 13) routing sp4_h_r_40 lc_trk_g3_0 (14 13) routing sp4_r_v_b_40 lc_trk_g3_0 (14 13) routing sp4_v_b_32 lc_trk_g3_0 @@ -446,7 +311,6 @@ (14 15) routing bnl_op_4 lc_trk_g3_4 (14 15) routing sp12_v_b_20 lc_trk_g3_4 (14 15) routing sp12_v_b_4 lc_trk_g3_4 -(14 15) routing sp4_h_r_28 lc_trk_g3_4 (14 15) routing sp4_h_r_44 lc_trk_g3_4 (14 15) routing sp4_r_v_b_44 lc_trk_g3_4 (14 15) routing sp4_v_t_25 lc_trk_g3_4 @@ -470,7 +334,6 @@ (14 4) routing sp12_h_r_0 lc_trk_g1_0 (14 4) routing sp4_h_r_16 lc_trk_g1_0 (14 4) routing sp4_h_r_8 lc_trk_g1_0 -(14 4) routing sp4_v_b_0 lc_trk_g1_0 (14 4) routing sp4_v_b_8 lc_trk_g1_0 (14 5) routing bnr_op_0 lc_trk_g1_0 (14 5) routing sp12_h_l_15 lc_trk_g1_0 @@ -490,7 +353,6 @@ (14 7) routing sp12_h_l_3 lc_trk_g1_4 (14 7) routing sp12_h_r_20 lc_trk_g1_4 (14 7) routing sp4_h_l_9 lc_trk_g1_4 -(14 7) routing sp4_h_r_4 lc_trk_g1_4 (14 7) routing sp4_r_v_b_28 lc_trk_g1_4 (14 7) routing sp4_v_b_12 lc_trk_g1_4 (14 8) routing bnl_op_0 lc_trk_g2_0 @@ -512,9 +374,6 @@ (15 0) routing sp12_h_r_1 lc_trk_g0_1 (15 0) routing sp4_h_r_1 lc_trk_g0_1 (15 0) routing sp4_h_r_17 lc_trk_g0_1 -(15 0) routing sp4_h_r_9 lc_trk_g0_1 -(15 0) routing sp4_v_t_4 lc_trk_g0_1 -(15 1) routing bot_op_0 lc_trk_g0_0 (15 1) routing lft_op_0 lc_trk_g0_0 (15 1) routing sp12_h_r_0 lc_trk_g0_0 (15 1) routing sp4_h_r_0 lc_trk_g0_0 @@ -523,7 +382,6 @@ (15 1) routing sp4_v_b_16 lc_trk_g0_0 (15 10) routing rgt_op_5 lc_trk_g2_5 (15 10) routing sp12_v_b_5 lc_trk_g2_5 -(15 10) routing sp4_h_r_29 lc_trk_g2_5 (15 10) routing sp4_h_r_37 lc_trk_g2_5 (15 10) routing sp4_h_r_45 lc_trk_g2_5 (15 10) routing sp4_v_b_45 lc_trk_g2_5 @@ -536,7 +394,6 @@ (15 11) routing sp4_h_r_44 lc_trk_g2_4 (15 11) routing sp4_v_b_44 lc_trk_g2_4 (15 11) routing tnl_op_4 lc_trk_g2_4 -(15 11) routing tnr_op_4 lc_trk_g2_4 (15 12) routing rgt_op_1 lc_trk_g3_1 (15 12) routing sp12_v_b_1 lc_trk_g3_1 (15 12) routing sp4_h_l_28 lc_trk_g3_1 @@ -544,11 +401,8 @@ (15 12) routing sp4_h_r_33 lc_trk_g3_1 (15 12) routing sp4_v_b_41 lc_trk_g3_1 (15 12) routing tnl_op_1 lc_trk_g3_1 -(15 12) routing tnr_op_1 lc_trk_g3_1 (15 13) routing rgt_op_0 lc_trk_g3_0 (15 13) routing sp12_v_b_0 lc_trk_g3_0 -(15 13) routing sp4_h_r_24 lc_trk_g3_0 -(15 13) routing sp4_h_r_32 lc_trk_g3_0 (15 13) routing sp4_h_r_40 lc_trk_g3_0 (15 13) routing sp4_v_b_40 lc_trk_g3_0 (15 13) routing tnl_op_0 lc_trk_g3_0 @@ -563,7 +417,6 @@ (15 14) routing tnr_op_5 lc_trk_g3_5 (15 15) routing rgt_op_4 lc_trk_g3_4 (15 15) routing sp12_v_b_4 lc_trk_g3_4 -(15 15) routing sp4_h_r_28 lc_trk_g3_4 (15 15) routing sp4_h_r_36 lc_trk_g3_4 (15 15) routing sp4_h_r_44 lc_trk_g3_4 (15 15) routing sp4_v_b_44 lc_trk_g3_4 @@ -573,9 +426,7 @@ (15 2) routing sp12_h_l_2 lc_trk_g0_5 (15 2) routing sp4_h_r_13 lc_trk_g0_5 (15 2) routing sp4_h_r_21 lc_trk_g0_5 -(15 2) routing sp4_h_r_5 lc_trk_g0_5 (15 2) routing sp4_v_t_8 lc_trk_g0_5 -(15 3) routing bot_op_4 lc_trk_g0_4 (15 3) routing lft_op_4 lc_trk_g0_4 (15 3) routing sp12_h_l_3 lc_trk_g0_4 (15 3) routing sp4_h_l_1 lc_trk_g0_4 @@ -588,7 +439,6 @@ (15 4) routing sp4_h_r_17 lc_trk_g1_1 (15 4) routing sp4_h_r_9 lc_trk_g1_1 (15 4) routing sp4_v_t_4 lc_trk_g1_1 -(15 5) routing bot_op_0 lc_trk_g1_0 (15 5) routing lft_op_0 lc_trk_g1_0 (15 5) routing sp12_h_r_0 lc_trk_g1_0 (15 5) routing sp4_h_r_0 lc_trk_g1_0 @@ -601,21 +451,17 @@ (15 6) routing sp4_h_r_21 lc_trk_g1_5 (15 6) routing sp4_h_r_5 lc_trk_g1_5 (15 6) routing sp4_v_t_8 lc_trk_g1_5 -(15 7) routing bot_op_4 lc_trk_g1_4 (15 7) routing lft_op_4 lc_trk_g1_4 (15 7) routing sp12_h_l_3 lc_trk_g1_4 (15 7) routing sp4_h_l_1 lc_trk_g1_4 (15 7) routing sp4_h_l_9 lc_trk_g1_4 -(15 7) routing sp4_h_r_4 lc_trk_g1_4 (15 7) routing sp4_v_b_20 lc_trk_g1_4 (15 8) routing rgt_op_1 lc_trk_g2_1 -(15 8) routing sp12_v_b_1 lc_trk_g2_1 (15 8) routing sp4_h_l_28 lc_trk_g2_1 (15 8) routing sp4_h_r_25 lc_trk_g2_1 (15 8) routing sp4_h_r_33 lc_trk_g2_1 (15 8) routing sp4_v_b_41 lc_trk_g2_1 (15 8) routing tnl_op_1 lc_trk_g2_1 -(15 8) routing tnr_op_1 lc_trk_g2_1 (15 9) routing rgt_op_0 lc_trk_g2_0 (15 9) routing sp12_v_b_0 lc_trk_g2_0 (15 9) routing sp4_h_r_24 lc_trk_g2_0 @@ -623,15 +469,10 @@ (15 9) routing sp4_h_r_40 lc_trk_g2_0 (15 9) routing sp4_v_b_40 lc_trk_g2_0 (15 9) routing tnl_op_0 lc_trk_g2_0 -(15 9) routing tnr_op_0 lc_trk_g2_0 -(16 0) routing sp12_h_l_14 lc_trk_g0_1 -(16 0) routing sp12_h_r_9 lc_trk_g0_1 (16 0) routing sp4_h_r_1 lc_trk_g0_1 (16 0) routing sp4_h_r_17 lc_trk_g0_1 -(16 0) routing sp4_h_r_9 lc_trk_g0_1 (16 0) routing sp4_v_b_1 lc_trk_g0_1 (16 0) routing sp4_v_b_9 lc_trk_g0_1 -(16 0) routing sp4_v_t_4 lc_trk_g0_1 (16 1) routing sp12_h_l_15 lc_trk_g0_0 (16 1) routing sp12_h_r_8 lc_trk_g0_0 (16 1) routing sp4_h_r_0 lc_trk_g0_0 @@ -640,9 +481,7 @@ (16 1) routing sp4_v_b_0 lc_trk_g0_0 (16 1) routing sp4_v_b_16 lc_trk_g0_0 (16 1) routing sp4_v_b_8 lc_trk_g0_0 -(16 10) routing sp12_v_b_13 lc_trk_g2_5 (16 10) routing sp12_v_t_18 lc_trk_g2_5 -(16 10) routing sp4_h_r_29 lc_trk_g2_5 (16 10) routing sp4_h_r_37 lc_trk_g2_5 (16 10) routing sp4_h_r_45 lc_trk_g2_5 (16 10) routing sp4_v_b_29 lc_trk_g2_5 @@ -666,8 +505,6 @@ (16 12) routing sp4_v_t_20 lc_trk_g3_1 (16 13) routing sp12_v_b_16 lc_trk_g3_0 (16 13) routing sp12_v_t_7 lc_trk_g3_0 -(16 13) routing sp4_h_r_24 lc_trk_g3_0 -(16 13) routing sp4_h_r_32 lc_trk_g3_0 (16 13) routing sp4_h_r_40 lc_trk_g3_0 (16 13) routing sp4_v_b_32 lc_trk_g3_0 (16 13) routing sp4_v_b_40 lc_trk_g3_0 @@ -682,17 +519,14 @@ (16 14) routing sp4_v_t_24 lc_trk_g3_5 (16 15) routing sp12_v_b_20 lc_trk_g3_4 (16 15) routing sp12_v_t_11 lc_trk_g3_4 -(16 15) routing sp4_h_r_28 lc_trk_g3_4 (16 15) routing sp4_h_r_36 lc_trk_g3_4 (16 15) routing sp4_h_r_44 lc_trk_g3_4 (16 15) routing sp4_v_b_28 lc_trk_g3_4 (16 15) routing sp4_v_b_44 lc_trk_g3_4 (16 15) routing sp4_v_t_25 lc_trk_g3_4 (16 2) routing sp12_h_l_10 lc_trk_g0_5 -(16 2) routing sp12_h_r_21 lc_trk_g0_5 (16 2) routing sp4_h_r_13 lc_trk_g0_5 (16 2) routing sp4_h_r_21 lc_trk_g0_5 -(16 2) routing sp4_h_r_5 lc_trk_g0_5 (16 2) routing sp4_v_b_13 lc_trk_g0_5 (16 2) routing sp4_v_b_5 lc_trk_g0_5 (16 2) routing sp4_v_t_8 lc_trk_g0_5 @@ -713,15 +547,12 @@ (16 4) routing sp4_v_b_9 lc_trk_g1_1 (16 4) routing sp4_v_t_4 lc_trk_g1_1 (16 5) routing sp12_h_l_15 lc_trk_g1_0 -(16 5) routing sp12_h_r_8 lc_trk_g1_0 (16 5) routing sp4_h_r_0 lc_trk_g1_0 (16 5) routing sp4_h_r_16 lc_trk_g1_0 (16 5) routing sp4_h_r_8 lc_trk_g1_0 -(16 5) routing sp4_v_b_0 lc_trk_g1_0 (16 5) routing sp4_v_b_16 lc_trk_g1_0 (16 5) routing sp4_v_b_8 lc_trk_g1_0 (16 6) routing sp12_h_l_10 lc_trk_g1_5 -(16 6) routing sp12_h_r_21 lc_trk_g1_5 (16 6) routing sp4_h_r_13 lc_trk_g1_5 (16 6) routing sp4_h_r_21 lc_trk_g1_5 (16 6) routing sp4_h_r_5 lc_trk_g1_5 @@ -732,7 +563,6 @@ (16 7) routing sp12_h_r_20 lc_trk_g1_4 (16 7) routing sp4_h_l_1 lc_trk_g1_4 (16 7) routing sp4_h_l_9 lc_trk_g1_4 -(16 7) routing sp4_h_r_4 lc_trk_g1_4 (16 7) routing sp4_v_b_12 lc_trk_g1_4 (16 7) routing sp4_v_b_20 lc_trk_g1_4 (16 7) routing sp4_v_b_4 lc_trk_g1_4 @@ -754,19 +584,13 @@ (16 9) routing sp4_v_t_13 lc_trk_g2_0 (17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_l_14 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_9 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_34 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_t_4 lc_trk_g0_1 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => bot_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_l_15 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 @@ -781,10 +605,8 @@ (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_8 lc_trk_g0_0 (17 10) Enable bit of Mux _local_links/g2_mux_5 => bnl_op_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => rgt_op_5 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_13 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_18 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_29 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_37 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_45 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5 @@ -808,7 +630,6 @@ (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_44 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_25 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => tnl_op_4 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnr_op_4 lc_trk_g2_4 (17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => rgt_op_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1 @@ -823,14 +644,11 @@ (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_41 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_20 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => tnl_op_1 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnr_op_1 lc_trk_g3_1 (17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_16 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_t_7 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_24 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_32 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_40 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0 @@ -859,7 +677,6 @@ (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_20 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_4 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_11 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_28 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_36 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_44 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4 @@ -870,20 +687,16 @@ (17 15) Enable bit of Mux _local_links/g3_mux_4 => tnl_op_4 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => tnr_op_4 lc_trk_g3_4 (17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_10 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_2 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_21 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_13 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_21 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_r_v_b_29 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_13 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_8 lc_trk_g0_5 (17 3) Enable bit of Mux _local_links/g0_mux_4 => bnr_op_4 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => bot_op_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_3 lc_trk_g0_4 @@ -910,24 +723,20 @@ (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_9 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_t_4 lc_trk_g1_1 (17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => bot_op_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_l_15 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_8 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_16 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_8 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_24 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_16 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0 (17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_10 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_2 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_21 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_13 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_21 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5 @@ -937,14 +746,12 @@ (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_8 lc_trk_g1_5 (17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => bot_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_3 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_12 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_20 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_1 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_9 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_28 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_12 lc_trk_g1_4 @@ -952,7 +759,6 @@ (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4 (17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_t_14 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_28 lc_trk_g2_1 @@ -964,7 +770,6 @@ (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_41 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_20 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1 (17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0 @@ -979,16 +784,13 @@ (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_40 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_13 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0 (18 0) routing bnr_op_1 lc_trk_g0_1 (18 0) routing lft_op_1 lc_trk_g0_1 (18 0) routing sp12_h_r_1 lc_trk_g0_1 (18 0) routing sp4_h_r_17 lc_trk_g0_1 -(18 0) routing sp4_h_r_9 lc_trk_g0_1 (18 0) routing sp4_v_b_1 lc_trk_g0_1 (18 0) routing sp4_v_b_9 lc_trk_g0_1 (18 1) routing bnr_op_1 lc_trk_g0_1 -(18 1) routing sp12_h_l_14 lc_trk_g0_1 (18 1) routing sp12_h_r_1 lc_trk_g0_1 (18 1) routing sp4_h_r_1 lc_trk_g0_1 (18 1) routing sp4_h_r_17 lc_trk_g0_1 @@ -1004,7 +806,6 @@ (18 11) routing bnl_op_5 lc_trk_g2_5 (18 11) routing sp12_v_b_5 lc_trk_g2_5 (18 11) routing sp12_v_t_18 lc_trk_g2_5 -(18 11) routing sp4_h_r_29 lc_trk_g2_5 (18 11) routing sp4_h_r_45 lc_trk_g2_5 (18 11) routing sp4_r_v_b_37 lc_trk_g2_5 (18 11) routing sp4_v_t_24 lc_trk_g2_5 @@ -1048,9 +849,7 @@ (18 2) routing sp4_v_b_5 lc_trk_g0_5 (18 3) routing bnr_op_5 lc_trk_g0_5 (18 3) routing sp12_h_l_2 lc_trk_g0_5 -(18 3) routing sp12_h_r_21 lc_trk_g0_5 (18 3) routing sp4_h_r_21 lc_trk_g0_5 -(18 3) routing sp4_h_r_5 lc_trk_g0_5 (18 3) routing sp4_r_v_b_29 lc_trk_g0_5 (18 3) routing sp4_v_b_13 lc_trk_g0_5 (18 4) routing bnr_op_1 lc_trk_g1_1 @@ -1076,20 +875,17 @@ (18 6) routing sp4_v_b_5 lc_trk_g1_5 (18 7) routing bnr_op_5 lc_trk_g1_5 (18 7) routing sp12_h_l_2 lc_trk_g1_5 -(18 7) routing sp12_h_r_21 lc_trk_g1_5 (18 7) routing sp4_h_r_21 lc_trk_g1_5 (18 7) routing sp4_h_r_5 lc_trk_g1_5 (18 7) routing sp4_r_v_b_29 lc_trk_g1_5 (18 7) routing sp4_v_b_13 lc_trk_g1_5 (18 8) routing bnl_op_1 lc_trk_g2_1 (18 8) routing rgt_op_1 lc_trk_g2_1 -(18 8) routing sp12_v_b_1 lc_trk_g2_1 (18 8) routing sp4_h_l_28 lc_trk_g2_1 (18 8) routing sp4_h_r_33 lc_trk_g2_1 (18 8) routing sp4_v_b_25 lc_trk_g2_1 (18 8) routing sp4_v_t_20 lc_trk_g2_1 (18 9) routing bnl_op_1 lc_trk_g2_1 -(18 9) routing sp12_v_b_1 lc_trk_g2_1 (18 9) routing sp12_v_t_14 lc_trk_g2_1 (18 9) routing sp4_h_l_28 lc_trk_g2_1 (18 9) routing sp4_h_r_25 lc_trk_g2_1 @@ -1113,13 +909,9 @@ (19 8) Enable bit of Mux _span_links/cross_mux_vert_9 => sp12_v_b_19 sp4_v_t_8 (19 9) Enable bit of Mux _span_links/cross_mux_vert_8 => sp12_v_t_14 sp4_v_b_20 (2 0) Enable bit of Mux _span_links/cross_mux_horz_4 => sp12_h_r_8 sp4_h_r_16 -(2 10) Enable bit of Mux _span_links/cross_mux_horz_9 => sp12_h_l_17 sp4_h_r_21 (2 12) Enable bit of Mux _span_links/cross_mux_horz_10 => sp12_h_r_20 sp4_h_l_11 -(2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_r_22 sp4_h_r_23 (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_0 wire_bram/ram/RCLK -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_2 wire_bram/ram/RCLK -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_3 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_5 wire_bram/ram/RCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_6 wire_bram/ram/RCLK @@ -1159,7 +951,6 @@ (21 11) routing bnl_op_7 lc_trk_g2_7 (21 11) routing sp12_v_t_20 lc_trk_g2_7 (21 11) routing sp12_v_t_4 lc_trk_g2_7 -(21 11) routing sp4_h_r_31 lc_trk_g2_7 (21 11) routing sp4_h_r_47 lc_trk_g2_7 (21 11) routing sp4_r_v_b_39 lc_trk_g2_7 (21 11) routing sp4_v_t_26 lc_trk_g2_7 @@ -1187,7 +978,6 @@ (21 14) routing sp4_v_b_31 lc_trk_g3_7 (21 14) routing sp4_v_t_26 lc_trk_g3_7 (21 15) routing bnl_op_7 lc_trk_g3_7 -(21 15) routing sp12_v_t_20 lc_trk_g3_7 (21 15) routing sp12_v_t_4 lc_trk_g3_7 (21 15) routing sp4_h_r_31 lc_trk_g3_7 (21 15) routing sp4_h_r_47 lc_trk_g3_7 @@ -1196,14 +986,12 @@ (21 15) routing tnl_op_7 lc_trk_g3_7 (21 2) routing bnr_op_7 lc_trk_g0_7 (21 2) routing lft_op_7 lc_trk_g0_7 -(21 2) routing sp12_h_r_7 lc_trk_g0_7 (21 2) routing sp4_h_r_15 lc_trk_g0_7 (21 2) routing sp4_h_r_23 lc_trk_g0_7 (21 2) routing sp4_v_b_7 lc_trk_g0_7 (21 2) routing sp4_v_t_2 lc_trk_g0_7 (21 3) routing bnr_op_7 lc_trk_g0_7 (21 3) routing sp12_h_l_20 lc_trk_g0_7 -(21 3) routing sp12_h_r_7 lc_trk_g0_7 (21 3) routing sp4_h_r_23 lc_trk_g0_7 (21 3) routing sp4_h_r_7 lc_trk_g0_7 (21 3) routing sp4_r_v_b_31 lc_trk_g0_7 @@ -1222,19 +1010,16 @@ (21 5) routing sp4_h_r_3 lc_trk_g1_3 (21 5) routing sp4_r_v_b_27 lc_trk_g1_3 (21 5) routing sp4_v_b_11 lc_trk_g1_3 -(21 6) routing bnr_op_7 lc_trk_g1_7 (21 6) routing lft_op_7 lc_trk_g1_7 (21 6) routing sp12_h_r_7 lc_trk_g1_7 (21 6) routing sp4_h_r_15 lc_trk_g1_7 (21 6) routing sp4_h_r_23 lc_trk_g1_7 (21 6) routing sp4_v_b_7 lc_trk_g1_7 (21 6) routing sp4_v_t_2 lc_trk_g1_7 -(21 7) routing bnr_op_7 lc_trk_g1_7 (21 7) routing sp12_h_l_20 lc_trk_g1_7 (21 7) routing sp12_h_r_7 lc_trk_g1_7 (21 7) routing sp4_h_r_23 lc_trk_g1_7 (21 7) routing sp4_h_r_7 lc_trk_g1_7 -(21 7) routing sp4_r_v_b_31 lc_trk_g1_7 (21 7) routing sp4_v_t_2 lc_trk_g1_7 (21 8) routing bnl_op_3 lc_trk_g2_3 (21 8) routing rgt_op_3 lc_trk_g2_3 @@ -1283,22 +1068,17 @@ (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_20 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_4 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_26 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_31 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_47 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_39 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_31 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_26 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_34 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7 (22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_14 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_22 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_5 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_19 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_27 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_46 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_14 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_38 lc_trk_g2_6 @@ -1306,7 +1086,6 @@ (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_t_19 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_t_27 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => tnl_op_6 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnr_op_6 lc_trk_g2_6 (22 12) Enable bit of Mux _local_links/g3_mux_3 => bnl_op_3 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => rgt_op_3 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_19 lc_trk_g3_3 @@ -1336,11 +1115,9 @@ (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_15 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_31 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => tnl_op_2 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnr_op_2 lc_trk_g3_2 (22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => rgt_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_20 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_4 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_26 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_31 lc_trk_g3_7 @@ -1351,7 +1128,6 @@ (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_26 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_34 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7 (22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_14 lc_trk_g3_6 @@ -1363,34 +1139,26 @@ (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_46 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_19 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_27 lc_trk_g3_6 (22 15) Enable bit of Mux _local_links/g3_mux_6 => tnl_op_6 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnr_op_6 lc_trk_g3_6 (22 2) Enable bit of Mux _local_links/g0_mux_7 => bnr_op_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_12 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_20 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_15 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_23 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_r_v_b_31 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_23 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_2 lc_trk_g0_7 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_14 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_22 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_11 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_r_v_b_30 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_14 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_t_11 lc_trk_g0_6 (22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3 @@ -1416,18 +1184,14 @@ (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_t_7 lc_trk_g1_2 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_12 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_20 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_15 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_23 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_31 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_23 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_7 lc_trk_g1_7 @@ -1494,15 +1258,11 @@ (23 10) routing sp12_v_t_12 lc_trk_g2_7 (23 10) routing sp12_v_t_20 lc_trk_g2_7 (23 10) routing sp4_h_l_26 lc_trk_g2_7 -(23 10) routing sp4_h_r_31 lc_trk_g2_7 (23 10) routing sp4_h_r_47 lc_trk_g2_7 (23 10) routing sp4_v_b_31 lc_trk_g2_7 (23 10) routing sp4_v_t_26 lc_trk_g2_7 -(23 10) routing sp4_v_t_34 lc_trk_g2_7 (23 11) routing sp12_v_b_14 lc_trk_g2_6 (23 11) routing sp12_v_b_22 lc_trk_g2_6 -(23 11) routing sp4_h_l_19 lc_trk_g2_6 -(23 11) routing sp4_h_l_27 lc_trk_g2_6 (23 11) routing sp4_h_r_46 lc_trk_g2_6 (23 11) routing sp4_v_b_46 lc_trk_g2_6 (23 11) routing sp4_v_t_19 lc_trk_g2_6 @@ -1524,7 +1284,6 @@ (23 13) routing sp4_v_t_15 lc_trk_g3_2 (23 13) routing sp4_v_t_31 lc_trk_g3_2 (23 14) routing sp12_v_t_12 lc_trk_g3_7 -(23 14) routing sp12_v_t_20 lc_trk_g3_7 (23 14) routing sp4_h_l_26 lc_trk_g3_7 (23 14) routing sp4_h_r_31 lc_trk_g3_7 (23 14) routing sp4_h_r_47 lc_trk_g3_7 @@ -1537,22 +1296,17 @@ (23 15) routing sp4_h_l_27 lc_trk_g3_6 (23 15) routing sp4_h_r_46 lc_trk_g3_6 (23 15) routing sp4_v_b_46 lc_trk_g3_6 -(23 15) routing sp4_v_t_19 lc_trk_g3_6 (23 15) routing sp4_v_t_27 lc_trk_g3_6 (23 2) routing sp12_h_l_12 lc_trk_g0_7 (23 2) routing sp12_h_l_20 lc_trk_g0_7 (23 2) routing sp4_h_r_15 lc_trk_g0_7 (23 2) routing sp4_h_r_23 lc_trk_g0_7 (23 2) routing sp4_h_r_7 lc_trk_g0_7 -(23 2) routing sp4_v_b_23 lc_trk_g0_7 (23 2) routing sp4_v_b_7 lc_trk_g0_7 (23 2) routing sp4_v_t_2 lc_trk_g0_7 (23 3) routing sp12_h_r_14 lc_trk_g0_6 (23 3) routing sp12_h_r_22 lc_trk_g0_6 (23 3) routing sp4_h_l_11 lc_trk_g0_6 -(23 3) routing sp4_h_l_3 lc_trk_g0_6 -(23 3) routing sp4_h_r_6 lc_trk_g0_6 -(23 3) routing sp4_v_b_14 lc_trk_g0_6 (23 3) routing sp4_v_b_6 lc_trk_g0_6 (23 3) routing sp4_v_t_11 lc_trk_g0_6 (23 4) routing sp12_h_l_16 lc_trk_g1_3 @@ -1568,10 +1322,8 @@ (23 5) routing sp4_h_r_10 lc_trk_g1_2 (23 5) routing sp4_h_r_18 lc_trk_g1_2 (23 5) routing sp4_h_r_2 lc_trk_g1_2 -(23 5) routing sp4_v_b_10 lc_trk_g1_2 (23 5) routing sp4_v_b_2 lc_trk_g1_2 (23 5) routing sp4_v_t_7 lc_trk_g1_2 -(23 6) routing sp12_h_l_12 lc_trk_g1_7 (23 6) routing sp12_h_l_20 lc_trk_g1_7 (23 6) routing sp4_h_r_15 lc_trk_g1_7 (23 6) routing sp4_h_r_23 lc_trk_g1_7 @@ -1618,19 +1370,13 @@ (24 10) routing rgt_op_7 lc_trk_g2_7 (24 10) routing sp12_v_t_4 lc_trk_g2_7 (24 10) routing sp4_h_l_26 lc_trk_g2_7 -(24 10) routing sp4_h_r_31 lc_trk_g2_7 (24 10) routing sp4_h_r_47 lc_trk_g2_7 -(24 10) routing sp4_v_t_34 lc_trk_g2_7 (24 10) routing tnl_op_7 lc_trk_g2_7 -(24 10) routing tnr_op_7 lc_trk_g2_7 (24 11) routing rgt_op_6 lc_trk_g2_6 (24 11) routing sp12_v_t_5 lc_trk_g2_6 -(24 11) routing sp4_h_l_19 lc_trk_g2_6 -(24 11) routing sp4_h_l_27 lc_trk_g2_6 (24 11) routing sp4_h_r_46 lc_trk_g2_6 (24 11) routing sp4_v_b_46 lc_trk_g2_6 (24 11) routing tnl_op_6 lc_trk_g2_6 -(24 11) routing tnr_op_6 lc_trk_g2_6 (24 12) routing rgt_op_3 lc_trk_g3_3 (24 12) routing sp12_v_b_3 lc_trk_g3_3 (24 12) routing sp4_h_l_14 lc_trk_g3_3 @@ -1646,7 +1392,6 @@ (24 13) routing sp4_h_r_42 lc_trk_g3_2 (24 13) routing sp4_v_t_31 lc_trk_g3_2 (24 13) routing tnl_op_2 lc_trk_g3_2 -(24 13) routing tnr_op_2 lc_trk_g3_2 (24 14) routing rgt_op_7 lc_trk_g3_7 (24 14) routing sp12_v_t_4 lc_trk_g3_7 (24 14) routing sp4_h_l_26 lc_trk_g3_7 @@ -1654,7 +1399,6 @@ (24 14) routing sp4_h_r_47 lc_trk_g3_7 (24 14) routing sp4_v_t_34 lc_trk_g3_7 (24 14) routing tnl_op_7 lc_trk_g3_7 -(24 14) routing tnr_op_7 lc_trk_g3_7 (24 15) routing rgt_op_6 lc_trk_g3_6 (24 15) routing sp12_v_t_5 lc_trk_g3_6 (24 15) routing sp4_h_l_19 lc_trk_g3_6 @@ -1662,18 +1406,13 @@ (24 15) routing sp4_h_r_46 lc_trk_g3_6 (24 15) routing sp4_v_b_46 lc_trk_g3_6 (24 15) routing tnl_op_6 lc_trk_g3_6 -(24 15) routing tnr_op_6 lc_trk_g3_6 (24 2) routing lft_op_7 lc_trk_g0_7 -(24 2) routing sp12_h_r_7 lc_trk_g0_7 (24 2) routing sp4_h_r_15 lc_trk_g0_7 (24 2) routing sp4_h_r_23 lc_trk_g0_7 (24 2) routing sp4_h_r_7 lc_trk_g0_7 -(24 2) routing sp4_v_b_23 lc_trk_g0_7 (24 3) routing lft_op_6 lc_trk_g0_6 (24 3) routing sp12_h_l_5 lc_trk_g0_6 (24 3) routing sp4_h_l_11 lc_trk_g0_6 -(24 3) routing sp4_h_l_3 lc_trk_g0_6 -(24 3) routing sp4_h_r_6 lc_trk_g0_6 (24 3) routing sp4_v_t_11 lc_trk_g0_6 (24 4) routing lft_op_3 lc_trk_g1_3 (24 4) routing sp12_h_r_3 lc_trk_g1_3 @@ -1732,14 +1471,12 @@ (25 10) routing bnl_op_6 lc_trk_g2_6 (25 10) routing rgt_op_6 lc_trk_g2_6 (25 10) routing sp12_v_t_5 lc_trk_g2_6 -(25 10) routing sp4_h_l_27 lc_trk_g2_6 (25 10) routing sp4_h_r_46 lc_trk_g2_6 (25 10) routing sp4_v_t_19 lc_trk_g2_6 (25 10) routing sp4_v_t_27 lc_trk_g2_6 (25 11) routing bnl_op_6 lc_trk_g2_6 (25 11) routing sp12_v_b_22 lc_trk_g2_6 (25 11) routing sp12_v_t_5 lc_trk_g2_6 -(25 11) routing sp4_h_l_19 lc_trk_g2_6 (25 11) routing sp4_h_r_46 lc_trk_g2_6 (25 11) routing sp4_r_v_b_38 lc_trk_g2_6 (25 11) routing sp4_v_t_27 lc_trk_g2_6 @@ -1764,7 +1501,6 @@ (25 14) routing sp12_v_t_5 lc_trk_g3_6 (25 14) routing sp4_h_l_27 lc_trk_g3_6 (25 14) routing sp4_h_r_46 lc_trk_g3_6 -(25 14) routing sp4_v_t_19 lc_trk_g3_6 (25 14) routing sp4_v_t_27 lc_trk_g3_6 (25 15) routing bnl_op_6 lc_trk_g3_6 (25 15) routing sp12_v_b_22 lc_trk_g3_6 @@ -1774,26 +1510,19 @@ (25 15) routing sp4_r_v_b_46 lc_trk_g3_6 (25 15) routing sp4_v_t_27 lc_trk_g3_6 (25 15) routing tnl_op_6 lc_trk_g3_6 -(25 2) routing bnr_op_6 lc_trk_g0_6 (25 2) routing lft_op_6 lc_trk_g0_6 (25 2) routing sp12_h_l_5 lc_trk_g0_6 (25 2) routing sp4_h_l_11 lc_trk_g0_6 -(25 2) routing sp4_h_l_3 lc_trk_g0_6 -(25 2) routing sp4_v_b_14 lc_trk_g0_6 (25 2) routing sp4_v_b_6 lc_trk_g0_6 -(25 3) routing bnr_op_6 lc_trk_g0_6 (25 3) routing sp12_h_l_5 lc_trk_g0_6 (25 3) routing sp12_h_r_22 lc_trk_g0_6 (25 3) routing sp4_h_l_11 lc_trk_g0_6 -(25 3) routing sp4_h_r_6 lc_trk_g0_6 (25 3) routing sp4_r_v_b_30 lc_trk_g0_6 -(25 3) routing sp4_v_b_14 lc_trk_g0_6 (25 4) routing bnr_op_2 lc_trk_g1_2 (25 4) routing lft_op_2 lc_trk_g1_2 (25 4) routing sp12_h_l_1 lc_trk_g1_2 (25 4) routing sp4_h_r_10 lc_trk_g1_2 (25 4) routing sp4_h_r_18 lc_trk_g1_2 -(25 4) routing sp4_v_b_10 lc_trk_g1_2 (25 4) routing sp4_v_b_2 lc_trk_g1_2 (25 5) routing bnr_op_2 lc_trk_g1_2 (25 5) routing sp12_h_l_1 lc_trk_g1_2 @@ -1801,7 +1530,6 @@ (25 5) routing sp4_h_r_18 lc_trk_g1_2 (25 5) routing sp4_h_r_2 lc_trk_g1_2 (25 5) routing sp4_r_v_b_26 lc_trk_g1_2 -(25 5) routing sp4_v_b_10 lc_trk_g1_2 (25 6) routing bnr_op_6 lc_trk_g1_6 (25 6) routing lft_op_6 lc_trk_g1_6 (25 6) routing sp12_h_l_5 lc_trk_g1_6 @@ -1879,7 +1607,6 @@ (26 13) routing lc_trk_g2_6 input0_6 (26 13) routing lc_trk_g3_3 input0_6 (26 13) routing lc_trk_g3_7 input0_6 -(26 14) routing lc_trk_g0_5 input0_7 (26 14) routing lc_trk_g0_7 input0_7 (26 14) routing lc_trk_g1_4 input0_7 (26 14) routing lc_trk_g1_6 input0_7 @@ -1960,12 +1687,9 @@ (26 9) routing lc_trk_g3_3 input0_4 (26 9) routing lc_trk_g3_7 input0_4 (27 0) routing lc_trk_g1_0 wire_bram/ram/WDATA_15 -(27 0) routing lc_trk_g1_2 wire_bram/ram/WDATA_15 (27 0) routing lc_trk_g1_4 wire_bram/ram/WDATA_15 -(27 0) routing lc_trk_g1_6 wire_bram/ram/WDATA_15 (27 0) routing lc_trk_g3_0 wire_bram/ram/WDATA_15 (27 0) routing lc_trk_g3_2 wire_bram/ram/WDATA_15 -(27 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_15 (27 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_15 (27 1) routing lc_trk_g1_1 input0_0 (27 1) routing lc_trk_g1_3 input0_0 @@ -1977,12 +1701,8 @@ (27 1) routing lc_trk_g3_7 input0_0 (27 10) routing lc_trk_g1_1 wire_bram/ram/WDATA_10 (27 10) routing lc_trk_g1_3 wire_bram/ram/WDATA_10 -(27 10) routing lc_trk_g1_5 wire_bram/ram/WDATA_10 (27 10) routing lc_trk_g1_7 wire_bram/ram/WDATA_10 -(27 10) routing lc_trk_g3_1 wire_bram/ram/WDATA_10 -(27 10) routing lc_trk_g3_3 wire_bram/ram/WDATA_10 (27 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_10 -(27 10) routing lc_trk_g3_7 wire_bram/ram/WDATA_10 (27 11) routing lc_trk_g1_0 input0_5 (27 11) routing lc_trk_g1_2 input0_5 (27 11) routing lc_trk_g1_4 input0_5 @@ -2010,11 +1730,6 @@ (27 14) routing lc_trk_g1_1 wire_bram/ram/WDATA_8 (27 14) routing lc_trk_g1_3 wire_bram/ram/WDATA_8 (27 14) routing lc_trk_g1_5 wire_bram/ram/WDATA_8 -(27 14) routing lc_trk_g1_7 wire_bram/ram/WDATA_8 -(27 14) routing lc_trk_g3_1 wire_bram/ram/WDATA_8 -(27 14) routing lc_trk_g3_3 wire_bram/ram/WDATA_8 -(27 14) routing lc_trk_g3_5 wire_bram/ram/WDATA_8 -(27 14) routing lc_trk_g3_7 wire_bram/ram/WDATA_8 (27 15) routing lc_trk_g1_0 input0_7 (27 15) routing lc_trk_g1_2 input0_7 (27 15) routing lc_trk_g1_4 input0_7 @@ -2025,12 +1740,6 @@ (27 15) routing lc_trk_g3_6 input0_7 (27 2) routing lc_trk_g1_1 wire_bram/ram/WDATA_14 (27 2) routing lc_trk_g1_3 wire_bram/ram/WDATA_14 -(27 2) routing lc_trk_g1_5 wire_bram/ram/WDATA_14 -(27 2) routing lc_trk_g1_7 wire_bram/ram/WDATA_14 -(27 2) routing lc_trk_g3_1 wire_bram/ram/WDATA_14 -(27 2) routing lc_trk_g3_3 wire_bram/ram/WDATA_14 -(27 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_14 -(27 2) routing lc_trk_g3_7 wire_bram/ram/WDATA_14 (27 3) routing lc_trk_g1_0 input0_1 (27 3) routing lc_trk_g1_2 input0_1 (27 3) routing lc_trk_g1_4 input0_1 @@ -2056,12 +1765,7 @@ (27 5) routing lc_trk_g3_5 input0_2 (27 5) routing lc_trk_g3_7 input0_2 (27 6) routing lc_trk_g1_1 wire_bram/ram/WDATA_12 -(27 6) routing lc_trk_g1_3 wire_bram/ram/WDATA_12 -(27 6) routing lc_trk_g1_5 wire_bram/ram/WDATA_12 (27 6) routing lc_trk_g1_7 wire_bram/ram/WDATA_12 -(27 6) routing lc_trk_g3_1 wire_bram/ram/WDATA_12 -(27 6) routing lc_trk_g3_3 wire_bram/ram/WDATA_12 -(27 6) routing lc_trk_g3_5 wire_bram/ram/WDATA_12 (27 6) routing lc_trk_g3_7 wire_bram/ram/WDATA_12 (27 7) routing lc_trk_g1_0 input0_3 (27 7) routing lc_trk_g1_2 input0_3 @@ -2071,11 +1775,7 @@ (27 7) routing lc_trk_g3_2 input0_3 (27 7) routing lc_trk_g3_4 input0_3 (27 7) routing lc_trk_g3_6 input0_3 -(27 8) routing lc_trk_g1_0 wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g1_2 wire_bram/ram/WDATA_11 -(27 8) routing lc_trk_g1_4 wire_bram/ram/WDATA_11 -(27 8) routing lc_trk_g1_6 wire_bram/ram/WDATA_11 -(27 8) routing lc_trk_g3_0 wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g3_2 wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g3_4 wire_bram/ram/WDATA_11 (27 8) routing lc_trk_g3_6 wire_bram/ram/WDATA_11 @@ -2087,13 +1787,10 @@ (27 9) routing lc_trk_g3_3 input0_4 (27 9) routing lc_trk_g3_5 input0_4 (27 9) routing lc_trk_g3_7 input0_4 -(28 0) routing lc_trk_g2_1 wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g2_3 wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g2_5 wire_bram/ram/WDATA_15 -(28 0) routing lc_trk_g2_7 wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g3_0 wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g3_2 wire_bram/ram/WDATA_15 -(28 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_15 (28 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_15 (28 1) routing lc_trk_g2_0 input0_0 (28 1) routing lc_trk_g2_2 input0_0 @@ -2103,14 +1800,10 @@ (28 1) routing lc_trk_g3_3 input0_0 (28 1) routing lc_trk_g3_5 input0_0 (28 1) routing lc_trk_g3_7 input0_0 -(28 10) routing lc_trk_g2_0 wire_bram/ram/WDATA_10 (28 10) routing lc_trk_g2_2 wire_bram/ram/WDATA_10 (28 10) routing lc_trk_g2_4 wire_bram/ram/WDATA_10 (28 10) routing lc_trk_g2_6 wire_bram/ram/WDATA_10 -(28 10) routing lc_trk_g3_1 wire_bram/ram/WDATA_10 -(28 10) routing lc_trk_g3_3 wire_bram/ram/WDATA_10 (28 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_10 -(28 10) routing lc_trk_g3_7 wire_bram/ram/WDATA_10 (28 11) routing lc_trk_g2_1 input0_5 (28 11) routing lc_trk_g2_3 input0_5 (28 11) routing lc_trk_g2_5 input0_5 @@ -2135,14 +1828,8 @@ (28 13) routing lc_trk_g3_3 input0_6 (28 13) routing lc_trk_g3_5 input0_6 (28 13) routing lc_trk_g3_7 input0_6 -(28 14) routing lc_trk_g2_0 wire_bram/ram/WDATA_8 (28 14) routing lc_trk_g2_2 wire_bram/ram/WDATA_8 (28 14) routing lc_trk_g2_4 wire_bram/ram/WDATA_8 -(28 14) routing lc_trk_g2_6 wire_bram/ram/WDATA_8 -(28 14) routing lc_trk_g3_1 wire_bram/ram/WDATA_8 -(28 14) routing lc_trk_g3_3 wire_bram/ram/WDATA_8 -(28 14) routing lc_trk_g3_5 wire_bram/ram/WDATA_8 -(28 14) routing lc_trk_g3_7 wire_bram/ram/WDATA_8 (28 15) routing lc_trk_g2_1 input0_7 (28 15) routing lc_trk_g2_3 input0_7 (28 15) routing lc_trk_g2_5 input0_7 @@ -2153,12 +1840,7 @@ (28 15) routing lc_trk_g3_6 input0_7 (28 2) routing lc_trk_g2_0 wire_bram/ram/WDATA_14 (28 2) routing lc_trk_g2_2 wire_bram/ram/WDATA_14 -(28 2) routing lc_trk_g2_4 wire_bram/ram/WDATA_14 (28 2) routing lc_trk_g2_6 wire_bram/ram/WDATA_14 -(28 2) routing lc_trk_g3_1 wire_bram/ram/WDATA_14 -(28 2) routing lc_trk_g3_3 wire_bram/ram/WDATA_14 -(28 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_14 -(28 2) routing lc_trk_g3_7 wire_bram/ram/WDATA_14 (28 3) routing lc_trk_g2_1 input0_1 (28 3) routing lc_trk_g2_3 input0_1 (28 3) routing lc_trk_g2_5 input0_1 @@ -2186,10 +1868,6 @@ (28 6) routing lc_trk_g2_0 wire_bram/ram/WDATA_12 (28 6) routing lc_trk_g2_2 wire_bram/ram/WDATA_12 (28 6) routing lc_trk_g2_4 wire_bram/ram/WDATA_12 -(28 6) routing lc_trk_g2_6 wire_bram/ram/WDATA_12 -(28 6) routing lc_trk_g3_1 wire_bram/ram/WDATA_12 -(28 6) routing lc_trk_g3_3 wire_bram/ram/WDATA_12 -(28 6) routing lc_trk_g3_5 wire_bram/ram/WDATA_12 (28 6) routing lc_trk_g3_7 wire_bram/ram/WDATA_12 (28 7) routing lc_trk_g2_1 input0_3 (28 7) routing lc_trk_g2_3 input0_3 @@ -2199,11 +1877,8 @@ (28 7) routing lc_trk_g3_2 input0_3 (28 7) routing lc_trk_g3_4 input0_3 (28 7) routing lc_trk_g3_6 input0_3 -(28 8) routing lc_trk_g2_1 wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g2_3 wire_bram/ram/WDATA_11 -(28 8) routing lc_trk_g2_5 wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g2_7 wire_bram/ram/WDATA_11 -(28 8) routing lc_trk_g3_0 wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g3_2 wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g3_4 wire_bram/ram/WDATA_11 (28 8) routing lc_trk_g3_6 wire_bram/ram/WDATA_11 @@ -2215,21 +1890,14 @@ (28 9) routing lc_trk_g3_3 input0_4 (28 9) routing lc_trk_g3_5 input0_4 (28 9) routing lc_trk_g3_7 input0_4 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_1 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_3 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_5 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_7 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_0 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_2 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_4 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_6 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_1 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_3 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_5 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_7 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_0 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_2 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_4 wire_bram/ram/WDATA_15 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_6 wire_bram/ram/WDATA_15 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_0 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_2 input0_0 @@ -2253,16 +1921,11 @@ (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_6 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_1 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_3 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_5 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_7 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_0 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_2 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_4 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_6 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_1 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_3 wire_bram/ram/WDATA_10 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_5 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_7 wire_bram/ram/WDATA_10 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_1 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_3 input0_5 (29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_5 input0_5 @@ -2282,7 +1945,6 @@ (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_1 wire_bram/ram/WDATA_9 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_3 wire_bram/ram/WDATA_9 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_5 wire_bram/ram/WDATA_9 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_7 wire_bram/ram/WDATA_9 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_0 wire_bram/ram/WDATA_9 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_2 wire_bram/ram/WDATA_9 (29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_4 wire_bram/ram/WDATA_9 @@ -2311,25 +1973,16 @@ (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_3 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_5 input0_6 (29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_7 input0_6 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_0 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_2 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_4 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_6 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_1 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_3 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_5 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_7 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_0 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_2 wire_bram/ram/WDATA_8 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_4 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_6 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_1 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_3 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_5 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_7 wire_bram/ram/WDATA_8 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_1 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_3 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_5 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_7 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_0 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_2 input0_7 @@ -2343,22 +1996,12 @@ (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_2 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_4 input0_7 (29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_6 input0_7 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_0 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_2 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_4 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_6 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_1 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_3 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_5 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_7 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_0 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_2 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_4 wire_bram/ram/WDATA_14 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_6 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_1 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_3 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_5 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_7 wire_bram/ram/WDATA_14 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_1 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_3 input0_1 (29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_5 input0_1 @@ -2412,16 +2055,10 @@ (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_4 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_6 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_1 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_3 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_5 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_7 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_0 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_2 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_4 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_6 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_1 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_3 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_5 wire_bram/ram/WDATA_12 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_7 wire_bram/ram/WDATA_12 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_1 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_3 input0_3 @@ -2441,17 +2078,10 @@ (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_6 input0_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_1 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_3 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_5 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_7 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_0 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_2 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_4 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_6 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_1 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_3 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_5 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_7 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_0 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_2 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_4 wire_bram/ram/WDATA_11 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_6 wire_bram/ram/WDATA_11 @@ -2475,13 +2105,10 @@ (3 0) routing sp12_v_t_23 sp12_v_b_0 (3 1) routing sp12_h_l_23 sp12_v_b_0 (3 1) routing sp12_h_r_0 sp12_v_b_0 -(3 10) routing sp12_h_r_1 sp12_h_l_22 (3 10) routing sp12_v_t_22 sp12_h_l_22 -(3 11) routing sp12_h_r_1 sp12_h_l_22 (3 11) routing sp12_v_b_1 sp12_h_l_22 (3 12) routing sp12_v_b_1 sp12_h_r_1 (3 12) routing sp12_v_t_22 sp12_h_r_1 -(3 13) routing sp12_h_l_22 sp12_h_r_1 (3 13) routing sp12_v_b_1 sp12_h_r_1 (3 14) routing sp12_h_r_1 sp12_v_t_22 (3 14) routing sp12_v_b_1 sp12_v_t_22 @@ -2493,7 +2120,6 @@ (3 3) routing sp12_v_b_0 sp12_h_l_23 (3 4) routing sp12_v_b_0 sp12_h_r_0 (3 4) routing sp12_v_t_23 sp12_h_r_0 -(3 5) routing sp12_h_l_23 sp12_h_r_0 (3 5) routing sp12_v_b_0 sp12_h_r_0 (3 6) routing sp12_h_r_0 sp12_v_t_23 (3 6) routing sp12_v_b_0 sp12_v_t_23 @@ -2504,39 +2130,26 @@ (3 9) routing sp12_h_l_22 sp12_v_b_1 (3 9) routing sp12_h_r_1 sp12_v_b_1 (30 0) routing lc_trk_g0_5 wire_bram/ram/WDATA_15 -(30 0) routing lc_trk_g0_7 wire_bram/ram/WDATA_15 (30 0) routing lc_trk_g1_4 wire_bram/ram/WDATA_15 -(30 0) routing lc_trk_g1_6 wire_bram/ram/WDATA_15 (30 0) routing lc_trk_g2_5 wire_bram/ram/WDATA_15 -(30 0) routing lc_trk_g2_7 wire_bram/ram/WDATA_15 -(30 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_15 (30 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_15 (30 1) routing lc_trk_g0_3 wire_bram/ram/WDATA_15 -(30 1) routing lc_trk_g0_7 wire_bram/ram/WDATA_15 -(30 1) routing lc_trk_g1_2 wire_bram/ram/WDATA_15 -(30 1) routing lc_trk_g1_6 wire_bram/ram/WDATA_15 (30 1) routing lc_trk_g2_3 wire_bram/ram/WDATA_15 -(30 1) routing lc_trk_g2_7 wire_bram/ram/WDATA_15 (30 1) routing lc_trk_g3_2 wire_bram/ram/WDATA_15 (30 1) routing lc_trk_g3_6 wire_bram/ram/WDATA_15 (30 10) routing lc_trk_g0_4 wire_bram/ram/WDATA_10 (30 10) routing lc_trk_g0_6 wire_bram/ram/WDATA_10 -(30 10) routing lc_trk_g1_5 wire_bram/ram/WDATA_10 (30 10) routing lc_trk_g1_7 wire_bram/ram/WDATA_10 (30 10) routing lc_trk_g2_4 wire_bram/ram/WDATA_10 (30 10) routing lc_trk_g2_6 wire_bram/ram/WDATA_10 (30 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_10 -(30 10) routing lc_trk_g3_7 wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g0_2 wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g0_6 wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g1_3 wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g1_7 wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g2_2 wire_bram/ram/WDATA_10 (30 11) routing lc_trk_g2_6 wire_bram/ram/WDATA_10 -(30 11) routing lc_trk_g3_3 wire_bram/ram/WDATA_10 -(30 11) routing lc_trk_g3_7 wire_bram/ram/WDATA_10 (30 12) routing lc_trk_g0_5 wire_bram/ram/WDATA_9 -(30 12) routing lc_trk_g0_7 wire_bram/ram/WDATA_9 (30 12) routing lc_trk_g1_4 wire_bram/ram/WDATA_9 (30 12) routing lc_trk_g1_6 wire_bram/ram/WDATA_9 (30 12) routing lc_trk_g2_5 wire_bram/ram/WDATA_9 @@ -2544,7 +2157,6 @@ (30 12) routing lc_trk_g3_4 wire_bram/ram/WDATA_9 (30 12) routing lc_trk_g3_6 wire_bram/ram/WDATA_9 (30 13) routing lc_trk_g0_3 wire_bram/ram/WDATA_9 -(30 13) routing lc_trk_g0_7 wire_bram/ram/WDATA_9 (30 13) routing lc_trk_g1_2 wire_bram/ram/WDATA_9 (30 13) routing lc_trk_g1_6 wire_bram/ram/WDATA_9 (30 13) routing lc_trk_g2_3 wire_bram/ram/WDATA_9 @@ -2554,35 +2166,16 @@ (30 14) routing lc_trk_g0_4 wire_bram/ram/WDATA_8 (30 14) routing lc_trk_g0_6 wire_bram/ram/WDATA_8 (30 14) routing lc_trk_g1_5 wire_bram/ram/WDATA_8 -(30 14) routing lc_trk_g1_7 wire_bram/ram/WDATA_8 (30 14) routing lc_trk_g2_4 wire_bram/ram/WDATA_8 -(30 14) routing lc_trk_g2_6 wire_bram/ram/WDATA_8 -(30 14) routing lc_trk_g3_5 wire_bram/ram/WDATA_8 -(30 14) routing lc_trk_g3_7 wire_bram/ram/WDATA_8 (30 15) routing lc_trk_g0_2 wire_bram/ram/WDATA_8 (30 15) routing lc_trk_g0_6 wire_bram/ram/WDATA_8 (30 15) routing lc_trk_g1_3 wire_bram/ram/WDATA_8 -(30 15) routing lc_trk_g1_7 wire_bram/ram/WDATA_8 (30 15) routing lc_trk_g2_2 wire_bram/ram/WDATA_8 -(30 15) routing lc_trk_g2_6 wire_bram/ram/WDATA_8 -(30 15) routing lc_trk_g3_3 wire_bram/ram/WDATA_8 -(30 15) routing lc_trk_g3_7 wire_bram/ram/WDATA_8 (30 2) routing lc_trk_g0_4 wire_bram/ram/WDATA_14 -(30 2) routing lc_trk_g0_6 wire_bram/ram/WDATA_14 -(30 2) routing lc_trk_g1_5 wire_bram/ram/WDATA_14 -(30 2) routing lc_trk_g1_7 wire_bram/ram/WDATA_14 -(30 2) routing lc_trk_g2_4 wire_bram/ram/WDATA_14 (30 2) routing lc_trk_g2_6 wire_bram/ram/WDATA_14 -(30 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_14 -(30 2) routing lc_trk_g3_7 wire_bram/ram/WDATA_14 -(30 3) routing lc_trk_g0_2 wire_bram/ram/WDATA_14 -(30 3) routing lc_trk_g0_6 wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g1_3 wire_bram/ram/WDATA_14 -(30 3) routing lc_trk_g1_7 wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g2_2 wire_bram/ram/WDATA_14 (30 3) routing lc_trk_g2_6 wire_bram/ram/WDATA_14 -(30 3) routing lc_trk_g3_3 wire_bram/ram/WDATA_14 -(30 3) routing lc_trk_g3_7 wire_bram/ram/WDATA_14 (30 4) routing lc_trk_g0_5 wire_bram/ram/WDATA_13 (30 4) routing lc_trk_g0_7 wire_bram/ram/WDATA_13 (30 4) routing lc_trk_g1_4 wire_bram/ram/WDATA_13 @@ -2601,108 +2194,70 @@ (30 5) routing lc_trk_g3_6 wire_bram/ram/WDATA_13 (30 6) routing lc_trk_g0_4 wire_bram/ram/WDATA_12 (30 6) routing lc_trk_g0_6 wire_bram/ram/WDATA_12 -(30 6) routing lc_trk_g1_5 wire_bram/ram/WDATA_12 (30 6) routing lc_trk_g1_7 wire_bram/ram/WDATA_12 (30 6) routing lc_trk_g2_4 wire_bram/ram/WDATA_12 -(30 6) routing lc_trk_g2_6 wire_bram/ram/WDATA_12 -(30 6) routing lc_trk_g3_5 wire_bram/ram/WDATA_12 (30 6) routing lc_trk_g3_7 wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g0_2 wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g0_6 wire_bram/ram/WDATA_12 -(30 7) routing lc_trk_g1_3 wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g1_7 wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g2_2 wire_bram/ram/WDATA_12 -(30 7) routing lc_trk_g2_6 wire_bram/ram/WDATA_12 -(30 7) routing lc_trk_g3_3 wire_bram/ram/WDATA_12 (30 7) routing lc_trk_g3_7 wire_bram/ram/WDATA_12 -(30 8) routing lc_trk_g0_5 wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g0_7 wire_bram/ram/WDATA_11 -(30 8) routing lc_trk_g1_4 wire_bram/ram/WDATA_11 -(30 8) routing lc_trk_g1_6 wire_bram/ram/WDATA_11 -(30 8) routing lc_trk_g2_5 wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g2_7 wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g3_4 wire_bram/ram/WDATA_11 (30 8) routing lc_trk_g3_6 wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g0_3 wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g0_7 wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g1_2 wire_bram/ram/WDATA_11 -(30 9) routing lc_trk_g1_6 wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g2_3 wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g2_7 wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g3_2 wire_bram/ram/WDATA_11 (30 9) routing lc_trk_g3_6 wire_bram/ram/WDATA_11 -(31 0) routing lc_trk_g0_5 wire_bram/ram/MASK_15 (31 0) routing lc_trk_g0_7 wire_bram/ram/MASK_15 (31 0) routing lc_trk_g1_4 wire_bram/ram/MASK_15 (31 0) routing lc_trk_g1_6 wire_bram/ram/MASK_15 -(31 0) routing lc_trk_g2_5 wire_bram/ram/MASK_15 -(31 0) routing lc_trk_g2_7 wire_bram/ram/MASK_15 -(31 0) routing lc_trk_g3_4 wire_bram/ram/MASK_15 (31 0) routing lc_trk_g3_6 wire_bram/ram/MASK_15 -(31 1) routing lc_trk_g0_3 wire_bram/ram/MASK_15 (31 1) routing lc_trk_g0_7 wire_bram/ram/MASK_15 (31 1) routing lc_trk_g1_2 wire_bram/ram/MASK_15 (31 1) routing lc_trk_g1_6 wire_bram/ram/MASK_15 (31 1) routing lc_trk_g2_3 wire_bram/ram/MASK_15 -(31 1) routing lc_trk_g2_7 wire_bram/ram/MASK_15 (31 1) routing lc_trk_g3_2 wire_bram/ram/MASK_15 (31 1) routing lc_trk_g3_6 wire_bram/ram/MASK_15 (31 10) routing lc_trk_g0_4 wire_bram/ram/MASK_10 -(31 10) routing lc_trk_g0_6 wire_bram/ram/MASK_10 (31 10) routing lc_trk_g1_5 wire_bram/ram/MASK_10 (31 10) routing lc_trk_g1_7 wire_bram/ram/MASK_10 (31 10) routing lc_trk_g2_4 wire_bram/ram/MASK_10 (31 10) routing lc_trk_g2_6 wire_bram/ram/MASK_10 (31 10) routing lc_trk_g3_5 wire_bram/ram/MASK_10 -(31 10) routing lc_trk_g3_7 wire_bram/ram/MASK_10 (31 11) routing lc_trk_g0_2 wire_bram/ram/MASK_10 -(31 11) routing lc_trk_g0_6 wire_bram/ram/MASK_10 (31 11) routing lc_trk_g1_3 wire_bram/ram/MASK_10 (31 11) routing lc_trk_g1_7 wire_bram/ram/MASK_10 (31 11) routing lc_trk_g2_2 wire_bram/ram/MASK_10 (31 11) routing lc_trk_g2_6 wire_bram/ram/MASK_10 -(31 11) routing lc_trk_g3_3 wire_bram/ram/MASK_10 -(31 11) routing lc_trk_g3_7 wire_bram/ram/MASK_10 (31 12) routing lc_trk_g0_5 wire_bram/ram/MASK_9 -(31 12) routing lc_trk_g0_7 wire_bram/ram/MASK_9 -(31 12) routing lc_trk_g1_4 wire_bram/ram/MASK_9 (31 12) routing lc_trk_g1_6 wire_bram/ram/MASK_9 (31 12) routing lc_trk_g2_5 wire_bram/ram/MASK_9 (31 12) routing lc_trk_g2_7 wire_bram/ram/MASK_9 (31 12) routing lc_trk_g3_4 wire_bram/ram/MASK_9 -(31 12) routing lc_trk_g3_6 wire_bram/ram/MASK_9 (31 13) routing lc_trk_g0_3 wire_bram/ram/MASK_9 -(31 13) routing lc_trk_g0_7 wire_bram/ram/MASK_9 (31 13) routing lc_trk_g1_2 wire_bram/ram/MASK_9 (31 13) routing lc_trk_g1_6 wire_bram/ram/MASK_9 (31 13) routing lc_trk_g2_3 wire_bram/ram/MASK_9 (31 13) routing lc_trk_g2_7 wire_bram/ram/MASK_9 (31 13) routing lc_trk_g3_2 wire_bram/ram/MASK_9 -(31 13) routing lc_trk_g3_6 wire_bram/ram/MASK_9 (31 14) routing lc_trk_g0_4 wire_bram/ram/MASK_8 -(31 14) routing lc_trk_g0_6 wire_bram/ram/MASK_8 -(31 14) routing lc_trk_g1_5 wire_bram/ram/MASK_8 -(31 14) routing lc_trk_g1_7 wire_bram/ram/MASK_8 (31 14) routing lc_trk_g2_4 wire_bram/ram/MASK_8 (31 14) routing lc_trk_g2_6 wire_bram/ram/MASK_8 (31 14) routing lc_trk_g3_5 wire_bram/ram/MASK_8 -(31 14) routing lc_trk_g3_7 wire_bram/ram/MASK_8 -(31 15) routing lc_trk_g0_2 wire_bram/ram/MASK_8 -(31 15) routing lc_trk_g0_6 wire_bram/ram/MASK_8 (31 15) routing lc_trk_g1_3 wire_bram/ram/MASK_8 -(31 15) routing lc_trk_g1_7 wire_bram/ram/MASK_8 (31 15) routing lc_trk_g2_2 wire_bram/ram/MASK_8 (31 15) routing lc_trk_g2_6 wire_bram/ram/MASK_8 (31 15) routing lc_trk_g3_3 wire_bram/ram/MASK_8 -(31 15) routing lc_trk_g3_7 wire_bram/ram/MASK_8 (31 2) routing lc_trk_g0_4 wire_bram/ram/MASK_14 (31 2) routing lc_trk_g0_6 wire_bram/ram/MASK_14 -(31 2) routing lc_trk_g1_5 wire_bram/ram/MASK_14 (31 2) routing lc_trk_g1_7 wire_bram/ram/MASK_14 -(31 2) routing lc_trk_g2_4 wire_bram/ram/MASK_14 (31 2) routing lc_trk_g2_6 wire_bram/ram/MASK_14 (31 2) routing lc_trk_g3_5 wire_bram/ram/MASK_14 -(31 2) routing lc_trk_g3_7 wire_bram/ram/MASK_14 (31 3) routing lc_trk_g0_2 wire_bram/ram/MASK_14 (31 3) routing lc_trk_g0_6 wire_bram/ram/MASK_14 (31 3) routing lc_trk_g1_3 wire_bram/ram/MASK_14 @@ -2710,107 +2265,64 @@ (31 3) routing lc_trk_g2_2 wire_bram/ram/MASK_14 (31 3) routing lc_trk_g2_6 wire_bram/ram/MASK_14 (31 3) routing lc_trk_g3_3 wire_bram/ram/MASK_14 -(31 3) routing lc_trk_g3_7 wire_bram/ram/MASK_14 -(31 4) routing lc_trk_g0_5 wire_bram/ram/MASK_13 (31 4) routing lc_trk_g0_7 wire_bram/ram/MASK_13 (31 4) routing lc_trk_g1_4 wire_bram/ram/MASK_13 (31 4) routing lc_trk_g1_6 wire_bram/ram/MASK_13 -(31 4) routing lc_trk_g2_5 wire_bram/ram/MASK_13 (31 4) routing lc_trk_g2_7 wire_bram/ram/MASK_13 (31 4) routing lc_trk_g3_4 wire_bram/ram/MASK_13 (31 4) routing lc_trk_g3_6 wire_bram/ram/MASK_13 (31 5) routing lc_trk_g0_3 wire_bram/ram/MASK_13 (31 5) routing lc_trk_g0_7 wire_bram/ram/MASK_13 -(31 5) routing lc_trk_g1_2 wire_bram/ram/MASK_13 (31 5) routing lc_trk_g1_6 wire_bram/ram/MASK_13 -(31 5) routing lc_trk_g2_3 wire_bram/ram/MASK_13 (31 5) routing lc_trk_g2_7 wire_bram/ram/MASK_13 -(31 5) routing lc_trk_g3_2 wire_bram/ram/MASK_13 (31 5) routing lc_trk_g3_6 wire_bram/ram/MASK_13 (31 6) routing lc_trk_g0_4 wire_bram/ram/MASK_12 (31 6) routing lc_trk_g0_6 wire_bram/ram/MASK_12 -(31 6) routing lc_trk_g1_5 wire_bram/ram/MASK_12 (31 6) routing lc_trk_g1_7 wire_bram/ram/MASK_12 (31 6) routing lc_trk_g2_4 wire_bram/ram/MASK_12 -(31 6) routing lc_trk_g2_6 wire_bram/ram/MASK_12 -(31 6) routing lc_trk_g3_5 wire_bram/ram/MASK_12 (31 6) routing lc_trk_g3_7 wire_bram/ram/MASK_12 -(31 7) routing lc_trk_g0_2 wire_bram/ram/MASK_12 (31 7) routing lc_trk_g0_6 wire_bram/ram/MASK_12 (31 7) routing lc_trk_g1_3 wire_bram/ram/MASK_12 (31 7) routing lc_trk_g1_7 wire_bram/ram/MASK_12 -(31 7) routing lc_trk_g2_2 wire_bram/ram/MASK_12 -(31 7) routing lc_trk_g2_6 wire_bram/ram/MASK_12 -(31 7) routing lc_trk_g3_3 wire_bram/ram/MASK_12 (31 7) routing lc_trk_g3_7 wire_bram/ram/MASK_12 (31 8) routing lc_trk_g0_5 wire_bram/ram/MASK_11 -(31 8) routing lc_trk_g0_7 wire_bram/ram/MASK_11 (31 8) routing lc_trk_g1_4 wire_bram/ram/MASK_11 (31 8) routing lc_trk_g1_6 wire_bram/ram/MASK_11 (31 8) routing lc_trk_g2_5 wire_bram/ram/MASK_11 -(31 8) routing lc_trk_g2_7 wire_bram/ram/MASK_11 (31 8) routing lc_trk_g3_4 wire_bram/ram/MASK_11 -(31 8) routing lc_trk_g3_6 wire_bram/ram/MASK_11 (31 9) routing lc_trk_g0_3 wire_bram/ram/MASK_11 -(31 9) routing lc_trk_g0_7 wire_bram/ram/MASK_11 -(31 9) routing lc_trk_g1_2 wire_bram/ram/MASK_11 (31 9) routing lc_trk_g1_6 wire_bram/ram/MASK_11 (31 9) routing lc_trk_g2_3 wire_bram/ram/MASK_11 -(31 9) routing lc_trk_g2_7 wire_bram/ram/MASK_11 (31 9) routing lc_trk_g3_2 wire_bram/ram/MASK_11 -(31 9) routing lc_trk_g3_6 wire_bram/ram/MASK_11 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_3 wire_bram/ram/MASK_15 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_5 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_7 wire_bram/ram/MASK_15 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_0 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_2 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_4 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_6 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_1 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_3 wire_bram/ram/MASK_15 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_5 wire_bram/ram/MASK_15 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_7 wire_bram/ram/MASK_15 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_0 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_2 wire_bram/ram/MASK_15 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_4 wire_bram/ram/MASK_15 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_6 wire_bram/ram/MASK_15 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_2 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_4 wire_bram/ram/MASK_10 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_6 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_1 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_3 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_5 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_7 wire_bram/ram/MASK_10 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_0 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_2 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_4 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_6 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_1 wire_bram/ram/MASK_10 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_3 wire_bram/ram/MASK_10 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_5 wire_bram/ram/MASK_10 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_7 wire_bram/ram/MASK_10 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_1 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_3 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_5 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_7 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_0 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_2 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_4 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_6 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_1 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_3 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_5 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_7 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_0 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_2 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_4 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_6 input2_5 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_3 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_5 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_7 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_0 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_2 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_4 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_6 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_1 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_3 wire_bram/ram/MASK_9 @@ -2819,7 +2331,6 @@ (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_0 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_2 wire_bram/ram/MASK_9 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_4 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_6 wire_bram/ram/MASK_9 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_0 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_2 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_4 input2_6 @@ -2836,13 +2347,8 @@ (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_3 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_5 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_7 input2_6 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_2 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_4 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_6 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_1 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_3 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_5 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_7 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_0 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_2 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_4 wire_bram/ram/MASK_8 @@ -2850,7 +2356,6 @@ (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_1 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_3 wire_bram/ram/MASK_8 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_5 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_7 wire_bram/ram/MASK_8 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_1 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_3 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_5 input2_7 @@ -2872,85 +2377,49 @@ (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_6 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_1 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_3 wire_bram/ram/MASK_14 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_5 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_7 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_0 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_2 wire_bram/ram/MASK_14 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_4 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_6 wire_bram/ram/MASK_14 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_1 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_3 wire_bram/ram/MASK_14 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_5 wire_bram/ram/MASK_14 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_7 wire_bram/ram/MASK_14 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_3 wire_bram/ram/MASK_13 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_5 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_7 wire_bram/ram/MASK_13 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_0 wire_bram/ram/MASK_13 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_2 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_4 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_6 wire_bram/ram/MASK_13 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_1 wire_bram/ram/MASK_13 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_3 wire_bram/ram/MASK_13 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_5 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_7 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_0 wire_bram/ram/MASK_13 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_2 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_4 wire_bram/ram/MASK_13 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_6 wire_bram/ram/MASK_13 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_2 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_4 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_6 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_1 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_3 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_5 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_7 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_0 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_2 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_4 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_6 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_1 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_3 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_5 wire_bram/ram/MASK_12 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_7 wire_bram/ram/MASK_12 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_3 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_5 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_7 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_0 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_2 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_4 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_6 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_1 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_3 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_5 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_7 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_0 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_2 wire_bram/ram/MASK_11 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_4 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_6 wire_bram/ram/MASK_11 (33 0) routing lc_trk_g2_1 wire_bram/ram/MASK_15 (33 0) routing lc_trk_g2_3 wire_bram/ram/MASK_15 -(33 0) routing lc_trk_g2_5 wire_bram/ram/MASK_15 -(33 0) routing lc_trk_g2_7 wire_bram/ram/MASK_15 -(33 0) routing lc_trk_g3_0 wire_bram/ram/MASK_15 (33 0) routing lc_trk_g3_2 wire_bram/ram/MASK_15 -(33 0) routing lc_trk_g3_4 wire_bram/ram/MASK_15 (33 0) routing lc_trk_g3_6 wire_bram/ram/MASK_15 -(33 10) routing lc_trk_g2_0 wire_bram/ram/MASK_10 (33 10) routing lc_trk_g2_2 wire_bram/ram/MASK_10 (33 10) routing lc_trk_g2_4 wire_bram/ram/MASK_10 (33 10) routing lc_trk_g2_6 wire_bram/ram/MASK_10 (33 10) routing lc_trk_g3_1 wire_bram/ram/MASK_10 -(33 10) routing lc_trk_g3_3 wire_bram/ram/MASK_10 (33 10) routing lc_trk_g3_5 wire_bram/ram/MASK_10 -(33 10) routing lc_trk_g3_7 wire_bram/ram/MASK_10 (33 11) routing lc_trk_g2_1 input2_5 -(33 11) routing lc_trk_g2_3 input2_5 (33 11) routing lc_trk_g2_5 input2_5 -(33 11) routing lc_trk_g2_7 input2_5 (33 11) routing lc_trk_g3_0 input2_5 -(33 11) routing lc_trk_g3_2 input2_5 (33 11) routing lc_trk_g3_4 input2_5 -(33 11) routing lc_trk_g3_6 input2_5 (33 12) routing lc_trk_g2_1 wire_bram/ram/MASK_9 (33 12) routing lc_trk_g2_3 wire_bram/ram/MASK_9 (33 12) routing lc_trk_g2_5 wire_bram/ram/MASK_9 @@ -2958,7 +2427,6 @@ (33 12) routing lc_trk_g3_0 wire_bram/ram/MASK_9 (33 12) routing lc_trk_g3_2 wire_bram/ram/MASK_9 (33 12) routing lc_trk_g3_4 wire_bram/ram/MASK_9 -(33 12) routing lc_trk_g3_6 wire_bram/ram/MASK_9 (33 13) routing lc_trk_g2_0 input2_6 (33 13) routing lc_trk_g2_2 input2_6 (33 13) routing lc_trk_g2_4 input2_6 @@ -2974,7 +2442,6 @@ (33 14) routing lc_trk_g3_1 wire_bram/ram/MASK_8 (33 14) routing lc_trk_g3_3 wire_bram/ram/MASK_8 (33 14) routing lc_trk_g3_5 wire_bram/ram/MASK_8 -(33 14) routing lc_trk_g3_7 wire_bram/ram/MASK_8 (33 15) routing lc_trk_g2_1 input2_7 (33 15) routing lc_trk_g2_3 input2_7 (33 15) routing lc_trk_g2_5 input2_7 @@ -2985,68 +2452,40 @@ (33 15) routing lc_trk_g3_6 input2_7 (33 2) routing lc_trk_g2_0 wire_bram/ram/MASK_14 (33 2) routing lc_trk_g2_2 wire_bram/ram/MASK_14 -(33 2) routing lc_trk_g2_4 wire_bram/ram/MASK_14 (33 2) routing lc_trk_g2_6 wire_bram/ram/MASK_14 -(33 2) routing lc_trk_g3_1 wire_bram/ram/MASK_14 (33 2) routing lc_trk_g3_3 wire_bram/ram/MASK_14 (33 2) routing lc_trk_g3_5 wire_bram/ram/MASK_14 -(33 2) routing lc_trk_g3_7 wire_bram/ram/MASK_14 -(33 4) routing lc_trk_g2_1 wire_bram/ram/MASK_13 -(33 4) routing lc_trk_g2_3 wire_bram/ram/MASK_13 -(33 4) routing lc_trk_g2_5 wire_bram/ram/MASK_13 (33 4) routing lc_trk_g2_7 wire_bram/ram/MASK_13 (33 4) routing lc_trk_g3_0 wire_bram/ram/MASK_13 -(33 4) routing lc_trk_g3_2 wire_bram/ram/MASK_13 (33 4) routing lc_trk_g3_4 wire_bram/ram/MASK_13 (33 4) routing lc_trk_g3_6 wire_bram/ram/MASK_13 -(33 6) routing lc_trk_g2_0 wire_bram/ram/MASK_12 -(33 6) routing lc_trk_g2_2 wire_bram/ram/MASK_12 (33 6) routing lc_trk_g2_4 wire_bram/ram/MASK_12 -(33 6) routing lc_trk_g2_6 wire_bram/ram/MASK_12 (33 6) routing lc_trk_g3_1 wire_bram/ram/MASK_12 -(33 6) routing lc_trk_g3_3 wire_bram/ram/MASK_12 -(33 6) routing lc_trk_g3_5 wire_bram/ram/MASK_12 (33 6) routing lc_trk_g3_7 wire_bram/ram/MASK_12 -(33 8) routing lc_trk_g2_1 wire_bram/ram/MASK_11 (33 8) routing lc_trk_g2_3 wire_bram/ram/MASK_11 (33 8) routing lc_trk_g2_5 wire_bram/ram/MASK_11 -(33 8) routing lc_trk_g2_7 wire_bram/ram/MASK_11 -(33 8) routing lc_trk_g3_0 wire_bram/ram/MASK_11 (33 8) routing lc_trk_g3_2 wire_bram/ram/MASK_11 (33 8) routing lc_trk_g3_4 wire_bram/ram/MASK_11 -(33 8) routing lc_trk_g3_6 wire_bram/ram/MASK_11 -(34 0) routing lc_trk_g1_0 wire_bram/ram/MASK_15 (34 0) routing lc_trk_g1_2 wire_bram/ram/MASK_15 (34 0) routing lc_trk_g1_4 wire_bram/ram/MASK_15 (34 0) routing lc_trk_g1_6 wire_bram/ram/MASK_15 -(34 0) routing lc_trk_g3_0 wire_bram/ram/MASK_15 (34 0) routing lc_trk_g3_2 wire_bram/ram/MASK_15 -(34 0) routing lc_trk_g3_4 wire_bram/ram/MASK_15 (34 0) routing lc_trk_g3_6 wire_bram/ram/MASK_15 (34 10) routing lc_trk_g1_1 wire_bram/ram/MASK_10 (34 10) routing lc_trk_g1_3 wire_bram/ram/MASK_10 (34 10) routing lc_trk_g1_5 wire_bram/ram/MASK_10 (34 10) routing lc_trk_g1_7 wire_bram/ram/MASK_10 (34 10) routing lc_trk_g3_1 wire_bram/ram/MASK_10 -(34 10) routing lc_trk_g3_3 wire_bram/ram/MASK_10 (34 10) routing lc_trk_g3_5 wire_bram/ram/MASK_10 -(34 10) routing lc_trk_g3_7 wire_bram/ram/MASK_10 (34 11) routing lc_trk_g1_0 input2_5 -(34 11) routing lc_trk_g1_2 input2_5 -(34 11) routing lc_trk_g1_4 input2_5 (34 11) routing lc_trk_g1_6 input2_5 (34 11) routing lc_trk_g3_0 input2_5 -(34 11) routing lc_trk_g3_2 input2_5 (34 11) routing lc_trk_g3_4 input2_5 -(34 11) routing lc_trk_g3_6 input2_5 -(34 12) routing lc_trk_g1_0 wire_bram/ram/MASK_9 (34 12) routing lc_trk_g1_2 wire_bram/ram/MASK_9 -(34 12) routing lc_trk_g1_4 wire_bram/ram/MASK_9 (34 12) routing lc_trk_g1_6 wire_bram/ram/MASK_9 (34 12) routing lc_trk_g3_0 wire_bram/ram/MASK_9 (34 12) routing lc_trk_g3_2 wire_bram/ram/MASK_9 (34 12) routing lc_trk_g3_4 wire_bram/ram/MASK_9 -(34 12) routing lc_trk_g3_6 wire_bram/ram/MASK_9 (34 13) routing lc_trk_g1_1 input2_6 (34 13) routing lc_trk_g1_3 input2_6 (34 13) routing lc_trk_g1_5 input2_6 @@ -3055,14 +2494,10 @@ (34 13) routing lc_trk_g3_3 input2_6 (34 13) routing lc_trk_g3_5 input2_6 (34 13) routing lc_trk_g3_7 input2_6 -(34 14) routing lc_trk_g1_1 wire_bram/ram/MASK_8 (34 14) routing lc_trk_g1_3 wire_bram/ram/MASK_8 -(34 14) routing lc_trk_g1_5 wire_bram/ram/MASK_8 -(34 14) routing lc_trk_g1_7 wire_bram/ram/MASK_8 (34 14) routing lc_trk_g3_1 wire_bram/ram/MASK_8 (34 14) routing lc_trk_g3_3 wire_bram/ram/MASK_8 (34 14) routing lc_trk_g3_5 wire_bram/ram/MASK_8 -(34 14) routing lc_trk_g3_7 wire_bram/ram/MASK_8 (34 15) routing lc_trk_g1_0 input2_7 (34 15) routing lc_trk_g1_2 input2_7 (34 15) routing lc_trk_g1_4 input2_7 @@ -3073,52 +2508,28 @@ (34 15) routing lc_trk_g3_6 input2_7 (34 2) routing lc_trk_g1_1 wire_bram/ram/MASK_14 (34 2) routing lc_trk_g1_3 wire_bram/ram/MASK_14 -(34 2) routing lc_trk_g1_5 wire_bram/ram/MASK_14 (34 2) routing lc_trk_g1_7 wire_bram/ram/MASK_14 -(34 2) routing lc_trk_g3_1 wire_bram/ram/MASK_14 (34 2) routing lc_trk_g3_3 wire_bram/ram/MASK_14 (34 2) routing lc_trk_g3_5 wire_bram/ram/MASK_14 -(34 2) routing lc_trk_g3_7 wire_bram/ram/MASK_14 -(34 4) routing lc_trk_g1_0 wire_bram/ram/MASK_13 -(34 4) routing lc_trk_g1_2 wire_bram/ram/MASK_13 (34 4) routing lc_trk_g1_4 wire_bram/ram/MASK_13 (34 4) routing lc_trk_g1_6 wire_bram/ram/MASK_13 (34 4) routing lc_trk_g3_0 wire_bram/ram/MASK_13 -(34 4) routing lc_trk_g3_2 wire_bram/ram/MASK_13 (34 4) routing lc_trk_g3_4 wire_bram/ram/MASK_13 (34 4) routing lc_trk_g3_6 wire_bram/ram/MASK_13 -(34 6) routing lc_trk_g1_1 wire_bram/ram/MASK_12 (34 6) routing lc_trk_g1_3 wire_bram/ram/MASK_12 -(34 6) routing lc_trk_g1_5 wire_bram/ram/MASK_12 (34 6) routing lc_trk_g1_7 wire_bram/ram/MASK_12 (34 6) routing lc_trk_g3_1 wire_bram/ram/MASK_12 -(34 6) routing lc_trk_g3_3 wire_bram/ram/MASK_12 -(34 6) routing lc_trk_g3_5 wire_bram/ram/MASK_12 (34 6) routing lc_trk_g3_7 wire_bram/ram/MASK_12 (34 8) routing lc_trk_g1_0 wire_bram/ram/MASK_11 -(34 8) routing lc_trk_g1_2 wire_bram/ram/MASK_11 (34 8) routing lc_trk_g1_4 wire_bram/ram/MASK_11 (34 8) routing lc_trk_g1_6 wire_bram/ram/MASK_11 -(34 8) routing lc_trk_g3_0 wire_bram/ram/MASK_11 (34 8) routing lc_trk_g3_2 wire_bram/ram/MASK_11 (34 8) routing lc_trk_g3_4 wire_bram/ram/MASK_11 -(34 8) routing lc_trk_g3_6 wire_bram/ram/MASK_11 -(35 10) routing lc_trk_g0_5 input2_5 -(35 10) routing lc_trk_g0_7 input2_5 -(35 10) routing lc_trk_g1_4 input2_5 (35 10) routing lc_trk_g1_6 input2_5 (35 10) routing lc_trk_g2_5 input2_5 -(35 10) routing lc_trk_g2_7 input2_5 (35 10) routing lc_trk_g3_4 input2_5 -(35 10) routing lc_trk_g3_6 input2_5 (35 11) routing lc_trk_g0_3 input2_5 -(35 11) routing lc_trk_g0_7 input2_5 -(35 11) routing lc_trk_g1_2 input2_5 (35 11) routing lc_trk_g1_6 input2_5 -(35 11) routing lc_trk_g2_3 input2_5 -(35 11) routing lc_trk_g2_7 input2_5 -(35 11) routing lc_trk_g3_2 input2_5 -(35 11) routing lc_trk_g3_6 input2_5 (35 12) routing lc_trk_g0_4 input2_6 (35 12) routing lc_trk_g0_6 input2_6 (35 12) routing lc_trk_g1_5 input2_6 @@ -3154,18 +2565,13 @@ (36 0) Enable bit of Mux _out_links/OutMux8_0 => wire_bram/ram/RDATA_15 sp4_h_r_32 (36 1) Enable bit of Mux _out_links/OutMux6_0 => wire_bram/ram/RDATA_15 sp4_h_r_0 (36 10) Enable bit of Mux _out_links/OutMux8_5 => wire_bram/ram/RDATA_10 sp4_h_r_42 -(36 11) Enable bit of Mux _out_links/OutMux6_5 => wire_bram/ram/RDATA_10 sp4_h_r_10 (36 12) Enable bit of Mux _out_links/OutMux8_6 => wire_bram/ram/RDATA_9 sp4_h_r_44 (36 13) Enable bit of Mux _out_links/OutMux6_6 => wire_bram/ram/RDATA_9 sp4_h_l_1 -(36 14) Enable bit of Mux _out_links/OutMux8_7 => wire_bram/ram/RDATA_8 sp4_h_r_46 (36 15) Enable bit of Mux _out_links/OutMux6_7 => wire_bram/ram/RDATA_8 sp4_h_l_3 (36 2) Enable bit of Mux _out_links/OutMux8_1 => wire_bram/ram/RDATA_14 sp4_h_r_34 -(36 3) Enable bit of Mux _out_links/OutMux6_1 => wire_bram/ram/RDATA_14 sp4_h_r_2 (36 4) Enable bit of Mux _out_links/OutMux8_2 => wire_bram/ram/RDATA_13 sp4_h_r_36 -(36 5) Enable bit of Mux _out_links/OutMux6_2 => wire_bram/ram/RDATA_13 sp4_h_r_4 (36 6) Enable bit of Mux _out_links/OutMux8_3 => wire_bram/ram/RDATA_12 sp4_h_l_27 (36 7) Enable bit of Mux _out_links/OutMux6_3 => wire_bram/ram/RDATA_12 sp4_h_r_6 -(36 8) Enable bit of Mux _out_links/OutMux8_4 => wire_bram/ram/RDATA_11 sp4_h_r_40 (36 9) Enable bit of Mux _out_links/OutMux6_4 => wire_bram/ram/RDATA_11 sp4_h_r_8 (37 0) Enable bit of Mux _out_links/OutMux5_0 => wire_bram/ram/RDATA_15 sp12_h_r_8 (37 1) Enable bit of Mux _out_links/OutMux7_0 => wire_bram/ram/RDATA_15 sp4_h_r_16 @@ -3180,13 +2586,10 @@ (37 4) Enable bit of Mux _out_links/OutMux5_2 => wire_bram/ram/RDATA_13 sp12_h_r_12 (37 5) Enable bit of Mux _out_links/OutMux7_2 => wire_bram/ram/RDATA_13 sp4_h_l_9 (37 6) Enable bit of Mux _out_links/OutMux5_3 => wire_bram/ram/RDATA_12 sp12_h_r_14 -(37 7) Enable bit of Mux _out_links/OutMux7_3 => wire_bram/ram/RDATA_12 sp4_h_l_11 (37 8) Enable bit of Mux _out_links/OutMux4_4 => wire_bram/ram/RDATA_11 sp12_h_r_0 (37 9) Enable bit of Mux _out_links/OutMux7_4 => wire_bram/ram/RDATA_11 sp4_h_r_24 (38 0) Enable bit of Mux _out_links/OutMux2_0 => wire_bram/ram/RDATA_15 sp4_v_b_32 -(38 1) Enable bit of Mux _out_links/OutMux0_0 => wire_bram/ram/RDATA_15 sp4_v_b_0 (38 10) Enable bit of Mux _out_links/OutMux1_5 => wire_bram/ram/RDATA_10 sp4_v_t_15 -(38 11) Enable bit of Mux _out_links/OutMux5_5 => wire_bram/ram/RDATA_10 sp12_h_l_17 (38 12) Enable bit of Mux _out_links/OutMux1_6 => wire_bram/ram/RDATA_9 sp4_v_b_28 (38 13) Enable bit of Mux _out_links/OutMux5_6 => wire_bram/ram/RDATA_9 sp12_h_r_20 (38 14) Enable bit of Mux _out_links/OutMux1_7 => wire_bram/ram/RDATA_8 sp4_v_t_19 @@ -3198,7 +2601,6 @@ (38 6) Enable bit of Mux _out_links/OutMux2_3 => wire_bram/ram/RDATA_12 sp4_v_t_27 (38 7) Enable bit of Mux _out_links/OutMux0_3 => wire_bram/ram/RDATA_12 sp4_v_b_6 (38 8) Enable bit of Mux _out_links/OutMux1_4 => wire_bram/ram/RDATA_11 sp4_v_t_13 -(38 9) Enable bit of Mux _out_links/OutMux5_4 => wire_bram/ram/RDATA_11 sp12_h_l_15 (39 0) Enable bit of Mux _out_links/OutMux3_0 => wire_bram/ram/RDATA_15 sp12_v_b_0 (39 1) Enable bit of Mux _out_links/OutMux1_0 => wire_bram/ram/RDATA_15 sp4_v_b_16 (39 10) Enable bit of Mux _out_links/OutMux2_5 => wire_bram/ram/RDATA_10 sp4_v_t_31 @@ -3219,15 +2621,12 @@ (4 0) routing sp4_h_l_43 sp4_v_b_0 (4 0) routing sp4_v_t_37 sp4_v_b_0 (4 0) routing sp4_v_t_41 sp4_v_b_0 -(4 1) routing sp4_h_l_41 sp4_h_r_0 (4 1) routing sp4_h_l_44 sp4_h_r_0 (4 1) routing sp4_v_b_6 sp4_h_r_0 -(4 1) routing sp4_v_t_42 sp4_h_r_0 (4 10) routing sp4_h_r_0 sp4_v_t_43 (4 10) routing sp4_h_r_6 sp4_v_t_43 (4 10) routing sp4_v_b_10 sp4_v_t_43 (4 10) routing sp4_v_b_6 sp4_v_t_43 -(4 11) routing sp4_h_r_10 sp4_h_l_43 (4 11) routing sp4_h_r_3 sp4_h_l_43 (4 11) routing sp4_v_b_1 sp4_h_l_43 (4 11) routing sp4_v_t_37 sp4_h_l_43 @@ -3235,16 +2634,11 @@ (4 12) routing sp4_h_l_44 sp4_v_b_9 (4 12) routing sp4_v_t_36 sp4_v_b_9 (4 12) routing sp4_v_t_44 sp4_v_b_9 -(4 13) routing sp4_h_l_36 sp4_h_r_9 -(4 13) routing sp4_h_l_43 sp4_h_r_9 -(4 13) routing sp4_v_b_3 sp4_h_r_9 (4 13) routing sp4_v_t_41 sp4_h_r_9 (4 14) routing sp4_h_r_3 sp4_v_t_44 (4 14) routing sp4_h_r_9 sp4_v_t_44 (4 14) routing sp4_v_b_1 sp4_v_t_44 (4 14) routing sp4_v_b_9 sp4_v_t_44 -(4 15) routing sp4_h_r_1 sp4_h_l_44 -(4 15) routing sp4_h_r_6 sp4_h_l_44 (4 15) routing sp4_v_b_4 sp4_h_l_44 (4 15) routing sp4_v_t_38 sp4_h_l_44 (4 2) routing sp4_h_r_0 sp4_v_t_37 @@ -3259,58 +2653,44 @@ (4 4) routing sp4_h_l_44 sp4_v_b_3 (4 4) routing sp4_v_t_38 sp4_v_b_3 (4 4) routing sp4_v_t_42 sp4_v_b_3 -(4 5) routing sp4_h_l_37 sp4_h_r_3 -(4 5) routing sp4_h_l_42 sp4_h_r_3 (4 5) routing sp4_v_b_9 sp4_h_r_3 (4 5) routing sp4_v_t_47 sp4_h_r_3 (4 6) routing sp4_h_r_3 sp4_v_t_38 (4 6) routing sp4_h_r_9 sp4_v_t_38 (4 6) routing sp4_v_b_3 sp4_v_t_38 (4 6) routing sp4_v_b_7 sp4_v_t_38 -(4 7) routing sp4_h_r_0 sp4_h_l_38 -(4 7) routing sp4_h_r_7 sp4_h_l_38 (4 7) routing sp4_v_b_10 sp4_h_l_38 (4 7) routing sp4_v_t_44 sp4_h_l_38 (4 8) routing sp4_h_l_37 sp4_v_b_6 (4 8) routing sp4_h_l_43 sp4_v_b_6 (4 8) routing sp4_v_t_43 sp4_v_b_6 (4 8) routing sp4_v_t_47 sp4_v_b_6 -(4 9) routing sp4_h_l_38 sp4_h_r_6 -(4 9) routing sp4_h_l_47 sp4_h_r_6 (4 9) routing sp4_v_b_0 sp4_h_r_6 (4 9) routing sp4_v_t_36 sp4_h_r_6 (40 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_bram/ram/RDATA_15 sp4_r_v_b_17 (40 1) Enable bit of Mux _out_links/OutMux4_0 => wire_bram/ram/RDATA_15 sp12_v_b_16 (40 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_bram/ram/RDATA_10 sp4_r_v_b_27 (40 11) Enable bit of Mux _out_links/OutMux3_5 => wire_bram/ram/RDATA_10 sp12_v_b_10 -(40 12) Enable bit of Mux _out_links/OutMuxa_6 => wire_bram/ram/RDATA_9 sp4_r_v_b_29 (40 13) Enable bit of Mux _out_links/OutMux3_6 => wire_bram/ram/RDATA_9 sp12_v_t_11 -(40 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_bram/ram/RDATA_8 sp4_r_v_b_31 (40 15) Enable bit of Mux _out_links/OutMux3_7 => wire_bram/ram/RDATA_8 sp12_v_b_14 (40 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_bram/ram/RDATA_14 sp4_r_v_b_19 (40 3) Enable bit of Mux _out_links/OutMux4_1 => wire_bram/ram/RDATA_14 sp12_v_b_18 (40 4) Enable bit of Mux _out_links/OutMuxa_2 => wire_bram/ram/RDATA_13 sp4_r_v_b_21 (40 5) Enable bit of Mux _out_links/OutMux4_2 => wire_bram/ram/RDATA_13 sp12_v_b_20 -(40 6) Enable bit of Mux _out_links/OutMuxa_3 => wire_bram/ram/RDATA_12 sp4_r_v_b_23 (40 7) Enable bit of Mux _out_links/OutMux4_3 => wire_bram/ram/RDATA_12 sp12_v_b_22 -(40 8) Enable bit of Mux _out_links/OutMuxa_4 => wire_bram/ram/RDATA_11 sp4_r_v_b_25 (40 9) Enable bit of Mux _out_links/OutMux3_4 => wire_bram/ram/RDATA_11 sp12_v_t_7 (41 0) Enable bit of Mux _out_links/OutMuxb_0 => wire_bram/ram/RDATA_15 sp4_r_v_b_33 -(41 1) Enable bit of Mux _out_links/OutMux9_0 => wire_bram/ram/RDATA_15 sp4_r_v_b_1 -(41 10) Enable bit of Mux _out_links/OutMuxb_5 => wire_bram/ram/RDATA_10 sp4_r_v_b_43 (41 11) Enable bit of Mux _out_links/OutMux9_5 => wire_bram/ram/RDATA_10 sp4_r_v_b_11 (41 12) Enable bit of Mux _out_links/OutMuxb_6 => wire_bram/ram/RDATA_9 sp4_r_v_b_45 (41 13) Enable bit of Mux _out_links/OutMux9_6 => wire_bram/ram/RDATA_9 sp4_r_v_b_13 (41 14) Enable bit of Mux _out_links/OutMuxb_7 => wire_bram/ram/RDATA_8 sp4_r_v_b_47 (41 15) Enable bit of Mux _out_links/OutMux9_7 => wire_bram/ram/RDATA_8 sp4_r_v_b_15 (41 2) Enable bit of Mux _out_links/OutMuxb_1 => wire_bram/ram/RDATA_14 sp4_r_v_b_35 -(41 3) Enable bit of Mux _out_links/OutMux9_1 => wire_bram/ram/RDATA_14 sp4_r_v_b_3 (41 4) Enable bit of Mux _out_links/OutMuxb_2 => wire_bram/ram/RDATA_13 sp4_r_v_b_37 (41 5) Enable bit of Mux _out_links/OutMux9_2 => wire_bram/ram/RDATA_13 sp4_r_v_b_5 (41 6) Enable bit of Mux _out_links/OutMuxb_3 => wire_bram/ram/RDATA_12 sp4_r_v_b_39 (41 7) Enable bit of Mux _out_links/OutMux9_3 => wire_bram/ram/RDATA_12 sp4_r_v_b_7 (41 8) Enable bit of Mux _out_links/OutMuxb_4 => wire_bram/ram/RDATA_11 sp4_r_v_b_41 -(41 9) Enable bit of Mux _out_links/OutMux9_4 => wire_bram/ram/RDATA_11 sp4_r_v_b_9 (5 0) routing sp4_h_l_44 sp4_h_r_0 (5 0) routing sp4_v_b_0 sp4_h_r_0 (5 0) routing sp4_v_b_6 sp4_h_r_0 @@ -3327,15 +2707,11 @@ (5 11) routing sp4_h_r_0 sp4_v_t_43 (5 11) routing sp4_h_r_6 sp4_v_t_43 (5 11) routing sp4_v_b_3 sp4_v_t_43 -(5 12) routing sp4_h_l_43 sp4_h_r_9 -(5 12) routing sp4_v_b_3 sp4_h_r_9 (5 12) routing sp4_v_b_9 sp4_h_r_9 -(5 12) routing sp4_v_t_44 sp4_h_r_9 (5 13) routing sp4_h_l_38 sp4_v_b_9 (5 13) routing sp4_h_l_44 sp4_v_b_9 (5 13) routing sp4_h_r_9 sp4_v_b_9 (5 13) routing sp4_v_t_43 sp4_v_b_9 -(5 14) routing sp4_h_r_6 sp4_h_l_44 (5 14) routing sp4_v_b_9 sp4_h_l_44 (5 14) routing sp4_v_t_38 sp4_h_l_44 (5 14) routing sp4_v_t_44 sp4_h_l_44 @@ -3351,15 +2727,12 @@ (5 3) routing sp4_h_r_0 sp4_v_t_37 (5 3) routing sp4_h_r_6 sp4_v_t_37 (5 3) routing sp4_v_b_9 sp4_v_t_37 -(5 4) routing sp4_h_l_37 sp4_h_r_3 -(5 4) routing sp4_v_b_3 sp4_h_r_3 (5 4) routing sp4_v_b_9 sp4_h_r_3 (5 4) routing sp4_v_t_38 sp4_h_r_3 (5 5) routing sp4_h_l_38 sp4_v_b_3 (5 5) routing sp4_h_l_44 sp4_v_b_3 (5 5) routing sp4_h_r_3 sp4_v_b_3 (5 5) routing sp4_v_t_37 sp4_v_b_3 -(5 6) routing sp4_h_r_0 sp4_h_l_38 (5 6) routing sp4_v_b_3 sp4_h_l_38 (5 6) routing sp4_v_t_38 sp4_h_l_38 (5 6) routing sp4_v_t_44 sp4_h_l_38 @@ -3367,7 +2740,6 @@ (5 7) routing sp4_h_r_3 sp4_v_t_38 (5 7) routing sp4_h_r_9 sp4_v_t_38 (5 7) routing sp4_v_b_0 sp4_v_t_38 -(5 8) routing sp4_h_l_38 sp4_h_r_6 (5 8) routing sp4_v_b_0 sp4_h_r_6 (5 8) routing sp4_v_b_6 sp4_h_r_6 (5 8) routing sp4_v_t_43 sp4_h_r_6 @@ -3379,15 +2751,12 @@ (6 0) routing sp4_h_r_7 sp4_v_b_0 (6 0) routing sp4_v_t_41 sp4_v_b_0 (6 0) routing sp4_v_t_44 sp4_v_b_0 -(6 1) routing sp4_h_l_37 sp4_h_r_0 -(6 1) routing sp4_h_l_41 sp4_h_r_0 (6 1) routing sp4_v_b_0 sp4_h_r_0 (6 1) routing sp4_v_b_6 sp4_h_r_0 (6 10) routing sp4_h_l_36 sp4_v_t_43 (6 10) routing sp4_h_r_0 sp4_v_t_43 (6 10) routing sp4_v_b_10 sp4_v_t_43 (6 10) routing sp4_v_b_3 sp4_v_t_43 -(6 11) routing sp4_h_r_10 sp4_h_l_43 (6 11) routing sp4_h_r_6 sp4_h_l_43 (6 11) routing sp4_v_t_37 sp4_h_l_43 (6 11) routing sp4_v_t_43 sp4_h_l_43 @@ -3395,23 +2764,17 @@ (6 12) routing sp4_h_r_4 sp4_v_b_9 (6 12) routing sp4_v_t_36 sp4_v_b_9 (6 12) routing sp4_v_t_43 sp4_v_b_9 -(6 13) routing sp4_h_l_36 sp4_h_r_9 -(6 13) routing sp4_h_l_44 sp4_h_r_9 -(6 13) routing sp4_v_b_3 sp4_h_r_9 (6 13) routing sp4_v_b_9 sp4_h_r_9 (6 14) routing sp4_h_l_41 sp4_v_t_44 (6 14) routing sp4_h_r_3 sp4_v_t_44 (6 14) routing sp4_v_b_1 sp4_v_t_44 (6 14) routing sp4_v_b_6 sp4_v_t_44 -(6 15) routing sp4_h_r_1 sp4_h_l_44 -(6 15) routing sp4_h_r_9 sp4_h_l_44 (6 15) routing sp4_v_t_38 sp4_h_l_44 (6 15) routing sp4_v_t_44 sp4_h_l_44 (6 2) routing sp4_h_l_42 sp4_v_t_37 (6 2) routing sp4_h_r_6 sp4_v_t_37 (6 2) routing sp4_v_b_4 sp4_v_t_37 (6 2) routing sp4_v_b_9 sp4_v_t_37 -(6 3) routing sp4_h_r_0 sp4_h_l_37 (6 3) routing sp4_h_r_4 sp4_h_l_37 (6 3) routing sp4_v_t_37 sp4_h_l_37 (6 3) routing sp4_v_t_43 sp4_h_l_37 @@ -3419,24 +2782,18 @@ (6 4) routing sp4_h_r_10 sp4_v_b_3 (6 4) routing sp4_v_t_37 sp4_v_b_3 (6 4) routing sp4_v_t_42 sp4_v_b_3 -(6 5) routing sp4_h_l_38 sp4_h_r_3 -(6 5) routing sp4_h_l_42 sp4_h_r_3 -(6 5) routing sp4_v_b_3 sp4_h_r_3 (6 5) routing sp4_v_b_9 sp4_h_r_3 (6 6) routing sp4_h_l_47 sp4_v_t_38 (6 6) routing sp4_h_r_9 sp4_v_t_38 (6 6) routing sp4_v_b_0 sp4_v_t_38 (6 6) routing sp4_v_b_7 sp4_v_t_38 (6 7) routing sp4_h_r_3 sp4_h_l_38 -(6 7) routing sp4_h_r_7 sp4_h_l_38 (6 7) routing sp4_v_t_38 sp4_h_l_38 (6 7) routing sp4_v_t_44 sp4_h_l_38 (6 8) routing sp4_h_l_37 sp4_v_b_6 (6 8) routing sp4_h_r_1 sp4_v_b_6 (6 8) routing sp4_v_t_38 sp4_v_b_6 (6 8) routing sp4_v_t_47 sp4_v_b_6 -(6 9) routing sp4_h_l_43 sp4_h_r_6 -(6 9) routing sp4_h_l_47 sp4_h_r_6 (6 9) routing sp4_v_b_0 sp4_h_r_6 (6 9) routing sp4_v_b_6 sp4_h_r_6 (7 1) Ram config bit: MEMB_Power_Up_Control @@ -3456,23 +2813,18 @@ (8 1) routing sp4_h_l_42 sp4_v_b_1 (8 1) routing sp4_h_r_1 sp4_v_b_1 (8 1) routing sp4_v_t_47 sp4_v_b_1 -(8 10) routing sp4_h_r_11 sp4_h_l_42 -(8 10) routing sp4_h_r_7 sp4_h_l_42 (8 10) routing sp4_v_t_36 sp4_h_l_42 (8 10) routing sp4_v_t_42 sp4_h_l_42 (8 11) routing sp4_h_l_42 sp4_v_t_42 (8 11) routing sp4_h_r_1 sp4_v_t_42 (8 11) routing sp4_h_r_7 sp4_v_t_42 (8 11) routing sp4_v_b_4 sp4_v_t_42 -(8 12) routing sp4_h_l_39 sp4_h_r_10 (8 12) routing sp4_h_l_47 sp4_h_r_10 -(8 12) routing sp4_v_b_10 sp4_h_r_10 (8 12) routing sp4_v_b_4 sp4_h_r_10 (8 13) routing sp4_h_l_41 sp4_v_b_10 (8 13) routing sp4_h_l_47 sp4_v_b_10 (8 13) routing sp4_h_r_10 sp4_v_b_10 (8 13) routing sp4_v_t_42 sp4_v_b_10 -(8 14) routing sp4_h_r_10 sp4_h_l_47 (8 14) routing sp4_h_r_2 sp4_h_l_47 (8 14) routing sp4_v_t_41 sp4_h_l_47 (8 14) routing sp4_v_t_47 sp4_h_l_47 @@ -3480,39 +2832,28 @@ (8 15) routing sp4_h_r_10 sp4_v_t_47 (8 15) routing sp4_h_r_4 sp4_v_t_47 (8 15) routing sp4_v_b_7 sp4_v_t_47 -(8 2) routing sp4_h_r_1 sp4_h_l_36 -(8 2) routing sp4_h_r_5 sp4_h_l_36 (8 2) routing sp4_v_t_36 sp4_h_l_36 (8 2) routing sp4_v_t_42 sp4_h_l_36 (8 3) routing sp4_h_l_36 sp4_v_t_36 (8 3) routing sp4_h_r_1 sp4_v_t_36 (8 3) routing sp4_h_r_7 sp4_v_t_36 (8 3) routing sp4_v_b_10 sp4_v_t_36 -(8 4) routing sp4_h_l_41 sp4_h_r_4 (8 4) routing sp4_h_l_45 sp4_h_r_4 -(8 4) routing sp4_v_b_10 sp4_h_r_4 (8 4) routing sp4_v_b_4 sp4_h_r_4 (8 5) routing sp4_h_l_41 sp4_v_b_4 (8 5) routing sp4_h_l_47 sp4_v_b_4 (8 5) routing sp4_h_r_4 sp4_v_b_4 (8 5) routing sp4_v_t_36 sp4_v_b_4 (8 6) routing sp4_h_r_4 sp4_h_l_41 -(8 6) routing sp4_h_r_8 sp4_h_l_41 (8 6) routing sp4_v_t_41 sp4_h_l_41 (8 6) routing sp4_v_t_47 sp4_h_l_41 (8 7) routing sp4_h_l_41 sp4_v_t_41 -(8 7) routing sp4_h_r_10 sp4_v_t_41 (8 7) routing sp4_h_r_4 sp4_v_t_41 (8 7) routing sp4_v_b_1 sp4_v_t_41 -(8 8) routing sp4_h_l_42 sp4_h_r_7 -(8 8) routing sp4_h_l_46 sp4_h_r_7 -(8 8) routing sp4_v_b_1 sp4_h_r_7 -(8 8) routing sp4_v_b_7 sp4_h_r_7 (8 9) routing sp4_h_l_36 sp4_v_b_7 (8 9) routing sp4_h_l_42 sp4_v_b_7 (8 9) routing sp4_h_r_7 sp4_v_b_7 (8 9) routing sp4_v_t_41 sp4_v_b_7 -(9 0) routing sp4_h_l_47 sp4_h_r_1 (9 0) routing sp4_v_b_1 sp4_h_r_1 (9 0) routing sp4_v_b_7 sp4_h_r_1 (9 0) routing sp4_v_t_36 sp4_h_r_1 @@ -3528,8 +2869,6 @@ (9 11) routing sp4_h_r_7 sp4_v_t_42 (9 11) routing sp4_v_b_11 sp4_v_t_42 (9 11) routing sp4_v_b_7 sp4_v_t_42 -(9 12) routing sp4_h_l_42 sp4_h_r_10 -(9 12) routing sp4_v_b_10 sp4_h_r_10 (9 12) routing sp4_v_b_4 sp4_h_r_10 (9 12) routing sp4_v_t_47 sp4_h_r_10 (9 13) routing sp4_h_l_41 sp4_v_b_10 @@ -3553,24 +2892,18 @@ (9 3) routing sp4_v_b_1 sp4_v_t_36 (9 3) routing sp4_v_b_5 sp4_v_t_36 (9 4) routing sp4_h_l_36 sp4_h_r_4 -(9 4) routing sp4_v_b_10 sp4_h_r_4 (9 4) routing sp4_v_b_4 sp4_h_r_4 (9 4) routing sp4_v_t_41 sp4_h_r_4 (9 5) routing sp4_h_l_41 sp4_v_b_4 (9 5) routing sp4_h_l_47 sp4_v_b_4 (9 5) routing sp4_v_t_41 sp4_v_b_4 (9 5) routing sp4_v_t_45 sp4_v_b_4 -(9 6) routing sp4_h_r_1 sp4_h_l_41 (9 6) routing sp4_v_b_4 sp4_h_l_41 (9 6) routing sp4_v_t_41 sp4_h_l_41 (9 6) routing sp4_v_t_47 sp4_h_l_41 -(9 7) routing sp4_h_r_10 sp4_v_t_41 (9 7) routing sp4_h_r_4 sp4_v_t_41 (9 7) routing sp4_v_b_4 sp4_v_t_41 (9 7) routing sp4_v_b_8 sp4_v_t_41 -(9 8) routing sp4_h_l_41 sp4_h_r_7 -(9 8) routing sp4_v_b_1 sp4_h_r_7 -(9 8) routing sp4_v_b_7 sp4_h_r_7 (9 8) routing sp4_v_t_42 sp4_h_r_7 (9 9) routing sp4_h_l_36 sp4_v_b_7 (9 9) routing sp4_h_l_42 sp4_v_b_7 diff --git a/icefuzz/cached_ramt_5k.txt b/icefuzz/cached_ramt_5k.txt index e5d7177..488b30a 100644 --- a/icefuzz/cached_ramt_5k.txt +++ b/icefuzz/cached_ramt_5k.txt @@ -1,92 +1,37 @@ (0 0) Negative Clock bit -(0 10) routing glb_netwk_2 glb2local_2 -(0 10) routing glb_netwk_3 glb2local_2 -(0 10) routing glb_netwk_6 glb2local_2 -(0 10) routing glb_netwk_7 glb2local_2 -(0 11) routing glb_netwk_1 glb2local_2 -(0 11) routing glb_netwk_3 glb2local_2 (0 11) routing glb_netwk_5 glb2local_2 -(0 11) routing glb_netwk_7 glb2local_2 -(0 12) routing glb_netwk_2 glb2local_3 -(0 12) routing glb_netwk_3 glb2local_3 -(0 12) routing glb_netwk_6 glb2local_3 -(0 12) routing glb_netwk_7 glb2local_3 -(0 13) routing glb_netwk_1 glb2local_3 -(0 13) routing glb_netwk_3 glb2local_3 (0 13) routing glb_netwk_5 glb2local_3 -(0 13) routing glb_netwk_7 glb2local_3 (0 14) routing glb_netwk_4 wire_bram/ram/WE -(0 14) routing glb_netwk_6 wire_bram/ram/WE (0 14) routing lc_trk_g2_4 wire_bram/ram/WE (0 14) routing lc_trk_g3_5 wire_bram/ram/WE -(0 15) routing glb_netwk_2 wire_bram/ram/WE -(0 15) routing glb_netwk_6 wire_bram/ram/WE (0 15) routing lc_trk_g1_5 wire_bram/ram/WE (0 15) routing lc_trk_g3_5 wire_bram/ram/WE (0 2) routing glb_netwk_2 wire_bram/ram/WCLK -(0 2) routing glb_netwk_3 wire_bram/ram/WCLK -(0 2) routing glb_netwk_6 wire_bram/ram/WCLK (0 2) routing glb_netwk_7 wire_bram/ram/WCLK (0 2) routing lc_trk_g2_0 wire_bram/ram/WCLK (0 2) routing lc_trk_g3_1 wire_bram/ram/WCLK -(0 3) routing glb_netwk_1 wire_bram/ram/WCLK -(0 3) routing glb_netwk_3 wire_bram/ram/WCLK (0 3) routing glb_netwk_5 wire_bram/ram/WCLK (0 3) routing glb_netwk_7 wire_bram/ram/WCLK (0 3) routing lc_trk_g1_1 wire_bram/ram/WCLK (0 3) routing lc_trk_g3_1 wire_bram/ram/WCLK (0 4) routing glb_netwk_5 wire_bram/ram/WCLKE -(0 4) routing glb_netwk_7 wire_bram/ram/WCLKE (0 4) routing lc_trk_g2_2 wire_bram/ram/WCLKE (0 4) routing lc_trk_g3_3 wire_bram/ram/WCLKE (0 5) routing glb_netwk_3 wire_bram/ram/WCLKE -(0 5) routing glb_netwk_7 wire_bram/ram/WCLKE (0 5) routing lc_trk_g1_3 wire_bram/ram/WCLKE (0 5) routing lc_trk_g3_3 wire_bram/ram/WCLKE -(0 6) routing glb_netwk_2 glb2local_0 (0 6) routing glb_netwk_3 glb2local_0 -(0 6) routing glb_netwk_6 glb2local_0 -(0 6) routing glb_netwk_7 glb2local_0 -(0 7) routing glb_netwk_1 glb2local_0 (0 7) routing glb_netwk_3 glb2local_0 (0 7) routing glb_netwk_5 glb2local_0 -(0 7) routing glb_netwk_7 glb2local_0 -(0 8) routing glb_netwk_2 glb2local_1 (0 8) routing glb_netwk_3 glb2local_1 -(0 8) routing glb_netwk_6 glb2local_1 -(0 8) routing glb_netwk_7 glb2local_1 -(0 9) routing glb_netwk_1 glb2local_1 (0 9) routing glb_netwk_3 glb2local_1 -(0 9) routing glb_netwk_5 glb2local_1 -(0 9) routing glb_netwk_7 glb2local_1 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_0 glb2local_2 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_2 glb2local_2 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2 (1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2 (1 11) routing glb_netwk_4 glb2local_2 (1 11) routing glb_netwk_5 glb2local_2 -(1 11) routing glb_netwk_6 glb2local_2 -(1 11) routing glb_netwk_7 glb2local_2 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_0 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_2 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3 (1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3 -(1 13) routing glb_netwk_4 glb2local_3 (1 13) routing glb_netwk_5 glb2local_3 -(1 13) routing glb_netwk_6 glb2local_3 -(1 13) routing glb_netwk_7 glb2local_3 -(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_0 wire_bram/ram/WE -(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_bram/ram/WE (1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_bram/ram/WE -(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_bram/ram/WE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_bram/ram/WE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g1_5 wire_bram/ram/WE (1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_bram/ram/WE @@ -95,15 +40,11 @@ (1 15) routing lc_trk_g1_5 wire_bram/ram/WE (1 15) routing lc_trk_g2_4 wire_bram/ram/WE (1 15) routing lc_trk_g3_5 wire_bram/ram/WE -(1 2) routing glb_netwk_4 wire_bram/ram/WCLK (1 2) routing glb_netwk_5 wire_bram/ram/WCLK -(1 2) routing glb_netwk_6 wire_bram/ram/WCLK (1 2) routing glb_netwk_7 wire_bram/ram/WCLK (1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_r_10 sp4_h_r_17 -(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_1 wire_bram/ram/WCLKE (1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_3 wire_bram/ram/WCLKE (1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_5 wire_bram/ram/WCLKE -(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_7 wire_bram/ram/WCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g0_2 wire_bram/ram/WCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g1_3 wire_bram/ram/WCLKE (1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g2_2 wire_bram/ram/WCLKE @@ -112,71 +53,41 @@ (1 5) routing lc_trk_g1_3 wire_bram/ram/WCLKE (1 5) routing lc_trk_g2_2 wire_bram/ram/WCLKE (1 5) routing lc_trk_g3_3 wire_bram/ram/WCLKE -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_0 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_2 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 (1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0 (1 7) routing glb_netwk_4 glb2local_0 (1 7) routing glb_netwk_5 glb2local_0 -(1 7) routing glb_netwk_6 glb2local_0 -(1 7) routing glb_netwk_7 glb2local_0 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_0 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_2 glb2local_1 (1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_7 glb2local_1 -(1 9) routing glb_netwk_4 glb2local_1 -(1 9) routing glb_netwk_5 glb2local_1 -(1 9) routing glb_netwk_6 glb2local_1 -(1 9) routing glb_netwk_7 glb2local_1 -(10 0) routing sp4_h_l_40 sp4_h_r_1 -(10 0) routing sp4_h_l_47 sp4_h_r_1 -(10 0) routing sp4_v_b_7 sp4_h_r_1 -(10 0) routing sp4_v_t_45 sp4_h_r_1 (10 1) routing sp4_h_l_42 sp4_v_b_1 (10 1) routing sp4_h_r_8 sp4_v_b_1 (10 1) routing sp4_v_t_40 sp4_v_b_1 (10 1) routing sp4_v_t_47 sp4_v_b_1 (10 10) routing sp4_h_r_11 sp4_h_l_42 -(10 10) routing sp4_h_r_4 sp4_h_l_42 (10 10) routing sp4_v_b_2 sp4_h_l_42 (10 10) routing sp4_v_t_36 sp4_h_l_42 (10 11) routing sp4_h_l_39 sp4_v_t_42 (10 11) routing sp4_h_r_1 sp4_v_t_42 (10 11) routing sp4_v_b_11 sp4_v_t_42 (10 11) routing sp4_v_b_4 sp4_v_t_42 -(10 12) routing sp4_h_l_39 sp4_h_r_10 -(10 12) routing sp4_h_l_42 sp4_h_r_10 (10 12) routing sp4_v_b_4 sp4_h_r_10 (10 12) routing sp4_v_t_40 sp4_h_r_10 (10 13) routing sp4_h_l_41 sp4_v_b_10 (10 13) routing sp4_h_r_5 sp4_v_b_10 (10 13) routing sp4_v_t_39 sp4_v_b_10 (10 13) routing sp4_v_t_42 sp4_v_b_10 -(10 14) routing sp4_h_r_2 sp4_h_l_47 -(10 14) routing sp4_h_r_7 sp4_h_l_47 (10 14) routing sp4_v_b_5 sp4_h_l_47 (10 14) routing sp4_v_t_41 sp4_h_l_47 (10 15) routing sp4_h_l_40 sp4_v_t_47 -(10 15) routing sp4_h_r_4 sp4_v_t_47 (10 15) routing sp4_v_b_2 sp4_v_t_47 (10 15) routing sp4_v_b_7 sp4_v_t_47 (10 2) routing sp4_h_r_10 sp4_h_l_36 -(10 2) routing sp4_h_r_5 sp4_h_l_36 (10 2) routing sp4_v_b_8 sp4_h_l_36 (10 2) routing sp4_v_t_42 sp4_h_l_36 (10 3) routing sp4_h_l_45 sp4_v_t_36 (10 3) routing sp4_h_r_7 sp4_v_t_36 (10 3) routing sp4_v_b_10 sp4_v_t_36 (10 3) routing sp4_v_b_5 sp4_v_t_36 -(10 4) routing sp4_h_l_36 sp4_h_r_4 (10 4) routing sp4_h_l_45 sp4_h_r_4 (10 4) routing sp4_v_b_10 sp4_h_r_4 (10 4) routing sp4_v_t_46 sp4_h_r_4 @@ -185,15 +96,12 @@ (10 5) routing sp4_v_t_36 sp4_v_b_4 (10 5) routing sp4_v_t_45 sp4_v_b_4 (10 6) routing sp4_h_r_1 sp4_h_l_41 -(10 6) routing sp4_h_r_8 sp4_h_l_41 (10 6) routing sp4_v_b_11 sp4_h_l_41 (10 6) routing sp4_v_t_47 sp4_h_l_41 (10 7) routing sp4_h_l_46 sp4_v_t_41 (10 7) routing sp4_h_r_10 sp4_v_t_41 (10 7) routing sp4_v_b_1 sp4_v_t_41 (10 7) routing sp4_v_b_8 sp4_v_t_41 -(10 8) routing sp4_h_l_41 sp4_h_r_7 -(10 8) routing sp4_h_l_46 sp4_h_r_7 (10 8) routing sp4_v_b_1 sp4_h_r_7 (10 8) routing sp4_v_t_39 sp4_h_r_7 (10 9) routing sp4_h_l_36 sp4_v_b_7 @@ -204,16 +112,10 @@ (11 0) routing sp4_h_r_9 sp4_v_b_2 (11 0) routing sp4_v_t_43 sp4_v_b_2 (11 0) routing sp4_v_t_46 sp4_v_b_2 -(11 1) routing sp4_h_l_39 sp4_h_r_2 -(11 1) routing sp4_h_l_43 sp4_h_r_2 -(11 1) routing sp4_v_b_2 sp4_h_r_2 (11 1) routing sp4_v_b_8 sp4_h_r_2 (11 10) routing sp4_h_l_38 sp4_v_t_45 -(11 10) routing sp4_h_r_2 sp4_v_t_45 (11 10) routing sp4_v_b_0 sp4_v_t_45 (11 10) routing sp4_v_b_5 sp4_v_t_45 -(11 11) routing sp4_h_r_0 sp4_h_l_45 -(11 11) routing sp4_h_r_8 sp4_h_l_45 (11 11) routing sp4_v_t_39 sp4_h_l_45 (11 11) routing sp4_v_t_45 sp4_h_l_45 (11 12) routing sp4_h_l_40 sp4_v_b_11 @@ -221,14 +123,12 @@ (11 12) routing sp4_v_t_38 sp4_v_b_11 (11 12) routing sp4_v_t_45 sp4_v_b_11 (11 13) routing sp4_h_l_38 sp4_h_r_11 -(11 13) routing sp4_h_l_46 sp4_h_r_11 (11 13) routing sp4_v_b_11 sp4_h_r_11 (11 13) routing sp4_v_b_5 sp4_h_r_11 (11 14) routing sp4_h_l_43 sp4_v_t_46 (11 14) routing sp4_h_r_5 sp4_v_t_46 (11 14) routing sp4_v_b_3 sp4_v_t_46 (11 14) routing sp4_v_b_8 sp4_v_t_46 -(11 15) routing sp4_h_r_11 sp4_h_l_46 (11 15) routing sp4_h_r_3 sp4_h_l_46 (11 15) routing sp4_v_t_40 sp4_h_l_46 (11 15) routing sp4_v_t_46 sp4_h_l_46 @@ -237,35 +137,22 @@ (11 2) routing sp4_v_b_11 sp4_v_t_39 (11 2) routing sp4_v_b_6 sp4_v_t_39 (11 3) routing sp4_h_r_2 sp4_h_l_39 -(11 3) routing sp4_h_r_6 sp4_h_l_39 (11 3) routing sp4_v_t_39 sp4_h_l_39 (11 3) routing sp4_v_t_45 sp4_h_l_39 (11 4) routing sp4_h_l_46 sp4_v_b_5 (11 4) routing sp4_h_r_0 sp4_v_b_5 (11 4) routing sp4_v_t_39 sp4_v_b_5 (11 4) routing sp4_v_t_44 sp4_v_b_5 -(11 5) routing sp4_h_l_40 sp4_h_r_5 -(11 5) routing sp4_h_l_44 sp4_h_r_5 -(11 5) routing sp4_v_b_11 sp4_h_r_5 (11 5) routing sp4_v_b_5 sp4_h_r_5 (11 6) routing sp4_h_l_37 sp4_v_t_40 (11 6) routing sp4_h_r_11 sp4_v_t_40 (11 6) routing sp4_v_b_2 sp4_v_t_40 (11 6) routing sp4_v_b_9 sp4_v_t_40 -(11 7) routing sp4_h_r_5 sp4_h_l_40 -(11 7) routing sp4_h_r_9 sp4_h_l_40 (11 7) routing sp4_v_t_40 sp4_h_l_40 -(11 7) routing sp4_v_t_46 sp4_h_l_40 (11 8) routing sp4_h_l_39 sp4_v_b_8 (11 8) routing sp4_h_r_3 sp4_v_b_8 (11 8) routing sp4_v_t_37 sp4_v_b_8 (11 8) routing sp4_v_t_40 sp4_v_b_8 -(11 9) routing sp4_h_l_37 sp4_h_r_8 -(11 9) routing sp4_h_l_45 sp4_h_r_8 -(11 9) routing sp4_v_b_2 sp4_h_r_8 -(11 9) routing sp4_v_b_8 sp4_h_r_8 -(12 0) routing sp4_h_l_46 sp4_h_r_2 -(12 0) routing sp4_v_b_2 sp4_h_r_2 (12 0) routing sp4_v_b_8 sp4_h_r_2 (12 0) routing sp4_v_t_39 sp4_h_r_2 (12 1) routing sp4_h_l_39 sp4_v_b_2 @@ -277,10 +164,7 @@ (12 10) routing sp4_v_t_39 sp4_h_l_45 (12 10) routing sp4_v_t_45 sp4_h_l_45 (12 11) routing sp4_h_l_45 sp4_v_t_45 -(12 11) routing sp4_h_r_2 sp4_v_t_45 -(12 11) routing sp4_h_r_8 sp4_v_t_45 (12 11) routing sp4_v_b_5 sp4_v_t_45 -(12 12) routing sp4_h_l_45 sp4_h_r_11 (12 12) routing sp4_v_b_11 sp4_h_r_11 (12 12) routing sp4_v_b_5 sp4_h_r_11 (12 12) routing sp4_v_t_46 sp4_h_r_11 @@ -288,7 +172,6 @@ (12 13) routing sp4_h_l_46 sp4_v_b_11 (12 13) routing sp4_h_r_11 sp4_v_b_11 (12 13) routing sp4_v_t_45 sp4_v_b_11 -(12 14) routing sp4_h_r_8 sp4_h_l_46 (12 14) routing sp4_v_b_11 sp4_h_l_46 (12 14) routing sp4_v_t_40 sp4_h_l_46 (12 14) routing sp4_v_t_46 sp4_h_l_46 @@ -296,8 +179,6 @@ (12 15) routing sp4_h_r_11 sp4_v_t_46 (12 15) routing sp4_h_r_5 sp4_v_t_46 (12 15) routing sp4_v_b_8 sp4_v_t_46 -(12 2) routing sp4_h_r_11 sp4_h_l_39 -(12 2) routing sp4_v_b_2 sp4_h_l_39 (12 2) routing sp4_v_t_39 sp4_h_l_39 (12 2) routing sp4_v_t_45 sp4_h_l_39 (12 3) routing sp4_h_l_39 sp4_v_t_39 @@ -305,24 +186,18 @@ (12 3) routing sp4_h_r_8 sp4_v_t_39 (12 3) routing sp4_v_b_11 sp4_v_t_39 (12 4) routing sp4_h_l_39 sp4_h_r_5 -(12 4) routing sp4_v_b_11 sp4_h_r_5 (12 4) routing sp4_v_b_5 sp4_h_r_5 (12 4) routing sp4_v_t_40 sp4_h_r_5 (12 5) routing sp4_h_l_40 sp4_v_b_5 (12 5) routing sp4_h_l_46 sp4_v_b_5 (12 5) routing sp4_h_r_5 sp4_v_b_5 (12 5) routing sp4_v_t_39 sp4_v_b_5 -(12 6) routing sp4_h_r_2 sp4_h_l_40 (12 6) routing sp4_v_b_5 sp4_h_l_40 (12 6) routing sp4_v_t_40 sp4_h_l_40 -(12 6) routing sp4_v_t_46 sp4_h_l_40 (12 7) routing sp4_h_l_40 sp4_v_t_40 (12 7) routing sp4_h_r_11 sp4_v_t_40 (12 7) routing sp4_h_r_5 sp4_v_t_40 (12 7) routing sp4_v_b_2 sp4_v_t_40 -(12 8) routing sp4_h_l_40 sp4_h_r_8 -(12 8) routing sp4_v_b_2 sp4_h_r_8 -(12 8) routing sp4_v_b_8 sp4_h_r_8 (12 8) routing sp4_v_t_45 sp4_h_r_8 (12 9) routing sp4_h_l_39 sp4_v_b_8 (12 9) routing sp4_h_l_45 sp4_v_b_8 @@ -332,24 +207,17 @@ (13 0) routing sp4_h_l_45 sp4_v_b_2 (13 0) routing sp4_v_t_39 sp4_v_b_2 (13 0) routing sp4_v_t_43 sp4_v_b_2 -(13 1) routing sp4_h_l_43 sp4_h_r_2 -(13 1) routing sp4_h_l_46 sp4_h_r_2 (13 1) routing sp4_v_b_8 sp4_h_r_2 (13 1) routing sp4_v_t_44 sp4_h_r_2 -(13 10) routing sp4_h_r_2 sp4_v_t_45 -(13 10) routing sp4_h_r_8 sp4_v_t_45 (13 10) routing sp4_v_b_0 sp4_v_t_45 (13 10) routing sp4_v_b_8 sp4_v_t_45 -(13 11) routing sp4_h_r_0 sp4_h_l_45 (13 11) routing sp4_h_r_5 sp4_h_l_45 -(13 11) routing sp4_v_b_3 sp4_h_l_45 (13 11) routing sp4_v_t_39 sp4_h_l_45 (13 12) routing sp4_h_l_40 sp4_v_b_11 (13 12) routing sp4_h_l_46 sp4_v_b_11 (13 12) routing sp4_v_t_38 sp4_v_b_11 (13 12) routing sp4_v_t_46 sp4_v_b_11 (13 13) routing sp4_h_l_38 sp4_h_r_11 -(13 13) routing sp4_h_l_45 sp4_h_r_11 (13 13) routing sp4_v_b_5 sp4_h_r_11 (13 13) routing sp4_v_t_43 sp4_h_r_11 (13 14) routing sp4_h_r_11 sp4_v_t_46 @@ -357,15 +225,12 @@ (13 14) routing sp4_v_b_11 sp4_v_t_46 (13 14) routing sp4_v_b_3 sp4_v_t_46 (13 15) routing sp4_h_r_3 sp4_h_l_46 -(13 15) routing sp4_h_r_8 sp4_h_l_46 (13 15) routing sp4_v_b_6 sp4_h_l_46 (13 15) routing sp4_v_t_40 sp4_h_l_46 (13 2) routing sp4_h_r_2 sp4_v_t_39 (13 2) routing sp4_h_r_8 sp4_v_t_39 (13 2) routing sp4_v_b_2 sp4_v_t_39 (13 2) routing sp4_v_b_6 sp4_v_t_39 -(13 3) routing sp4_h_r_11 sp4_h_l_39 -(13 3) routing sp4_h_r_6 sp4_h_l_39 (13 3) routing sp4_v_b_9 sp4_h_l_39 (13 3) routing sp4_v_t_45 sp4_h_l_39 (13 4) routing sp4_h_l_40 sp4_v_b_5 @@ -373,50 +238,35 @@ (13 4) routing sp4_v_t_40 sp4_v_b_5 (13 4) routing sp4_v_t_44 sp4_v_b_5 (13 5) routing sp4_h_l_39 sp4_h_r_5 -(13 5) routing sp4_h_l_44 sp4_h_r_5 -(13 5) routing sp4_v_b_11 sp4_h_r_5 -(13 5) routing sp4_v_t_37 sp4_h_r_5 (13 6) routing sp4_h_r_11 sp4_v_t_40 (13 6) routing sp4_h_r_5 sp4_v_t_40 (13 6) routing sp4_v_b_5 sp4_v_t_40 (13 6) routing sp4_v_b_9 sp4_v_t_40 -(13 7) routing sp4_h_r_2 sp4_h_l_40 -(13 7) routing sp4_h_r_9 sp4_h_l_40 (13 7) routing sp4_v_b_0 sp4_h_l_40 -(13 7) routing sp4_v_t_46 sp4_h_l_40 (13 8) routing sp4_h_l_39 sp4_v_b_8 (13 8) routing sp4_h_l_45 sp4_v_b_8 (13 8) routing sp4_v_t_37 sp4_v_b_8 (13 8) routing sp4_v_t_45 sp4_v_b_8 -(13 9) routing sp4_h_l_37 sp4_h_r_8 -(13 9) routing sp4_h_l_40 sp4_h_r_8 -(13 9) routing sp4_v_b_2 sp4_h_r_8 (13 9) routing sp4_v_t_38 sp4_h_r_8 (14 0) routing bnr_op_0 lc_trk_g0_0 (14 0) routing lft_op_0 lc_trk_g0_0 -(14 0) routing sp12_h_r_0 lc_trk_g0_0 (14 0) routing sp4_h_l_5 lc_trk_g0_0 (14 0) routing sp4_h_r_8 lc_trk_g0_0 (14 0) routing sp4_v_b_0 lc_trk_g0_0 (14 0) routing sp4_v_b_8 lc_trk_g0_0 (14 1) routing bnr_op_0 lc_trk_g0_0 -(14 1) routing sp12_h_r_0 lc_trk_g0_0 -(14 1) routing sp12_h_r_16 lc_trk_g0_0 (14 1) routing sp4_h_l_5 lc_trk_g0_0 (14 1) routing sp4_h_r_0 lc_trk_g0_0 (14 1) routing sp4_r_v_b_35 lc_trk_g0_0 (14 1) routing sp4_v_b_8 lc_trk_g0_0 -(14 1) routing top_op_0 lc_trk_g0_0 (14 10) routing bnl_op_4 lc_trk_g2_4 (14 10) routing rgt_op_4 lc_trk_g2_4 -(14 10) routing sp12_v_t_3 lc_trk_g2_4 (14 10) routing sp4_h_r_36 lc_trk_g2_4 (14 10) routing sp4_h_r_44 lc_trk_g2_4 (14 10) routing sp4_v_b_28 lc_trk_g2_4 (14 10) routing sp4_v_t_25 lc_trk_g2_4 (14 11) routing bnl_op_4 lc_trk_g2_4 (14 11) routing sp12_v_t_19 lc_trk_g2_4 -(14 11) routing sp12_v_t_3 lc_trk_g2_4 (14 11) routing sp4_h_l_17 lc_trk_g2_4 (14 11) routing sp4_h_r_44 lc_trk_g2_4 (14 11) routing sp4_r_v_b_36 lc_trk_g2_4 @@ -425,14 +275,12 @@ (14 12) routing bnl_op_0 lc_trk_g3_0 (14 12) routing rgt_op_0 lc_trk_g3_0 (14 12) routing sp12_v_b_0 lc_trk_g3_0 -(14 12) routing sp4_h_l_21 lc_trk_g3_0 (14 12) routing sp4_h_l_29 lc_trk_g3_0 (14 12) routing sp4_v_t_13 lc_trk_g3_0 (14 12) routing sp4_v_t_21 lc_trk_g3_0 (14 13) routing bnl_op_0 lc_trk_g3_0 (14 13) routing sp12_v_b_0 lc_trk_g3_0 (14 13) routing sp12_v_b_16 lc_trk_g3_0 -(14 13) routing sp4_h_l_13 lc_trk_g3_0 (14 13) routing sp4_h_l_29 lc_trk_g3_0 (14 13) routing sp4_r_v_b_40 lc_trk_g3_0 (14 13) routing sp4_v_t_21 lc_trk_g3_0 @@ -447,7 +295,6 @@ (14 15) routing bnl_op_4 lc_trk_g3_4 (14 15) routing sp12_v_t_19 lc_trk_g3_4 (14 15) routing sp12_v_t_3 lc_trk_g3_4 -(14 15) routing sp4_h_l_17 lc_trk_g3_4 (14 15) routing sp4_h_r_44 lc_trk_g3_4 (14 15) routing sp4_r_v_b_44 lc_trk_g3_4 (14 15) routing sp4_v_t_25 lc_trk_g3_4 @@ -461,7 +308,6 @@ (14 2) routing sp4_v_t_1 lc_trk_g0_4 (14 3) routing bnr_op_4 lc_trk_g0_4 (14 3) routing sp12_h_l_3 lc_trk_g0_4 -(14 3) routing sp12_h_r_20 lc_trk_g0_4 (14 3) routing sp4_h_r_20 lc_trk_g0_4 (14 3) routing sp4_h_r_4 lc_trk_g0_4 (14 3) routing sp4_r_v_b_28 lc_trk_g0_4 @@ -481,24 +327,18 @@ (14 5) routing sp4_h_r_0 lc_trk_g1_0 (14 5) routing sp4_r_v_b_24 lc_trk_g1_0 (14 5) routing sp4_v_b_8 lc_trk_g1_0 -(14 5) routing top_op_0 lc_trk_g1_0 (14 6) routing bnr_op_4 lc_trk_g1_4 (14 6) routing lft_op_4 lc_trk_g1_4 -(14 6) routing sp12_h_l_3 lc_trk_g1_4 (14 6) routing sp4_h_r_12 lc_trk_g1_4 (14 6) routing sp4_h_r_20 lc_trk_g1_4 (14 6) routing sp4_v_b_4 lc_trk_g1_4 (14 6) routing sp4_v_t_1 lc_trk_g1_4 (14 7) routing bnr_op_4 lc_trk_g1_4 -(14 7) routing sp12_h_l_3 lc_trk_g1_4 -(14 7) routing sp12_h_r_20 lc_trk_g1_4 (14 7) routing sp4_h_r_20 lc_trk_g1_4 (14 7) routing sp4_h_r_4 lc_trk_g1_4 (14 7) routing sp4_r_v_b_28 lc_trk_g1_4 (14 7) routing sp4_v_t_1 lc_trk_g1_4 -(14 7) routing top_op_4 lc_trk_g1_4 (14 8) routing bnl_op_0 lc_trk_g2_0 -(14 8) routing rgt_op_0 lc_trk_g2_0 (14 8) routing sp12_v_b_0 lc_trk_g2_0 (14 8) routing sp4_h_l_21 lc_trk_g2_0 (14 8) routing sp4_h_l_29 lc_trk_g2_0 @@ -519,40 +359,31 @@ (15 0) routing sp4_h_r_9 lc_trk_g0_1 (15 0) routing sp4_v_b_17 lc_trk_g0_1 (15 1) routing lft_op_0 lc_trk_g0_0 -(15 1) routing sp12_h_r_0 lc_trk_g0_0 (15 1) routing sp4_h_l_5 lc_trk_g0_0 (15 1) routing sp4_h_r_0 lc_trk_g0_0 (15 1) routing sp4_h_r_8 lc_trk_g0_0 (15 1) routing sp4_v_b_16 lc_trk_g0_0 -(15 1) routing top_op_0 lc_trk_g0_0 -(15 10) routing rgt_op_5 lc_trk_g2_5 (15 10) routing sp12_v_b_5 lc_trk_g2_5 (15 10) routing sp4_h_l_16 lc_trk_g2_5 -(15 10) routing sp4_h_r_37 lc_trk_g2_5 (15 10) routing sp4_h_r_45 lc_trk_g2_5 (15 10) routing sp4_v_b_45 lc_trk_g2_5 (15 10) routing tnl_op_5 lc_trk_g2_5 (15 10) routing tnr_op_5 lc_trk_g2_5 (15 11) routing rgt_op_4 lc_trk_g2_4 -(15 11) routing sp12_v_t_3 lc_trk_g2_4 (15 11) routing sp4_h_l_17 lc_trk_g2_4 (15 11) routing sp4_h_r_36 lc_trk_g2_4 (15 11) routing sp4_h_r_44 lc_trk_g2_4 (15 11) routing sp4_v_t_33 lc_trk_g2_4 (15 11) routing tnl_op_4 lc_trk_g2_4 (15 11) routing tnr_op_4 lc_trk_g2_4 -(15 12) routing rgt_op_1 lc_trk_g3_1 (15 12) routing sp12_v_b_1 lc_trk_g3_1 (15 12) routing sp4_h_l_20 lc_trk_g3_1 (15 12) routing sp4_h_l_28 lc_trk_g3_1 (15 12) routing sp4_h_r_25 lc_trk_g3_1 (15 12) routing sp4_v_b_41 lc_trk_g3_1 (15 12) routing tnl_op_1 lc_trk_g3_1 -(15 12) routing tnr_op_1 lc_trk_g3_1 (15 13) routing rgt_op_0 lc_trk_g3_0 (15 13) routing sp12_v_b_0 lc_trk_g3_0 -(15 13) routing sp4_h_l_13 lc_trk_g3_0 -(15 13) routing sp4_h_l_21 lc_trk_g3_0 (15 13) routing sp4_h_l_29 lc_trk_g3_0 (15 13) routing sp4_v_b_40 lc_trk_g3_0 (15 13) routing tnl_op_0 lc_trk_g3_0 @@ -564,20 +395,16 @@ (15 14) routing sp4_h_r_45 lc_trk_g3_5 (15 14) routing sp4_v_b_45 lc_trk_g3_5 (15 14) routing tnl_op_5 lc_trk_g3_5 -(15 14) routing tnr_op_5 lc_trk_g3_5 (15 15) routing rgt_op_4 lc_trk_g3_4 (15 15) routing sp12_v_t_3 lc_trk_g3_4 -(15 15) routing sp4_h_l_17 lc_trk_g3_4 (15 15) routing sp4_h_r_36 lc_trk_g3_4 (15 15) routing sp4_h_r_44 lc_trk_g3_4 (15 15) routing sp4_v_t_33 lc_trk_g3_4 (15 15) routing tnl_op_4 lc_trk_g3_4 -(15 15) routing tnr_op_4 lc_trk_g3_4 (15 2) routing lft_op_5 lc_trk_g0_5 (15 2) routing sp12_h_r_5 lc_trk_g0_5 (15 2) routing sp4_h_l_8 lc_trk_g0_5 (15 2) routing sp4_h_r_13 lc_trk_g0_5 -(15 2) routing sp4_h_r_5 lc_trk_g0_5 (15 2) routing sp4_v_t_8 lc_trk_g0_5 (15 3) routing lft_op_4 lc_trk_g0_4 (15 3) routing sp12_h_l_3 lc_trk_g0_4 @@ -598,21 +425,16 @@ (15 5) routing sp4_h_r_0 lc_trk_g1_0 (15 5) routing sp4_h_r_8 lc_trk_g1_0 (15 5) routing sp4_v_b_16 lc_trk_g1_0 -(15 5) routing top_op_0 lc_trk_g1_0 (15 6) routing lft_op_5 lc_trk_g1_5 -(15 6) routing sp12_h_r_5 lc_trk_g1_5 (15 6) routing sp4_h_l_8 lc_trk_g1_5 (15 6) routing sp4_h_r_13 lc_trk_g1_5 (15 6) routing sp4_h_r_5 lc_trk_g1_5 (15 6) routing sp4_v_t_8 lc_trk_g1_5 (15 7) routing lft_op_4 lc_trk_g1_4 -(15 7) routing sp12_h_l_3 lc_trk_g1_4 (15 7) routing sp4_h_r_12 lc_trk_g1_4 (15 7) routing sp4_h_r_20 lc_trk_g1_4 (15 7) routing sp4_h_r_4 lc_trk_g1_4 (15 7) routing sp4_v_b_20 lc_trk_g1_4 -(15 7) routing top_op_4 lc_trk_g1_4 -(15 8) routing rgt_op_1 lc_trk_g2_1 (15 8) routing sp12_v_b_1 lc_trk_g2_1 (15 8) routing sp4_h_l_20 lc_trk_g2_1 (15 8) routing sp4_h_l_28 lc_trk_g2_1 @@ -620,7 +442,6 @@ (15 8) routing sp4_v_b_41 lc_trk_g2_1 (15 8) routing tnl_op_1 lc_trk_g2_1 (15 8) routing tnr_op_1 lc_trk_g2_1 -(15 9) routing rgt_op_0 lc_trk_g2_0 (15 9) routing sp12_v_b_0 lc_trk_g2_0 (15 9) routing sp4_h_l_13 lc_trk_g2_0 (15 9) routing sp4_h_l_21 lc_trk_g2_0 @@ -628,15 +449,12 @@ (15 9) routing sp4_v_b_40 lc_trk_g2_0 (15 9) routing tnl_op_0 lc_trk_g2_0 (15 9) routing tnr_op_0 lc_trk_g2_0 -(16 0) routing sp12_h_l_6 lc_trk_g0_1 -(16 0) routing sp12_h_r_17 lc_trk_g0_1 (16 0) routing sp4_h_r_1 lc_trk_g0_1 (16 0) routing sp4_h_r_17 lc_trk_g0_1 (16 0) routing sp4_h_r_9 lc_trk_g0_1 (16 0) routing sp4_v_b_1 lc_trk_g0_1 (16 0) routing sp4_v_b_17 lc_trk_g0_1 (16 0) routing sp4_v_b_9 lc_trk_g0_1 -(16 1) routing sp12_h_r_16 lc_trk_g0_0 (16 1) routing sp12_h_r_8 lc_trk_g0_0 (16 1) routing sp4_h_l_5 lc_trk_g0_0 (16 1) routing sp4_h_r_0 lc_trk_g0_0 @@ -647,7 +465,6 @@ (16 10) routing sp12_v_b_21 lc_trk_g2_5 (16 10) routing sp12_v_t_10 lc_trk_g2_5 (16 10) routing sp4_h_l_16 lc_trk_g2_5 -(16 10) routing sp4_h_r_37 lc_trk_g2_5 (16 10) routing sp4_h_r_45 lc_trk_g2_5 (16 10) routing sp4_v_b_29 lc_trk_g2_5 (16 10) routing sp4_v_b_37 lc_trk_g2_5 @@ -670,8 +487,6 @@ (16 12) routing sp4_v_b_41 lc_trk_g3_1 (16 13) routing sp12_v_b_16 lc_trk_g3_0 (16 13) routing sp12_v_t_7 lc_trk_g3_0 -(16 13) routing sp4_h_l_13 lc_trk_g3_0 -(16 13) routing sp4_h_l_21 lc_trk_g3_0 (16 13) routing sp4_h_l_29 lc_trk_g3_0 (16 13) routing sp4_v_b_40 lc_trk_g3_0 (16 13) routing sp4_v_t_13 lc_trk_g3_0 @@ -686,22 +501,17 @@ (16 14) routing sp4_v_b_45 lc_trk_g3_5 (16 15) routing sp12_v_b_12 lc_trk_g3_4 (16 15) routing sp12_v_t_19 lc_trk_g3_4 -(16 15) routing sp4_h_l_17 lc_trk_g3_4 (16 15) routing sp4_h_r_36 lc_trk_g3_4 (16 15) routing sp4_h_r_44 lc_trk_g3_4 (16 15) routing sp4_v_b_28 lc_trk_g3_4 (16 15) routing sp4_v_t_25 lc_trk_g3_4 (16 15) routing sp4_v_t_33 lc_trk_g3_4 -(16 2) routing sp12_h_l_18 lc_trk_g0_5 (16 2) routing sp12_h_r_13 lc_trk_g0_5 (16 2) routing sp4_h_l_8 lc_trk_g0_5 (16 2) routing sp4_h_r_13 lc_trk_g0_5 -(16 2) routing sp4_h_r_5 lc_trk_g0_5 (16 2) routing sp4_v_b_13 lc_trk_g0_5 (16 2) routing sp4_v_b_5 lc_trk_g0_5 (16 2) routing sp4_v_t_8 lc_trk_g0_5 -(16 3) routing sp12_h_r_12 lc_trk_g0_4 -(16 3) routing sp12_h_r_20 lc_trk_g0_4 (16 3) routing sp4_h_r_12 lc_trk_g0_4 (16 3) routing sp4_h_r_20 lc_trk_g0_4 (16 3) routing sp4_h_r_4 lc_trk_g0_4 @@ -709,7 +519,6 @@ (16 3) routing sp4_v_b_4 lc_trk_g0_4 (16 3) routing sp4_v_t_1 lc_trk_g0_4 (16 4) routing sp12_h_l_6 lc_trk_g1_1 -(16 4) routing sp12_h_r_17 lc_trk_g1_1 (16 4) routing sp4_h_r_1 lc_trk_g1_1 (16 4) routing sp4_h_r_17 lc_trk_g1_1 (16 4) routing sp4_h_r_9 lc_trk_g1_1 @@ -724,7 +533,6 @@ (16 5) routing sp4_v_b_0 lc_trk_g1_0 (16 5) routing sp4_v_b_16 lc_trk_g1_0 (16 5) routing sp4_v_b_8 lc_trk_g1_0 -(16 6) routing sp12_h_l_18 lc_trk_g1_5 (16 6) routing sp12_h_r_13 lc_trk_g1_5 (16 6) routing sp4_h_l_8 lc_trk_g1_5 (16 6) routing sp4_h_r_13 lc_trk_g1_5 @@ -733,7 +541,6 @@ (16 6) routing sp4_v_b_5 lc_trk_g1_5 (16 6) routing sp4_v_t_8 lc_trk_g1_5 (16 7) routing sp12_h_r_12 lc_trk_g1_4 -(16 7) routing sp12_h_r_20 lc_trk_g1_4 (16 7) routing sp4_h_r_12 lc_trk_g1_4 (16 7) routing sp4_h_r_20 lc_trk_g1_4 (16 7) routing sp4_h_r_4 lc_trk_g1_4 @@ -758,9 +565,7 @@ (16 9) routing sp4_v_t_21 lc_trk_g2_0 (17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_l_6 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_17 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1 (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1 @@ -771,8 +576,6 @@ (17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 (17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_16 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_8 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_l_5 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0 @@ -782,14 +585,11 @@ (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_0 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_16 lc_trk_g0_0 (17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_8 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => top_op_0 lc_trk_g0_0 (17 10) Enable bit of Mux _local_links/g2_mux_5 => bnl_op_5 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => rgt_op_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_21 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_5 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_10 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_16 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_37 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_45 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5 (17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5 @@ -802,7 +602,6 @@ (17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_12 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_19 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_3 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_l_17 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_36 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_44 lc_trk_g2_4 @@ -814,7 +613,6 @@ (17 11) Enable bit of Mux _local_links/g2_mux_4 => tnl_op_4 lc_trk_g2_4 (17 11) Enable bit of Mux _local_links/g2_mux_4 => tnr_op_4 lc_trk_g2_4 (17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => rgt_op_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_17 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_9 lc_trk_g3_1 @@ -827,14 +625,11 @@ (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_33 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_41 lc_trk_g3_1 (17 12) Enable bit of Mux _local_links/g3_mux_1 => tnl_op_1 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnr_op_1 lc_trk_g3_1 (17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_16 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_t_7 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_13 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_21 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_29 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0 (17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0 @@ -857,13 +652,11 @@ (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_37 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_45 lc_trk_g3_5 (17 14) Enable bit of Mux _local_links/g3_mux_5 => tnl_op_5 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnr_op_5 lc_trk_g3_5 (17 15) Enable bit of Mux _local_links/g3_mux_4 => bnl_op_4 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => rgt_op_4 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_12 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_19 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_3 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_17 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_36 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_44 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4 @@ -872,16 +665,13 @@ (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_25 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_33 lc_trk_g3_4 (17 15) Enable bit of Mux _local_links/g3_mux_4 => tnl_op_4 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnr_op_4 lc_trk_g3_4 (17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_18 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_13 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_l_8 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_13 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_5 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_r_v_b_29 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_13 lc_trk_g0_5 (17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5 @@ -890,8 +680,6 @@ (17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_3 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_12 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_20 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_12 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_20 lc_trk_g0_4 (17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_4 lc_trk_g0_4 @@ -904,7 +692,6 @@ (17 4) Enable bit of Mux _local_links/g1_mux_1 => lft_op_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_l_6 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_1 lc_trk_g1_1 -(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_17 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_17 lc_trk_g1_1 (17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_9 lc_trk_g1_1 @@ -926,12 +713,8 @@ (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_0 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_16 lc_trk_g1_0 (17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => top_op_0 lc_trk_g1_0 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_18 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_13 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_5 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_l_8 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_13 lc_trk_g1_5 (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5 @@ -942,9 +725,7 @@ (17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_8 lc_trk_g1_5 (17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_3 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_12 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_20 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_12 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_20 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4 @@ -953,9 +734,7 @@ (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_20 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4 (17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_t_1 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => top_op_4 lc_trk_g1_4 (17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_17 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1 @@ -970,7 +749,6 @@ (17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1 (17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1 (17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_16 lc_trk_g2_0 (17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_t_7 lc_trk_g2_0 @@ -993,15 +771,12 @@ (18 0) routing sp4_v_b_9 lc_trk_g0_1 (18 1) routing bnr_op_1 lc_trk_g0_1 (18 1) routing sp12_h_r_1 lc_trk_g0_1 -(18 1) routing sp12_h_r_17 lc_trk_g0_1 (18 1) routing sp4_h_r_1 lc_trk_g0_1 (18 1) routing sp4_h_r_17 lc_trk_g0_1 (18 1) routing sp4_r_v_b_34 lc_trk_g0_1 (18 1) routing sp4_v_b_9 lc_trk_g0_1 (18 10) routing bnl_op_5 lc_trk_g2_5 -(18 10) routing rgt_op_5 lc_trk_g2_5 (18 10) routing sp12_v_b_5 lc_trk_g2_5 -(18 10) routing sp4_h_r_37 lc_trk_g2_5 (18 10) routing sp4_h_r_45 lc_trk_g2_5 (18 10) routing sp4_v_b_29 lc_trk_g2_5 (18 10) routing sp4_v_b_37 lc_trk_g2_5 @@ -1014,7 +789,6 @@ (18 11) routing sp4_v_b_37 lc_trk_g2_5 (18 11) routing tnl_op_5 lc_trk_g2_5 (18 12) routing bnl_op_1 lc_trk_g3_1 -(18 12) routing rgt_op_1 lc_trk_g3_1 (18 12) routing sp12_v_b_1 lc_trk_g3_1 (18 12) routing sp4_h_l_20 lc_trk_g3_1 (18 12) routing sp4_h_l_28 lc_trk_g3_1 @@ -1051,10 +825,8 @@ (18 2) routing sp4_v_b_13 lc_trk_g0_5 (18 2) routing sp4_v_b_5 lc_trk_g0_5 (18 3) routing bnr_op_5 lc_trk_g0_5 -(18 3) routing sp12_h_l_18 lc_trk_g0_5 (18 3) routing sp12_h_r_5 lc_trk_g0_5 (18 3) routing sp4_h_l_8 lc_trk_g0_5 -(18 3) routing sp4_h_r_5 lc_trk_g0_5 (18 3) routing sp4_r_v_b_29 lc_trk_g0_5 (18 3) routing sp4_v_b_13 lc_trk_g0_5 (18 4) routing bnr_op_1 lc_trk_g1_1 @@ -1066,27 +838,20 @@ (18 4) routing sp4_v_b_9 lc_trk_g1_1 (18 5) routing bnr_op_1 lc_trk_g1_1 (18 5) routing sp12_h_r_1 lc_trk_g1_1 -(18 5) routing sp12_h_r_17 lc_trk_g1_1 (18 5) routing sp4_h_r_1 lc_trk_g1_1 (18 5) routing sp4_h_r_17 lc_trk_g1_1 (18 5) routing sp4_r_v_b_25 lc_trk_g1_1 (18 5) routing sp4_v_b_9 lc_trk_g1_1 -(18 6) routing bnr_op_5 lc_trk_g1_5 (18 6) routing lft_op_5 lc_trk_g1_5 -(18 6) routing sp12_h_r_5 lc_trk_g1_5 (18 6) routing sp4_h_l_8 lc_trk_g1_5 (18 6) routing sp4_h_r_13 lc_trk_g1_5 (18 6) routing sp4_v_b_13 lc_trk_g1_5 (18 6) routing sp4_v_b_5 lc_trk_g1_5 -(18 7) routing bnr_op_5 lc_trk_g1_5 -(18 7) routing sp12_h_l_18 lc_trk_g1_5 -(18 7) routing sp12_h_r_5 lc_trk_g1_5 (18 7) routing sp4_h_l_8 lc_trk_g1_5 (18 7) routing sp4_h_r_5 lc_trk_g1_5 (18 7) routing sp4_r_v_b_29 lc_trk_g1_5 (18 7) routing sp4_v_b_13 lc_trk_g1_5 (18 8) routing bnl_op_1 lc_trk_g2_1 -(18 8) routing rgt_op_1 lc_trk_g2_1 (18 8) routing sp12_v_b_1 lc_trk_g2_1 (18 8) routing sp4_h_l_20 lc_trk_g2_1 (18 8) routing sp4_h_l_28 lc_trk_g2_1 @@ -1105,7 +870,6 @@ (19 10) Enable bit of Mux _span_links/cross_mux_vert_11 => sp12_v_b_23 sp4_v_t_10 (19 11) Enable bit of Mux _span_links/cross_mux_vert_10 => sp12_v_b_21 sp4_v_b_22 (19 12) Enable bit of Mux _span_links/cross_mux_horz_1 => sp12_h_r_2 sp4_h_r_13 -(19 13) Enable bit of Mux _span_links/cross_mux_horz_0 => sp12_h_r_0 sp4_h_r_12 (19 14) Enable bit of Mux _span_links/cross_mux_horz_3 => sp12_h_l_5 sp4_h_l_2 (19 15) Enable bit of Mux _span_links/cross_mux_horz_2 => sp12_h_l_3 sp4_h_l_3 (19 2) Enable bit of Mux _span_links/cross_mux_vert_3 => sp12_v_b_7 sp4_v_t_2 @@ -1116,17 +880,11 @@ (19 7) Enable bit of Mux _span_links/cross_mux_vert_6 => sp12_v_t_10 sp4_v_t_7 (19 8) Enable bit of Mux _span_links/cross_mux_vert_9 => sp12_v_t_16 sp4_v_t_8 (19 9) Enable bit of Mux _span_links/cross_mux_vert_8 => sp12_v_b_17 sp4_v_b_20 -(2 0) Enable bit of Mux _span_links/cross_mux_horz_4 => sp12_h_r_8 sp4_h_l_5 (2 10) Enable bit of Mux _span_links/cross_mux_horz_9 => sp12_h_r_18 sp4_h_l_8 -(2 12) Enable bit of Mux _span_links/cross_mux_horz_10 => sp12_h_r_20 sp4_h_r_22 (2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_l_21 sp4_h_l_10 (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_0 wire_bram/ram/WCLK -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_2 wire_bram/ram/WCLK -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_3 wire_bram/ram/WCLK -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_5 wire_bram/ram/WCLK -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_6 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_7 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g0_0 wire_bram/ram/WCLK (2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g1_1 wire_bram/ram/WCLK @@ -1136,19 +894,14 @@ (2 3) routing lc_trk_g1_1 wire_bram/ram/WCLK (2 3) routing lc_trk_g2_0 wire_bram/ram/WCLK (2 3) routing lc_trk_g3_1 wire_bram/ram/WCLK -(2 4) Enable bit of Mux _span_links/cross_mux_horz_6 => sp12_h_r_12 sp4_h_l_7 (2 6) Enable bit of Mux _span_links/cross_mux_horz_7 => sp12_h_l_13 sp4_h_r_19 -(2 8) Enable bit of Mux _span_links/cross_mux_horz_8 => sp12_h_r_16 sp4_h_r_20 (21 0) routing bnr_op_3 lc_trk_g0_3 (21 0) routing lft_op_3 lc_trk_g0_3 -(21 0) routing sp12_h_l_0 lc_trk_g0_3 (21 0) routing sp4_h_r_11 lc_trk_g0_3 (21 0) routing sp4_h_r_19 lc_trk_g0_3 (21 0) routing sp4_v_b_11 lc_trk_g0_3 (21 0) routing sp4_v_b_3 lc_trk_g0_3 (21 1) routing bnr_op_3 lc_trk_g0_3 -(21 1) routing sp12_h_l_0 lc_trk_g0_3 -(21 1) routing sp12_h_l_16 lc_trk_g0_3 (21 1) routing sp4_h_r_19 lc_trk_g0_3 (21 1) routing sp4_h_r_3 lc_trk_g0_3 (21 1) routing sp4_r_v_b_32 lc_trk_g0_3 @@ -1163,11 +916,9 @@ (21 11) routing bnl_op_7 lc_trk_g2_7 (21 11) routing sp12_v_b_23 lc_trk_g2_7 (21 11) routing sp12_v_b_7 lc_trk_g2_7 -(21 11) routing sp4_h_l_18 lc_trk_g2_7 (21 11) routing sp4_h_r_47 lc_trk_g2_7 (21 11) routing sp4_r_v_b_39 lc_trk_g2_7 (21 11) routing sp4_v_t_26 lc_trk_g2_7 -(21 11) routing tnl_op_7 lc_trk_g2_7 (21 12) routing bnl_op_3 lc_trk_g3_3 (21 12) routing rgt_op_3 lc_trk_g3_3 (21 12) routing sp12_v_t_0 lc_trk_g3_3 @@ -1184,30 +935,23 @@ (21 13) routing sp4_v_t_22 lc_trk_g3_3 (21 13) routing tnl_op_3 lc_trk_g3_3 (21 14) routing bnl_op_7 lc_trk_g3_7 -(21 14) routing rgt_op_7 lc_trk_g3_7 (21 14) routing sp12_v_b_7 lc_trk_g3_7 -(21 14) routing sp4_h_l_26 lc_trk_g3_7 (21 14) routing sp4_h_r_47 lc_trk_g3_7 (21 14) routing sp4_v_t_18 lc_trk_g3_7 (21 14) routing sp4_v_t_26 lc_trk_g3_7 (21 15) routing bnl_op_7 lc_trk_g3_7 (21 15) routing sp12_v_b_23 lc_trk_g3_7 (21 15) routing sp12_v_b_7 lc_trk_g3_7 -(21 15) routing sp4_h_l_18 lc_trk_g3_7 (21 15) routing sp4_h_r_47 lc_trk_g3_7 (21 15) routing sp4_r_v_b_47 lc_trk_g3_7 (21 15) routing sp4_v_t_26 lc_trk_g3_7 (21 15) routing tnl_op_7 lc_trk_g3_7 (21 2) routing bnr_op_7 lc_trk_g0_7 (21 2) routing lft_op_7 lc_trk_g0_7 -(21 2) routing sp12_h_l_4 lc_trk_g0_7 (21 2) routing sp4_h_l_10 lc_trk_g0_7 -(21 2) routing sp4_h_l_2 lc_trk_g0_7 (21 2) routing sp4_v_b_7 lc_trk_g0_7 (21 2) routing sp4_v_t_2 lc_trk_g0_7 (21 3) routing bnr_op_7 lc_trk_g0_7 -(21 3) routing sp12_h_l_4 lc_trk_g0_7 -(21 3) routing sp12_h_r_23 lc_trk_g0_7 (21 3) routing sp4_h_l_10 lc_trk_g0_7 (21 3) routing sp4_h_r_7 lc_trk_g0_7 (21 3) routing sp4_r_v_b_31 lc_trk_g0_7 @@ -1221,27 +965,20 @@ (21 4) routing sp4_v_b_3 lc_trk_g1_3 (21 5) routing bnr_op_3 lc_trk_g1_3 (21 5) routing sp12_h_l_0 lc_trk_g1_3 -(21 5) routing sp12_h_l_16 lc_trk_g1_3 (21 5) routing sp4_h_r_19 lc_trk_g1_3 (21 5) routing sp4_h_r_3 lc_trk_g1_3 (21 5) routing sp4_r_v_b_27 lc_trk_g1_3 (21 5) routing sp4_v_b_11 lc_trk_g1_3 -(21 6) routing bnr_op_7 lc_trk_g1_7 (21 6) routing lft_op_7 lc_trk_g1_7 -(21 6) routing sp12_h_l_4 lc_trk_g1_7 (21 6) routing sp4_h_l_10 lc_trk_g1_7 (21 6) routing sp4_h_l_2 lc_trk_g1_7 (21 6) routing sp4_v_b_7 lc_trk_g1_7 (21 6) routing sp4_v_t_2 lc_trk_g1_7 -(21 7) routing bnr_op_7 lc_trk_g1_7 -(21 7) routing sp12_h_l_4 lc_trk_g1_7 -(21 7) routing sp12_h_r_23 lc_trk_g1_7 (21 7) routing sp4_h_l_10 lc_trk_g1_7 (21 7) routing sp4_h_r_7 lc_trk_g1_7 (21 7) routing sp4_r_v_b_31 lc_trk_g1_7 (21 7) routing sp4_v_t_2 lc_trk_g1_7 (21 8) routing bnl_op_3 lc_trk_g2_3 -(21 8) routing rgt_op_3 lc_trk_g2_3 (21 8) routing sp12_v_t_0 lc_trk_g2_3 (21 8) routing sp4_h_l_30 lc_trk_g2_3 (21 8) routing sp4_h_r_35 lc_trk_g2_3 @@ -1251,15 +988,11 @@ (21 9) routing sp12_v_t_0 lc_trk_g2_3 (21 9) routing sp12_v_t_16 lc_trk_g2_3 (21 9) routing sp4_h_l_30 lc_trk_g2_3 -(21 9) routing sp4_h_r_27 lc_trk_g2_3 (21 9) routing sp4_r_v_b_35 lc_trk_g2_3 (21 9) routing sp4_v_t_22 lc_trk_g2_3 (21 9) routing tnl_op_3 lc_trk_g2_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => bnr_op_3 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => lft_op_3 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_0 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_16 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_19 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3 @@ -1268,7 +1001,6 @@ (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_11 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_19 lc_trk_g0_3 (22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_10 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_18 lc_trk_g0_2 @@ -1281,13 +1013,11 @@ (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_10 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_2 lc_trk_g0_2 (22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_t_7 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => top_op_2 lc_trk_g0_2 (22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_23 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_18 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_26 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_47 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7 @@ -1295,14 +1025,12 @@ (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_47 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_18 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_26 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7 (22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7 (22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_14 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_21 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_27 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_30 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_46 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_14 lc_trk_g2_6 @@ -1310,7 +1038,6 @@ (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_30 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_38 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_46 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnl_op_6 lc_trk_g2_6 (22 11) Enable bit of Mux _local_links/g2_mux_6 => tnr_op_6 lc_trk_g2_6 (22 12) Enable bit of Mux _local_links/g3_mux_3 => bnl_op_3 lc_trk_g3_3 (22 12) Enable bit of Mux _local_links/g3_mux_3 => rgt_op_3 lc_trk_g3_3 @@ -1340,15 +1067,11 @@ (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_b_26 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_23 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_31 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnl_op_2 lc_trk_g3_2 (22 13) Enable bit of Mux _local_links/g3_mux_2 => tnr_op_2 lc_trk_g3_2 (22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => rgt_op_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_23 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_7 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_18 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_26 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_47 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7 (22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7 @@ -1375,11 +1098,7 @@ (22 2) Enable bit of Mux _local_links/g0_mux_7 => bnr_op_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_12 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_4 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_23 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_10 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_2 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_r_v_b_31 lc_trk_g0_7 (22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7 @@ -1389,7 +1108,6 @@ (22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_13 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_21 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6 (22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_22 lc_trk_g0_6 @@ -1402,8 +1120,6 @@ (22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_0 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_16 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_11 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_11 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_19 lc_trk_g1_3 (22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_3 lc_trk_g1_3 @@ -1415,22 +1131,15 @@ (22 5) Enable bit of Mux _local_links/g1_mux_2 => bnr_op_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => lft_op_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_10 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_18 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_l_7 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_10 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2 (22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_t_7 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => top_op_2 lc_trk_g1_2 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_12 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_4 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_23 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_10 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_2 lc_trk_g1_7 (22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7 @@ -1446,20 +1155,16 @@ (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_22 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_14 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_22 lc_trk_g1_6 (22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => top_op_6 lc_trk_g1_6 (22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_11 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_0 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_16 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_30 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_27 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_35 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3 (22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3 @@ -1473,7 +1178,6 @@ (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_2 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_17 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_9 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_l_15 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_34 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_42 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_10 lc_trk_g2_2 @@ -1483,8 +1187,6 @@ (22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_31 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2 (22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2 -(23 0) routing sp12_h_l_16 lc_trk_g0_3 -(23 0) routing sp12_h_r_11 lc_trk_g0_3 (23 0) routing sp4_h_r_11 lc_trk_g0_3 (23 0) routing sp4_h_r_19 lc_trk_g0_3 (23 0) routing sp4_h_r_3 lc_trk_g0_3 @@ -1501,7 +1203,6 @@ (23 1) routing sp4_v_t_7 lc_trk_g0_2 (23 10) routing sp12_v_b_23 lc_trk_g2_7 (23 10) routing sp12_v_t_12 lc_trk_g2_7 -(23 10) routing sp4_h_l_18 lc_trk_g2_7 (23 10) routing sp4_h_l_26 lc_trk_g2_7 (23 10) routing sp4_h_r_47 lc_trk_g2_7 (23 10) routing sp4_v_b_47 lc_trk_g2_7 @@ -1509,7 +1210,6 @@ (23 10) routing sp4_v_t_26 lc_trk_g2_7 (23 11) routing sp12_v_b_14 lc_trk_g2_6 (23 11) routing sp12_v_t_21 lc_trk_g2_6 -(23 11) routing sp4_h_l_27 lc_trk_g2_6 (23 11) routing sp4_h_r_30 lc_trk_g2_6 (23 11) routing sp4_h_r_46 lc_trk_g2_6 (23 11) routing sp4_v_b_30 lc_trk_g2_6 @@ -1533,8 +1233,6 @@ (23 13) routing sp4_v_t_31 lc_trk_g3_2 (23 14) routing sp12_v_b_23 lc_trk_g3_7 (23 14) routing sp12_v_t_12 lc_trk_g3_7 -(23 14) routing sp4_h_l_18 lc_trk_g3_7 -(23 14) routing sp4_h_l_26 lc_trk_g3_7 (23 14) routing sp4_h_r_47 lc_trk_g3_7 (23 14) routing sp4_v_b_47 lc_trk_g3_7 (23 14) routing sp4_v_t_18 lc_trk_g3_7 @@ -1547,24 +1245,18 @@ (23 15) routing sp4_v_b_30 lc_trk_g3_6 (23 15) routing sp4_v_b_38 lc_trk_g3_6 (23 15) routing sp4_v_b_46 lc_trk_g3_6 -(23 2) routing sp12_h_l_12 lc_trk_g0_7 -(23 2) routing sp12_h_r_23 lc_trk_g0_7 (23 2) routing sp4_h_l_10 lc_trk_g0_7 -(23 2) routing sp4_h_l_2 lc_trk_g0_7 (23 2) routing sp4_h_r_7 lc_trk_g0_7 (23 2) routing sp4_v_b_7 lc_trk_g0_7 (23 2) routing sp4_v_t_10 lc_trk_g0_7 (23 2) routing sp4_v_t_2 lc_trk_g0_7 (23 3) routing sp12_h_l_13 lc_trk_g0_6 -(23 3) routing sp12_h_l_21 lc_trk_g0_6 (23 3) routing sp4_h_l_3 lc_trk_g0_6 (23 3) routing sp4_h_r_22 lc_trk_g0_6 (23 3) routing sp4_h_r_6 lc_trk_g0_6 (23 3) routing sp4_v_b_14 lc_trk_g0_6 (23 3) routing sp4_v_b_22 lc_trk_g0_6 (23 3) routing sp4_v_b_6 lc_trk_g0_6 -(23 4) routing sp12_h_l_16 lc_trk_g1_3 -(23 4) routing sp12_h_r_11 lc_trk_g1_3 (23 4) routing sp4_h_r_11 lc_trk_g1_3 (23 4) routing sp4_h_r_19 lc_trk_g1_3 (23 4) routing sp4_h_r_3 lc_trk_g1_3 @@ -1572,15 +1264,11 @@ (23 4) routing sp4_v_b_19 lc_trk_g1_3 (23 4) routing sp4_v_b_3 lc_trk_g1_3 (23 5) routing sp12_h_r_10 lc_trk_g1_2 -(23 5) routing sp12_h_r_18 lc_trk_g1_2 (23 5) routing sp4_h_l_7 lc_trk_g1_2 (23 5) routing sp4_h_r_10 lc_trk_g1_2 -(23 5) routing sp4_h_r_2 lc_trk_g1_2 (23 5) routing sp4_v_b_10 lc_trk_g1_2 (23 5) routing sp4_v_b_2 lc_trk_g1_2 (23 5) routing sp4_v_t_7 lc_trk_g1_2 -(23 6) routing sp12_h_l_12 lc_trk_g1_7 -(23 6) routing sp12_h_r_23 lc_trk_g1_7 (23 6) routing sp4_h_l_10 lc_trk_g1_7 (23 6) routing sp4_h_l_2 lc_trk_g1_7 (23 6) routing sp4_h_r_7 lc_trk_g1_7 @@ -1591,28 +1279,24 @@ (23 7) routing sp12_h_l_21 lc_trk_g1_6 (23 7) routing sp4_h_l_3 lc_trk_g1_6 (23 7) routing sp4_h_r_22 lc_trk_g1_6 -(23 7) routing sp4_h_r_6 lc_trk_g1_6 (23 7) routing sp4_v_b_14 lc_trk_g1_6 (23 7) routing sp4_v_b_22 lc_trk_g1_6 (23 7) routing sp4_v_b_6 lc_trk_g1_6 (23 8) routing sp12_v_b_11 lc_trk_g2_3 (23 8) routing sp12_v_t_16 lc_trk_g2_3 (23 8) routing sp4_h_l_30 lc_trk_g2_3 -(23 8) routing sp4_h_r_27 lc_trk_g2_3 (23 8) routing sp4_h_r_35 lc_trk_g2_3 (23 8) routing sp4_v_t_14 lc_trk_g2_3 (23 8) routing sp4_v_t_22 lc_trk_g2_3 (23 8) routing sp4_v_t_30 lc_trk_g2_3 (23 9) routing sp12_v_t_17 lc_trk_g2_2 (23 9) routing sp12_v_t_9 lc_trk_g2_2 -(23 9) routing sp4_h_l_15 lc_trk_g2_2 (23 9) routing sp4_h_r_34 lc_trk_g2_2 (23 9) routing sp4_h_r_42 lc_trk_g2_2 (23 9) routing sp4_v_b_26 lc_trk_g2_2 (23 9) routing sp4_v_t_23 lc_trk_g2_2 (23 9) routing sp4_v_t_31 lc_trk_g2_2 (24 0) routing lft_op_3 lc_trk_g0_3 -(24 0) routing sp12_h_l_0 lc_trk_g0_3 (24 0) routing sp4_h_r_11 lc_trk_g0_3 (24 0) routing sp4_h_r_19 lc_trk_g0_3 (24 0) routing sp4_h_r_3 lc_trk_g0_3 @@ -1623,22 +1307,17 @@ (24 1) routing sp4_h_r_10 lc_trk_g0_2 (24 1) routing sp4_h_r_2 lc_trk_g0_2 (24 1) routing sp4_v_t_7 lc_trk_g0_2 -(24 1) routing top_op_2 lc_trk_g0_2 (24 10) routing rgt_op_7 lc_trk_g2_7 (24 10) routing sp12_v_b_7 lc_trk_g2_7 -(24 10) routing sp4_h_l_18 lc_trk_g2_7 (24 10) routing sp4_h_l_26 lc_trk_g2_7 (24 10) routing sp4_h_r_47 lc_trk_g2_7 (24 10) routing sp4_v_b_47 lc_trk_g2_7 -(24 10) routing tnl_op_7 lc_trk_g2_7 (24 10) routing tnr_op_7 lc_trk_g2_7 (24 11) routing rgt_op_6 lc_trk_g2_6 (24 11) routing sp12_v_b_6 lc_trk_g2_6 -(24 11) routing sp4_h_l_27 lc_trk_g2_6 (24 11) routing sp4_h_r_30 lc_trk_g2_6 (24 11) routing sp4_h_r_46 lc_trk_g2_6 (24 11) routing sp4_v_b_46 lc_trk_g2_6 -(24 11) routing tnl_op_6 lc_trk_g2_6 (24 11) routing tnr_op_6 lc_trk_g2_6 (24 12) routing rgt_op_3 lc_trk_g3_3 (24 12) routing sp12_v_t_0 lc_trk_g3_3 @@ -1654,12 +1333,8 @@ (24 13) routing sp4_h_r_34 lc_trk_g3_2 (24 13) routing sp4_h_r_42 lc_trk_g3_2 (24 13) routing sp4_v_t_31 lc_trk_g3_2 -(24 13) routing tnl_op_2 lc_trk_g3_2 (24 13) routing tnr_op_2 lc_trk_g3_2 -(24 14) routing rgt_op_7 lc_trk_g3_7 (24 14) routing sp12_v_b_7 lc_trk_g3_7 -(24 14) routing sp4_h_l_18 lc_trk_g3_7 -(24 14) routing sp4_h_l_26 lc_trk_g3_7 (24 14) routing sp4_h_r_47 lc_trk_g3_7 (24 14) routing sp4_v_b_47 lc_trk_g3_7 (24 14) routing tnl_op_7 lc_trk_g3_7 @@ -1673,9 +1348,7 @@ (24 15) routing tnl_op_6 lc_trk_g3_6 (24 15) routing tnr_op_6 lc_trk_g3_6 (24 2) routing lft_op_7 lc_trk_g0_7 -(24 2) routing sp12_h_l_4 lc_trk_g0_7 (24 2) routing sp4_h_l_10 lc_trk_g0_7 -(24 2) routing sp4_h_l_2 lc_trk_g0_7 (24 2) routing sp4_h_r_7 lc_trk_g0_7 (24 2) routing sp4_v_t_10 lc_trk_g0_7 (24 3) routing lft_op_6 lc_trk_g0_6 @@ -1695,11 +1368,8 @@ (24 5) routing sp12_h_r_2 lc_trk_g1_2 (24 5) routing sp4_h_l_7 lc_trk_g1_2 (24 5) routing sp4_h_r_10 lc_trk_g1_2 -(24 5) routing sp4_h_r_2 lc_trk_g1_2 (24 5) routing sp4_v_t_7 lc_trk_g1_2 -(24 5) routing top_op_2 lc_trk_g1_2 (24 6) routing lft_op_7 lc_trk_g1_7 -(24 6) routing sp12_h_l_4 lc_trk_g1_7 (24 6) routing sp4_h_l_10 lc_trk_g1_7 (24 6) routing sp4_h_l_2 lc_trk_g1_7 (24 6) routing sp4_h_r_7 lc_trk_g1_7 @@ -1708,44 +1378,35 @@ (24 7) routing sp12_h_l_5 lc_trk_g1_6 (24 7) routing sp4_h_l_3 lc_trk_g1_6 (24 7) routing sp4_h_r_22 lc_trk_g1_6 -(24 7) routing sp4_h_r_6 lc_trk_g1_6 (24 7) routing sp4_v_b_22 lc_trk_g1_6 -(24 7) routing top_op_6 lc_trk_g1_6 -(24 8) routing rgt_op_3 lc_trk_g2_3 (24 8) routing sp12_v_t_0 lc_trk_g2_3 (24 8) routing sp4_h_l_30 lc_trk_g2_3 -(24 8) routing sp4_h_r_27 lc_trk_g2_3 (24 8) routing sp4_h_r_35 lc_trk_g2_3 (24 8) routing sp4_v_t_30 lc_trk_g2_3 (24 8) routing tnl_op_3 lc_trk_g2_3 (24 8) routing tnr_op_3 lc_trk_g2_3 (24 9) routing rgt_op_2 lc_trk_g2_2 (24 9) routing sp12_v_b_2 lc_trk_g2_2 -(24 9) routing sp4_h_l_15 lc_trk_g2_2 (24 9) routing sp4_h_r_34 lc_trk_g2_2 (24 9) routing sp4_h_r_42 lc_trk_g2_2 (24 9) routing sp4_v_t_31 lc_trk_g2_2 (24 9) routing tnl_op_2 lc_trk_g2_2 (24 9) routing tnr_op_2 lc_trk_g2_2 -(25 0) routing bnr_op_2 lc_trk_g0_2 (25 0) routing lft_op_2 lc_trk_g0_2 (25 0) routing sp12_h_r_2 lc_trk_g0_2 (25 0) routing sp4_h_l_7 lc_trk_g0_2 (25 0) routing sp4_h_r_10 lc_trk_g0_2 (25 0) routing sp4_v_b_10 lc_trk_g0_2 (25 0) routing sp4_v_b_2 lc_trk_g0_2 -(25 1) routing bnr_op_2 lc_trk_g0_2 (25 1) routing sp12_h_r_18 lc_trk_g0_2 (25 1) routing sp12_h_r_2 lc_trk_g0_2 (25 1) routing sp4_h_l_7 lc_trk_g0_2 (25 1) routing sp4_h_r_2 lc_trk_g0_2 (25 1) routing sp4_r_v_b_33 lc_trk_g0_2 (25 1) routing sp4_v_b_10 lc_trk_g0_2 -(25 1) routing top_op_2 lc_trk_g0_2 (25 10) routing bnl_op_6 lc_trk_g2_6 (25 10) routing rgt_op_6 lc_trk_g2_6 (25 10) routing sp12_v_b_6 lc_trk_g2_6 -(25 10) routing sp4_h_l_27 lc_trk_g2_6 (25 10) routing sp4_h_r_46 lc_trk_g2_6 (25 10) routing sp4_v_b_30 lc_trk_g2_6 (25 10) routing sp4_v_b_38 lc_trk_g2_6 @@ -1756,7 +1417,6 @@ (25 11) routing sp4_h_r_46 lc_trk_g2_6 (25 11) routing sp4_r_v_b_38 lc_trk_g2_6 (25 11) routing sp4_v_b_38 lc_trk_g2_6 -(25 11) routing tnl_op_6 lc_trk_g2_6 (25 12) routing bnl_op_2 lc_trk_g3_2 (25 12) routing rgt_op_2 lc_trk_g3_2 (25 12) routing sp12_v_b_2 lc_trk_g3_2 @@ -1771,7 +1431,6 @@ (25 13) routing sp4_h_r_42 lc_trk_g3_2 (25 13) routing sp4_r_v_b_42 lc_trk_g3_2 (25 13) routing sp4_v_t_23 lc_trk_g3_2 -(25 13) routing tnl_op_2 lc_trk_g3_2 (25 14) routing bnl_op_6 lc_trk_g3_6 (25 14) routing rgt_op_6 lc_trk_g3_6 (25 14) routing sp12_v_b_6 lc_trk_g3_6 @@ -1795,7 +1454,6 @@ (25 2) routing sp4_v_b_14 lc_trk_g0_6 (25 2) routing sp4_v_b_6 lc_trk_g0_6 (25 3) routing bnr_op_6 lc_trk_g0_6 -(25 3) routing sp12_h_l_21 lc_trk_g0_6 (25 3) routing sp12_h_l_5 lc_trk_g0_6 (25 3) routing sp4_h_r_22 lc_trk_g0_6 (25 3) routing sp4_h_r_6 lc_trk_g0_6 @@ -1810,13 +1468,10 @@ (25 4) routing sp4_v_b_10 lc_trk_g1_2 (25 4) routing sp4_v_b_2 lc_trk_g1_2 (25 5) routing bnr_op_2 lc_trk_g1_2 -(25 5) routing sp12_h_r_18 lc_trk_g1_2 (25 5) routing sp12_h_r_2 lc_trk_g1_2 (25 5) routing sp4_h_l_7 lc_trk_g1_2 -(25 5) routing sp4_h_r_2 lc_trk_g1_2 (25 5) routing sp4_r_v_b_26 lc_trk_g1_2 (25 5) routing sp4_v_b_10 lc_trk_g1_2 -(25 5) routing top_op_2 lc_trk_g1_2 (25 6) routing bnr_op_6 lc_trk_g1_6 (25 6) routing lft_op_6 lc_trk_g1_6 (25 6) routing sp12_h_l_5 lc_trk_g1_6 @@ -1828,10 +1483,8 @@ (25 7) routing sp12_h_l_21 lc_trk_g1_6 (25 7) routing sp12_h_l_5 lc_trk_g1_6 (25 7) routing sp4_h_r_22 lc_trk_g1_6 -(25 7) routing sp4_h_r_6 lc_trk_g1_6 (25 7) routing sp4_r_v_b_30 lc_trk_g1_6 (25 7) routing sp4_v_b_14 lc_trk_g1_6 -(25 7) routing top_op_6 lc_trk_g1_6 (25 8) routing bnl_op_2 lc_trk_g2_2 (25 8) routing rgt_op_2 lc_trk_g2_2 (25 8) routing sp12_v_b_2 lc_trk_g2_2 @@ -1842,7 +1495,6 @@ (25 9) routing bnl_op_2 lc_trk_g2_2 (25 9) routing sp12_v_b_2 lc_trk_g2_2 (25 9) routing sp12_v_t_17 lc_trk_g2_2 -(25 9) routing sp4_h_l_15 lc_trk_g2_2 (25 9) routing sp4_h_r_42 lc_trk_g2_2 (25 9) routing sp4_r_v_b_34 lc_trk_g2_2 (25 9) routing sp4_v_t_23 lc_trk_g2_2 @@ -1980,7 +1632,6 @@ (27 0) routing lc_trk_g1_4 wire_bram/ram/WDATA_7 (27 0) routing lc_trk_g1_6 wire_bram/ram/WDATA_7 (27 0) routing lc_trk_g3_0 wire_bram/ram/WDATA_7 -(27 0) routing lc_trk_g3_2 wire_bram/ram/WDATA_7 (27 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_7 (27 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_7 (27 1) routing lc_trk_g1_1 input0_0 @@ -1993,7 +1644,6 @@ (27 1) routing lc_trk_g3_7 input0_0 (27 10) routing lc_trk_g1_1 wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g1_3 wire_bram/ram/WDATA_2 -(27 10) routing lc_trk_g1_5 wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g1_7 wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g3_1 wire_bram/ram/WDATA_2 (27 10) routing lc_trk_g3_3 wire_bram/ram/WDATA_2 @@ -2024,7 +1674,6 @@ (27 13) routing lc_trk_g3_5 input0_6 (27 13) routing lc_trk_g3_7 input0_6 (27 14) routing lc_trk_g1_1 wire_bram/ram/WDATA_0 -(27 14) routing lc_trk_g1_3 wire_bram/ram/WDATA_0 (27 14) routing lc_trk_g1_5 wire_bram/ram/WDATA_0 (27 14) routing lc_trk_g1_7 wire_bram/ram/WDATA_0 (27 14) routing lc_trk_g3_1 wire_bram/ram/WDATA_0 @@ -2039,7 +1688,6 @@ (27 15) routing lc_trk_g3_2 input0_7 (27 15) routing lc_trk_g3_4 input0_7 (27 15) routing lc_trk_g3_6 input0_7 -(27 2) routing lc_trk_g1_1 wire_bram/ram/WDATA_6 (27 2) routing lc_trk_g1_3 wire_bram/ram/WDATA_6 (27 2) routing lc_trk_g1_5 wire_bram/ram/WDATA_6 (27 2) routing lc_trk_g1_7 wire_bram/ram/WDATA_6 @@ -2071,10 +1719,8 @@ (27 5) routing lc_trk_g3_3 input0_2 (27 5) routing lc_trk_g3_5 input0_2 (27 5) routing lc_trk_g3_7 input0_2 -(27 6) routing lc_trk_g1_1 wire_bram/ram/WDATA_4 (27 6) routing lc_trk_g1_3 wire_bram/ram/WDATA_4 (27 6) routing lc_trk_g1_5 wire_bram/ram/WDATA_4 -(27 6) routing lc_trk_g1_7 wire_bram/ram/WDATA_4 (27 6) routing lc_trk_g3_1 wire_bram/ram/WDATA_4 (27 6) routing lc_trk_g3_3 wire_bram/ram/WDATA_4 (27 6) routing lc_trk_g3_5 wire_bram/ram/WDATA_4 @@ -2105,10 +1751,8 @@ (27 9) routing lc_trk_g3_7 input0_4 (28 0) routing lc_trk_g2_1 wire_bram/ram/WDATA_7 (28 0) routing lc_trk_g2_3 wire_bram/ram/WDATA_7 -(28 0) routing lc_trk_g2_5 wire_bram/ram/WDATA_7 (28 0) routing lc_trk_g2_7 wire_bram/ram/WDATA_7 (28 0) routing lc_trk_g3_0 wire_bram/ram/WDATA_7 -(28 0) routing lc_trk_g3_2 wire_bram/ram/WDATA_7 (28 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_7 (28 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_7 (28 1) routing lc_trk_g2_0 input0_0 @@ -2199,7 +1843,6 @@ (28 5) routing lc_trk_g3_3 input0_2 (28 5) routing lc_trk_g3_5 input0_2 (28 5) routing lc_trk_g3_7 input0_2 -(28 6) routing lc_trk_g2_0 wire_bram/ram/WDATA_4 (28 6) routing lc_trk_g2_2 wire_bram/ram/WDATA_4 (28 6) routing lc_trk_g2_4 wire_bram/ram/WDATA_4 (28 6) routing lc_trk_g2_6 wire_bram/ram/WDATA_4 @@ -2233,7 +1876,6 @@ (28 9) routing lc_trk_g3_7 input0_4 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_1 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_3 wire_bram/ram/WDATA_7 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_5 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_7 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_0 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_2 wire_bram/ram/WDATA_7 @@ -2241,10 +1883,8 @@ (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_6 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_1 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_3 wire_bram/ram/WDATA_7 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_5 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_7 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_0 wire_bram/ram/WDATA_7 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_2 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_4 wire_bram/ram/WDATA_7 (29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_6 wire_bram/ram/WDATA_7 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_0 input0_0 @@ -2263,13 +1903,11 @@ (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_3 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_5 input0_0 (29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_7 input0_0 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_0 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_2 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_4 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_6 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_1 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_3 wire_bram/ram/WDATA_2 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_5 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_7 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_0 wire_bram/ram/WDATA_2 (29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_2 wire_bram/ram/WDATA_2 @@ -2332,7 +1970,6 @@ (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_4 wire_bram/ram/WDATA_0 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_6 wire_bram/ram/WDATA_0 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_1 wire_bram/ram/WDATA_0 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_3 wire_bram/ram/WDATA_0 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_5 wire_bram/ram/WDATA_0 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_7 wire_bram/ram/WDATA_0 (29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_0 wire_bram/ram/WDATA_0 @@ -2363,7 +2000,6 @@ (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_2 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_4 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_6 wire_bram/ram/WDATA_6 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_1 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_3 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_5 wire_bram/ram/WDATA_6 (29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_7 wire_bram/ram/WDATA_6 @@ -2427,11 +2063,8 @@ (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_2 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_4 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_6 wire_bram/ram/WDATA_4 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_1 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_3 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_5 wire_bram/ram/WDATA_4 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_7 wire_bram/ram/WDATA_4 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_0 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_2 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_4 wire_bram/ram/WDATA_4 (29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_6 wire_bram/ram/WDATA_4 @@ -2455,7 +2088,6 @@ (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_2 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_4 input0_3 (29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_6 input0_3 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_1 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_3 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_5 wire_bram/ram/WDATA_3 (29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_7 wire_bram/ram/WDATA_3 @@ -2491,9 +2123,7 @@ (3 0) routing sp12_v_t_23 sp12_v_b_0 (3 1) routing sp12_h_l_23 sp12_v_b_0 (3 1) routing sp12_h_r_0 sp12_v_b_0 -(3 10) routing sp12_h_r_1 sp12_h_l_22 (3 10) routing sp12_v_t_22 sp12_h_l_22 -(3 11) routing sp12_h_r_1 sp12_h_l_22 (3 11) routing sp12_v_b_1 sp12_h_l_22 (3 12) routing sp12_v_b_1 sp12_h_r_1 (3 12) routing sp12_v_t_22 sp12_h_r_1 @@ -2519,11 +2149,9 @@ (3 8) routing sp12_v_t_22 sp12_v_b_1 (3 9) routing sp12_h_l_22 sp12_v_b_1 (3 9) routing sp12_h_r_1 sp12_v_b_1 -(30 0) routing lc_trk_g0_5 wire_bram/ram/WDATA_7 (30 0) routing lc_trk_g0_7 wire_bram/ram/WDATA_7 (30 0) routing lc_trk_g1_4 wire_bram/ram/WDATA_7 (30 0) routing lc_trk_g1_6 wire_bram/ram/WDATA_7 -(30 0) routing lc_trk_g2_5 wire_bram/ram/WDATA_7 (30 0) routing lc_trk_g2_7 wire_bram/ram/WDATA_7 (30 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_7 (30 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_7 @@ -2533,11 +2161,9 @@ (30 1) routing lc_trk_g1_6 wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g2_3 wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g2_7 wire_bram/ram/WDATA_7 -(30 1) routing lc_trk_g3_2 wire_bram/ram/WDATA_7 (30 1) routing lc_trk_g3_6 wire_bram/ram/WDATA_7 (30 10) routing lc_trk_g0_4 wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g0_6 wire_bram/ram/WDATA_2 -(30 10) routing lc_trk_g1_5 wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g1_7 wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g2_4 wire_bram/ram/WDATA_2 (30 10) routing lc_trk_g2_6 wire_bram/ram/WDATA_2 @@ -2577,7 +2203,6 @@ (30 14) routing lc_trk_g3_7 wire_bram/ram/WDATA_0 (30 15) routing lc_trk_g0_2 wire_bram/ram/WDATA_0 (30 15) routing lc_trk_g0_6 wire_bram/ram/WDATA_0 -(30 15) routing lc_trk_g1_3 wire_bram/ram/WDATA_0 (30 15) routing lc_trk_g1_7 wire_bram/ram/WDATA_0 (30 15) routing lc_trk_g2_2 wire_bram/ram/WDATA_0 (30 15) routing lc_trk_g2_6 wire_bram/ram/WDATA_0 @@ -2618,7 +2243,6 @@ (30 6) routing lc_trk_g0_4 wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g0_6 wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g1_5 wire_bram/ram/WDATA_4 -(30 6) routing lc_trk_g1_7 wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g2_4 wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g2_6 wire_bram/ram/WDATA_4 (30 6) routing lc_trk_g3_5 wire_bram/ram/WDATA_4 @@ -2626,7 +2250,6 @@ (30 7) routing lc_trk_g0_2 wire_bram/ram/WDATA_4 (30 7) routing lc_trk_g0_6 wire_bram/ram/WDATA_4 (30 7) routing lc_trk_g1_3 wire_bram/ram/WDATA_4 -(30 7) routing lc_trk_g1_7 wire_bram/ram/WDATA_4 (30 7) routing lc_trk_g2_2 wire_bram/ram/WDATA_4 (30 7) routing lc_trk_g2_6 wire_bram/ram/WDATA_4 (30 7) routing lc_trk_g3_3 wire_bram/ram/WDATA_4 @@ -2648,188 +2271,111 @@ (30 9) routing lc_trk_g3_2 wire_bram/ram/WDATA_3 (30 9) routing lc_trk_g3_6 wire_bram/ram/WDATA_3 (31 0) routing lc_trk_g0_5 wire_bram/ram/MASK_7 -(31 0) routing lc_trk_g0_7 wire_bram/ram/MASK_7 -(31 0) routing lc_trk_g1_4 wire_bram/ram/MASK_7 -(31 0) routing lc_trk_g1_6 wire_bram/ram/MASK_7 (31 0) routing lc_trk_g2_5 wire_bram/ram/MASK_7 (31 0) routing lc_trk_g2_7 wire_bram/ram/MASK_7 -(31 0) routing lc_trk_g3_4 wire_bram/ram/MASK_7 -(31 0) routing lc_trk_g3_6 wire_bram/ram/MASK_7 -(31 1) routing lc_trk_g0_3 wire_bram/ram/MASK_7 -(31 1) routing lc_trk_g0_7 wire_bram/ram/MASK_7 -(31 1) routing lc_trk_g1_2 wire_bram/ram/MASK_7 -(31 1) routing lc_trk_g1_6 wire_bram/ram/MASK_7 -(31 1) routing lc_trk_g2_3 wire_bram/ram/MASK_7 (31 1) routing lc_trk_g2_7 wire_bram/ram/MASK_7 (31 1) routing lc_trk_g3_2 wire_bram/ram/MASK_7 -(31 1) routing lc_trk_g3_6 wire_bram/ram/MASK_7 (31 10) routing lc_trk_g0_4 wire_bram/ram/MASK_2 -(31 10) routing lc_trk_g0_6 wire_bram/ram/MASK_2 (31 10) routing lc_trk_g1_5 wire_bram/ram/MASK_2 -(31 10) routing lc_trk_g1_7 wire_bram/ram/MASK_2 (31 10) routing lc_trk_g2_4 wire_bram/ram/MASK_2 -(31 10) routing lc_trk_g2_6 wire_bram/ram/MASK_2 (31 10) routing lc_trk_g3_5 wire_bram/ram/MASK_2 (31 10) routing lc_trk_g3_7 wire_bram/ram/MASK_2 (31 11) routing lc_trk_g0_2 wire_bram/ram/MASK_2 -(31 11) routing lc_trk_g0_6 wire_bram/ram/MASK_2 (31 11) routing lc_trk_g1_3 wire_bram/ram/MASK_2 -(31 11) routing lc_trk_g1_7 wire_bram/ram/MASK_2 -(31 11) routing lc_trk_g2_2 wire_bram/ram/MASK_2 -(31 11) routing lc_trk_g2_6 wire_bram/ram/MASK_2 (31 11) routing lc_trk_g3_3 wire_bram/ram/MASK_2 (31 11) routing lc_trk_g3_7 wire_bram/ram/MASK_2 (31 12) routing lc_trk_g0_5 wire_bram/ram/MASK_1 (31 12) routing lc_trk_g0_7 wire_bram/ram/MASK_1 (31 12) routing lc_trk_g1_4 wire_bram/ram/MASK_1 -(31 12) routing lc_trk_g1_6 wire_bram/ram/MASK_1 (31 12) routing lc_trk_g2_5 wire_bram/ram/MASK_1 (31 12) routing lc_trk_g2_7 wire_bram/ram/MASK_1 (31 12) routing lc_trk_g3_4 wire_bram/ram/MASK_1 (31 12) routing lc_trk_g3_6 wire_bram/ram/MASK_1 -(31 13) routing lc_trk_g0_3 wire_bram/ram/MASK_1 (31 13) routing lc_trk_g0_7 wire_bram/ram/MASK_1 -(31 13) routing lc_trk_g1_2 wire_bram/ram/MASK_1 -(31 13) routing lc_trk_g1_6 wire_bram/ram/MASK_1 -(31 13) routing lc_trk_g2_3 wire_bram/ram/MASK_1 (31 13) routing lc_trk_g2_7 wire_bram/ram/MASK_1 (31 13) routing lc_trk_g3_2 wire_bram/ram/MASK_1 (31 13) routing lc_trk_g3_6 wire_bram/ram/MASK_1 -(31 14) routing lc_trk_g0_4 wire_bram/ram/MASK_0 (31 14) routing lc_trk_g0_6 wire_bram/ram/MASK_0 -(31 14) routing lc_trk_g1_5 wire_bram/ram/MASK_0 (31 14) routing lc_trk_g1_7 wire_bram/ram/MASK_0 (31 14) routing lc_trk_g2_4 wire_bram/ram/MASK_0 (31 14) routing lc_trk_g2_6 wire_bram/ram/MASK_0 (31 14) routing lc_trk_g3_5 wire_bram/ram/MASK_0 (31 14) routing lc_trk_g3_7 wire_bram/ram/MASK_0 -(31 15) routing lc_trk_g0_2 wire_bram/ram/MASK_0 (31 15) routing lc_trk_g0_6 wire_bram/ram/MASK_0 -(31 15) routing lc_trk_g1_3 wire_bram/ram/MASK_0 (31 15) routing lc_trk_g1_7 wire_bram/ram/MASK_0 -(31 15) routing lc_trk_g2_2 wire_bram/ram/MASK_0 (31 15) routing lc_trk_g2_6 wire_bram/ram/MASK_0 (31 15) routing lc_trk_g3_3 wire_bram/ram/MASK_0 (31 15) routing lc_trk_g3_7 wire_bram/ram/MASK_0 -(31 2) routing lc_trk_g0_4 wire_bram/ram/MASK_6 (31 2) routing lc_trk_g0_6 wire_bram/ram/MASK_6 (31 2) routing lc_trk_g1_5 wire_bram/ram/MASK_6 -(31 2) routing lc_trk_g1_7 wire_bram/ram/MASK_6 -(31 2) routing lc_trk_g2_4 wire_bram/ram/MASK_6 (31 2) routing lc_trk_g2_6 wire_bram/ram/MASK_6 (31 2) routing lc_trk_g3_5 wire_bram/ram/MASK_6 (31 2) routing lc_trk_g3_7 wire_bram/ram/MASK_6 -(31 3) routing lc_trk_g0_2 wire_bram/ram/MASK_6 (31 3) routing lc_trk_g0_6 wire_bram/ram/MASK_6 -(31 3) routing lc_trk_g1_3 wire_bram/ram/MASK_6 -(31 3) routing lc_trk_g1_7 wire_bram/ram/MASK_6 (31 3) routing lc_trk_g2_2 wire_bram/ram/MASK_6 (31 3) routing lc_trk_g2_6 wire_bram/ram/MASK_6 (31 3) routing lc_trk_g3_3 wire_bram/ram/MASK_6 (31 3) routing lc_trk_g3_7 wire_bram/ram/MASK_6 -(31 4) routing lc_trk_g0_5 wire_bram/ram/MASK_5 -(31 4) routing lc_trk_g0_7 wire_bram/ram/MASK_5 -(31 4) routing lc_trk_g1_4 wire_bram/ram/MASK_5 (31 4) routing lc_trk_g1_6 wire_bram/ram/MASK_5 (31 4) routing lc_trk_g2_5 wire_bram/ram/MASK_5 (31 4) routing lc_trk_g2_7 wire_bram/ram/MASK_5 (31 4) routing lc_trk_g3_4 wire_bram/ram/MASK_5 (31 4) routing lc_trk_g3_6 wire_bram/ram/MASK_5 -(31 5) routing lc_trk_g0_3 wire_bram/ram/MASK_5 -(31 5) routing lc_trk_g0_7 wire_bram/ram/MASK_5 -(31 5) routing lc_trk_g1_2 wire_bram/ram/MASK_5 (31 5) routing lc_trk_g1_6 wire_bram/ram/MASK_5 -(31 5) routing lc_trk_g2_3 wire_bram/ram/MASK_5 (31 5) routing lc_trk_g2_7 wire_bram/ram/MASK_5 -(31 5) routing lc_trk_g3_2 wire_bram/ram/MASK_5 (31 5) routing lc_trk_g3_6 wire_bram/ram/MASK_5 (31 6) routing lc_trk_g0_4 wire_bram/ram/MASK_4 -(31 6) routing lc_trk_g0_6 wire_bram/ram/MASK_4 (31 6) routing lc_trk_g1_5 wire_bram/ram/MASK_4 -(31 6) routing lc_trk_g1_7 wire_bram/ram/MASK_4 (31 6) routing lc_trk_g2_4 wire_bram/ram/MASK_4 -(31 6) routing lc_trk_g2_6 wire_bram/ram/MASK_4 (31 6) routing lc_trk_g3_5 wire_bram/ram/MASK_4 (31 6) routing lc_trk_g3_7 wire_bram/ram/MASK_4 (31 7) routing lc_trk_g0_2 wire_bram/ram/MASK_4 -(31 7) routing lc_trk_g0_6 wire_bram/ram/MASK_4 -(31 7) routing lc_trk_g1_3 wire_bram/ram/MASK_4 -(31 7) routing lc_trk_g1_7 wire_bram/ram/MASK_4 (31 7) routing lc_trk_g2_2 wire_bram/ram/MASK_4 -(31 7) routing lc_trk_g2_6 wire_bram/ram/MASK_4 (31 7) routing lc_trk_g3_3 wire_bram/ram/MASK_4 (31 7) routing lc_trk_g3_7 wire_bram/ram/MASK_4 (31 8) routing lc_trk_g0_5 wire_bram/ram/MASK_3 -(31 8) routing lc_trk_g0_7 wire_bram/ram/MASK_3 -(31 8) routing lc_trk_g1_4 wire_bram/ram/MASK_3 -(31 8) routing lc_trk_g1_6 wire_bram/ram/MASK_3 (31 8) routing lc_trk_g2_5 wire_bram/ram/MASK_3 (31 8) routing lc_trk_g2_7 wire_bram/ram/MASK_3 (31 8) routing lc_trk_g3_4 wire_bram/ram/MASK_3 (31 8) routing lc_trk_g3_6 wire_bram/ram/MASK_3 (31 9) routing lc_trk_g0_3 wire_bram/ram/MASK_3 -(31 9) routing lc_trk_g0_7 wire_bram/ram/MASK_3 (31 9) routing lc_trk_g1_2 wire_bram/ram/MASK_3 -(31 9) routing lc_trk_g1_6 wire_bram/ram/MASK_3 (31 9) routing lc_trk_g2_3 wire_bram/ram/MASK_3 (31 9) routing lc_trk_g2_7 wire_bram/ram/MASK_3 (31 9) routing lc_trk_g3_2 wire_bram/ram/MASK_3 (31 9) routing lc_trk_g3_6 wire_bram/ram/MASK_3 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_3 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_5 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_7 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_0 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_2 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_4 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_6 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_1 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_3 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_5 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_7 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_0 wire_bram/ram/MASK_7 (32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_2 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_4 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_6 wire_bram/ram/MASK_7 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_2 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_4 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_6 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_1 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_3 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_5 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_7 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_0 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_2 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_4 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_6 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_1 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_3 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_5 wire_bram/ram/MASK_2 (32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_7 wire_bram/ram/MASK_2 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_1 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_3 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_5 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_7 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_0 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_2 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_4 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_6 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_1 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_3 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_5 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_7 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_0 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_2 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_4 input2_5 (32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_6 input2_5 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_3 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_5 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_7 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_0 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_2 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_4 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_6 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_1 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_3 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_5 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_7 wire_bram/ram/MASK_1 (32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_0 wire_bram/ram/MASK_1 @@ -2852,15 +2398,10 @@ (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_3 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_5 input2_6 (32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_7 input2_6 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_2 wire_bram/ram/MASK_0 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_4 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_6 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_1 wire_bram/ram/MASK_0 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_3 wire_bram/ram/MASK_0 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_5 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_7 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_0 wire_bram/ram/MASK_0 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_2 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_4 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_6 wire_bram/ram/MASK_0 (32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_1 wire_bram/ram/MASK_0 @@ -2883,84 +2424,54 @@ (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_2 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_4 input2_7 (32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_6 input2_7 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_2 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_4 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_6 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_1 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_3 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_5 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_7 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_0 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_2 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_4 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_6 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_1 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_3 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_5 wire_bram/ram/MASK_6 (32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_7 wire_bram/ram/MASK_6 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_3 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_5 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_7 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_0 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_2 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_4 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_6 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_1 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_3 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_5 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_7 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_0 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_2 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_4 wire_bram/ram/MASK_5 (32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_6 wire_bram/ram/MASK_5 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_2 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_4 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_6 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_1 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_3 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_5 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_7 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_0 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_2 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_4 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_6 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_1 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_3 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_5 wire_bram/ram/MASK_4 (32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_7 wire_bram/ram/MASK_4 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_3 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_5 wire_bram/ram/MASK_3 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_7 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_0 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_2 wire_bram/ram/MASK_3 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_4 wire_bram/ram/MASK_3 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_6 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_1 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_3 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_5 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_7 wire_bram/ram/MASK_3 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_0 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_2 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_4 wire_bram/ram/MASK_3 (32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_6 wire_bram/ram/MASK_3 (33 0) routing lc_trk_g2_1 wire_bram/ram/MASK_7 -(33 0) routing lc_trk_g2_3 wire_bram/ram/MASK_7 (33 0) routing lc_trk_g2_5 wire_bram/ram/MASK_7 (33 0) routing lc_trk_g2_7 wire_bram/ram/MASK_7 (33 0) routing lc_trk_g3_0 wire_bram/ram/MASK_7 (33 0) routing lc_trk_g3_2 wire_bram/ram/MASK_7 -(33 0) routing lc_trk_g3_4 wire_bram/ram/MASK_7 -(33 0) routing lc_trk_g3_6 wire_bram/ram/MASK_7 (33 10) routing lc_trk_g2_0 wire_bram/ram/MASK_2 -(33 10) routing lc_trk_g2_2 wire_bram/ram/MASK_2 (33 10) routing lc_trk_g2_4 wire_bram/ram/MASK_2 -(33 10) routing lc_trk_g2_6 wire_bram/ram/MASK_2 -(33 10) routing lc_trk_g3_1 wire_bram/ram/MASK_2 (33 10) routing lc_trk_g3_3 wire_bram/ram/MASK_2 (33 10) routing lc_trk_g3_5 wire_bram/ram/MASK_2 (33 10) routing lc_trk_g3_7 wire_bram/ram/MASK_2 (33 11) routing lc_trk_g2_1 input2_5 -(33 11) routing lc_trk_g2_3 input2_5 (33 11) routing lc_trk_g2_5 input2_5 (33 11) routing lc_trk_g2_7 input2_5 (33 11) routing lc_trk_g3_0 input2_5 @@ -2968,7 +2479,6 @@ (33 11) routing lc_trk_g3_4 input2_5 (33 11) routing lc_trk_g3_6 input2_5 (33 12) routing lc_trk_g2_1 wire_bram/ram/MASK_1 -(33 12) routing lc_trk_g2_3 wire_bram/ram/MASK_1 (33 12) routing lc_trk_g2_5 wire_bram/ram/MASK_1 (33 12) routing lc_trk_g2_7 wire_bram/ram/MASK_1 (33 12) routing lc_trk_g3_0 wire_bram/ram/MASK_1 @@ -2984,7 +2494,6 @@ (33 13) routing lc_trk_g3_5 input2_6 (33 13) routing lc_trk_g3_7 input2_6 (33 14) routing lc_trk_g2_0 wire_bram/ram/MASK_0 -(33 14) routing lc_trk_g2_2 wire_bram/ram/MASK_0 (33 14) routing lc_trk_g2_4 wire_bram/ram/MASK_0 (33 14) routing lc_trk_g2_6 wire_bram/ram/MASK_0 (33 14) routing lc_trk_g3_1 wire_bram/ram/MASK_0 @@ -3001,24 +2510,18 @@ (33 15) routing lc_trk_g3_6 input2_7 (33 2) routing lc_trk_g2_0 wire_bram/ram/MASK_6 (33 2) routing lc_trk_g2_2 wire_bram/ram/MASK_6 -(33 2) routing lc_trk_g2_4 wire_bram/ram/MASK_6 (33 2) routing lc_trk_g2_6 wire_bram/ram/MASK_6 -(33 2) routing lc_trk_g3_1 wire_bram/ram/MASK_6 (33 2) routing lc_trk_g3_3 wire_bram/ram/MASK_6 (33 2) routing lc_trk_g3_5 wire_bram/ram/MASK_6 (33 2) routing lc_trk_g3_7 wire_bram/ram/MASK_6 (33 4) routing lc_trk_g2_1 wire_bram/ram/MASK_5 -(33 4) routing lc_trk_g2_3 wire_bram/ram/MASK_5 (33 4) routing lc_trk_g2_5 wire_bram/ram/MASK_5 (33 4) routing lc_trk_g2_7 wire_bram/ram/MASK_5 (33 4) routing lc_trk_g3_0 wire_bram/ram/MASK_5 -(33 4) routing lc_trk_g3_2 wire_bram/ram/MASK_5 (33 4) routing lc_trk_g3_4 wire_bram/ram/MASK_5 (33 4) routing lc_trk_g3_6 wire_bram/ram/MASK_5 -(33 6) routing lc_trk_g2_0 wire_bram/ram/MASK_4 (33 6) routing lc_trk_g2_2 wire_bram/ram/MASK_4 (33 6) routing lc_trk_g2_4 wire_bram/ram/MASK_4 -(33 6) routing lc_trk_g2_6 wire_bram/ram/MASK_4 (33 6) routing lc_trk_g3_1 wire_bram/ram/MASK_4 (33 6) routing lc_trk_g3_3 wire_bram/ram/MASK_4 (33 6) routing lc_trk_g3_5 wire_bram/ram/MASK_4 @@ -3027,28 +2530,17 @@ (33 8) routing lc_trk_g2_3 wire_bram/ram/MASK_3 (33 8) routing lc_trk_g2_5 wire_bram/ram/MASK_3 (33 8) routing lc_trk_g2_7 wire_bram/ram/MASK_3 -(33 8) routing lc_trk_g3_0 wire_bram/ram/MASK_3 (33 8) routing lc_trk_g3_2 wire_bram/ram/MASK_3 (33 8) routing lc_trk_g3_4 wire_bram/ram/MASK_3 (33 8) routing lc_trk_g3_6 wire_bram/ram/MASK_3 -(34 0) routing lc_trk_g1_0 wire_bram/ram/MASK_7 -(34 0) routing lc_trk_g1_2 wire_bram/ram/MASK_7 -(34 0) routing lc_trk_g1_4 wire_bram/ram/MASK_7 -(34 0) routing lc_trk_g1_6 wire_bram/ram/MASK_7 (34 0) routing lc_trk_g3_0 wire_bram/ram/MASK_7 (34 0) routing lc_trk_g3_2 wire_bram/ram/MASK_7 -(34 0) routing lc_trk_g3_4 wire_bram/ram/MASK_7 -(34 0) routing lc_trk_g3_6 wire_bram/ram/MASK_7 (34 10) routing lc_trk_g1_1 wire_bram/ram/MASK_2 (34 10) routing lc_trk_g1_3 wire_bram/ram/MASK_2 (34 10) routing lc_trk_g1_5 wire_bram/ram/MASK_2 -(34 10) routing lc_trk_g1_7 wire_bram/ram/MASK_2 -(34 10) routing lc_trk_g3_1 wire_bram/ram/MASK_2 (34 10) routing lc_trk_g3_3 wire_bram/ram/MASK_2 (34 10) routing lc_trk_g3_5 wire_bram/ram/MASK_2 (34 10) routing lc_trk_g3_7 wire_bram/ram/MASK_2 -(34 11) routing lc_trk_g1_0 input2_5 -(34 11) routing lc_trk_g1_2 input2_5 (34 11) routing lc_trk_g1_4 input2_5 (34 11) routing lc_trk_g1_6 input2_5 (34 11) routing lc_trk_g3_0 input2_5 @@ -3056,9 +2548,7 @@ (34 11) routing lc_trk_g3_4 input2_5 (34 11) routing lc_trk_g3_6 input2_5 (34 12) routing lc_trk_g1_0 wire_bram/ram/MASK_1 -(34 12) routing lc_trk_g1_2 wire_bram/ram/MASK_1 (34 12) routing lc_trk_g1_4 wire_bram/ram/MASK_1 -(34 12) routing lc_trk_g1_6 wire_bram/ram/MASK_1 (34 12) routing lc_trk_g3_0 wire_bram/ram/MASK_1 (34 12) routing lc_trk_g3_2 wire_bram/ram/MASK_1 (34 12) routing lc_trk_g3_4 wire_bram/ram/MASK_1 @@ -3072,8 +2562,6 @@ (34 13) routing lc_trk_g3_5 input2_6 (34 13) routing lc_trk_g3_7 input2_6 (34 14) routing lc_trk_g1_1 wire_bram/ram/MASK_0 -(34 14) routing lc_trk_g1_3 wire_bram/ram/MASK_0 -(34 14) routing lc_trk_g1_5 wire_bram/ram/MASK_0 (34 14) routing lc_trk_g1_7 wire_bram/ram/MASK_0 (34 14) routing lc_trk_g3_1 wire_bram/ram/MASK_0 (34 14) routing lc_trk_g3_3 wire_bram/ram/MASK_0 @@ -3087,40 +2575,26 @@ (34 15) routing lc_trk_g3_2 input2_7 (34 15) routing lc_trk_g3_4 input2_7 (34 15) routing lc_trk_g3_6 input2_7 -(34 2) routing lc_trk_g1_1 wire_bram/ram/MASK_6 -(34 2) routing lc_trk_g1_3 wire_bram/ram/MASK_6 (34 2) routing lc_trk_g1_5 wire_bram/ram/MASK_6 -(34 2) routing lc_trk_g1_7 wire_bram/ram/MASK_6 -(34 2) routing lc_trk_g3_1 wire_bram/ram/MASK_6 (34 2) routing lc_trk_g3_3 wire_bram/ram/MASK_6 (34 2) routing lc_trk_g3_5 wire_bram/ram/MASK_6 (34 2) routing lc_trk_g3_7 wire_bram/ram/MASK_6 (34 4) routing lc_trk_g1_0 wire_bram/ram/MASK_5 -(34 4) routing lc_trk_g1_2 wire_bram/ram/MASK_5 -(34 4) routing lc_trk_g1_4 wire_bram/ram/MASK_5 (34 4) routing lc_trk_g1_6 wire_bram/ram/MASK_5 (34 4) routing lc_trk_g3_0 wire_bram/ram/MASK_5 -(34 4) routing lc_trk_g3_2 wire_bram/ram/MASK_5 (34 4) routing lc_trk_g3_4 wire_bram/ram/MASK_5 (34 4) routing lc_trk_g3_6 wire_bram/ram/MASK_5 (34 6) routing lc_trk_g1_1 wire_bram/ram/MASK_4 -(34 6) routing lc_trk_g1_3 wire_bram/ram/MASK_4 (34 6) routing lc_trk_g1_5 wire_bram/ram/MASK_4 -(34 6) routing lc_trk_g1_7 wire_bram/ram/MASK_4 (34 6) routing lc_trk_g3_1 wire_bram/ram/MASK_4 (34 6) routing lc_trk_g3_3 wire_bram/ram/MASK_4 (34 6) routing lc_trk_g3_5 wire_bram/ram/MASK_4 (34 6) routing lc_trk_g3_7 wire_bram/ram/MASK_4 (34 8) routing lc_trk_g1_0 wire_bram/ram/MASK_3 (34 8) routing lc_trk_g1_2 wire_bram/ram/MASK_3 -(34 8) routing lc_trk_g1_4 wire_bram/ram/MASK_3 -(34 8) routing lc_trk_g1_6 wire_bram/ram/MASK_3 -(34 8) routing lc_trk_g3_0 wire_bram/ram/MASK_3 (34 8) routing lc_trk_g3_2 wire_bram/ram/MASK_3 (34 8) routing lc_trk_g3_4 wire_bram/ram/MASK_3 (34 8) routing lc_trk_g3_6 wire_bram/ram/MASK_3 -(35 10) routing lc_trk_g0_5 input2_5 -(35 10) routing lc_trk_g0_7 input2_5 (35 10) routing lc_trk_g1_4 input2_5 (35 10) routing lc_trk_g1_6 input2_5 (35 10) routing lc_trk_g2_5 input2_5 @@ -3128,10 +2602,7 @@ (35 10) routing lc_trk_g3_4 input2_5 (35 10) routing lc_trk_g3_6 input2_5 (35 11) routing lc_trk_g0_3 input2_5 -(35 11) routing lc_trk_g0_7 input2_5 -(35 11) routing lc_trk_g1_2 input2_5 (35 11) routing lc_trk_g1_6 input2_5 -(35 11) routing lc_trk_g2_3 input2_5 (35 11) routing lc_trk_g2_7 input2_5 (35 11) routing lc_trk_g3_2 input2_5 (35 11) routing lc_trk_g3_6 input2_5 @@ -3173,16 +2644,12 @@ (36 11) Enable bit of Mux _out_links/OutMux6_5 => wire_bram/ram/RDATA_2 sp4_h_r_10 (36 12) Enable bit of Mux _out_links/OutMux8_6 => wire_bram/ram/RDATA_1 sp4_h_r_44 (36 13) Enable bit of Mux _out_links/OutMux6_6 => wire_bram/ram/RDATA_1 sp4_h_r_12 -(36 14) Enable bit of Mux _out_links/OutMux8_7 => wire_bram/ram/RDATA_0 sp4_h_r_46 (36 15) Enable bit of Mux _out_links/OutMux6_7 => wire_bram/ram/RDATA_0 sp4_h_l_3 (36 2) Enable bit of Mux _out_links/OutMux8_1 => wire_bram/ram/RDATA_6 sp4_h_r_34 (36 3) Enable bit of Mux _out_links/OutMux6_1 => wire_bram/ram/RDATA_6 sp4_h_r_2 (36 4) Enable bit of Mux _out_links/OutMux8_2 => wire_bram/ram/RDATA_5 sp4_h_r_36 -(36 5) Enable bit of Mux _out_links/OutMux6_2 => wire_bram/ram/RDATA_5 sp4_h_r_4 (36 6) Enable bit of Mux _out_links/OutMux8_3 => wire_bram/ram/RDATA_4 sp4_h_l_27 (36 7) Enable bit of Mux _out_links/OutMux6_3 => wire_bram/ram/RDATA_4 sp4_h_r_6 -(36 8) Enable bit of Mux _out_links/OutMux8_4 => wire_bram/ram/RDATA_3 sp4_h_l_29 -(36 9) Enable bit of Mux _out_links/OutMux6_4 => wire_bram/ram/RDATA_3 sp4_h_r_8 (37 0) Enable bit of Mux _out_links/OutMux5_0 => wire_bram/ram/RDATA_7 sp12_h_r_8 (37 1) Enable bit of Mux _out_links/OutMux7_0 => wire_bram/ram/RDATA_7 sp4_h_l_5 (37 10) Enable bit of Mux _out_links/OutMux4_5 => wire_bram/ram/RDATA_2 sp12_h_r_2 @@ -3213,7 +2680,6 @@ (38 5) Enable bit of Mux _out_links/OutMux0_2 => wire_bram/ram/RDATA_5 sp4_v_b_4 (38 6) Enable bit of Mux _out_links/OutMux2_3 => wire_bram/ram/RDATA_4 sp4_v_b_38 (38 7) Enable bit of Mux _out_links/OutMux0_3 => wire_bram/ram/RDATA_4 sp4_v_b_6 -(38 8) Enable bit of Mux _out_links/OutMux1_4 => wire_bram/ram/RDATA_3 sp4_v_t_13 (38 9) Enable bit of Mux _out_links/OutMux5_4 => wire_bram/ram/RDATA_3 sp12_h_r_16 (39 0) Enable bit of Mux _out_links/OutMux3_0 => wire_bram/ram/RDATA_7 sp12_v_b_0 (39 1) Enable bit of Mux _out_links/OutMux1_0 => wire_bram/ram/RDATA_7 sp4_v_b_16 @@ -3235,65 +2701,44 @@ (4 0) routing sp4_h_l_43 sp4_v_b_0 (4 0) routing sp4_v_t_37 sp4_v_b_0 (4 0) routing sp4_v_t_41 sp4_v_b_0 -(4 1) routing sp4_h_l_41 sp4_h_r_0 -(4 1) routing sp4_h_l_44 sp4_h_r_0 -(4 1) routing sp4_v_b_6 sp4_h_r_0 -(4 1) routing sp4_v_t_42 sp4_h_r_0 (4 10) routing sp4_h_r_0 sp4_v_t_43 -(4 10) routing sp4_h_r_6 sp4_v_t_43 (4 10) routing sp4_v_b_10 sp4_v_t_43 (4 10) routing sp4_v_b_6 sp4_v_t_43 (4 11) routing sp4_h_r_10 sp4_h_l_43 -(4 11) routing sp4_h_r_3 sp4_h_l_43 (4 11) routing sp4_v_b_1 sp4_h_l_43 (4 11) routing sp4_v_t_37 sp4_h_l_43 (4 12) routing sp4_h_l_38 sp4_v_b_9 (4 12) routing sp4_h_l_44 sp4_v_b_9 (4 12) routing sp4_v_t_36 sp4_v_b_9 (4 12) routing sp4_v_t_44 sp4_v_b_9 -(4 13) routing sp4_h_l_36 sp4_h_r_9 (4 13) routing sp4_h_l_43 sp4_h_r_9 -(4 13) routing sp4_v_b_3 sp4_h_r_9 (4 13) routing sp4_v_t_41 sp4_h_r_9 (4 14) routing sp4_h_r_3 sp4_v_t_44 (4 14) routing sp4_h_r_9 sp4_v_t_44 (4 14) routing sp4_v_b_1 sp4_v_t_44 (4 14) routing sp4_v_b_9 sp4_v_t_44 -(4 15) routing sp4_h_r_1 sp4_h_l_44 -(4 15) routing sp4_h_r_6 sp4_h_l_44 (4 15) routing sp4_v_b_4 sp4_h_l_44 (4 15) routing sp4_v_t_38 sp4_h_l_44 -(4 2) routing sp4_h_r_0 sp4_v_t_37 (4 2) routing sp4_h_r_6 sp4_v_t_37 (4 2) routing sp4_v_b_0 sp4_v_t_37 (4 2) routing sp4_v_b_4 sp4_v_t_37 -(4 3) routing sp4_h_r_4 sp4_h_l_37 -(4 3) routing sp4_h_r_9 sp4_h_l_37 (4 3) routing sp4_v_b_7 sp4_h_l_37 -(4 3) routing sp4_v_t_43 sp4_h_l_37 (4 4) routing sp4_h_l_38 sp4_v_b_3 (4 4) routing sp4_h_l_44 sp4_v_b_3 (4 4) routing sp4_v_t_38 sp4_v_b_3 (4 4) routing sp4_v_t_42 sp4_v_b_3 -(4 5) routing sp4_h_l_37 sp4_h_r_3 -(4 5) routing sp4_h_l_42 sp4_h_r_3 (4 5) routing sp4_v_b_9 sp4_h_r_3 -(4 5) routing sp4_v_t_47 sp4_h_r_3 (4 6) routing sp4_h_r_3 sp4_v_t_38 (4 6) routing sp4_h_r_9 sp4_v_t_38 (4 6) routing sp4_v_b_3 sp4_v_t_38 (4 6) routing sp4_v_b_7 sp4_v_t_38 (4 7) routing sp4_h_r_0 sp4_h_l_38 -(4 7) routing sp4_h_r_7 sp4_h_l_38 (4 7) routing sp4_v_b_10 sp4_h_l_38 (4 7) routing sp4_v_t_44 sp4_h_l_38 (4 8) routing sp4_h_l_37 sp4_v_b_6 (4 8) routing sp4_h_l_43 sp4_v_b_6 (4 8) routing sp4_v_t_43 sp4_v_b_6 (4 8) routing sp4_v_t_47 sp4_v_b_6 -(4 9) routing sp4_h_l_38 sp4_h_r_6 -(4 9) routing sp4_h_l_47 sp4_h_r_6 -(4 9) routing sp4_v_b_0 sp4_h_r_6 (4 9) routing sp4_v_t_36 sp4_h_r_6 (40 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_bram/ram/RDATA_7 sp4_r_v_b_17 (40 1) Enable bit of Mux _out_links/OutMux4_0 => wire_bram/ram/RDATA_7 sp12_v_b_16 @@ -3327,31 +2772,24 @@ (41 7) Enable bit of Mux _out_links/OutMux9_3 => wire_bram/ram/RDATA_4 sp4_r_v_b_7 (41 8) Enable bit of Mux _out_links/OutMuxb_4 => wire_bram/ram/RDATA_3 sp4_r_v_b_41 (41 9) Enable bit of Mux _out_links/OutMux9_4 => wire_bram/ram/RDATA_3 sp4_r_v_b_9 -(5 0) routing sp4_h_l_44 sp4_h_r_0 -(5 0) routing sp4_v_b_0 sp4_h_r_0 -(5 0) routing sp4_v_b_6 sp4_h_r_0 (5 0) routing sp4_v_t_37 sp4_h_r_0 (5 1) routing sp4_h_l_37 sp4_v_b_0 (5 1) routing sp4_h_l_43 sp4_v_b_0 (5 1) routing sp4_h_r_0 sp4_v_b_0 (5 1) routing sp4_v_t_44 sp4_v_b_0 -(5 10) routing sp4_h_r_3 sp4_h_l_43 (5 10) routing sp4_v_b_6 sp4_h_l_43 (5 10) routing sp4_v_t_37 sp4_h_l_43 (5 10) routing sp4_v_t_43 sp4_h_l_43 (5 11) routing sp4_h_l_43 sp4_v_t_43 (5 11) routing sp4_h_r_0 sp4_v_t_43 -(5 11) routing sp4_h_r_6 sp4_v_t_43 (5 11) routing sp4_v_b_3 sp4_v_t_43 (5 12) routing sp4_h_l_43 sp4_h_r_9 -(5 12) routing sp4_v_b_3 sp4_h_r_9 (5 12) routing sp4_v_b_9 sp4_h_r_9 (5 12) routing sp4_v_t_44 sp4_h_r_9 (5 13) routing sp4_h_l_38 sp4_v_b_9 (5 13) routing sp4_h_l_44 sp4_v_b_9 (5 13) routing sp4_h_r_9 sp4_v_b_9 (5 13) routing sp4_v_t_43 sp4_v_b_9 -(5 14) routing sp4_h_r_6 sp4_h_l_44 (5 14) routing sp4_v_b_9 sp4_h_l_44 (5 14) routing sp4_v_t_38 sp4_h_l_44 (5 14) routing sp4_v_t_44 sp4_h_l_44 @@ -3359,34 +2797,24 @@ (5 15) routing sp4_h_r_3 sp4_v_t_44 (5 15) routing sp4_h_r_9 sp4_v_t_44 (5 15) routing sp4_v_b_6 sp4_v_t_44 -(5 2) routing sp4_h_r_9 sp4_h_l_37 (5 2) routing sp4_v_b_0 sp4_h_l_37 (5 2) routing sp4_v_t_37 sp4_h_l_37 -(5 2) routing sp4_v_t_43 sp4_h_l_37 (5 3) routing sp4_h_l_37 sp4_v_t_37 -(5 3) routing sp4_h_r_0 sp4_v_t_37 (5 3) routing sp4_h_r_6 sp4_v_t_37 (5 3) routing sp4_v_b_9 sp4_v_t_37 -(5 4) routing sp4_h_l_37 sp4_h_r_3 -(5 4) routing sp4_v_b_3 sp4_h_r_3 (5 4) routing sp4_v_b_9 sp4_h_r_3 -(5 4) routing sp4_v_t_38 sp4_h_r_3 (5 5) routing sp4_h_l_38 sp4_v_b_3 (5 5) routing sp4_h_l_44 sp4_v_b_3 (5 5) routing sp4_h_r_3 sp4_v_b_3 (5 5) routing sp4_v_t_37 sp4_v_b_3 (5 6) routing sp4_h_r_0 sp4_h_l_38 (5 6) routing sp4_v_b_3 sp4_h_l_38 -(5 6) routing sp4_v_t_38 sp4_h_l_38 (5 6) routing sp4_v_t_44 sp4_h_l_38 (5 7) routing sp4_h_l_38 sp4_v_t_38 (5 7) routing sp4_h_r_3 sp4_v_t_38 (5 7) routing sp4_h_r_9 sp4_v_t_38 (5 7) routing sp4_v_b_0 sp4_v_t_38 -(5 8) routing sp4_h_l_38 sp4_h_r_6 -(5 8) routing sp4_v_b_0 sp4_h_r_6 (5 8) routing sp4_v_b_6 sp4_h_r_6 -(5 8) routing sp4_v_t_43 sp4_h_r_6 (5 9) routing sp4_h_l_37 sp4_v_b_6 (5 9) routing sp4_h_l_43 sp4_v_b_6 (5 9) routing sp4_h_r_6 sp4_v_b_6 @@ -3396,9 +2824,6 @@ (6 0) routing sp4_v_t_41 sp4_v_b_0 (6 0) routing sp4_v_t_44 sp4_v_b_0 (6 1) routing sp4_h_l_37 sp4_h_r_0 -(6 1) routing sp4_h_l_41 sp4_h_r_0 -(6 1) routing sp4_v_b_0 sp4_h_r_0 -(6 1) routing sp4_v_b_6 sp4_h_r_0 (6 10) routing sp4_h_l_36 sp4_v_t_43 (6 10) routing sp4_h_r_0 sp4_v_t_43 (6 10) routing sp4_v_b_10 sp4_v_t_43 @@ -3411,15 +2836,10 @@ (6 12) routing sp4_h_r_4 sp4_v_b_9 (6 12) routing sp4_v_t_36 sp4_v_b_9 (6 12) routing sp4_v_t_43 sp4_v_b_9 -(6 13) routing sp4_h_l_36 sp4_h_r_9 -(6 13) routing sp4_h_l_44 sp4_h_r_9 -(6 13) routing sp4_v_b_3 sp4_h_r_9 (6 13) routing sp4_v_b_9 sp4_h_r_9 -(6 14) routing sp4_h_l_41 sp4_v_t_44 (6 14) routing sp4_h_r_3 sp4_v_t_44 (6 14) routing sp4_v_b_1 sp4_v_t_44 (6 14) routing sp4_v_b_6 sp4_v_t_44 -(6 15) routing sp4_h_r_1 sp4_h_l_44 (6 15) routing sp4_h_r_9 sp4_h_l_44 (6 15) routing sp4_v_t_38 sp4_h_l_44 (6 15) routing sp4_v_t_44 sp4_h_l_44 @@ -3427,33 +2847,20 @@ (6 2) routing sp4_h_r_6 sp4_v_t_37 (6 2) routing sp4_v_b_4 sp4_v_t_37 (6 2) routing sp4_v_b_9 sp4_v_t_37 -(6 3) routing sp4_h_r_0 sp4_h_l_37 -(6 3) routing sp4_h_r_4 sp4_h_l_37 (6 3) routing sp4_v_t_37 sp4_h_l_37 -(6 3) routing sp4_v_t_43 sp4_h_l_37 (6 4) routing sp4_h_l_44 sp4_v_b_3 (6 4) routing sp4_h_r_10 sp4_v_b_3 (6 4) routing sp4_v_t_37 sp4_v_b_3 (6 4) routing sp4_v_t_42 sp4_v_b_3 -(6 5) routing sp4_h_l_38 sp4_h_r_3 -(6 5) routing sp4_h_l_42 sp4_h_r_3 -(6 5) routing sp4_v_b_3 sp4_h_r_3 (6 5) routing sp4_v_b_9 sp4_h_r_3 (6 6) routing sp4_h_l_47 sp4_v_t_38 (6 6) routing sp4_h_r_9 sp4_v_t_38 (6 6) routing sp4_v_b_0 sp4_v_t_38 (6 6) routing sp4_v_b_7 sp4_v_t_38 -(6 7) routing sp4_h_r_3 sp4_h_l_38 -(6 7) routing sp4_h_r_7 sp4_h_l_38 -(6 7) routing sp4_v_t_38 sp4_h_l_38 (6 7) routing sp4_v_t_44 sp4_h_l_38 (6 8) routing sp4_h_l_37 sp4_v_b_6 -(6 8) routing sp4_h_r_1 sp4_v_b_6 (6 8) routing sp4_v_t_38 sp4_v_b_6 (6 8) routing sp4_v_t_47 sp4_v_b_6 -(6 9) routing sp4_h_l_43 sp4_h_r_6 -(6 9) routing sp4_h_l_47 sp4_h_r_6 -(6 9) routing sp4_v_b_0 sp4_h_r_6 (6 9) routing sp4_v_b_6 sp4_h_r_6 (7 0) Ram config bit: MEMT_bram_cbit_1 (7 1) Ram config bit: MEMT_bram_cbit_0 @@ -3471,7 +2878,6 @@ (7 4) Cascade buffer Enable bit: MEMT_LC03_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC04_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC05_inmux00_bram_cbit_5 -(7 4) Cascade buffer Enable bit: MEMT_LC06_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC06_inmux02_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC07_inmux00_bram_cbit_5 (7 4) Cascade buffer Enable bit: MEMT_LC07_inmux02_bram_cbit_5 @@ -3481,7 +2887,6 @@ (7 5) Cascade bit: MEMT_LC03_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC04_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC05_inmux00_bram_cbit_4 -(7 5) Cascade bit: MEMT_LC06_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC06_inmux02_bram_cbit_4 (7 5) Cascade bit: MEMT_LC07_inmux00_bram_cbit_4 (7 5) Cascade bit: MEMT_LC07_inmux02_bram_cbit_4 @@ -3507,40 +2912,27 @@ (7 7) Cascade bit: MEMT_LC07_inmux02_bram_cbit_6 (7 8) Column buffer control bit: MEMT_colbuf_cntl_1 (7 9) Column buffer control bit: MEMT_colbuf_cntl_0 -(8 0) routing sp4_h_l_36 sp4_h_r_1 -(8 0) routing sp4_h_l_40 sp4_h_r_1 -(8 0) routing sp4_v_b_1 sp4_h_r_1 -(8 0) routing sp4_v_b_7 sp4_h_r_1 (8 1) routing sp4_h_l_36 sp4_v_b_1 (8 1) routing sp4_h_l_42 sp4_v_b_1 (8 1) routing sp4_h_r_1 sp4_v_b_1 (8 1) routing sp4_v_t_47 sp4_v_b_1 (8 10) routing sp4_h_r_11 sp4_h_l_42 -(8 10) routing sp4_h_r_7 sp4_h_l_42 (8 10) routing sp4_v_t_36 sp4_h_l_42 (8 10) routing sp4_v_t_42 sp4_h_l_42 -(8 11) routing sp4_h_l_42 sp4_v_t_42 (8 11) routing sp4_h_r_1 sp4_v_t_42 (8 11) routing sp4_h_r_7 sp4_v_t_42 (8 11) routing sp4_v_b_4 sp4_v_t_42 -(8 12) routing sp4_h_l_39 sp4_h_r_10 -(8 12) routing sp4_h_l_47 sp4_h_r_10 -(8 12) routing sp4_v_b_10 sp4_h_r_10 (8 12) routing sp4_v_b_4 sp4_h_r_10 (8 13) routing sp4_h_l_41 sp4_v_b_10 (8 13) routing sp4_h_l_47 sp4_v_b_10 (8 13) routing sp4_h_r_10 sp4_v_b_10 (8 13) routing sp4_v_t_42 sp4_v_b_10 (8 14) routing sp4_h_r_10 sp4_h_l_47 -(8 14) routing sp4_h_r_2 sp4_h_l_47 (8 14) routing sp4_v_t_41 sp4_h_l_47 (8 14) routing sp4_v_t_47 sp4_h_l_47 (8 15) routing sp4_h_l_47 sp4_v_t_47 (8 15) routing sp4_h_r_10 sp4_v_t_47 -(8 15) routing sp4_h_r_4 sp4_v_t_47 (8 15) routing sp4_v_b_7 sp4_v_t_47 -(8 2) routing sp4_h_r_1 sp4_h_l_36 -(8 2) routing sp4_h_r_5 sp4_h_l_36 (8 2) routing sp4_v_t_36 sp4_h_l_36 (8 2) routing sp4_v_t_42 sp4_h_l_36 (8 3) routing sp4_h_l_36 sp4_v_t_36 @@ -3553,54 +2945,37 @@ (8 4) routing sp4_v_b_4 sp4_h_r_4 (8 5) routing sp4_h_l_41 sp4_v_b_4 (8 5) routing sp4_h_l_47 sp4_v_b_4 -(8 5) routing sp4_h_r_4 sp4_v_b_4 (8 5) routing sp4_v_t_36 sp4_v_b_4 -(8 6) routing sp4_h_r_4 sp4_h_l_41 -(8 6) routing sp4_h_r_8 sp4_h_l_41 (8 6) routing sp4_v_t_41 sp4_h_l_41 (8 6) routing sp4_v_t_47 sp4_h_l_41 (8 7) routing sp4_h_l_41 sp4_v_t_41 (8 7) routing sp4_h_r_10 sp4_v_t_41 -(8 7) routing sp4_h_r_4 sp4_v_t_41 (8 7) routing sp4_v_b_1 sp4_v_t_41 -(8 8) routing sp4_h_l_42 sp4_h_r_7 -(8 8) routing sp4_h_l_46 sp4_h_r_7 (8 8) routing sp4_v_b_1 sp4_h_r_7 -(8 8) routing sp4_v_b_7 sp4_h_r_7 (8 9) routing sp4_h_l_36 sp4_v_b_7 (8 9) routing sp4_h_l_42 sp4_v_b_7 (8 9) routing sp4_h_r_7 sp4_v_b_7 (8 9) routing sp4_v_t_41 sp4_v_b_7 -(9 0) routing sp4_h_l_47 sp4_h_r_1 -(9 0) routing sp4_v_b_1 sp4_h_r_1 -(9 0) routing sp4_v_b_7 sp4_h_r_1 (9 0) routing sp4_v_t_36 sp4_h_r_1 (9 1) routing sp4_h_l_36 sp4_v_b_1 (9 1) routing sp4_h_l_42 sp4_v_b_1 (9 1) routing sp4_v_t_36 sp4_v_b_1 (9 1) routing sp4_v_t_40 sp4_v_b_1 -(9 10) routing sp4_h_r_4 sp4_h_l_42 -(9 10) routing sp4_v_b_7 sp4_h_l_42 (9 10) routing sp4_v_t_36 sp4_h_l_42 (9 10) routing sp4_v_t_42 sp4_h_l_42 (9 11) routing sp4_h_r_1 sp4_v_t_42 (9 11) routing sp4_h_r_7 sp4_v_t_42 (9 11) routing sp4_v_b_11 sp4_v_t_42 (9 11) routing sp4_v_b_7 sp4_v_t_42 -(9 12) routing sp4_h_l_42 sp4_h_r_10 -(9 12) routing sp4_v_b_10 sp4_h_r_10 (9 12) routing sp4_v_b_4 sp4_h_r_10 (9 12) routing sp4_v_t_47 sp4_h_r_10 (9 13) routing sp4_h_l_41 sp4_v_b_10 (9 13) routing sp4_h_l_47 sp4_v_b_10 (9 13) routing sp4_v_t_39 sp4_v_b_10 (9 13) routing sp4_v_t_47 sp4_v_b_10 -(9 14) routing sp4_h_r_7 sp4_h_l_47 -(9 14) routing sp4_v_b_10 sp4_h_l_47 (9 14) routing sp4_v_t_41 sp4_h_l_47 (9 14) routing sp4_v_t_47 sp4_h_l_47 (9 15) routing sp4_h_r_10 sp4_v_t_47 -(9 15) routing sp4_h_r_4 sp4_v_t_47 (9 15) routing sp4_v_b_10 sp4_v_t_47 (9 15) routing sp4_v_b_2 sp4_v_t_47 (9 2) routing sp4_h_r_10 sp4_h_l_36 @@ -3611,7 +2986,6 @@ (9 3) routing sp4_h_r_7 sp4_v_t_36 (9 3) routing sp4_v_b_1 sp4_v_t_36 (9 3) routing sp4_v_b_5 sp4_v_t_36 -(9 4) routing sp4_h_l_36 sp4_h_r_4 (9 4) routing sp4_v_b_10 sp4_h_r_4 (9 4) routing sp4_v_b_4 sp4_h_r_4 (9 4) routing sp4_v_t_41 sp4_h_r_4 @@ -3624,13 +2998,9 @@ (9 6) routing sp4_v_t_41 sp4_h_l_41 (9 6) routing sp4_v_t_47 sp4_h_l_41 (9 7) routing sp4_h_r_10 sp4_v_t_41 -(9 7) routing sp4_h_r_4 sp4_v_t_41 (9 7) routing sp4_v_b_4 sp4_v_t_41 (9 7) routing sp4_v_b_8 sp4_v_t_41 -(9 8) routing sp4_h_l_41 sp4_h_r_7 (9 8) routing sp4_v_b_1 sp4_h_r_7 -(9 8) routing sp4_v_b_7 sp4_h_r_7 -(9 8) routing sp4_v_t_42 sp4_h_r_7 (9 9) routing sp4_h_l_36 sp4_v_b_7 (9 9) routing sp4_h_l_42 sp4_v_b_7 (9 9) routing sp4_v_t_42 sp4_v_b_7 diff --git a/icefuzz/fuzzconfig.py b/icefuzz/fuzzconfig.py index 2181e77..1af5834 100644 --- a/icefuzz/fuzzconfig.py +++ b/icefuzz/fuzzconfig.py @@ -71,3 +71,12 @@ elif device_class == "5k": #TODO(tannewt): Add 39, 40, 41 to this list. It causes placement failures for some reason. gpins = "20 35 37 44".split() + +def output_makefile(working_dir, fuzzname): + with open(working_dir + "/Makefile", "w") as f: + print("all: %s" % " ".join(["%s_%02d.bin" % (fuzzname, i) for i in range(num)]), file=f) + for i in range(num): + basename = "%s_%02d" % (fuzzname, i) + print("%s.bin:" % basename, file=f) + print("\t-bash ../icecube.sh %s > %s.log 2>&1 && rm -rf %s.tmp || tail %s.log" % (basename, basename, basename, basename), file=f) + print("\tpython3 ../glbcheck.py %s.asc %s.glb" % (basename, basename), file=f) diff --git a/icefuzz/glbcheck.py b/icefuzz/glbcheck.py index 4c86f0e..742c335 100644 --- a/icefuzz/glbcheck.py +++ b/icefuzz/glbcheck.py @@ -30,13 +30,13 @@ with open(argv[1]) as f: with open(argv[2]) as f: current_tile = None for line in f: - if line.find("Tile_") >= 0: + if line.startswith(("Tile", "IO_Tile", "RAM_Tile", "LogicTile")): f = line.replace("IO_", "").replace("RAM_", "").split("_") assert len(f) == 3 current_tile = "%02d.%02d" % (int(f[1]), int(f[2])) continue - if line.find("GlobalNetwork") >= 0: + if line.find("GlobalNetwork") >= 0 or line.startswith(("IpCon", "DSP")): current_tile = None continue @@ -54,10 +54,15 @@ only_in_asc = asc_bits - glb_bits only_in_glb = glb_bits - asc_bits assert len(only_in_asc) != 0 or len(only_in_glb) != 0 -if len(only_in_asc) != 0: - print("Only in ASC: %s" % sorted(only_in_asc)) -if len(only_in_glb) != 0: - print("Only in GLB: %s" % sorted(only_in_glb)) +print("Only in ASC:") +for bit in sorted(only_in_asc): + print(bit) + +print() + +print("Only in GLB:") +for bit in sorted(only_in_glb): + print(bit) exit(1) diff --git a/icefuzz/make_aig.py b/icefuzz/make_aig.py index 14431d5..60f5946 100644 --- a/icefuzz/make_aig.py +++ b/icefuzz/make_aig.py @@ -4,13 +4,17 @@ from fuzzconfig import * import numpy as np import os -os.system("rm -rf work_aig") -os.mkdir("work_aig") +device_class = os.getenv("ICEDEVICE") + +working_dir = "work_%s_aig" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) w = len(pins) // 2 for idx in range(num): - with open("work_aig/aig_%02d.v" % idx, "w") as f: + with open(working_dir + "/aig_%02d.v" % idx, "w") as f: print("module top(input [%d:0] a, output [%d:0] y);" % (w-1, w-1), file=f) sigs = ["a[%d]" % i for i in range(w)] @@ -47,14 +51,11 @@ for idx in range(num): print("endmodule", file=f) - with open("work_aig/aig_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/aig_%02d.pcf" % idx, "w") as f: p = np.random.permutation(pins) for i in range(w): print("set_io a[%d] %s" % (i, p[i]), file=f) print("set_io y[%d] %s" % (i, p[i+w]), file=f) -with open("work_aig/Makefile", "w") as f: - print("all: %s" % " ".join(["aig_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("aig_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh aig_%02d > aig_%02d.log 2>&1 && rm -rf aig_%02d.tmp || tail aig_%02d.log" % (i, i, i, i), file=f) + +output_makefile(working_dir, "aig") diff --git a/icefuzz/make_binop.py b/icefuzz/make_binop.py index b84ee7d..ada9d56 100644 --- a/icefuzz/make_binop.py +++ b/icefuzz/make_binop.py @@ -4,23 +4,24 @@ from fuzzconfig import * import numpy as np import os -os.system("rm -rf work_binop") -os.mkdir("work_binop") +device_class = os.getenv("ICEDEVICE") + +working_dir = "work_%s_binop" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) for idx in range(num): - with open("work_binop/binop_%02d.v" % idx, "w") as f: + with open(working_dir + "/binop_%02d.v" % idx, "w") as f: print("module top(input a, b, output y);", file=f) print(" assign y = a%sb;" % np.random.choice([" ^ ", " ^ ~", " & ", " & ~", " | ", " | ~"]), file=f) print("endmodule", file=f) - with open("work_binop/binop_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/binop_%02d.pcf" % idx, "w") as f: p = np.random.permutation(pins) print("set_io a %s" % p[0], file=f) print("set_io b %s" % p[1], file=f) print("set_io y %s" % p[2], file=f) -with open("work_binop/Makefile", "w") as f: - print("all: %s" % " ".join(["binop_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("binop_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh binop_%02d > binop_%02d.log 2>&1 && rm -rf binop_%02d.tmp || tail binop_%02d.log" % (i, i, i, i), file=f) + +output_makefile(working_dir, "binop") diff --git a/icefuzz/make_cluster.py b/icefuzz/make_cluster.py index 0188de3..554d746 100644 --- a/icefuzz/make_cluster.py +++ b/icefuzz/make_cluster.py @@ -4,24 +4,23 @@ from fuzzconfig import * import numpy as np import os -os.system("rm -rf work_cluster") -os.mkdir("work_cluster") +device_class = os.getenv("ICEDEVICE") + +working_dir = "work_%s_cluster" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) for idx in range(num): - with open("work_cluster/cluster_%02d.v" % idx, "w") as f: + with open(working_dir + "/cluster_%02d.v" % idx, "w") as f: print("module top(input [3:0] a, output [3:0] y);", file=f) print(" assign y = {|a, &a, ^a, a[3:2] == a[1:0]};", file=f) print("endmodule", file=f) - with open("work_cluster/cluster_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/cluster_%02d.pcf" % idx, "w") as f: i = np.random.randint(len(pins)) netnames = np.random.permutation(["a[%d]" % i for i in range(4)] + ["y[%d]" % i for i in range(4)]) for net in netnames: print("set_io %s %s" % (net, pins[i]), file=f) i = (i + 1) % len(pins) -with open("work_cluster/Makefile", "w") as f: - print("all: %s" % " ".join(["cluster_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("cluster_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh cluster_%02d > cluster_%02d.log 2>&1 && rm -rf cluster_%02d.tmp || tail cluster_%02d.log" % (i, i, i, i), file=f) - +output_makefile(working_dir, "cluster") diff --git a/icefuzz/make_fanout.py b/icefuzz/make_fanout.py index 01aa405..95d61d5 100644 --- a/icefuzz/make_fanout.py +++ b/icefuzz/make_fanout.py @@ -4,25 +4,26 @@ from fuzzconfig import * import numpy as np import os -os.system("rm -rf work_fanout") -os.mkdir("work_fanout") +device_class = os.getenv("ICEDEVICE") + +working_dir = "work_%s_fanout" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) for idx in range(num): output_count = len(pins) - 2 - with open("work_fanout/fanout_%02d.v" % idx, "w") as f: + with open(working_dir + "/fanout_%02d.v" % idx, "w") as f: print("module top(input [1:0] a, output [%d:0] y);" % (output_count,), file=f) print(" assign y = {%d{a}};" % (output_count,), file=f) print("endmodule", file=f) - with open("work_fanout/fanout_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/fanout_%02d.pcf" % idx, "w") as f: p = np.random.permutation(pins) for i in range(output_count): print("set_io y[%d] %s" % (i, p[i]), file=f) print("set_io a[0] %s" % p[output_count], file=f) print("set_io a[1] %s" % p[output_count+1], file=f) -with open("work_fanout/Makefile", "w") as f: - print("all: %s" % " ".join(["fanout_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("fanout_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh fanout_%02d > fanout_%02d.log 2>&1 && rm -rf fanout_%02d.tmp || tail fanout_%02d.log" % (i, i, i, i), file=f) + +output_makefile(working_dir, "fanout") diff --git a/icefuzz/make_fflogic.py b/icefuzz/make_fflogic.py index e107ec7..bac0569 100644 --- a/icefuzz/make_fflogic.py +++ b/icefuzz/make_fflogic.py @@ -4,8 +4,12 @@ from fuzzconfig import * import numpy as np import os -os.system("rm -rf work_fflogic") -os.mkdir("work_fflogic") +device_class = os.getenv("ICEDEVICE") + +working_dir = "work_%s_fflogic" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) w = (len(pins) - 4) // 5 @@ -38,7 +42,7 @@ def print_seq_op(dst, src1, src2, op, f): assert False for idx in range(num): - with open("work_fflogic/fflogic_%02d.v" % idx, "w") as f: + with open(working_dir + "/fflogic_%02d.v" % idx, "w") as f: print("module top(input clk, rst, en, input [%d:0] a, b, c, d, output [%d:0] y, output z);" % (w-1, w-1), file=f) print(" reg [%d:0] p, q;" % (w-1,), file=f) @@ -47,8 +51,5 @@ for idx in range(num): print(" assign y = p %s q, z = clk ^ rst ^ en;" % random_op(), file=f) print("endmodule", file=f) -with open("work_fflogic/Makefile", "w") as f: - print("all: %s" % " ".join(["fflogic_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("fflogic_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh fflogic_%02d > fflogic_%02d.log 2>&1 && rm -rf fflogic_%02d.tmp || tail fflogic_%02d.log" % (i, i, i, i), file=f) + +output_makefile(working_dir, "fflogic") diff --git a/icefuzz/make_gbio.py b/icefuzz/make_gbio.py index bbc4ae9..a12bea9 100644 --- a/icefuzz/make_gbio.py +++ b/icefuzz/make_gbio.py @@ -4,11 +4,13 @@ from fuzzconfig import * import numpy as np import os -os.system("rm -rf work_gbio") -os.mkdir("work_gbio") - device_class = os.getenv("ICEDEVICE") +working_dir = "work_%s_gbio" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) + for p in gpins: if p in pins: pins.remove(p) @@ -17,7 +19,7 @@ for p in gpins: w = min(min((len(pins) - 8) // 4, len(gpins)), 8) for idx in range(num): - with open("work_gbio/gbio_%02d.v" % idx, "w") as f: + with open(working_dir + "/gbio_%02d.v" % idx, "w") as f: glbs = np.random.permutation(list(range(8))) if w <= 4: @@ -81,7 +83,7 @@ for idx in range(num): globals_0, glbs[0], glbs[1], glbs[1], glbs[2], glbs[3] ), file=f) - with open("work_gbio/gbio_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/gbio_%02d.pcf" % idx, "w") as f: p = np.random.permutation(pins) g = np.random.permutation(gpins) for i in range(w): @@ -93,8 +95,5 @@ for idx in range(num): print("set_io %s %s" % (n, p[4*w+i]), file=f) print("set_io q %s" % (p[-1]), file=f) -with open("work_gbio/Makefile", "w") as f: - print("all: %s" % " ".join(["gbio_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("gbio_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh gbio_%02d > gbio_%02d.log 2>&1 && rm -rf gbio_%02d.tmp || tail gbio_%02d.log" % (i, i, i, i), file=f) + +output_makefile(working_dir, "gbio") diff --git a/icefuzz/make_gbio2.py b/icefuzz/make_gbio2.py index 41187ee..fedc8c8 100644 --- a/icefuzz/make_gbio2.py +++ b/icefuzz/make_gbio2.py @@ -4,8 +4,12 @@ from fuzzconfig import * import numpy as np import os -os.system("rm -rf work_gbio2") -os.mkdir("work_gbio2") +device_class = os.getenv("ICEDEVICE") + +working_dir = "work_%s_gbio2" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) for p in gpins: if p in pins: pins.remove(p) @@ -15,7 +19,7 @@ for p in gpins: w = min(min((len(pins) - 8) // 4, len(gpins)), 8) for idx in range(num): - with open("work_gbio2/gbio2_%02d.v" % idx, "w") as f: + with open(working_dir + "/gbio2_%02d.v" % idx, "w") as f: glbs = np.random.permutation(list(range(8))) print(""" module top ( @@ -71,7 +75,7 @@ for idx in range(num): """ % ( glbs[0], glbs[1], glbs[1], glbs[2], glbs[3] ), file=f) - with open("work_gbio2/gbio2_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/gbio2_%02d.pcf" % idx, "w") as f: p = np.random.permutation(pins) g = np.random.permutation(gpins) for i in range(w): @@ -83,8 +87,5 @@ for idx in range(num): print("set_io %s %s" % (n, p[4*w+i]), file=f) print("set_io q %s" % (p[-1]), file=f) -with open("work_gbio2/Makefile", "w") as f: - print("all: %s" % " ".join(["gbio2_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("gbio2_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh gbio2_%02d > gbio2_%02d.log 2>&1 && rm -rf gbio2_%02d.tmp || tail gbio2_%02d.log" % (i, i, i, i), file=f) + +output_makefile(working_dir, "gbio2") diff --git a/icefuzz/make_io.py b/icefuzz/make_io.py index 99ad2e5..7e931f6 100644 --- a/icefuzz/make_io.py +++ b/icefuzz/make_io.py @@ -4,13 +4,17 @@ from fuzzconfig import * import numpy as np import os -os.system("rm -rf work_io") -os.mkdir("work_io") +device_class = os.getenv("ICEDEVICE") + +working_dir = "work_%s_io" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) w = num_iobanks for idx in range(num): - with open("work_io/io_%02d.v" % idx, "w") as f: + with open(working_dir + "/io_%02d.v" % idx, "w") as f: glbs = np.random.permutation(list(range(8))) print(""" module top ( @@ -48,14 +52,11 @@ for idx in range(num): np.random.choice(["0000", "0110", "1010", "1110", "0101", "1001", "1101", "0100", "1000", "1100", "0111", "1111"]), np.random.choice(["00", "01", "10", "11"]), np.random.choice(["0", "1"]), np.random.choice(["0", "1"]), w-1 ), file=f) - with open("work_io/io_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/io_%02d.pcf" % idx, "w") as f: p = list(np.random.permutation(pins)) for k in ["pin", "latch_in", "clk_en", "clk_in", "clk_out", "oen", "dout_0", "dout_1", "din_0", "din_1"]: for i in range(w): print("set_io %s[%d] %s" % (k, i, p.pop()), file=f) -with open("work_io/Makefile", "w") as f: - print("all: %s" % " ".join(["io_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("io_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh io_%02d > io_%02d.log 2>&1 && rm -rf io_%02d.tmp || tail io_%02d.log" % (i, i, i, i), file=f) + +output_makefile(working_dir, "io") diff --git a/icefuzz/make_iopack.py b/icefuzz/make_iopack.py index bc13416..e062004 100644 --- a/icefuzz/make_iopack.py +++ b/icefuzz/make_iopack.py @@ -10,8 +10,12 @@ num_xor = 8 num_luts = 8 num_outputs_range = (5, 20) -os.system("rm -rf work_iopack") -os.mkdir("work_iopack") +device_class = os.getenv("ICEDEVICE") + +working_dir = "work_%s_iopack" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) def get_pin_directions(): pindirs = ["i" for i in range(len(pins))] @@ -32,7 +36,7 @@ def get_nearby_inputs(p, n, r): return [choice(ipins) for i in range(n)] for idx in range(num): - with open("work_iopack/iopack_%02d.v" % idx, "w") as f: + with open(working_dir + "/iopack_%02d.v" % idx, "w") as f: pindirs = get_pin_directions() print("module top(%s);" % ", ".join(["%sput p%d" % ("in" if pindirs[i] == "i" else "out", i) for i in range(len(pins))]), file=f) for outp in range(len(pins)): @@ -45,13 +49,9 @@ for idx in range(num): xor_nets.add("%sp%d_in%d" % (choice(["~", ""]), outp, i)) print(" assign p%d = ^{%s};" % (outp, ", ".join(sorted(xor_nets))), file=f) print("endmodule", file=f) - with open("work_iopack/iopack_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/iopack_%02d.pcf" % idx, "w") as f: for i in range(len(pins)): print("set_io p%d %s" % (i, pins[i]), file=f) -with open("work_iopack/Makefile", "w") as f: - print("all: %s" % " ".join(["iopack_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("iopack_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh iopack_%02d > iopack_%02d.log 2>&1 && rm -rf iopack_%02d.tmp || tail iopack_%02d.log" % (i, i, i, i), file=f) +output_makefile(working_dir, "iopack") diff --git a/icefuzz/make_logic.py b/icefuzz/make_logic.py index 7d4b62b..9a83b21 100644 --- a/icefuzz/make_logic.py +++ b/icefuzz/make_logic.py @@ -4,19 +4,23 @@ from fuzzconfig import * import numpy as np import os -os.system("rm -rf work_logic") -os.mkdir("work_logic") +device_class = os.getenv("ICEDEVICE") + +working_dir = "work_%s_logic" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) def random_op(): return np.random.choice(["+", "-", "^", "&", "|", "&~", "|~"]) for idx in range(num): bus_width = len(pins) // 5 - with open("work_logic/logic_%02d.v" % idx, "w") as f: + with open(working_dir + "/logic_%02d.v" % idx, "w") as f: print("module top(input [%d:0] a, b, c, d, output [%d:0] y);" % (bus_width, bus_width), file=f) print(" assign y = (a %s b) %s (c %s d);" % (random_op(), random_op(), random_op()), file=f) print("endmodule", file=f) - with open("work_logic/logic_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/logic_%02d.pcf" % idx, "w") as f: p = np.random.permutation(pins) for i in range(bus_width): print("set_io a[%d] %s" % (i, p[i]), file=f) @@ -25,8 +29,4 @@ for idx in range(num): print("set_io d[%d] %s" % (i, p[i+bus_width*3]), file=f) print("set_io y[%d] %s" % (i, p[i+bus_width*4]), file=f) -with open("work_logic/Makefile", "w") as f: - print("all: %s" % " ".join(["logic_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("logic_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh logic_%02d > logic_%02d.log 2>&1 && rm -rf logic_%02d.tmp || tail logic_%02d.log" % (i, i, i, i), file=f) +output_makefile(working_dir, "logic") diff --git a/icefuzz/make_mem.py b/icefuzz/make_mem.py index ab38849..0fe5aa4 100644 --- a/icefuzz/make_mem.py +++ b/icefuzz/make_mem.py @@ -4,11 +4,15 @@ from fuzzconfig import * import numpy as np import os -os.system("rm -rf work_mem") -os.mkdir("work_mem") +device_class = os.getenv("ICEDEVICE") + +working_dir = "work_%s_mem" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) for idx in range(num): - with open("work_mem/mem_%02d.v" % idx, "w") as f: + with open(working_dir + "/mem_%02d.v" % idx, "w") as f: print(""" module top(input clk, i0, i1, i2, i3, output reg o0, o1, o2, o3, o4); reg [9:0] raddr, waddr, rdata, wdata; @@ -27,14 +31,11 @@ for idx in range(num): end endmodule """, file=f) - with open("work_mem/mem_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/mem_%02d.pcf" % idx, "w") as f: p = list(np.random.permutation(pins)) for port in [ "clk", "i0", "i1", "i2", "i3", "o0", "o1", "o2", "o3", "o4" ]: print("set_io %s %s" % (port, p.pop()), file=f) -with open("work_mem/Makefile", "w") as f: - print("all: %s" % " ".join(["mem_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("mem_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh mem_%02d > mem_%02d.log 2>&1 && rm -rf mem_%02d.tmp || tail mem_%02d.log" % (i, i, i, i), file=f) + +output_makefile(working_dir, "mem") diff --git a/icefuzz/make_mesh.py b/icefuzz/make_mesh.py index 73d69d8..2b50bdf 100644 --- a/icefuzz/make_mesh.py +++ b/icefuzz/make_mesh.py @@ -4,8 +4,13 @@ from fuzzconfig import * import numpy as np import os -os.system("rm -rf work_mesh") -os.mkdir("work_mesh") + +device_class = os.getenv("ICEDEVICE") + +working_dir = "work_%s_mesh" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) # This test maps a random set of pins to another random set of outputs. @@ -13,19 +18,16 @@ device_class = os.getenv("ICEDEVICE") for idx in range(num): io_count = len(pins) // 2 - with open("work_mesh/mesh_%02d.v" % idx, "w") as f: + with open(working_dir + "/mesh_%02d.v" % idx, "w") as f: print("module top(input [%d:0] a, output [%d:0] y);" % (io_count, io_count), file=f) print(" assign y = a;", file=f) print("endmodule", file=f) - with open("work_mesh/mesh_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/mesh_%02d.pcf" % idx, "w") as f: p = np.random.permutation(pins) for i in range(io_count): print("set_io a[%d] %s" % (i, p[i]), file=f) for i in range(io_count): print("set_io y[%d] %s" % (i, p[io_count+i]), file=f) -with open("work_mesh/Makefile", "w") as f: - print("all: %s" % " ".join(["mesh_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("mesh_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh mesh_%02d > mesh_%02d.log 2>&1 && rm -rf mesh_%02d.tmp || tail mesh_%02d.log" % (i, i, i, i), file=f) + +output_makefile(working_dir, "mesh") diff --git a/icefuzz/make_pin2pin.py b/icefuzz/make_pin2pin.py index 1dfe60e..c2e13e6 100644 --- a/icefuzz/make_pin2pin.py +++ b/icefuzz/make_pin2pin.py @@ -4,22 +4,23 @@ from fuzzconfig import * import numpy as np import os -os.system("rm -rf work_pin2pin") -os.mkdir("work_pin2pin") +device_class = os.getenv("ICEDEVICE") + +working_dir = "work_%s_pin2pin" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) for idx in range(num): - with open("work_pin2pin/pin2pin_%02d.v" % idx, "w") as f: + with open(working_dir + "/pin2pin_%02d.v" % idx, "w") as f: print("module top(input a, output y);", file=f) print(" assign y = a;", file=f) print("endmodule", file=f) - with open("work_pin2pin/pin2pin_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/pin2pin_%02d.pcf" % idx, "w") as f: p = np.random.permutation(pins) print("set_io a %s" % p[0], file=f) print("set_io y %s" % p[1], file=f) -with open("work_pin2pin/Makefile", "w") as f: - print("all: %s" % " ".join(["pin2pin_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("pin2pin_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh pin2pin_%02d > pin2pin_%02d.log 2>&1 && rm -rf pin2pin_%02d.tmp || tail pin2pin_%02d.log" % (i, i, i, i), file=f) + +output_makefile(working_dir, "pin2pin") diff --git a/icefuzz/make_pll.py b/icefuzz/make_pll.py index d438b5e..757a222 100644 --- a/icefuzz/make_pll.py +++ b/icefuzz/make_pll.py @@ -11,9 +11,14 @@ def randbin(n): for p in gpins: if p in pins: pins.remove(p) + -os.system("rm -rf work_pll") -os.mkdir("work_pll") +device_class = os.getenv("ICEDEVICE") + +working_dir = "work_%s_pll" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) for idx in range(num): pin_names = list() @@ -110,20 +115,17 @@ for idx in range(num): pll_inst.append("defparam uut.TEST_MODE = 1'b0;") - with open("work_pll/pll_%02d.v" % idx, "w") as f: + with open(working_dir + "/pll_%02d.v" % idx, "w") as f: print("module top(%s);" % ", ".join(pin_names), file=f) print("\n".join(vlog_body), file=f) print("\n".join(pll_inst), file=f) print("endmodule", file=f) - with open("work_pll/pll_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/pll_%02d.pcf" % idx, "w") as f: for pll_pin, package_pin in zip(pin_names, list(permutation(pins))[0:len(pin_names)]): if pll_pin == "packagepin": package_pin = "49" print("set_io %s %s" % (pll_pin, package_pin), file=f) -with open("work_pll/Makefile", "w") as f: - print("all: %s" % " ".join(["pll_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("pll_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh pll_%02d > pll_%02d.log 2>&1 && rm -rf pll_%02d.tmp || tail pll_%02d.log" % (i, i, i, i), file=f) + +output_makefile(working_dir, "pll") diff --git a/icefuzz/make_prim.py b/icefuzz/make_prim.py index 77b5d9b..b96a100 100644 --- a/icefuzz/make_prim.py +++ b/icefuzz/make_prim.py @@ -4,13 +4,17 @@ from fuzzconfig import * import numpy as np import os -os.system("rm -rf work_prim") -os.mkdir("work_prim") +device_class = os.getenv("ICEDEVICE") + +working_dir = "work_%s_prim" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) w = len(pins) // 4 for idx in range(num): - with open("work_prim/prim_%02d.v" % idx, "w") as f: + with open(working_dir + "/prim_%02d.v" % idx, "w") as f: clkedge = np.random.choice(["pos", "neg"]) print("module top(input clk, input [%s:0] a, b, output reg x, output reg [%s:0] y);""" % ( w-1, w-1 ), file=f) print(" reg [%s:0] aa, bb;""" % ( w-1 ), file=f) @@ -25,7 +29,7 @@ for idx in range(num): else: print(" always @(%sedge clk) y <= %s%s;" % (clkedge, np.random.choice(["~", "-", ""]), np.random.choice(["a", "b"])), file=f) print("endmodule", file=f) - with open("work_prim/prim_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/prim_%02d.pcf" % idx, "w") as f: p = np.random.permutation(pins) if np.random.choice([True, False]): for i in range(w): @@ -43,8 +47,5 @@ for idx in range(num): if np.random.choice([True, False]): print("set_io clk %s" % p[3*w+2], file=f) -with open("work_prim/Makefile", "w") as f: - print("all: %s" % " ".join(["prim_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("prim_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh prim_%02d > prim_%02d.log 2>&1 && rm -rf prim_%02d.tmp || tail prim_%02d.log" % (i, i, i, i), file=f) + +output_makefile(working_dir, "prim") diff --git a/icefuzz/make_ram40.py b/icefuzz/make_ram40.py index b19d5e6..f4acb4e 100644 --- a/icefuzz/make_ram40.py +++ b/icefuzz/make_ram40.py @@ -4,11 +4,15 @@ from fuzzconfig import * import numpy as np import os -os.system("rm -rf work_ram40") -os.mkdir("work_ram40") +device_class = os.getenv("ICEDEVICE") + +working_dir = "work_%s_ram40" % (device_class, ) + +os.system("rm -rf " + working_dir) +os.mkdir(working_dir) for idx in range(num): - with open("work_ram40/ram40_%02d.v" % idx, "w") as f: + with open(working_dir + "/ram40_%02d.v" % idx, "w") as f: glbs = ["glb[%d]" % i for i in range(np.random.randint(8)+1)] glbs_choice = ["wa", "ra", "msk", "wd", "we", "wce", "wc", "re", "rce", "rc"] print(""" @@ -96,15 +100,12 @@ for idx in range(num): bits[k] = "rdata_%d[%d] ^ %s" % (i, k, bits[k]) print("assign out_pins = rdata_%d;" % i, file=f) print("endmodule", file=f) - with open("work_ram40/ram40_%02d.pcf" % idx, "w") as f: + with open(working_dir + "/ram40_%02d.pcf" % idx, "w") as f: p = list(np.random.permutation(pins)) for i in range(len(pins) - 16): print("set_io in_pins[%d] %s" % (i, p.pop()), file=f) for i in range(16): print("set_io out_pins[%d] %s" % (i, p.pop()), file=f) -with open("work_ram40/Makefile", "w") as f: - print("all: %s" % " ".join(["ram40_%02d.bin" % i for i in range(num)]), file=f) - for i in range(num): - print("ram40_%02d.bin:" % i, file=f) - print("\t-bash ../icecube.sh ram40_%02d > ram40_%02d.log 2>&1 && rm -rf ram40_%02d.tmp || tail ram40_%02d.log" % (i, i, i, i), file=f) + +output_makefile(working_dir, "ram40") -- cgit v1.2.3