From 4af8569777fe3aea19ce4e03543441734d6c4272 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 30 Aug 2015 21:45:11 +0200 Subject: Added test-cases for all sb_pll40 primitives --- icefuzz/tests/sb_pll40_2_pad.v | 60 +++++++++++++++++++++++++++++++++++++ icefuzz/tests/sb_pll40_2f_core.v | 65 ++++++++++++++++++++++++++++++++++++++++ icefuzz/tests/sb_pll40_2f_pad.v | 65 ++++++++++++++++++++++++++++++++++++++++ icefuzz/tests/sb_pll40_core.v | 24 +++++---------- icefuzz/tests/sb_pll40_pad.v | 57 +++++++++++++++++++++++++++++++++++ 5 files changed, 254 insertions(+), 17 deletions(-) create mode 100644 icefuzz/tests/sb_pll40_2_pad.v create mode 100644 icefuzz/tests/sb_pll40_2f_core.v create mode 100644 icefuzz/tests/sb_pll40_2f_pad.v create mode 100644 icefuzz/tests/sb_pll40_pad.v (limited to 'icefuzz') diff --git a/icefuzz/tests/sb_pll40_2_pad.v b/icefuzz/tests/sb_pll40_2_pad.v new file mode 100644 index 0000000..4137a22 --- /dev/null +++ b/icefuzz/tests/sb_pll40_2_pad.v @@ -0,0 +1,60 @@ +module top( + input PACKAGEPIN, + output [1:0] PLLOUTCORE, + output [1:0] PLLOUTGLOBAL, + input EXTFEEDBACK, + input [7:0] DYNAMICDELAY, + output LOCK, + input BYPASS, + input RESETB, + input LATCHINPUTVALUE, + + //Test Pins + output SDO, + input SDI, + input SCLK +); + SB_PLL40_2_PAD #( + .FEEDBACK_PATH("DELAY"), + // .FEEDBACK_PATH("SIMPLE"), + // .FEEDBACK_PATH("PHASE_AND_DELAY"), + // .FEEDBACK_PATH("EXTERNAL"), + + .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"), + // .DELAY_ADJUSTMENT_MODE_FEEDBACK("DYNAMIC"), + + .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"), + // .DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"), + + .PLLOUT_SELECT_PORTB("GENCLK"), + // .PLLOUT_SELECT_PORTB("GENCLK_HALF"), + // .PLLOUT_SELECT_PORTB("SHIFTREG_90deg"), + // .PLLOUT_SELECT_PORTB("SHIFTREG_0deg"), + + .SHIFTREG_DIV_MODE(1'b0), + .FDA_FEEDBACK(4'b1111), + .FDA_RELATIVE(4'b1111), + .DIVR(4'b0000), + .DIVF(7'b0000000), + .DIVQ(3'b001), + .FILTER_RANGE(3'b000), + .ENABLE_ICEGATE_PORTA(1'b0), + .ENABLE_ICEGATE_PORTB(1'b0), + .TEST_MODE(1'b0) + ) uut ( + .PACKAGEPIN (PACKAGEPIN ), + .PLLOUTCOREA (PLLOUTCORE [0]), + .PLLOUTGLOBALA (PLLOUTGLOBAL[0]), + .PLLOUTCOREB (PLLOUTCORE [1]), + .PLLOUTGLOBALB (PLLOUTGLOBAL[1]), + .EXTFEEDBACK (EXTFEEDBACK ), + .DYNAMICDELAY (DYNAMICDELAY ), + .LOCK (LOCK ), + .BYPASS (BYPASS ), + .RESETB (RESETB ), + .LATCHINPUTVALUE(LATCHINPUTVALUE), + .SDO (SDO ), + .SDI (SDI ), + .SCLK (SCLK ) + ); +endmodule diff --git a/icefuzz/tests/sb_pll40_2f_core.v b/icefuzz/tests/sb_pll40_2f_core.v new file mode 100644 index 0000000..8055e12 --- /dev/null +++ b/icefuzz/tests/sb_pll40_2f_core.v @@ -0,0 +1,65 @@ +module top( + input REFERENCECLK, + output [1:0] PLLOUTCORE, + output [1:0] PLLOUTGLOBAL, + input EXTFEEDBACK, + input [7:0] DYNAMICDELAY, + output LOCK, + input BYPASS, + input RESETB, + input LATCHINPUTVALUE, + + //Test Pins + output SDO, + input SDI, + input SCLK +); + SB_PLL40_2F_CORE #( + .FEEDBACK_PATH("DELAY"), + // .FEEDBACK_PATH("SIMPLE"), + // .FEEDBACK_PATH("PHASE_AND_DELAY"), + // .FEEDBACK_PATH("EXTERNAL"), + + .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"), + // .DELAY_ADJUSTMENT_MODE_FEEDBACK("DYNAMIC"), + + .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"), + // .DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"), + + .PLLOUT_SELECT_PORTA("GENCLK"), + // .PLLOUT_SELECT_PORTA("GENCLK_HALF"), + // .PLLOUT_SELECT_PORTA("SHIFTREG_90deg"), + // .PLLOUT_SELECT_PORTA("SHIFTREG_0deg"), + + .PLLOUT_SELECT_PORTB("GENCLK"), + // .PLLOUT_SELECT_PORTB("GENCLK_HALF"), + // .PLLOUT_SELECT_PORTB("SHIFTREG_90deg"), + // .PLLOUT_SELECT_PORTB("SHIFTREG_0deg"), + + .SHIFTREG_DIV_MODE(1'b0), + .FDA_FEEDBACK(4'b1111), + .FDA_RELATIVE(4'b1111), + .DIVR(4'b0000), + .DIVF(7'b0000000), + .DIVQ(3'b001), + .FILTER_RANGE(3'b000), + .ENABLE_ICEGATE_PORTA(1'b0), + .ENABLE_ICEGATE_PORTB(1'b0), + .TEST_MODE(1'b0) + ) uut ( + .REFERENCECLK (REFERENCECLK ), + .PLLOUTCOREA (PLLOUTCORE [0]), + .PLLOUTGLOBALA (PLLOUTGLOBAL[0]), + .PLLOUTCOREB (PLLOUTCORE [1]), + .PLLOUTGLOBALB (PLLOUTGLOBAL[1]), + .EXTFEEDBACK (EXTFEEDBACK ), + .DYNAMICDELAY (DYNAMICDELAY ), + .LOCK (LOCK ), + .BYPASS (BYPASS ), + .RESETB (RESETB ), + .LATCHINPUTVALUE(LATCHINPUTVALUE), + .SDO (SDO ), + .SDI (SDI ), + .SCLK (SCLK ) + ); +endmodule diff --git a/icefuzz/tests/sb_pll40_2f_pad.v b/icefuzz/tests/sb_pll40_2f_pad.v new file mode 100644 index 0000000..65bfad4 --- /dev/null +++ b/icefuzz/tests/sb_pll40_2f_pad.v @@ -0,0 +1,65 @@ +module top( + input PACKAGEPIN, + output [1:0] PLLOUTCORE, + output [1:0] PLLOUTGLOBAL, + input EXTFEEDBACK, + input [7:0] DYNAMICDELAY, + output LOCK, + input BYPASS, + input RESETB, + input LATCHINPUTVALUE, + + //Test Pins + output SDO, + input SDI, + input SCLK +); + SB_PLL40_2F_PAD #( + .FEEDBACK_PATH("DELAY"), + // .FEEDBACK_PATH("SIMPLE"), + // .FEEDBACK_PATH("PHASE_AND_DELAY"), + // .FEEDBACK_PATH("EXTERNAL"), + + .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"), + // .DELAY_ADJUSTMENT_MODE_FEEDBACK("DYNAMIC"), + + .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"), + // .DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"), + + .PLLOUT_SELECT_PORTA("GENCLK"), + // .PLLOUT_SELECT_PORTA("GENCLK_HALF"), + // .PLLOUT_SELECT_PORTA("SHIFTREG_90deg"), + // .PLLOUT_SELECT_PORTA("SHIFTREG_0deg"), + + .PLLOUT_SELECT_PORTB("GENCLK"), + // .PLLOUT_SELECT_PORTB("GENCLK_HALF"), + // .PLLOUT_SELECT_PORTB("SHIFTREG_90deg"), + // .PLLOUT_SELECT_PORTB("SHIFTREG_0deg"), + + .SHIFTREG_DIV_MODE(1'b0), + .FDA_FEEDBACK(4'b1111), + .FDA_RELATIVE(4'b1111), + .DIVR(4'b0000), + .DIVF(7'b0000000), + .DIVQ(3'b001), + .FILTER_RANGE(3'b000), + .ENABLE_ICEGATE_PORTA(1'b0), + .ENABLE_ICEGATE_PORTB(1'b0), + .TEST_MODE(1'b0) + ) uut ( + .PACKAGEPIN (PACKAGEPIN ), + .PLLOUTCOREA (PLLOUTCORE [0]), + .PLLOUTGLOBALA (PLLOUTGLOBAL[0]), + .PLLOUTCOREB (PLLOUTCORE [1]), + .PLLOUTGLOBALB (PLLOUTGLOBAL[1]), + .EXTFEEDBACK (EXTFEEDBACK ), + .DYNAMICDELAY (DYNAMICDELAY ), + .LOCK (LOCK ), + .BYPASS (BYPASS ), + .RESETB (RESETB ), + .LATCHINPUTVALUE(LATCHINPUTVALUE), + .SDO (SDO ), + .SDI (SDI ), + .SCLK (SCLK ) + ); +endmodule diff --git a/icefuzz/tests/sb_pll40_core.v b/icefuzz/tests/sb_pll40_core.v index 298fb73..9954eca 100644 --- a/icefuzz/tests/sb_pll40_core.v +++ b/icefuzz/tests/sb_pll40_core.v @@ -1,7 +1,7 @@ module top( input REFERENCECLK, - output [1:0] PLLOUTCORE, - output [1:0] PLLOUTGLOBAL, + output PLLOUTCORE, + output PLLOUTGLOBAL, input EXTFEEDBACK, input [7:0] DYNAMICDELAY, output LOCK, @@ -14,7 +14,7 @@ module top( input SDI, input SCLK ); - SB_PLL40_2F_CORE #( + SB_PLL40_CORE #( .FEEDBACK_PATH("DELAY"), // .FEEDBACK_PATH("SIMPLE"), // .FEEDBACK_PATH("PHASE_AND_DELAY"), @@ -26,10 +26,7 @@ module top( .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"), // .DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"), - .PLLOUT_SELECT_PORTA("GENCLK"), - .PLLOUT_SELECT_PORTB("GENCLK"), - - // .PLLOUT_SELECT("GENCLK"), + .PLLOUT_SELECT("GENCLK"), // .PLLOUT_SELECT("GENCLK_HALF"), // .PLLOUT_SELECT("SHIFTREG_90deg"), // .PLLOUT_SELECT("SHIFTREG_0deg"), @@ -41,19 +38,12 @@ module top( .DIVF(7'b0000000), .DIVQ(3'b001), .FILTER_RANGE(3'b000), - // .ENABLE_ICEGATE(1'b0), - .ENABLE_ICEGATE_PORTA(1'b0), - .ENABLE_ICEGATE_PORTB(1'b0), + .ENABLE_ICEGATE(1'b0), .TEST_MODE(1'b0) ) uut ( .REFERENCECLK (REFERENCECLK ), - // .PACKAGEPIN (REFERENCECLK ), - // .PLLOUTCORE (PLLOUTCORE ), - // .PLLOUTGLOBAL (PLLOUTGLOBAL ), - .PLLOUTCOREA (PLLOUTCORE [0]), - .PLLOUTGLOBALA (PLLOUTGLOBAL[0]), - .PLLOUTCOREB (PLLOUTCORE [1]), - .PLLOUTGLOBALB (PLLOUTGLOBAL[1]), + .PLLOUTCORE (PLLOUTCORE ), + .PLLOUTGLOBAL (PLLOUTGLOBAL ), .EXTFEEDBACK (EXTFEEDBACK ), .DYNAMICDELAY (DYNAMICDELAY ), .LOCK (LOCK ), diff --git a/icefuzz/tests/sb_pll40_pad.v b/icefuzz/tests/sb_pll40_pad.v new file mode 100644 index 0000000..180d04b --- /dev/null +++ b/icefuzz/tests/sb_pll40_pad.v @@ -0,0 +1,57 @@ +module top( + input PACKAGEPIN, + output PLLOUTCORE, + output PLLOUTGLOBAL, + input EXTFEEDBACK, + input [7:0] DYNAMICDELAY, + output LOCK, + input BYPASS, + input RESETB, + input LATCHINPUTVALUE, + + //Test Pins + output SDO, + input SDI, + input SCLK +); + SB_PLL40_PAD #( + .FEEDBACK_PATH("DELAY"), + // .FEEDBACK_PATH("SIMPLE"), + // .FEEDBACK_PATH("PHASE_AND_DELAY"), + // .FEEDBACK_PATH("EXTERNAL"), + + .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"), + // .DELAY_ADJUSTMENT_MODE_FEEDBACK("DYNAMIC"), + + .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"), + // .DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"), + + .PLLOUT_SELECT("GENCLK"), + // .PLLOUT_SELECT("GENCLK_HALF"), + // .PLLOUT_SELECT("SHIFTREG_90deg"), + // .PLLOUT_SELECT("SHIFTREG_0deg"), + + .SHIFTREG_DIV_MODE(1'b0), + .FDA_FEEDBACK(4'b1111), + .FDA_RELATIVE(4'b1111), + .DIVR(4'b0000), + .DIVF(7'b0000000), + .DIVQ(3'b001), + .FILTER_RANGE(3'b000), + .ENABLE_ICEGATE(1'b0), + .TEST_MODE(1'b0) + ) uut ( + .PACKAGEPIN (PACKAGEPIN ), + .PLLOUTCORE (PLLOUTCORE ), + .PLLOUTGLOBAL (PLLOUTGLOBAL ), + .EXTFEEDBACK (EXTFEEDBACK ), + .DYNAMICDELAY (DYNAMICDELAY ), + .LOCK (LOCK ), + .BYPASS (BYPASS ), + .RESETB (RESETB ), + .LATCHINPUTVALUE(LATCHINPUTVALUE), + .SDO (SDO ), + .SDI (SDI ), + .SCLK (SCLK ) + ); +endmodule -- cgit v1.2.3