From dfeb92a46b2228b4f3886a9c06502ccd0dde5562 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 18 Jul 2015 13:05:02 +0200 Subject: Import of icestorm-snapshot-150322.zip --- icebox/Makefile | 25 + icebox/icebox.py | 824 +++++++++++++ icebox/icebox_chipdb.py | 121 ++ icebox/icebox_diff.py | 57 + icebox/icebox_explain.py | 157 +++ icebox/icebox_html.py | 523 ++++++++ icebox/icebox_maps.py | 152 +++ icebox/icebox_vlog.py | 367 ++++++ icebox/iceboxdb.py | 2985 ++++++++++++++++++++++++++++++++++++++++++++++ 9 files changed, 5211 insertions(+) create mode 100644 icebox/Makefile create mode 100644 icebox/icebox.py create mode 100755 icebox/icebox_chipdb.py create mode 100755 icebox/icebox_diff.py create mode 100755 icebox/icebox_explain.py create mode 100755 icebox/icebox_html.py create mode 100755 icebox/icebox_maps.py create mode 100755 icebox/icebox_vlog.py create mode 100644 icebox/iceboxdb.py (limited to 'icebox') diff --git a/icebox/Makefile b/icebox/Makefile new file mode 100644 index 0000000..3f74e18 --- /dev/null +++ b/icebox/Makefile @@ -0,0 +1,25 @@ + +all: + +install: + cp icebox.py /usr/local/bin/icebox.py + cp iceboxdb.py /usr/local/bin/iceboxdb.py + cp icebox_chipdb.py /usr/local/bin/icebox_chipdb + cp icebox_diff.py /usr/local/bin/icebox_diff + cp icebox_explain.py /usr/local/bin/icebox_explain + cp icebox_html.py /usr/local/bin/icebox_html + cp icebox_maps.py /usr/local/bin/icebox_maps + cp icebox_vlog.py /usr/local/bin/icebox_vlog + +uninstall: + rm -f /usr/local/bin/icebox.py + rm -f /usr/local/bin/iceboxdb.py + rm -f /usr/local/bin/icebox_chipdb + rm -f /usr/local/bin/icebox_diff + rm -f /usr/local/bin/icebox_explain + rm -f /usr/local/bin/icebox_html + rm -f /usr/local/bin/icebox_maps + rm -f /usr/local/bin/icebox_vlog + +.PHONY: install uninstall + diff --git a/icebox/icebox.py b/icebox/icebox.py new file mode 100644 index 0000000..f3dc113 --- /dev/null +++ b/icebox/icebox.py @@ -0,0 +1,824 @@ +#!/usr/bin/python +# +# Copyright (C) 2015 Clifford Wolf +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +from __future__ import division +from __future__ import print_function +import iceboxdb +import re, sys + +class iceconfig: + def __init__(self): + self.clear() + + def clear(self): + self.max_x = 0 + self.max_y = 0 + self.logic_tiles = dict() + self.io_tiles = dict() + self.ram_tiles = dict() + self.ram_init = dict() + + def setup_empty_1k(self): + self.clear() + self.max_x = 13 + self.max_y = 17 + + for x in range(1, self.max_x): + for y in range(1, self.max_y): + if x in (3, 10): + self.ram_tiles[(x, y)] = ["0" * 42 for i in range(16)] + else: + self.logic_tiles[(x, y)] = ["0" * 54 for i in range(16)] + + for x in range(1, self.max_x): + self.io_tiles[(x, 0)] = ["0" * 18 for i in range(16)] + self.io_tiles[(x, self.max_y)] = ["0" * 18 for i in range(16)] + + for y in range(1, self.max_y): + self.io_tiles[(0, y)] = ["0" * 18 for i in range(16)] + self.io_tiles[(self.max_x, y)] = ["0" * 18 for i in range(16)] + + def tile(self, x, y): + if (x, y) in self.io_tiles: return self.io_tiles[(x, y)] + if (x, y) in self.logic_tiles: return self.logic_tiles[(x, y)] + if (x, y) in self.ram_tiles: return self.ram_tiles[(x, y)] + return None + + def tile_db(self, x, y): + if x == 0: return iotile_l_db + if y == 0: return iotile_b_db + if x == self.max_x: return iotile_r_db + if y == self.max_y: return iotile_t_db + if (x, y) in self.ram_tiles: return ramtile_db + if (x, y) in self.logic_tiles: return logictile_db + assert False + + def tile_type(self, x, y): + if x == 0: return "IO" + if y == 0: return "IO" + if x == self.max_x: return "IO" + if y == self.max_y: return "IO" + if (x, y) in self.ram_tiles: return "RAM" + if (x, y) in self.logic_tiles: return "LOGIC" + assert False + + def tile_pos(self, x, y): + if x == 0 and 0 < y < self.max_y: return "l" + if y == 0 and 0 < x < self.max_x: return "b" + if x == self.max_x and 0 < y < self.max_y: return "r" + if y == self.max_y and 0 < x < self.max_x: return "t" + if 0 < x < self.max_x and 0 < y < self.max_y: return "x" + return None + + def tile_has_entry(self, x, y, entry): + if entry[1] in ("routing", "buffer"): + return self.tile_has_net(x, y, entry[2]) and self.tile_has_net(x, y, entry[3]) + return True + + + def tile_has_net(self, x, y, netname): + if netname.startswith("logic_op_"): + if netname.startswith("logic_op_bot_"): + if y == self.max_y and 0 < x < self.max_x: return True + if netname.startswith("logic_op_bnl_"): + if x == self.max_x and 1 < y < self.max_y: return True + if y == self.max_y and 1 < x < self.max_x: return True + if netname.startswith("logic_op_bnr_"): + if x == 0 and 1 < y < self.max_y: return True + if y == self.max_y and 0 < x < self.max_x-1: return True + + if netname.startswith("logic_op_top_"): + if y == 0 and 0 < x < self.max_x: return True + if netname.startswith("logic_op_tnl_"): + if x == self.max_x and 0 < y < self.max_y-1: return True + if y == 0 and 1 < x < self.max_x: return True + if netname.startswith("logic_op_tnr_"): + if x == 0 and 0 < y < self.max_y-1: return True + if y == 0 and 0 < x < self.max_x-1: return True + + if netname.startswith("logic_op_lft_"): + if x == self.max_x: return True + if netname.startswith("logic_op_rgt_"): + if x == 0: return True + + return False + + if not 0 <= x <= self.max_x: return False + if not 0 <= y <= self.max_y: return False + return pos_has_net(self.tile_pos(x, y), netname) + + def tile_follow_net(self, x, y, direction, netname): + if x == 1 and y not in (0, self.max_y) and direction == 'l': return pos_follow_net("x", "L", netname) + if y == 1 and x not in (0, self.max_x) and direction == 'b': return pos_follow_net("x", "B", netname) + if x == self.max_x-1 and y not in (0, self.max_y) and direction == 'r': return pos_follow_net("x", "R", netname) + if y == self.max_y-1 and x not in (0, self.max_x) and direction == 't': return pos_follow_net("x", "T", netname) + return pos_follow_net(self.tile_pos(x, y), direction, netname) + + def follow_funcnet(self, x, y, func): + neighbours = set() + def do_direction(name, nx, ny): + if 0 < nx < self.max_x and 0 < ny < self.max_y: + neighbours.add((nx, ny, "neigh_op_%s_%d" % (name, func))) + if nx in (0, self.max_x) and 0 < ny < self.max_y and nx != x: + neighbours.add((nx, ny, "logic_op_%s_%d" % (name, func))) + if ny in (0, self.max_y) and 0 < nx < self.max_x and ny != y: + neighbours.add((nx, ny, "logic_op_%s_%d" % (name, func))) + do_direction("bot", x, y+1) + do_direction("bnl", x+1, y+1) + do_direction("bnr", x-1, y+1) + do_direction("top", x, y-1) + do_direction("tnl", x+1, y-1) + do_direction("tnr", x-1, y-1) + do_direction("lft", x+1, y ) + do_direction("rgt", x-1, y ) + return neighbours + + def lookup_funcnet(self, nx, ny, x, y, func): + npos = self.tile_pos(nx, ny) + pos = self.tile_pos(x, y) + + if npos is not None and pos is not None: + if npos == "x": + return (nx, ny, "lutff_%d/out" % func) + + elif pos == "x" and npos in ("l", "r", "t", "b"): + if func in (0, 4): return (nx, ny, "io_0/D_IN_0") + if func in (1, 5): return (nx, ny, "io_0/D_IN_1") + if func in (2, 6): return (nx, ny, "io_1/D_IN_0") + if func in (3, 7): return (nx, ny, "io_1/D_IN_1") + + return None + + def rlookup_funcnet(self, x, y, netname): + funcnets = set() + + if netname == "io_0/D_IN_0": + for net in self.follow_funcnet(x, y, 0) | self.follow_funcnet(x, y, 4): + if self.tile_pos(net[0], net[1]) == "x": funcnets.add(net) + + if netname == "io_0/D_IN_1": + for net in self.follow_funcnet(x, y, 1) | self.follow_funcnet(x, y, 5): + if self.tile_pos(net[0], net[1]) == "x": funcnets.add(net) + + if netname == "io_1/D_IN_0": + for net in self.follow_funcnet(x, y, 2) | self.follow_funcnet(x, y, 6): + if self.tile_pos(net[0], net[1]) == "x": funcnets.add(net) + + if netname == "io_1/D_IN_1": + for net in self.follow_funcnet(x, y, 3) | self.follow_funcnet(x, y, 7): + if self.tile_pos(net[0], net[1]) == "x": funcnets.add(net) + + match = re.match(r"lutff_(\d+)/out", netname) + if match: + funcnets |= self.follow_funcnet(x, y, int(match.group(1))) + + return funcnets + + def follow_net(self, netspec): + x, y, netname = netspec + neighbours = self.rlookup_funcnet(x, y, netname) + + if netname == "carry_in" and y > 1: + neighbours.add((x, y-1, "lutff_7/cout")) + + if netname == "lutff_7/cout" and y+1 < self.max_y: + neighbours.add((x, y+1, "carry_in")) + + if netname.startswith("glb_netwk_"): + for nx in range(self.max_x+1): + for ny in range(self.max_y+1): + if self.tile_pos(nx, ny) is not None: + neighbours.add((nx, ny, netname)) + + match = re.match(r"sp4_r_v_b_(\d+)", netname) + if match and 0 < x < self.max_x-1: + neighbours.add((x+1, y, sp4v_normalize("sp4_v_b_" + match.group(1)))) + + match = re.match(r"sp4_v_[bt]_(\d+)", netname) + if match and 1 < x < self.max_x: + n = sp4v_normalize(netname, "b") + if n is not None: + n = n.replace("sp4_", "sp4_r_") + neighbours.add((x-1, y, n)) + + match = re.match(r"(logic|neigh)_op_(...)_(\d+)", netname) + if match: + if match.group(2) == "bot": nx, ny = (x, y-1) + if match.group(2) == "bnl": nx, ny = (x-1, y-1) + if match.group(2) == "bnr": nx, ny = (x+1, y-1) + if match.group(2) == "top": nx, ny = (x, y+1) + if match.group(2) == "tnl": nx, ny = (x-1, y+1) + if match.group(2) == "tnr": nx, ny = (x+1, y+1) + if match.group(2) == "lft": nx, ny = (x-1, y ) + if match.group(2) == "rgt": nx, ny = (x+1, y ) + n = self.lookup_funcnet(nx, ny, x, y, int(match.group(3))) + if n is not None: + neighbours.add(n) + + for direction in ["l", "r", "t", "b"]: + n = self.tile_follow_net(x, y, direction, netname) + if n is not None: + if direction == "l": s = (x-1, y, n) + if direction == "r": s = (x+1, y, n) + if direction == "t": s = (x, y+1, n) + if direction == "b": s = (x, y-1, n) + + if s[0] in (0, self.max_x) and s[1] in (0, self.max_y): + if re.match("span4_(vert|horz)_[lrtb]_\d+$", n): + vert_net = n.replace("_l_", "_t_").replace("_r_", "_b_").replace("_horz_", "_vert_") + horz_net = n.replace("_t_", "_l_").replace("_b_", "_r_").replace("_vert_", "_horz_") + + if s[0] == 0 and s[1] == 0: + if direction == "l": s = (0, 1, vert_net) + if direction == "b": s = (1, 0, horz_net) + + if s[0] == self.max_x and s[1] == self.max_y: + if direction == "r": s = (self.max_x, self.max_y-1, vert_net) + if direction == "t": s = (self.max_x-1, self.max_y, horz_net) + + vert_net = netname.replace("_l_", "_t_").replace("_r_", "_b_").replace("_horz_", "_vert_") + horz_net = netname.replace("_t_", "_l_").replace("_b_", "_r_").replace("_vert_", "_horz_") + + if s[0] == 0 and s[1] == self.max_y: + if direction == "l": s = (0, self.max_y-1, vert_net) + if direction == "t": s = (1, self.max_y, horz_net) + + if s[0] == self.max_x and s[1] == 0: + if direction == "r": s = (self.max_x, 1, vert_net) + if direction == "b": s = (self.max_x-1, 0, horz_net) + + if self.tile_has_net(s[0], s[1], s[2]): + neighbours.add((s[0], s[1], s[2])) + return neighbours + + def group_segments(self, all_from_tiles=set()): + seed_segments = set() + seen_segments = set() + connected_segments = dict() + grouped_segments = set() + + for idx, tile in self.io_tiles.items(): + tc = tileconfig(tile) + pintypes = [ list("000000"), list("000000") ] + for entry in self.tile_db(idx[0], idx[1]): + if entry[1].startswith("IOB_") and entry[2].startswith("PINTYPE_") and tc.match(entry[0]): + pintypes[int(entry[1][-1])][int(entry[2][-1])] = "1" + if "".join(pintypes[0][2:6]) != "0000": + seed_segments.add((idx[0], idx[1], "io_0/D_OUT_0")) + if "".join(pintypes[1][2:6]) != "0000": + seed_segments.add((idx[0], idx[1], "io_1/D_OUT_0")) + + def add_seed_segments(idx, tile, db): + tc = tileconfig(tile) + for entry in db: + if entry[1] in ("routing", "buffer"): + config_match = tc.match(entry[0]) + if idx in all_from_tiles or config_match: + if not self.tile_has_net(idx[0], idx[1], entry[2]): continue + if not self.tile_has_net(idx[0], idx[1], entry[3]): continue + s1 = (idx[0], idx[1], entry[2]) + s2 = (idx[0], idx[1], entry[3]) + if config_match: + connected_segments.setdefault(s1, set()).add(s2) + connected_segments.setdefault(s2, set()).add(s1) + seed_segments.add(s1) + seed_segments.add(s2) + + for idx, tile in self.io_tiles.items(): + add_seed_segments(idx, tile, self.tile_db(idx[0], idx[1])) + + for idx, tile in self.logic_tiles.items(): + if idx in all_from_tiles: + seed_segments.add((idx[0], idx[1], "lutff_7/cout")) + add_seed_segments(idx, tile, logictile_db) + + for idx, tile in self.ram_tiles.items(): + add_seed_segments(idx, tile, ramtile_db) + + while seed_segments: + queue = set() + segments = set() + queue.add(seed_segments.pop()) + while queue: + for s in self.expand_net(queue.pop()): + if s not in segments: + segments.add(s) + assert s not in seen_segments + seen_segments.add(s) + seed_segments.discard(s) + if s in connected_segments: + for cs in connected_segments[s]: + if not cs in segments: + queue.add(cs) + for s in segments: + assert s not in seed_segments + grouped_segments.add(tuple(sorted(segments))) + + return grouped_segments + + def expand_net(self, netspec): + queue = set() + segments = set() + queue.add(netspec) + while queue: + n = queue.pop() + segments.add(n) + for k in self.follow_net(n): + if k not in segments: + queue.add(k) + return segments + + def read_file(self, filename, logprefix=""): + self.clear() + current_data = None + expected_data_lines = 0 + with open(filename, "r") as f: + for linenum, linetext in enumerate(f): + # print("DEBUG: input line %d: %s" % (linenum, linetext.strip())) + line = linetext.strip().split() + if len(line) == 0: + assert expected_data_lines == 0 + continue + if line[0][0] != ".": + if line[0][0] != "0" and line[0][0] != "1": + print("%sWarning: ignoring data block in line %d: %s" % (logprefix, linenum, linetext.strip())) + expected_data_lines = 0 + continue + assert expected_data_lines != 0 + current_data.append(line[0]) + expected_data_lines -= 1 + continue + assert expected_data_lines == 0 + if line[0] in (".io_tile", ".logic_tile", ".ram_tile"): + current_data = list() + expected_data_lines = 16 + self.max_x = max(self.max_x, int(line[1])) + self.max_y = max(self.max_y, int(line[2])) + if line[0] == ".io_tile": + self.io_tiles[(int(line[1]), int(line[2]))] = current_data + continue + if line[0] == ".logic_tile": + self.logic_tiles[(int(line[1]), int(line[2]))] = current_data + continue + if line[0] == ".ram_tile": + self.ram_tiles[(int(line[1]), int(line[2]))] = current_data + continue + if line[0] == ".device": + assert line[1] == "1k" + continue + print("%sWarning: ignoring line %d: %s" % (logprefix, linenum, linetext.strip())) + +class tileconfig: + def __init__(self, tile): + self.bits = set() + for k, line in enumerate(tile): + for i in range(len(line)): + if line[i] == "1": + self.bits.add("B%d[%d]" % (k, i)) + else: + self.bits.add("!B%d[%d]" % (k, i)) + def match(self, pattern): + for bit in pattern: + if not bit in self.bits: + return False + return True + +if False: + ## Lattice span net name normalization + + valid_sp4_h_l = set([1, 2, 4, 5, 7, 9, 10, 11, 15, 16, 17, 21, 24, 34, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47]) + valid_sp4_h_r = set([0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 19, 21, 24, 25, 27, 30, 31, 33, 34, 35, 36, 38, 39, 40, 41, 42, 43, 44, 45, 46]) + + valid_sp4_v_t = set([1, 3, 5, 9, 12, 14, 16, 17, 18, 21, 22, 23, 26, 28, 29, 30, 32, 33, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47]) + valid_sp4_v_b = set([0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 15, 17, 18, 19, 21, 22, 23, 24, 26, 30, 33, 36, 37, 38, 42, 46, 47]) + + valid_sp12_h_l = set([3, 4, 5, 12, 14, 16, 17, 18, 21, 22, 23]) + valid_sp12_h_r = set([0, 1, 2, 3, 5, 8, 9, 10, 11, 12, 13, 14, 16, 20, 23]) + + valid_sp12_v_t = set([0, 1, 2, 3, 6, 9, 10, 12, 14, 21, 22, 23]) + valid_sp12_v_b = set([0, 1, 6, 7, 8, 11, 12, 14, 16, 18, 19, 20, 21, 23]) + +else: + ## IceStorm span net name normalization + + valid_sp4_h_l = set(range(36, 48)) + valid_sp4_h_r = set(range(48)) + + valid_sp4_v_t = set(range(36, 48)) + valid_sp4_v_b = set(range(48)) + + valid_sp12_h_l = set(range(22, 24)) + valid_sp12_h_r = set(range(24)) + + valid_sp12_v_t = set(range(22, 24)) + valid_sp12_v_b = set(range(24)) + +def sp4h_normalize(netname, edge=""): + m = re.match("sp4_h_([lr])_(\d+)$", netname) + assert m + if not m: return None + cur_edge = m.group(1) + cur_index = int(m.group(2)) + + if cur_edge == edge: + return netname + + if cur_edge == "r" and (edge == "l" or (edge == "" and cur_index not in valid_sp4_h_r)): + if cur_index < 12: + return None + return "sp4_h_l_%d" % ((cur_index-12)^1) + + if cur_edge == "l" and (edge == "r" or (edge == "" and cur_index not in valid_sp4_h_l)): + if cur_index >= 36: + return None + return "sp4_h_r_%d" % ((cur_index+12)^1) + + return netname + +def sp4v_normalize(netname, edge=""): + m = re.match("sp4_v_([bt])_(\d+)$", netname) + assert m + if not m: return None + cur_edge = m.group(1) + cur_index = int(m.group(2)) + + if cur_edge == edge: + return netname + + if cur_edge == "b" and (edge == "t" or (edge == "" and cur_index not in valid_sp4_v_b)): + if cur_index < 12: + return None + return "sp4_v_t_%d" % ((cur_index-12)^1) + + if cur_edge == "t" and (edge == "b" or (edge == "" and cur_index not in valid_sp4_v_t)): + if cur_index >= 36: + return None + return "sp4_v_b_%d" % ((cur_index+12)^1) + + return netname + +def sp12h_normalize(netname, edge=""): + m = re.match("sp12_h_([lr])_(\d+)$", netname) + assert m + if not m: return None + cur_edge = m.group(1) + cur_index = int(m.group(2)) + + if cur_edge == edge: + return netname + + if cur_edge == "r" and (edge == "l" or (edge == "" and cur_index not in valid_sp12_h_r)): + if cur_index < 2: + return None + return "sp12_h_l_%d" % ((cur_index-2)^1) + + if cur_edge == "l" and (edge == "r" or (edge == "" and cur_index not in valid_sp12_h_l)): + if cur_index >= 22: + return None + return "sp12_h_r_%d" % ((cur_index+2)^1) + + return netname + +def sp12v_normalize(netname, edge=""): + m = re.match("sp12_v_([bt])_(\d+)$", netname) + assert m + if not m: return None + cur_edge = m.group(1) + cur_index = int(m.group(2)) + + if cur_edge == edge: + return netname + + if cur_edge == "b" and (edge == "t" or (edge == "" and cur_index not in valid_sp12_v_b)): + if cur_index < 2: + return None + return "sp12_v_t_%d" % ((cur_index-2)^1) + + if cur_edge == "t" and (edge == "b" or (edge == "" and cur_index not in valid_sp12_v_t)): + if cur_index >= 22: + return None + return "sp12_v_b_%d" % ((cur_index+2)^1) + + return netname + +def netname_normalize(netname, edge=""): + if netname.startswith("sp4_v_"): return sp4v_normalize(netname, edge) + if netname.startswith("sp4_h_"): return sp4h_normalize(netname, edge) + if netname.startswith("sp12_v_"): return sp12v_normalize(netname, edge) + if netname.startswith("sp12_h_"): return sp12h_normalize(netname, edge) + if netname.startswith("input_2_"): netname = netname.replace("input_2_", "wire_logic_cluster/lc_") + "/in_2" + netname = netname.replace("lc_trk_", "local_") + netname = netname.replace("lc_", "lutff_") + netname = netname.replace("wire_logic_cluster/", "") + netname = netname.replace("wire_io_cluster/", "") + match = re.match(r"(...)_op_(.*)", netname) + if match: + netname = "neigh_op_%s_%s" % (match.group(1), match.group(2)) + if re.match(r"lutff_7/(cen|clk|s_r)", netname): + netname = netname.replace("lutff_7/", "lutff_global/") + if re.match(r"io_1/(cen|inclk|outclk)", netname): + netname = netname.replace("io_1/", "io_global/") + if netname == "carry_in_mux/cout": + return "carry_in_mux" + return netname + +def pos_has_net(pos, netname): + if pos in ("l", "r"): + if re.search(r"_vert_\d+$", netname): return False + if re.search(r"_horz_[rl]_\d+$", netname): return False + if pos in ("t", "b"): + if re.search(r"_horz_\d+$", netname): return False + if re.search(r"_vert_[bt]_\d+$", netname): return False + return True + +def pos_follow_net(pos, direction, netname): + if pos == "x": + m = re.match("sp4_h_[lr]_(\d+)$", netname) + if m and direction in ("l", "L"): + n = sp4h_normalize(netname, "l") + if n is not None: + if direction == "l": + n = re.sub("_l_", "_r_", n) + n = sp4h_normalize(n) + else: + n = re.sub("_l_", "_", n) + n = re.sub("sp4_h_", "span4_horz_", n) + return n + if m and direction in ("r", "R"): + n = sp4h_normalize(netname, "r") + if n is not None: + if direction == "r": + n = re.sub("_r_", "_l_", n) + n = sp4h_normalize(n) + else: + n = re.sub("_r_", "_", n) + n = re.sub("sp4_h_", "span4_horz_", n) + return n + + m = re.match("sp4_v_[tb]_(\d+)$", netname) + if m and direction in ("t", "T"): + n = sp4v_normalize(netname, "t") + if n is not None: + if direction == "t": + n = re.sub("_t_", "_b_", n) + n = sp4v_normalize(n) + else: + n = re.sub("_t_", "_", n) + n = re.sub("sp4_v_", "span4_vert_", n) + return n + if m and direction in ("b", "B"): + n = sp4v_normalize(netname, "b") + if n is not None: + if direction == "b": + n = re.sub("_b_", "_t_", n) + n = sp4v_normalize(n) + else: + n = re.sub("_b_", "_", n) + n = re.sub("sp4_v_", "span4_vert_", n) + return n + + m = re.match("sp12_h_[lr]_(\d+)$", netname) + if m and direction in ("l", "L"): + n = sp12h_normalize(netname, "l") + if n is not None: + if direction == "l": + n = re.sub("_l_", "_r_", n) + n = sp12h_normalize(n) + else: + n = re.sub("_l_", "_", n) + n = re.sub("sp12_h_", "span12_horz_", n) + return n + if m and direction in ("r", "R"): + n = sp12h_normalize(netname, "r") + if n is not None: + if direction == "r": + n = re.sub("_r_", "_l_", n) + n = sp12h_normalize(n) + else: + n = re.sub("_r_", "_", n) + n = re.sub("sp12_h_", "span12_horz_", n) + return n + + m = re.match("sp12_v_[tb]_(\d+)$", netname) + if m and direction in ("t", "T"): + n = sp12v_normalize(netname, "t") + if n is not None: + if direction == "t": + n = re.sub("_t_", "_b_", n) + n = sp12v_normalize(n) + else: + n = re.sub("_t_", "_", n) + n = re.sub("sp12_v_", "span12_vert_", n) + return n + if m and direction in ("b", "B"): + n = sp12v_normalize(netname, "b") + if n is not None: + if direction == "b": + n = re.sub("_b_", "_t_", n) + n = sp12v_normalize(n) + else: + n = re.sub("_b_", "_", n) + n = re.sub("sp12_v_", "span12_vert_", n) + return n + + if pos in ("l", "r" ): + m = re.match("span4_vert_([bt])_(\d+)$", netname) + if m: + case, idx = direction + m.group(1), int(m.group(2)) + if case == "tt": + return "span4_vert_b_%d" % idx + if case == "tb" and idx >= 4: + return "span4_vert_b_%d" % (idx-4) + if case == "bb" and idx < 12: + return "span4_vert_b_%d" % (idx+4) + if case == "bb" and idx >= 12: + return "span4_vert_t_%d" % idx + + if pos in ("t", "b" ): + m = re.match("span4_horz_([rl])_(\d+)$", netname) + if m: + case, idx = direction + m.group(1), int(m.group(2)) + if case == "ll": + return "span4_horz_r_%d" % idx + if case == "lr" and idx >= 4: + return "span4_horz_r_%d" % (idx-4) + if case == "rr" and idx < 12: + return "span4_horz_r_%d" % (idx+4) + if case == "rr" and idx >= 12: + return "span4_horz_l_%d" % idx + + if pos == "l" and direction == "r": + m = re.match("span4_horz_(\d+)$", netname) + if m: return sp4h_normalize("sp4_h_l_%s" % m.group(1)) + m = re.match("span12_horz_(\d+)$", netname) + if m: return sp12h_normalize("sp12_h_l_%s" % m.group(1)) + + if pos == "r" and direction == "l": + m = re.match("span4_horz_(\d+)$", netname) + if m: return sp4h_normalize("sp4_h_r_%s" % m.group(1)) + m = re.match("span12_horz_(\d+)$", netname) + if m: return sp12h_normalize("sp12_h_r_%s" % m.group(1)) + + if pos == "t" and direction == "b": + m = re.match("span4_vert_(\d+)$", netname) + if m: return sp4v_normalize("sp4_v_t_%s" % m.group(1)) + m = re.match("span12_vert_(\d+)$", netname) + if m: return sp12v_normalize("sp12_v_t_%s" % m.group(1)) + + if pos == "b" and direction == "t": + m = re.match("span4_vert_(\d+)$", netname) + if m: return sp4v_normalize("sp4_v_b_%s" % m.group(1)) + m = re.match("span12_vert_(\d+)$", netname) + if m: return sp12v_normalize("sp12_v_b_%s" % m.group(1)) + + return None + +def get_lutff_bits(tile, index): + bits = list("--------------------") + for k, line in enumerate(tile): + for i in range(36, 46): + lutff_idx = k // 2 + lutff_bitnum = (i-36) + 10*(k%2) + if lutff_idx == index: + bits[lutff_bitnum] = line[i]; + return bits + +def get_lutff_lut_bits(tile, index): + lutff_bits = get_lutff_bits(tile, index) + return [lutff_bits[i] for i in [4, 14, 15, 5, 6, 16, 17, 7, 3, 13, 12, 2, 1, 11, 10, 0]] + +def get_lutff_seq_bits(tile, index): + lutff_bits = get_lutff_bits(tile, index) + return [lutff_bits[i] for i in [8, 9, 18, 19]] + +def get_carry_cascade_bit(tile): + return tile[1][49] + +def get_carry_bit(tile): + return tile[1][50] + +def get_negclk_bit(tile): + return tile[0][0] + +def cmp_netnames(a, b): + a = re.sub(r"\d+", lambda m: "%09d" % int(m.group(0)), a) + b = re.sub(r"\d+", lambda m: "%09d" % int(m.group(0)), b) + return cmp(a, b) + +def run_checks_neigh(): + print("Running consistency checks on neighbour finder..") + ic = iceconfig() + ic.max_x = 6 + ic.max_y = 6 + + all_segments = set() + + def add_segments(idx, db): + for entry in db: + if entry[1] in ("routing", "buffer"): + if not ic.tile_has_net(idx[0], idx[1], entry[2]): continue + if not ic.tile_has_net(idx[0], idx[1], entry[3]): continue + all_segments.add((idx[0], idx[1], entry[2])) + all_segments.add((idx[0], idx[1], entry[3])) + + for x in range(ic.max_x+1): + for y in range(ic.max_x+1): + if x in (0, ic.max_x) and y in (0, ic.max_y): + continue + if x in (0, ic.max_x) or y in (0, ic.max_y): + add_segments((x, y), ic.tile_db(x, y)) + else: + add_segments((x, y), logictile_db) + all_segments.add((x, y, "lutff_7/cout")) + + for s1 in all_segments: + for s2 in ic.follow_net(s1): + if s1 not in ic.follow_net(s2): + print("ERROR: %s -> %s, but not vice versa!" % (s1, s2)) + print("Neighbours of %s:" % (s1,)) + for s in ic.follow_net(s1): + print(" ", s) + print("Neighbours of %s:" % (s2,)) + for s in ic.follow_net(s2): + print(" ", s) + print() + +def run_checks(): + run_checks_neigh() + +def parse_db(text): + db = list() + for line in text.split("\n"): + line = line.split("\t") + if len(line) == 0 or line[0] == "": + continue + line[0] = line[0].split(",") + db.append(line) + return db + +iotile_full_db = parse_db(iceboxdb.database_io_txt) +logictile_db = parse_db(iceboxdb.database_logic_txt) +ramtile_db = parse_db(iceboxdb.database_ram_txt) +pinloc_db = [[int(s) for s in line.split()] for line in iceboxdb.pinloc_txt.split("\n") if line != ""] + +iotile_l_db = list() +iotile_r_db = list() +iotile_t_db = list() +iotile_b_db = list() + +for entry in iotile_full_db: + if entry[1] == "buffer" and entry[2].startswith("IO_L."): + new_entry = entry[:] + new_entry[2] = new_entry[2][5:] + iotile_l_db.append(new_entry) + elif entry[1] == "buffer" and entry[2].startswith("IO_R."): + new_entry = entry[:] + new_entry[2] = new_entry[2][5:] + iotile_r_db.append(new_entry) + elif entry[1] == "buffer" and entry[2].startswith("IO_T."): + new_entry = entry[:] + new_entry[2] = new_entry[2][5:] + iotile_t_db.append(new_entry) + elif entry[1] == "buffer" and entry[2].startswith("IO_B."): + new_entry = entry[:] + new_entry[2] = new_entry[2][5:] + iotile_b_db.append(new_entry) + else: + iotile_l_db.append(entry) + iotile_r_db.append(entry) + iotile_t_db.append(entry) + iotile_b_db.append(entry) + +logictile_db.append([["B1[49]"], "buffer", "carry_in", "carry_in_mux"]) +logictile_db.append([["B1[50]"], "CarryInSet"]) + +for db in [iotile_l_db, iotile_r_db, iotile_t_db, iotile_b_db, logictile_db, ramtile_db]: + for entry in db: + if entry[1] in ("buffer", "routing"): + entry[2] = netname_normalize(entry[2]) + entry[3] = netname_normalize(entry[3]) + unique_entries = dict() + while db: + entry = db.pop() + key = " ".join(entry[1:]) + str(entry) + unique_entries[key] = entry + for key in sorted(unique_entries): + db.append(unique_entries[key]) + +if __name__ == "__main__": + run_checks() + diff --git a/icebox/icebox_chipdb.py b/icebox/icebox_chipdb.py new file mode 100755 index 0000000..3441bd3 --- /dev/null +++ b/icebox/icebox_chipdb.py @@ -0,0 +1,121 @@ +#!/usr/bin/python +# +# Copyright (C) 2015 Clifford Wolf +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +from __future__ import division +from __future__ import print_function + +import icebox +import getopt, sys, re + +ic = icebox.iceconfig() +ic.setup_empty_1k() + +all_tiles = set() +for x in range(ic.max_x+1): + for y in range(ic.max_y+1): + if ic.tile(x, y) is not None: + all_tiles.add((x, y)) + +seg_to_net = dict() +net_to_segs = list() + +print("""# +# IceBox Database Dump for iCE40 HX1K / LP1K +# +# +# Quick File Format Reference: +# ---------------------------- +# +# +# .io_tile X Y +# .logic_tile X Y +# .ram_tile X Y +# +# declares the existence of a IO/LOGIC/RAM tile with the given coordinates +# +# +# .net NET_INDEX +# X1 Y1 name1 +# X2 Y2 name2 +# ... +# +# declares a net on the chip and lists its various names in different tiles +# +# +# .buffer X Y DST_NET_INDEX CONFIG_BITS_NAMES +# CONFIG_BITS_VALUES_1 SRC_NET_INDEX_1 +# CONFIG_BITS_VALUES_2 SRC_NET_INDEX_2 +# ... +# +# declares a buffer in the specified tile +# +# +# .routing X Y DST_NET_INDEX CONFIG_BITS_NAMES +# CONFIG_BITS_VALUES_1 SRC_NET_INDEX_1 +# CONFIG_BITS_VALUES_2 SRC_NET_INDEX_2 +# ... +# +# declares a routing switch in the specified tile +# +""") + +for idx in sorted(ic.io_tiles): + print(".io_tile %d %d" % idx) +print() + +for idx in sorted(ic.logic_tiles): + print(".logic_tile %d %d" % idx) +print() + +for idx in sorted(ic.ram_tiles): + print(".ram_tile %d %d" % idx) +print() + +for group in sorted(ic.group_segments(all_tiles)): + netidx = len(net_to_segs) + net_to_segs.append(group) + print(".net %d" % netidx) + for seg in group: + print("%d %d %s" % seg) + assert seg not in seg_to_net + seg_to_net[seg] = netidx + print() + +for idx in sorted(all_tiles): + db = ic.tile_db(idx[0], idx[1]) + db_by_bits = dict() + for entry in db: + if entry[1] in ("buffer", "routing") and ic.tile_has_net(idx[0], idx[1], entry[2]) and ic.tile_has_net(idx[0], idx[1], entry[3]): + bits = tuple([entry[1]] + sorted([bit.replace("!", "") for bit in entry[0]])) + db_by_bits.setdefault(bits, list()).append(entry) + for bits in sorted(db_by_bits): + dst_net = None + for entry in sorted(db_by_bits[bits]): + assert (idx[0], idx[1], entry[3]) in seg_to_net + if dst_net is None: + dst_net = seg_to_net[(idx[0], idx[1], entry[3])] + else: + assert dst_net == seg_to_net[(idx[0], idx[1], entry[3])] + print(".%s %d %d %d %s" % (bits[0], idx[0], idx[1], dst_net, " ".join(bits[1:]))) + for entry in sorted(db_by_bits[bits]): + pattern = "" + for bit in bits[1:]: + pattern += "1" if bit in entry[0] else "0" + assert (idx[0], idx[1], entry[2]) in seg_to_net + print("%s %d" % (pattern, seg_to_net[(idx[0], idx[1], entry[2])])) + print() + diff --git a/icebox/icebox_diff.py b/icebox/icebox_diff.py new file mode 100755 index 0000000..d1790a9 --- /dev/null +++ b/icebox/icebox_diff.py @@ -0,0 +1,57 @@ +#!/usr/bin/python +# +# Copyright (C) 2015 Clifford Wolf +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +from __future__ import division +from __future__ import print_function + +import icebox +import sys + +print("Reading file '%s'.." % sys.argv[1]) +ic1 = icebox.iceconfig() +ic1.read_file(sys.argv[1]) + +print("Reading file '%s'.." % sys.argv[2]) +ic2 = icebox.iceconfig() +ic2.read_file(sys.argv[2]) + +def diff_tiles(stmt, tiles1, tiles2): + for i in sorted(set(tiles1.keys() + tiles2.keys())): + if not i in tiles1: + print("+ %s %d %d" % (stmt, i[0], i[1])) + for line in tiles2[i]: + print("+ %s" % line) + continue + if not i in tiles2: + print("- %s %d %d" % (stmt, i[0], i[1])) + for line in tiles1[i]: + print("- %s" % line) + continue + if tiles1[i] == tiles2[i]: + continue + print(" %s %d %d" % (stmt, i[0], i[1])) + for c in range(len(tiles1[i])): + if tiles1[i][c] == tiles2[i][c]: + print(" %s" % tiles1[i][c]) + else: + print("- %s" % tiles1[i][c]) + print("+ %s" % tiles2[i][c]) + +diff_tiles(".io_tile", ic1.io_tiles, ic2.io_tiles) +diff_tiles(".logic_tile", ic1.logic_tiles, ic2.logic_tiles) +diff_tiles(".ram_tile", ic1.ram_tiles, ic2.ram_tiles) + diff --git a/icebox/icebox_explain.py b/icebox/icebox_explain.py new file mode 100755 index 0000000..26575f1 --- /dev/null +++ b/icebox/icebox_explain.py @@ -0,0 +1,157 @@ +#!/usr/bin/python +# +# Copyright (C) 2015 Clifford Wolf +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +from __future__ import division +from __future__ import print_function + +import icebox +import getopt, sys, re + +print_bits = False +print_map = False +single_tile = None + +def usage(): + print(""" +Usage: icebox_explain [options] + + -b + print config bit names for each config statement + + -m + print tile config bitmaps + + -t ' ' + print only the specified tile +""") + sys.exit(0) + +try: + opts, args = getopt.getopt(sys.argv[1:], "bmt:") +except: + usage() + +for o, a in opts: + if o == "-b": + print_bits = True + elif o == "-m": + print_map = True + elif o == "-t": + single_tile = tuple([int(s) for s in a.split()]) + else: + usage() + +print("Reading file '%s'.." % args[0]) +ic = icebox.iceconfig() +ic.read_file(args[0]) +print("Fabric size (without IO tiles): %d x %d" % (ic.max_x-1, ic.max_y-1)) + +def print_tile(stmt, ic, x, y, tile, db): + if single_tile is not None and single_tile != (x, y): + return + + bits = set() + mapped_bits = set() + for k, line in enumerate(tile): + for i in range(len(line)): + if line[i] == "1": + bits.add("B%d[%d]" % (k, i)) + else: + bits.add("!B%d[%d]" % (k, i)) + + if re.search(r"logic_tile", stmt): + active_luts = set([i for i in range(8) if "1" in icebox.get_lutff_bits(tile, i)]) + + text = set() + used_lc = set() + text_default_mask = 0 + for entry in db: + if re.match(r"LC_", entry[1]): + continue + if entry[1] in ("routing", "buffer"): + if not ic.tile_has_net(x, y, entry[2]): continue + if not ic.tile_has_net(x, y, entry[3]): continue + match = True + for bit in entry[0]: + if not bit in bits: + match = False + if match: + for bit in entry[0]: + mapped_bits.add(bit) + if entry[1] == "IoCtrl" and entry[2] == "IE_0": + text_default_mask |= 1 + if entry[1] == "IoCtrl" and entry[2] == "IE_1": + text_default_mask |= 2 + if entry[1] == "RamConfig" and entry[2] == "MEMB_Power_Up_Control": + text_default_mask |= 4 + if print_bits: + text.add("<%s> %s" % (" ".join(entry[0]), " ".join(entry[1:]))) + else: + text.add(" ".join(entry[1:])) + bitinfo = list() + print_bitinfo = False + for k, line in enumerate(tile): + bitinfo.append("") + extra_text = "" + for i in range(len(line)): + if 36 <= i <= 45 and re.search(r"logic_tile", stmt): + lutff_idx = k // 2 + lutff_bitnum = (i-36) + 10*(k%2) + if line[i] == "1": + used_lc.add(lutff_idx) + bitinfo[-1] += "*" + else: + bitinfo[-1] += "-" + elif line[i] == "1" and "B%d[%d]" % (k, i) not in mapped_bits: + print_bitinfo = True + extra_text += " B%d[%d]" % (k, i) + bitinfo[-1] += "?" + else: + bitinfo[-1] += "+" if line[i] == "1" else "-" + bitinfo[-1] += extra_text + for lcidx in sorted(used_lc): + lutff_options = "".join(icebox.get_lutff_seq_bits(tile, lcidx)) + if lutff_options[0] == "1": lutff_options += " CarryEnable" + if lutff_options[1] == "1": lutff_options += " DffEnable" + if lutff_options[2] == "1": lutff_options += " Set_NoReset" + if lutff_options[3] == "1": lutff_options += " AsyncSetReset" + text.add("LC_%d %s %s" % (lcidx, "".join(icebox.get_lutff_lut_bits(tile, lcidx)), lutff_options)) + if not print_bitinfo: + if text_default_mask == 3 and len(text) == 2: + return + if text_default_mask == 4 and len(text) == 1: + return + if len(text) or print_bitinfo: + print("\n%s" % stmt) + if print_bitinfo: + print("Warning: No DB entries for some bits:") + if print_bitinfo or print_map: + for k, line in enumerate(bitinfo): + print("%4s %s" % ("B%d" % k, line)) + for line in sorted(text): + print(line) + +for idx in ic.io_tiles: + print_tile(".io_tile %d %d" % idx, ic, idx[0], idx[1], ic.io_tiles[idx], ic.tile_db(idx[0], idx[1])) + +for idx in ic.logic_tiles: + print_tile(".logic_tile %d %d" % idx, ic, idx[0], idx[1], ic.logic_tiles[idx], ic.tile_db(idx[0], idx[1])) + +for idx in ic.ram_tiles: + print_tile(".ram_tile %d %d" % idx, ic, idx[0], idx[1], ic.ram_tiles[idx], ic.tile_db(idx[0], idx[1])) +print() + diff --git a/icebox/icebox_html.py b/icebox/icebox_html.py new file mode 100755 index 0000000..f7ebd67 --- /dev/null +++ b/icebox/icebox_html.py @@ -0,0 +1,523 @@ +#!/usr/bin/python +# +# Copyright (C) 2015 Clifford Wolf +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +from __future__ import division +from __future__ import print_function + +import icebox +import getopt, sys, os, re + +chipname = "iCE40 HX1K" +outdir = None +tx, ty = 0, 0 + +def usage(): + print("Usage: %s [options]" % sys.argv[0]) + print(" -x tile_x_coordinate") + print(" -y tile_y_coordinate") + print(" -d outdir") + sys.exit(0) + +try: + opts, args = getopt.getopt(sys.argv[1:], "x:y:d:") +except: + usage() + +for o, a in opts: + if o == "-x": + tx = int(a) + elif o == "-y": + ty = int(a) + elif o == "-d": + outdir = a + else: + usage() + +ic = icebox.iceconfig() +ic.setup_empty_1k() + +mktiles = set() + +for x in range(1, 6) + range(8, 13): + mktiles.add((x, 0)) + mktiles.add((x, 17)) + +for x in range(0, 6) + range(8, 14): + mktiles.add((x, 1)) + mktiles.add((x, 16)) + +for x in range(0, 5) + range(9, 14): + mktiles.add((x, 2)) + mktiles.add((x, 15)) + +for x in range(6, 8): + for y in range(8, 10): + mktiles.add((x, y)) + +expand_count=[0] + +def print_expand_div(title): + print('[+] Show %s') + +def print_expand_all(): + print('[+] Expand All' % (expand_count[0], expand_count[0])) + expand_count[0] += 1 + +def print_index(): + print("Project IceStorm – %s Overview" % chipname) + print("

Project IceStorm – %s Overview

" % chipname) + + print("""Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs +and providing simple tools for analyzing and creating bitstream files. This is work in progress.""") + + print("""

This documentation is auto-generated by icebox_html.py from IceBox.
+A machine-readable form of the database can be downloaded here.

""") + + print("""

The iCE40 FPGA fabric is organized into tiles. The configuration bits +themself have the same meaning in all tiles of the same type. But the way the tiles +are connected to each other depends on the types of neighbouring cells. Furthermore, +some wire names are different for (e.g.) a IO tile on the left border and an IO tile on +the top border.

""") + + print("""

Click on a highlighted tile below to view the bitstream details for the +tile. The highlighted tiles cover all combinations of neighbouring cells that can be found +in iCE40 FPGAs.

""") + + print('

') + for y in range(ic.max_y, -1, -1): + print("") + for x in range(ic.max_x + 1): + print('') + elif (x, y) in mktiles: + if ic.tile_type(x, y) == "IO": color = "#aee" + if ic.tile_type(x, y) == "LOGIC": color = "#eae" + if ic.tile_type(x, y) == "RAM": color = "#eea" + print('bgcolor="%s">%s
(%d %d)' % (color, x, y, ic.tile_type(x, y), x, y)) + else: + if ic.tile_type(x, y) == "IO": color = "#8aa" + if ic.tile_type(x, y) == "LOGIC": color = "#a8a" + if ic.tile_type(x, y) == "RAM": color = "#aa8" + print('bgcolor="%s">%s
(%d %d)' % (color, ic.tile_type(x, y), x, y)) + print("") + print("
 

") + +def print_tile(tx, ty): + tile = ic.tile(tx, ty) + tile_type = ic.tile_type(tx, ty) + + print("Project IceStorm – %s %s Tile (%d %d)" % (chipname, tile_type, tx, ty)) + print("

Project IceStorm – %s %s Tile (%d %d)

" % (chipname, tile_type, tx, ty)) + + print("""Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs +and providing simple tools for analyzing and creating bitstream files. This is work in progress.""") + + print("""

This page describes the %s Tile (%d %d), what nets and +configuration bits it has and how it is connected to its neighbourhood.

""" % (tile_type, tx, ty)) + + visible_tiles = set() + + print('

') + for y in range(ty+2, ty-3, -1): + print("") + for x in range(tx-2, tx+3): + print('') + else: + if (x, y) in mktiles: + if ic.tile_type(x, y) == "IO": color = "#aee" + if ic.tile_type(x, y) == "LOGIC": color = "#eae" + if ic.tile_type(x, y) == "RAM": color = "#eea" + print('bgcolor="%s">%s Tile
(%d %d)' % (color, x, y, ic.tile_type(x, y), x, y)) + else: + if ic.tile_type(x, y) == "IO": color = "#8aa" + if ic.tile_type(x, y) == "LOGIC": color = "#a8a" + if ic.tile_type(x, y) == "RAM": color = "#aa8" + print('bgcolor="%s">%s Tile
(%d %d)' % (color, ic.tile_type(x, y), x, y)) + visible_tiles.add((x, y)) + print("") + print("
 

") + + # print_expand_all() + + print("

Configuration Bitmap

") + + print("

A %s Tile has %d config bits in %d groups of %d bits each:
" % (tile_type, len(tile)*len(tile[0]), len(tile), len(tile[0]))) + print(("%s

" % (", ".join(['%sB%d[%d:0]' % (" " if i < 10 else "", i, len(tile[i])-1) for i in range(len(tile))]))).replace(" B8", "
 B8")) + + bitmap_cells = list() + for line_nr in range(len(tile)): + line = list() + bitmap_cells.append(line) + for bit_nr in range(len(tile[line_nr])): + line.append({"bgcolor": "#aaa", "label": "?"}) + + for entry in ic.tile_db(tx, ty): + if not ic.tile_has_entry(tx, ty, entry): + continue + for bit in [bit.replace("!", "") for bit in entry[0]]: + match = re.match(r"B(\d+)\[(\d+)\]$", bit) + idx1 = int(match.group(1)) + idx2 = int(match.group(2)) + if entry[1] == "routing": + bitmap_cells[idx1][idx2]["bgcolor"] = "#faa" + bitmap_cells[idx1][idx2]["label"] = "R" + bitmap_cells[idx1][idx2]["is_routing"] = True + elif entry[1] == "buffer": + bitmap_cells[idx1][idx2]["bgcolor"] = "#afa" + bitmap_cells[idx1][idx2]["label"] = "B" + bitmap_cells[idx1][idx2]["is_routing"] = True + else: + bitmap_cells[idx1][idx2]["bgcolor"] = "#aaf" + if entry[1] == "ColBufCtrl": + bitmap_cells[idx1][idx2]["label"] = "O" + elif entry[1].startswith("LC_"): + bitmap_cells[idx1][idx2]["label"] = "L" + elif entry[1].startswith("NegClk"): + bitmap_cells[idx1][idx2]["label"] = "N" + elif entry[1].startswith("CarryInSet"): + bitmap_cells[idx1][idx2]["label"] = "C" + elif entry[1].startswith("IOB_"): + bitmap_cells[idx1][idx2]["label"] = "I" + elif entry[1].startswith("IoCtrl"): + bitmap_cells[idx1][idx2]["label"] = "I" + elif entry[1].startswith("Cascade"): + bitmap_cells[idx1][idx2]["label"] = "A" + elif entry[1].startswith("RamConfig"): + bitmap_cells[idx1][idx2]["label"] = "R" + else: + assert False + bitmap_cells[idx1][idx2]["label"] = '%s' % (idx1, idx2, bitmap_cells[idx1][idx2]["label"]) + + print('') + print("") + for cell_nr in range(len(line)): + print('' % cell_nr) + print("") + for line_nr, line in enumerate(bitmap_cells): + print("") + print('' % line_nr) + for cell in line: + print('' % (cell["bgcolor"], cell["label"])) + print('' % line_nr) + print("") + print("") + for cell_nr in range(len(line)): + print('' % cell_nr) + print("") + print("
%d
B%d%sB%d
%d
") + + print("

Nets and Connectivity

") + + print("""

This section lists all nets in the tile and how this +nets are connected with nets from cells in its neighbourhood.

""") + + grouped_segs = ic.group_segments(set([(tx, ty)])) + groups_indexed = dict() + this_tile_nets = dict() + + for segs in sorted(grouped_segs): + this_segs = list() + neighbour_segs = dict() + for s in segs: + if s[0] == tx and s[1] == ty: + this_segs.append(s[2]) + match = re.match(r"(.*?_)(\d+)(.*)", s[2]) + if match: + this_tile_nets.setdefault(match.group(1) + "*" + match.group(3), set()).add(int(match.group(2))) + else: + this_tile_nets.setdefault(s[2], set()).add(-1) + if (s[0], s[1]) in visible_tiles: + neighbour_segs.setdefault((s[0], s[1]), list()).append(s[2]) + if this_segs: + this_name = ", ".join(sorted(this_segs)) + assert this_name not in groups_indexed + groups_indexed[this_name] = neighbour_segs + + print("

List of nets in %s Tile (%d %d)

" % (tile_type, tx, ty)) + + def net2cat(netname): + cat = (99, "Unsorted") + if netname.startswith("glb_netwk_"): cat = (10, "Global Networks") + if netname.startswith("glb2local_"): cat = (10, "Global Networks") + if netname.startswith("wire_gbuf"): cat = (10, "Global Networks") + if netname.startswith("local_"): cat = (20, "Local Tracks") + if netname.startswith("carry_in"): cat = (25, "Logic Block") + if netname.startswith("io_"): cat = (25, "IO Block") + if netname.startswith("lutff_"): cat = (25, "Logic Block") + if netname.startswith("lutff_0"): cat = (30, "Logic Unit 0") + if netname.startswith("lutff_1"): cat = (30, "Logic Unit 1") + if netname.startswith("lutff_2"): cat = (30, "Logic Unit 2") + if netname.startswith("lutff_3"): cat = (30, "Logic Unit 3") + if netname.startswith("lutff_4"): cat = (30, "Logic Unit 4") + if netname.startswith("lutff_5"): cat = (30, "Logic Unit 5") + if netname.startswith("lutff_6"): cat = (30, "Logic Unit 6") + if netname.startswith("lutff_7"): cat = (30, "Logic Unit 7") + if netname.startswith("neigh_op_"): cat = (40, "Neighbourhood") + if netname.startswith("logic_op_"): cat = (40, "Neighbourhood") + if netname.startswith("sp4_v_"): cat = (50, "Span-4 Vertical") + if netname.startswith("span4_vert_"): cat = (50, "Span-4 Vertical") + if netname.startswith("sp4_r_v_"): cat = (55, "Span-4 Right Vertical") + if netname.startswith("sp4_h_"): cat = (60, "Span-4 Horizontal") + if netname.startswith("span4_horz_"): cat = (60, "Span-4 Horizontal") + if netname.startswith("sp12_v_"): cat = (70, "Span-12 Vertical") + if netname.startswith("span12_vert_"): cat = (70, "Span-12 Vertical") + if netname.startswith("sp12_h_"): cat = (80, "Span-12 Horizontal") + if netname.startswith("span12_horz_"): cat = (80, "Span-12 Horizontal") + return cat + + nets_in_cats = dict() + + for this_name in sorted(this_tile_nets): + nets_in_cats.setdefault(net2cat(this_name), list()).append(this_name) + + for cat in sorted(nets_in_cats): + print('

%s

' % cat[1]) + print('

    ') + for this_name in sorted(nets_in_cats[cat]): + indices = [i for i in this_tile_nets[this_name] if i >= 0] + if -1 in this_tile_nets[this_name]: + print("
  • %s
    • " % this_name) + if len(indices) == 1: + print("
  • %s
    • " % this_name.replace("*", "%d" % indices[0])) + elif len(indices) > 0: + print("
  • %s
    • " % this_name.replace("*", "{" + ",".join(["%d" % i for i in sorted(indices)]) + "}")) + print("

") + + print("

Nets and their permanent connections to nets in neighbour tiles

") + + # print_expand_div("connection details") + + all_cats = set() + for this_name in sorted(groups_indexed): + all_cats.add(net2cat(this_name)) + + for cat in sorted(all_cats): + print('

%s

' % cat[1]) + print('

    ') + for this_name in sorted(groups_indexed): + if net2cat(this_name) == cat: + neighbour_segs = groups_indexed[this_name] + print("
  • %s" % this_name) + if neighbour_segs: + print("
      ") + for nidx in sorted(neighbour_segs): + if nidx == (tx, ty): + print("
    • (%d %d) %s
      • " % (nidx[0], nidx[1], ", ".join(sorted(neighbour_segs[nidx])))) + else: + print("
    • (%d %d) %s
      • " % (nidx[0], nidx[1], ", ".join(sorted(neighbour_segs[nidx])))) + print("
    ") + print("
    • ") + print("

") + + # print_expand_end() + + print("

Routing Configuration

") + + print("""

This section lists the routing configuration bits in the tile. +The entries titled "routing" configure transfer gates, the entries titled +"buffer" configure tri-state drivers.

""") + + grpgrp = dict() + config_groups = dict() + other_config_groups = dict() + + for entry in ic.tile_db(tx, ty): + if not ic.tile_has_entry(tx, ty, entry): + continue + if entry[1] in ("routing", "buffer"): + cfggrp = entry[1] + " " + entry[3] + "," + ",".join(sorted([bit.replace("!", "") for bit in entry[0]])) + config_groups.setdefault(cfggrp, list()).append(entry) + grpgrp.setdefault(net2cat(entry[3]), set()).add(cfggrp) + else: + grp = other_config_groups.setdefault(" ".join(entry[1:]), set()) + for bit in entry[0]: grp.add(bit) + + for cat in sorted(grpgrp): + print('

%s

' % cat[1]) + + bits_in_cat = set() + + for cfggrp in sorted(grpgrp[cat]): + grp = config_groups[cfggrp] + for bit in cfggrp.split(",")[1:]: + match = re.match(r"B(\d+)\[(\d+)\]", bit) + bits_in_cat.add((int(match.group(1)), int(match.group(2)))) + + print('') + print("") + for cell_nr in range(len(bitmap_cells[0])): + print('' % cell_nr) + print("") + for line_nr, line in enumerate(bitmap_cells): + print("") + print('' % line_nr) + for cell_nr, cell in enumerate(line): + color = cell["bgcolor"] + if (line_nr, cell_nr) not in bits_in_cat: color="#aaa" + print('' % (color, cell["label"])) + print('' % line_nr) + print("") + print("") + for cell_nr in range(len(line)): + print('' % cell_nr) + print("") + print("
%d
B%d%sB%d
%d
") + + # print_expand_div("details") + + src_nets = set() + dst_nets = set() + links = dict() + + for cfggrp in sorted(grpgrp[cat]): + grp = config_groups[cfggrp] + for entry in grp: + src_nets.add(entry[2]) + dst_nets.add(entry[3]) + if entry[1] == "buffer": + assert (entry[2], entry[3]) not in links + links[(entry[2], entry[3])] = 'B' + else: + assert (entry[2], entry[3]) not in links + links[(entry[2], entry[3])] = 'R' + + print('
Connectivity Matrix
') + print('') + dst_net_prefix = "" + dst_net_list = sorted(dst_nets, icebox.cmp_netnames) + if len(dst_net_list) > 1: + while len(set([n[0] for n in dst_net_list])) == 1: + dst_net_prefix += dst_net_list[0][0] + for i in range(len(dst_net_list)): + dst_net_list[i] = dst_net_list[i][1:] + while dst_net_prefix != "" and dst_net_prefix[-1] != "_": + for i in range(len(dst_net_list)): + dst_net_list[i] = dst_net_prefix[-1] + dst_net_list[i] + dst_net_prefix = dst_net_prefix[0:-1] + print('' % (len(dst_net_list), dst_net_prefix)) + print('') + for dn in dst_net_list: + print('' % dn) + print("") + for sn in sorted(src_nets, icebox.cmp_netnames): + print("") + print('' % sn) + for dn in sorted(dst_nets, icebox.cmp_netnames): + if (sn, dn) in links: + print(links[(sn, dn)]) + else: + print('') + print("") + print("
%s
%s
%s 
") + + print('
Configuration Stamps
') + for cfggrp in sorted(grpgrp[cat]): + grp = config_groups[cfggrp] + bits = cfggrp.split(",")[1:] + print('

') + for bit in bits: + print('' % (re.sub(r"B(\d+)\[(\d+)\]", r"B.\1.\2", bit), bit)) + group_lines = list() + is_buffer = True + for entry in grp: + line = '' + for bit in bits: + if bit in entry[0]: + line += '' + else: + line += '' + is_buffer = entry[1] == "buffer" + line += '' % (entry[1], entry[2], entry[3]) + group_lines.append(line) + if is_buffer: + print('') + else: + print('') + for line in sorted(group_lines): + print(line) + print('
%s
10%s%s%s
FunctionSource-NetDestination-Net
FunctionNetNet

') + + # print_expand_end() + + print("

Non-routing Configuration

") + + print("

This section lists the non-routing configuration bits in the tile.

") + + print('') + print("") + for cell_nr in range(len(bitmap_cells[0])): + print('' % cell_nr) + print("") + for line_nr, line in enumerate(bitmap_cells): + print("") + print('' % line_nr) + for cell_nr, cell in enumerate(line): + color = cell["bgcolor"] + if "is_routing" in cell: color="#aaa" + print('' % (color, cell["label"])) + print('' % line_nr) + print("") + print("") + for cell_nr in range(len(line)): + print('' % cell_nr) + print("") + print("
%d
B%d%sB%d
%d
") + + print('

') + for cfggrp in sorted(other_config_groups): + bits = " ".join(['%s' % (re.sub(r"B(\d+)\[(\d+)\]", r"B.\1.\2", bit), bit) for bit in sorted(other_config_groups[cfggrp])]) + cfggrp = cfggrp.replace(" " + list(other_config_groups[cfggrp])[0], "") + print('' % (cfggrp, bits)) + print('
FunctionBits
%s%s

') + + +if outdir is not None: + stdout = sys.stdout + + if not os.path.exists(outdir): + print("Creating %s/" % outdir, file=stdout) + os.makedirs(outdir) + + print("Writing %s/index.html.." % outdir, file=stdout) + sys.stdout = open("%s/index.html" % outdir, "w") + print_index() + + for x in range(ic.max_x+1): + for y in range(ic.max_y+1): + if (x, y) in mktiles: + print("Writing %s/tile_%d_%d.html.." % (outdir, x, y), file=stdout) + sys.stdout = open("%s/tile_%d_%d.html" % (outdir, x, y), "w") + print_tile(x, y) + + print("Writing %s/chipdb.txt..." % outdir, file=stdout) + os.system("python icebox_chipdb.py > %s/chipdb.txt" % outdir) + + sys.stdout = stdout + +elif (tx, ty) == (0, 0): + print_index() + +else: + print_tile(tx, ty) + diff --git a/icebox/icebox_maps.py b/icebox/icebox_maps.py new file mode 100755 index 0000000..81ce919 --- /dev/null +++ b/icebox/icebox_maps.py @@ -0,0 +1,152 @@ +#!/usr/bin/python +# +# Copyright (C) 2015 Clifford Wolf +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +from __future__ import division +from __future__ import print_function + +import icebox +import getopt, sys, re + +mode = None + +def usage(): + print("Usage:") + print(" icebox_maps -m bitmaps") + print(" icebox_maps -m io_tile_nets_l") + print(" icebox_maps -m io_tile_nets_r") + print(" icebox_maps -m io_tile_nets_t") + print(" icebox_maps -m io_tile_nets_b") + print(" icebox_maps -m logic_tile_nets") + print(" icebox_maps -m ram_tile_nets") + sys.exit(0) + +try: + opts, args = getopt.getopt(sys.argv[1:], "m:") +except: + usage() + +for o, a in opts: + if o == "-m": + mode = a.strip() + else: + usage() + +def get_bit_group(x, y, db): + bit = "B%d[%d]" % (y, x) + nbit = "!B%d[%d]" % (y, x) + funcs = set() + for entry in db: + if bit in entry[0] or nbit in entry[0]: + if entry[1] in ("IOB_0", "IOB_1", "IoCtrl"): + funcs.add("i") + elif entry[1] == "routing": + funcs.add("r") + elif entry[1] == "buffer": + funcs.add("b") + elif re.match("LC_", entry[1]): + funcs.add("l") + elif entry[1] == "NegClk": + funcs.add("N") + elif entry[1] == "ColBufCtrl": + funcs.add("o") + elif entry[1] == "CarryInSet": + funcs.add("C") + elif entry[1] == "Cascade": + funcs.add("a") + else: + funcs.add("?") + if len(funcs) == 1: + return funcs.pop() + if len(funcs) > 1: + return "X" + return "-" + +def print_tilemap(stmt, db, n): + print() + print(stmt) + for y in range(16): + for x in range(n): + print(get_bit_group(x, y, db), end="") + print() + +def print_db_nets(stmt, db, pos): + print() + print(stmt, end="") + netnames = set() + for entry in db: + if entry[1] in ("routing", "buffer"): + if icebox.pos_has_net(pos[0], entry[2]): netnames.add(entry[2]) + if icebox.pos_has_net(pos[0], entry[3]): netnames.add(entry[3]) + last_prefix = "" + for net in sorted(netnames, icebox.cmp_netnames): + match = re.match(r"(.*?)(\d+)$", net) + if match: + if last_prefix == match.group(1): + print(",%s" % match.group(2), end="") + else: + print() + print(net, end="") + last_prefix = match.group(1) + else: + print() + print(net, end="") + last_prefix = "*" + print() + +if mode == "bitmaps": + print_tilemap(".io_tile_bitmap_l", icebox.iotile_l_db, 18) + print_tilemap(".io_tile_bitmap_r", icebox.iotile_r_db, 18) + print_tilemap(".io_tile_bitmap_t", icebox.iotile_t_db, 18) + print_tilemap(".io_tile_bitmap_b", icebox.iotile_b_db, 18) + print_tilemap(".logic_tile_bitmap", icebox.logictile_db, 54) + print_tilemap(".ram_tile_bitmap", icebox.ramtile_db, 42) + print() + print(".bitmap_legend") + print("- ... unknown bit") + print("? ... unknown bit type") + print("X ... database conflict") + print("i ... IOB_0 IOB_1 IoCtrl") + print("a ... Carry_In_Mux Cascade") + print("r ... routing") + print("b ... buffer") + print("l ... logic bits") + print("o ... ColBufCtrl") + print("C ... CarryInSet") + print("N ... NegClk") + print() + +elif mode == "io_tile_nets_l": + print_db_nets(".io_tile_nets_l", icebox.iotile_l_db, "l") + +elif mode == "io_tile_nets_r": + print_db_nets(".io_tile_nets_r", icebox.iotile_r_db, "r") + +elif mode == "io_tile_nets_t": + print_db_nets(".io_tile_nets_t", icebox.iotile_t_db, "t") + +elif mode == "io_tile_nets_b": + print_db_nets(".io_tile_nets_b", icebox.iotile_b_db, "b") + +elif mode == "logic_tile_nets": + print_db_nets(".logic_tile_nets", icebox.logictile_db, "c") + +elif mode == "ram_tile_nets": + print_db_nets(".ram_tile_nets", icebox.ramtile_db, "c") + +else: + usage() + diff --git a/icebox/icebox_vlog.py b/icebox/icebox_vlog.py new file mode 100755 index 0000000..ded96a6 --- /dev/null +++ b/icebox/icebox_vlog.py @@ -0,0 +1,367 @@ +#!/usr/bin/python +# +# Copyright (C) 2015 Clifford Wolf +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +from __future__ import division +from __future__ import print_function + +import icebox +import getopt, sys, re + +strip_comments = False +strip_interconn = False +lookup_pins = False +pcf_data = dict() +portnames = set() +unmatched_ports = set() +auto_clk = False +auto_en = False + +def usage(): + print(""" +Usage: icebox_vlog [options] + + -s + strip comments from output + + -S + strip comments about interconn wires from output + + -a + auto-detect global clock and enable signals + (require ports "clk" and "en" in pcf file) + + -l + convert io tile port names to chip pin numbers + + -p + use the set_io command from the specified pcf file + + -P + like -p, enable some hacks for pcf files created + by the iCEcube2 placer. +""") + sys.exit(0) + +try: + opts, args = getopt.getopt(sys.argv[1:], "sSlap:P:") +except: + usage() + +for o, a in opts: + if o == "-s": + strip_comments = True + elif o == "-S": + strip_interconn = True + elif o == "-l": + lookup_pins = True + elif o == "-a": + auto_clk = True + auto_en = True + elif o in ("-p", "-P"): + with open(a, "r") as f: + for line in f: + line = re.sub(r"#.*", "", line.strip()).split() + if len(line) and line[0] == "set_io": + p = line[1] + if o == "-P": + p = p.lower() + p = p.replace("_ibuf", "") + p = p.replace("_obuf", "") + p = p.replace("_gb_io", "") + portnames.add(p) + if not re.match(r"[a-zA-Z_][a-zA-Z0-9_]*$", p): + p = "\\%s " % p + unmatched_ports.add(p) + pinloc = tuple([int(s) for s in line[2:]]) + pcf_data[pinloc] = p + else: + usage() + +if not strip_comments: + print("// Reading file '%s'.." % args[0]) +ic = icebox.iceconfig() +ic.read_file(args[0]) +print() + +text_wires = list() +text_ports = list() + +luts_queue = set() +text_func = list() + +netidx = [0] +nets = dict() +seg2net = dict() + +auto_clk_nets = set() +auto_en_nets = set() + +def is_interconn(netname): + if netname.startswith("sp4_"): return True + if netname.startswith("sp12_"): return True + if netname.startswith("span4_"): return True + if netname.startswith("span12_"): return True + if netname.startswith("logic_op_"): return True + if netname.startswith("neigh_op_"): return True + if netname.startswith("local_"): return True + return False + +for segs in sorted(ic.group_segments()): + while True: + netidx[0] += 1 + n = "n%d" % netidx[0] + if n not in portnames: break + + net_segs = set() + renamed_net_to_port = False + + for s in segs: + match = re.match("io_(\d+)/D_(IN|OUT)_(\d+)$", s[2]) + if match: + if match.group(2) == "IN": + p = "io_%d_%d_%s_din_%s" % (s[0], s[1], match.group(1), match.group(3)) + net_segs.add(p) + else: + p = "io_%d_%d_%s_dout_%s" % (s[0], s[1], match.group(1), match.group(3)) + net_segs.add(p) + if lookup_pins or pcf_data: + for entry in icebox.pinloc_db: + if s[0] == entry[1] and s[1] == entry[2] and int(match.group(1)) == entry[3]: + if (entry[0],) in pcf_data: + p = pcf_data[(entry[0],)] + unmatched_ports.discard(p) + elif (entry[1], entry[2], entry[3]) in pcf_data: + p = pcf_data[(entry[1], entry[2], entry[3])] + unmatched_ports.discard(p) + elif lookup_pins: + p = "pin_%d" % entry[0] + if p == "clk": + auto_clk = False + if p == "en": + auto_en = False + if not renamed_net_to_port: + n = p + if match.group(2) == "IN": + text_ports.append("input %s" % p) + else: + text_ports.append("output %s" % p) + text_wires.append("wire %s;" % n) + renamed_net_to_port = True + elif match.group(2) == "IN": + text_ports.append("input %s" % p) + text_wires.append("assign %s = %s;" % (n, p)) + else: + text_ports.append("output %s" % p) + text_wires.append("assign %s = %s;" % (p, n)) + + match = re.match("lutff_(\d+)/", s[2]) + if match: + luts_queue.add((s[0], s[1], int(match.group(1)))) + + nets[n] = segs + + for s in segs: + seg2net[s] = n + + if not renamed_net_to_port: + text_wires.append("wire %s;" % n) + + for s in segs: + if not strip_interconn or not is_interconn(s[2]): + if s[2].startswith("glb_netwk_"): + net_segs.add((0, 0, s[2])) + else: + net_segs.add(s) + + if not renamed_net_to_port: + has_clk = False + has_cen = False + has_global = False + has_driver = False + for s in sorted(net_segs): + if s[2].startswith("glb_netwk_"): + has_global = True + elif re.search(r"/out", s[2]): + has_driver = True + elif s[2] == "lutff_global/clk": + has_clk = True + elif s[2] == "lutff_global/cen": + has_cen = True + if has_global and not has_driver: + if has_clk: + auto_clk_nets.add(n) + if has_cen and not has_clk: + auto_en_nets.add(n) + + if not strip_comments: + for s in sorted(net_segs): + text_wires.append("// %s" % (s,)) + text_wires.append("") + +for p in unmatched_ports: + text_ports.append("input %s" % p) + +if auto_clk and auto_clk_nets and "clk" in unmatched_ports: + assert len(auto_clk_nets) == 1 + if not strip_comments: + text_wires.append("// automatically detected clock network") + text_wires.append("assign %s = clk;" % auto_clk_nets.pop()) + if not strip_comments: + text_wires.append("") + unmatched_ports.remove("clk") + +if auto_en and auto_en_nets and "en" in unmatched_ports: + assert len(auto_en_nets) == 1 + if not strip_comments: + text_wires.append("// automatically detected enable network") + text_wires.append("assign %s = en;" % auto_en_nets.pop()) + if not strip_comments: + text_wires.append("") + unmatched_ports.remove("en") + +def seg_to_net(seg, default=None): + if seg not in seg2net: + if default is not None: + return default + while True: + netidx[0] += 1 + n = "n%d" % netidx[0] + if n not in portnames: break + nets[n] = set([seg]) + seg2net[seg] = n + text_wires.append("wire %s;" % n) + if not strip_comments: + if not strip_interconn or not is_interconn(seg[2]): + text_wires.append("// %s" % (seg,)) + text_wires.append("") + return seg2net[seg] + +wire_to_reg = set() +lut_assigns = list() +const_assigns = list() +carry_assigns = list() +always_stmts = list() +max_net_len = 0 + +for lut in luts_queue: + seq_bits = icebox.get_lutff_seq_bits(ic.logic_tiles[(lut[0], lut[1])], lut[2]) + if seq_bits[0] == "1": + seg_to_net((lut[0], lut[1], "lutff_%d/cout" % lut[2])) + +for lut in luts_queue: + tile = ic.logic_tiles[(lut[0], lut[1])] + lut_bits = icebox.get_lutff_lut_bits(tile, lut[2]) + seq_bits = icebox.get_lutff_seq_bits(tile, lut[2]) + net_in0 = seg_to_net((lut[0], lut[1], "lutff_%d/in_0" % lut[2]), "0") + net_in1 = seg_to_net((lut[0], lut[1], "lutff_%d/in_1" % lut[2]), "0") + net_in2 = seg_to_net((lut[0], lut[1], "lutff_%d/in_2" % lut[2]), "0") + net_in3 = seg_to_net((lut[0], lut[1], "lutff_%d/in_3" % lut[2]), "0") + net_out = seg_to_net((lut[0], lut[1], "lutff_%d/out" % lut[2])) + if seq_bits[0] == "1": + net_cout = seg_to_net((lut[0], lut[1], "lutff_%d/cout" % lut[2])) + net_in1 = seg_to_net((lut[0], lut[1], "lutff_%d/in_1" % lut[2]), "0") + net_in2 = seg_to_net((lut[0], lut[1], "lutff_%d/in_2" % lut[2]), "0") + if lut[2] == 0: + net_cin = seg_to_net((lut[0], lut[1], "carry_in_mux")) + if icebox.get_carry_cascade_bit(tile) == "0": + if not strip_comments: + text_wires.append("// Carry-In for (%d %d)" % (lut[0], lut[1])) + text_wires.append("assign %s = %s;" % (net_cin, icebox.get_carry_bit(tile))) + if not strip_comments: + text_wires.append("") + else: + net_cin = seg_to_net((lut[0], lut[1], "lutff_%d/cout" % (lut[2]-1)), "0") + carry_assigns.append([net_cout, "/* CARRY %2d %2d %2d */ (%s & %s) | ((%s | %s) & %s)" % + (lut[0], lut[1], lut[2], net_in1, net_in2, net_in1, net_in2, net_cin)]) + if seq_bits[1] == "1": + while True: + netidx[0] += 1 + n = "n%d" % netidx[0] + if n not in portnames: break + text_wires.append("wire %s;" % n) + if not strip_comments: + text_wires.append("// FF %s" % (lut,)) + text_wires.append("") + net_cen = seg_to_net((lut[0], lut[1], "lutff_global/cen"), "1") + net_clk = seg_to_net((lut[0], lut[1], "lutff_global/clk"), "0") + net_sr = seg_to_net((lut[0], lut[1], "lutff_global/s_r"), "0") + if seq_bits[3] == "0": + always_stmts.append("/* FF %2d %2d %2d */ always @(%sedge %s) if (%s) %s <= %s ? %s : %s;" % + (lut[0], lut[1], lut[2], "neg" if icebox.get_negclk_bit(tile) == "1" else "pos", + net_clk, net_cen, net_out, net_sr, seq_bits[2], n)) + else: + always_stmts.append("/* FF %2d %2d %2d */ always @(%sedge %s, posedge %s) if (%s) %s <= %s; else if (%s) %s <= %s;" % + (lut[0], lut[1], lut[2], "neg" if icebox.get_negclk_bit(tile) == "1" else "pos", + net_clk, net_sr, net_sr, net_out, seq_bits[2], net_cen, net_out, n)) + wire_to_reg.add(net_out) + net_out = n + if not "1" in lut_bits: + const_assigns.append([net_out, "1'b0"]) + elif not "0" in lut_bits: + const_assigns.append([net_out, "1'b1"]) + else: + def make_lut_expr(bits, sigs): + if not sigs: + return "%s" % bits[0] + l_expr = make_lut_expr(bits[0:len(bits)//2], sigs[1:]) + h_expr = make_lut_expr(bits[len(bits)//2:len(bits)], sigs[1:]) + if h_expr == l_expr: return h_expr + if sigs[0] == "0": return l_expr + if sigs[0] == "1": return h_expr + if h_expr == "1" and l_expr == "0": return sigs[0] + if h_expr == "0" and l_expr == "1": return "!" + sigs[0] + return "%s ? %s : %s" % (sigs[0], h_expr, l_expr) + lut_expr = make_lut_expr(lut_bits, [net_in3, net_in2, net_in1, net_in0]) + lut_assigns.append([net_out, "/* LUT %2d %2d %2d */ %s" % (lut[0], lut[1], lut[2], lut_expr)]) + max_net_len = max(max_net_len, len(net_out)) + +for a in const_assigns + lut_assigns + carry_assigns: + text_func.append("assign %-*s = %s;" % (max_net_len, a[0], a[1])) + +print("module chip (%s);\n" % ", ".join(text_ports)) + +new_text_wires = list() +for line in text_wires: + match = re.match(r"wire ([^ ;]+)(.*)", line) + if match and match.group(1) in wire_to_reg: + line = "reg " + match.group(1) + match.group(2) + if strip_comments: + if new_text_wires and new_text_wires[-1].split()[0] == line.split()[0] and new_text_wires[-1][-1] == ";": + new_text_wires[-1] = new_text_wires[-1][0:-1] + "," + line[len(line.split()[0]):] + else: + new_text_wires.append(line) + else: + print(line) +for line in new_text_wires: + print(line) +if strip_comments: + print() + +for line in text_func: + print(line) +for line in always_stmts: + print(line) +print() + +for p in unmatched_ports: + print("// Warning: unmatched port '%s'" %p) +if unmatched_ports: + print() + +print("endmodule") +print() + diff --git a/icebox/iceboxdb.py b/icebox/iceboxdb.py new file mode 100644 index 0000000..dd4e0c7 --- /dev/null +++ b/icebox/iceboxdb.py @@ -0,0 +1,2985 @@ +database_io_txt = """ +B1[9] ColBufCtrl IO_half_column_clock_enable_0 B1[9] +B0[9] ColBufCtrl IO_half_column_clock_enable_1 B0[9] +B3[9] ColBufCtrl IO_half_column_clock_enable_2 B3[9] +B2[9] ColBufCtrl IO_half_column_clock_enable_3 B2[9] +B5[9] ColBufCtrl IO_half_column_clock_enable_4 B5[9] +B4[9] ColBufCtrl IO_half_column_clock_enable_5 B4[9] +B7[9] ColBufCtrl IO_half_column_clock_enable_6 B7[9] +B6[9] ColBufCtrl IO_half_column_clock_enable_7 B6[9] +B3[17] IOB_0 PINTYPE_0 +B3[16] IOB_0 PINTYPE_1 +B0[17] IOB_0 PINTYPE_2 +B0[16] IOB_0 PINTYPE_3 +B4[16] IOB_0 PINTYPE_4 +B4[17] IOB_0 PINTYPE_5 +B13[17] IOB_1 PINTYPE_0 +B13[16] IOB_1 PINTYPE_1 +B10[17] IOB_1 PINTYPE_2 +B10[16] IOB_1 PINTYPE_3 +B14[16] IOB_1 PINTYPE_4 +B14[17] IOB_1 PINTYPE_5 +B9[3] IoCtrl IE_0 +B6[3] IoCtrl IE_1 +B6[2] IoCtrl REN_0 +B1[3] IoCtrl REN_1 +B9[13],B15[13] NegClk +B0[4],!B1[4],!B1[5],!B1[6],B1[7] buffer IO_B.logic_op_tnl_0 lc_trk_g0_0 +B8[4],!B9[4],!B9[5],!B9[6],B9[7] buffer IO_B.logic_op_tnl_0 lc_trk_g1_0 +!B0[5],!B0[6],B0[7],B0[8],!B1[8] buffer IO_B.logic_op_tnl_1 lc_trk_g0_1 +!B8[5],!B8[6],B8[7],B8[8],!B9[8] buffer IO_B.logic_op_tnl_1 lc_trk_g1_1 +B2[4],!B3[4],!B3[5],!B3[6],B3[7] buffer IO_B.logic_op_tnl_2 lc_trk_g0_2 +B10[4],!B11[4],!B11[5],!B11[6],B11[7] buffer IO_B.logic_op_tnl_2 lc_trk_g1_2 +!B2[5],!B2[6],B2[7],B2[8],!B3[8] buffer IO_B.logic_op_tnl_3 lc_trk_g0_3 +!B10[5],!B10[6],B10[7],B10[8],!B11[8] buffer IO_B.logic_op_tnl_3 lc_trk_g1_3 +B4[4],!B5[4],!B5[5],!B5[6],B5[7] buffer IO_B.logic_op_tnl_4 lc_trk_g0_4 +B12[4],!B13[4],!B13[5],!B13[6],B13[7] buffer IO_B.logic_op_tnl_4 lc_trk_g1_4 +!B4[5],!B4[6],B4[7],B4[8],!B5[8] buffer IO_B.logic_op_tnl_5 lc_trk_g0_5 +!B12[5],!B12[6],B12[7],B12[8],!B13[8] buffer IO_B.logic_op_tnl_5 lc_trk_g1_5 +B6[4],!B7[4],!B7[5],!B7[6],B7[7] buffer IO_B.logic_op_tnl_6 lc_trk_g0_6 +B14[4],!B15[4],!B15[5],!B15[6],B15[7] buffer IO_B.logic_op_tnl_6 lc_trk_g1_6 +!B6[5],!B6[6],B6[7],B6[8],!B7[8] buffer IO_B.logic_op_tnl_7 lc_trk_g0_7 +!B14[5],!B14[6],B14[7],B14[8],!B15[8] buffer IO_B.logic_op_tnl_7 lc_trk_g1_7 +!B0[4],!B1[4],B1[5],!B1[6],B1[7] buffer IO_B.logic_op_tnr_0 lc_trk_g0_0 +!B8[4],!B9[4],B9[5],!B9[6],B9[7] buffer IO_B.logic_op_tnr_0 lc_trk_g1_0 +B0[5],!B0[6],B0[7],!B0[8],!B1[8] buffer IO_B.logic_op_tnr_1 lc_trk_g0_1 +B8[5],!B8[6],B8[7],!B8[8],!B9[8] buffer IO_B.logic_op_tnr_1 lc_trk_g1_1 +!B2[4],!B3[4],B3[5],!B3[6],B3[7] buffer IO_B.logic_op_tnr_2 lc_trk_g0_2 +!B10[4],!B11[4],B11[5],!B11[6],B11[7] buffer IO_B.logic_op_tnr_2 lc_trk_g1_2 +B2[5],!B2[6],B2[7],!B2[8],!B3[8] buffer IO_B.logic_op_tnr_3 lc_trk_g0_3 +B10[5],!B10[6],B10[7],!B10[8],!B11[8] buffer IO_B.logic_op_tnr_3 lc_trk_g1_3 +!B4[4],!B5[4],B5[5],!B5[6],B5[7] buffer IO_B.logic_op_tnr_4 lc_trk_g0_4 +!B12[4],!B13[4],B13[5],!B13[6],B13[7] buffer IO_B.logic_op_tnr_4 lc_trk_g1_4 +B4[5],!B4[6],B4[7],!B4[8],!B5[8] buffer IO_B.logic_op_tnr_5 lc_trk_g0_5 +B12[5],!B12[6],B12[7],!B12[8],!B13[8] buffer IO_B.logic_op_tnr_5 lc_trk_g1_5 +!B6[4],!B7[4],B7[5],!B7[6],B7[7] buffer IO_B.logic_op_tnr_6 lc_trk_g0_6 +!B14[4],!B15[4],B15[5],!B15[6],B15[7] buffer IO_B.logic_op_tnr_6 lc_trk_g1_6 +B6[5],!B6[6],B6[7],!B6[8],!B7[8] buffer IO_B.logic_op_tnr_7 lc_trk_g0_7 +B14[5],!B14[6],B14[7],!B14[8],!B15[8] buffer IO_B.logic_op_tnr_7 lc_trk_g1_7 +B0[4],B1[4],!B1[5],!B1[6],B1[7] buffer IO_B.logic_op_top_0 lc_trk_g0_0 +B8[4],B9[4],!B9[5],!B9[6],B9[7] buffer IO_B.logic_op_top_0 lc_trk_g1_0 +!B0[5],!B0[6],B0[7],B0[8],B1[8] buffer IO_B.logic_op_top_1 lc_trk_g0_1 +!B8[5],!B8[6],B8[7],B8[8],B9[8] buffer IO_B.logic_op_top_1 lc_trk_g1_1 +B2[4],B3[4],!B3[5],!B3[6],B3[7] buffer IO_B.logic_op_top_2 lc_trk_g0_2 +B10[4],B11[4],!B11[5],!B11[6],B11[7] buffer IO_B.logic_op_top_2 lc_trk_g1_2 +!B2[5],!B2[6],B2[7],B2[8],B3[8] buffer IO_B.logic_op_top_3 lc_trk_g0_3 +!B10[5],!B10[6],B10[7],B10[8],B11[8] buffer IO_B.logic_op_top_3 lc_trk_g1_3 +B4[4],B5[4],!B5[5],!B5[6],B5[7] buffer IO_B.logic_op_top_4 lc_trk_g0_4 +B12[4],B13[4],!B13[5],!B13[6],B13[7] buffer IO_B.logic_op_top_4 lc_trk_g1_4 +!B4[5],!B4[6],B4[7],B4[8],B5[8] buffer IO_B.logic_op_top_5 lc_trk_g0_5 +!B12[5],!B12[6],B12[7],B12[8],B13[8] buffer IO_B.logic_op_top_5 lc_trk_g1_5 +B6[4],B7[4],!B7[5],!B7[6],B7[7] buffer IO_B.logic_op_top_6 lc_trk_g0_6 +B14[4],B15[4],!B15[5],!B15[6],B15[7] buffer IO_B.logic_op_top_6 lc_trk_g1_6 +!B6[5],!B6[6],B6[7],B6[8],B7[8] buffer IO_B.logic_op_top_7 lc_trk_g0_7 +!B14[5],!B14[6],B14[7],B14[8],B15[8] buffer IO_B.logic_op_top_7 lc_trk_g1_7 +!B0[4],!B1[4],B1[5],!B1[6],B1[7] buffer IO_L.logic_op_bnr_0 lc_trk_g0_0 +!B8[4],!B9[4],B9[5],!B9[6],B9[7] buffer IO_L.logic_op_bnr_0 lc_trk_g1_0 +B0[5],!B0[6],B0[7],!B0[8],!B1[8] buffer IO_L.logic_op_bnr_1 lc_trk_g0_1 +B8[5],!B8[6],B8[7],!B8[8],!B9[8] buffer IO_L.logic_op_bnr_1 lc_trk_g1_1 +!B2[4],!B3[4],B3[5],!B3[6],B3[7] buffer IO_L.logic_op_bnr_2 lc_trk_g0_2 +!B10[4],!B11[4],B11[5],!B11[6],B11[7] buffer IO_L.logic_op_bnr_2 lc_trk_g1_2 +B2[5],!B2[6],B2[7],!B2[8],!B3[8] buffer IO_L.logic_op_bnr_3 lc_trk_g0_3 +B10[5],!B10[6],B10[7],!B10[8],!B11[8] buffer IO_L.logic_op_bnr_3 lc_trk_g1_3 +!B4[4],!B5[4],B5[5],!B5[6],B5[7] buffer IO_L.logic_op_bnr_4 lc_trk_g0_4 +!B12[4],!B13[4],B13[5],!B13[6],B13[7] buffer IO_L.logic_op_bnr_4 lc_trk_g1_4 +B4[5],!B4[6],B4[7],!B4[8],!B5[8] buffer IO_L.logic_op_bnr_5 lc_trk_g0_5 +B12[5],!B12[6],B12[7],!B12[8],!B13[8] buffer IO_L.logic_op_bnr_5 lc_trk_g1_5 +!B6[4],!B7[4],B7[5],!B7[6],B7[7] buffer IO_L.logic_op_bnr_6 lc_trk_g0_6 +!B14[4],!B15[4],B15[5],!B15[6],B15[7] buffer IO_L.logic_op_bnr_6 lc_trk_g1_6 +B6[5],!B6[6],B6[7],!B6[8],!B7[8] buffer IO_L.logic_op_bnr_7 lc_trk_g0_7 +B14[5],!B14[6],B14[7],!B14[8],!B15[8] buffer IO_L.logic_op_bnr_7 lc_trk_g1_7 +B0[4],B1[4],!B1[5],!B1[6],B1[7] buffer IO_L.logic_op_rgt_0 lc_trk_g0_0 +B8[4],B9[4],!B9[5],!B9[6],B9[7] buffer IO_L.logic_op_rgt_0 lc_trk_g1_0 +!B0[5],!B0[6],B0[7],B0[8],B1[8] buffer IO_L.logic_op_rgt_1 lc_trk_g0_1 +!B8[5],!B8[6],B8[7],B8[8],B9[8] buffer IO_L.logic_op_rgt_1 lc_trk_g1_1 +B2[4],B3[4],!B3[5],!B3[6],B3[7] buffer IO_L.logic_op_rgt_2 lc_trk_g0_2 +B10[4],B11[4],!B11[5],!B11[6],B11[7] buffer IO_L.logic_op_rgt_2 lc_trk_g1_2 +!B2[5],!B2[6],B2[7],B2[8],B3[8] buffer IO_L.logic_op_rgt_3 lc_trk_g0_3 +!B10[5],!B10[6],B10[7],B10[8],B11[8] buffer IO_L.logic_op_rgt_3 lc_trk_g1_3 +B4[4],B5[4],!B5[5],!B5[6],B5[7] buffer IO_L.logic_op_rgt_4 lc_trk_g0_4 +B12[4],B13[4],!B13[5],!B13[6],B13[7] buffer IO_L.logic_op_rgt_4 lc_trk_g1_4 +!B4[5],!B4[6],B4[7],B4[8],B5[8] buffer IO_L.logic_op_rgt_5 lc_trk_g0_5 +!B12[5],!B12[6],B12[7],B12[8],B13[8] buffer IO_L.logic_op_rgt_5 lc_trk_g1_5 +B6[4],B7[4],!B7[5],!B7[6],B7[7] buffer IO_L.logic_op_rgt_6 lc_trk_g0_6 +B14[4],B15[4],!B15[5],!B15[6],B15[7] buffer IO_L.logic_op_rgt_6 lc_trk_g1_6 +!B6[5],!B6[6],B6[7],B6[8],B7[8] buffer IO_L.logic_op_rgt_7 lc_trk_g0_7 +!B14[5],!B14[6],B14[7],B14[8],B15[8] buffer IO_L.logic_op_rgt_7 lc_trk_g1_7 +B0[4],!B1[4],!B1[5],!B1[6],B1[7] buffer IO_L.logic_op_tnr_0 lc_trk_g0_0 +B8[4],!B9[4],!B9[5],!B9[6],B9[7] buffer IO_L.logic_op_tnr_0 lc_trk_g1_0 +!B0[5],!B0[6],B0[7],B0[8],!B1[8] buffer IO_L.logic_op_tnr_1 lc_trk_g0_1 +!B8[5],!B8[6],B8[7],B8[8],!B9[8] buffer IO_L.logic_op_tnr_1 lc_trk_g1_1 +B2[4],!B3[4],!B3[5],!B3[6],B3[7] buffer IO_L.logic_op_tnr_2 lc_trk_g0_2 +B10[4],!B11[4],!B11[5],!B11[6],B11[7] buffer IO_L.logic_op_tnr_2 lc_trk_g1_2 +!B2[5],!B2[6],B2[7],B2[8],!B3[8] buffer IO_L.logic_op_tnr_3 lc_trk_g0_3 +!B10[5],!B10[6],B10[7],B10[8],!B11[8] buffer IO_L.logic_op_tnr_3 lc_trk_g1_3 +B4[4],!B5[4],!B5[5],!B5[6],B5[7] buffer IO_L.logic_op_tnr_4 lc_trk_g0_4 +B12[4],!B13[4],!B13[5],!B13[6],B13[7] buffer IO_L.logic_op_tnr_4 lc_trk_g1_4 +!B4[5],!B4[6],B4[7],B4[8],!B5[8] buffer IO_L.logic_op_tnr_5 lc_trk_g0_5 +!B12[5],!B12[6],B12[7],B12[8],!B13[8] buffer IO_L.logic_op_tnr_5 lc_trk_g1_5 +B6[4],!B7[4],!B7[5],!B7[6],B7[7] buffer IO_L.logic_op_tnr_6 lc_trk_g0_6 +B14[4],!B15[4],!B15[5],!B15[6],B15[7] buffer IO_L.logic_op_tnr_6 lc_trk_g1_6 +!B6[5],!B6[6],B6[7],B6[8],!B7[8] buffer IO_L.logic_op_tnr_7 lc_trk_g0_7 +!B14[5],!B14[6],B14[7],B14[8],!B15[8] buffer IO_L.logic_op_tnr_7 lc_trk_g1_7 +!B0[4],!B1[4],B1[5],!B1[6],B1[7] buffer IO_R.logic_op_bnl_0 lc_trk_g0_0 +!B8[4],!B9[4],B9[5],!B9[6],B9[7] buffer IO_R.logic_op_bnl_0 lc_trk_g1_0 +B0[5],!B0[6],B0[7],!B0[8],!B1[8] buffer IO_R.logic_op_bnl_1 lc_trk_g0_1 +B8[5],!B8[6],B8[7],!B8[8],!B9[8] buffer IO_R.logic_op_bnl_1 lc_trk_g1_1 +!B2[4],!B3[4],B3[5],!B3[6],B3[7] buffer IO_R.logic_op_bnl_2 lc_trk_g0_2 +!B10[4],!B11[4],B11[5],!B11[6],B11[7] buffer IO_R.logic_op_bnl_2 lc_trk_g1_2 +B2[5],!B2[6],B2[7],!B2[8],!B3[8] buffer IO_R.logic_op_bnl_3 lc_trk_g0_3 +B10[5],!B10[6],B10[7],!B10[8],!B11[8] buffer IO_R.logic_op_bnl_3 lc_trk_g1_3 +!B4[4],!B5[4],B5[5],!B5[6],B5[7] buffer IO_R.logic_op_bnl_4 lc_trk_g0_4 +!B12[4],!B13[4],B13[5],!B13[6],B13[7] buffer IO_R.logic_op_bnl_4 lc_trk_g1_4 +B4[5],!B4[6],B4[7],!B4[8],!B5[8] buffer IO_R.logic_op_bnl_5 lc_trk_g0_5 +B12[5],!B12[6],B12[7],!B12[8],!B13[8] buffer IO_R.logic_op_bnl_5 lc_trk_g1_5 +!B6[4],!B7[4],B7[5],!B7[6],B7[7] buffer IO_R.logic_op_bnl_6 lc_trk_g0_6 +!B14[4],!B15[4],B15[5],!B15[6],B15[7] buffer IO_R.logic_op_bnl_6 lc_trk_g1_6 +B6[5],!B6[6],B6[7],!B6[8],!B7[8] buffer IO_R.logic_op_bnl_7 lc_trk_g0_7 +B14[5],!B14[6],B14[7],!B14[8],!B15[8] buffer IO_R.logic_op_bnl_7 lc_trk_g1_7 +B0[4],B1[4],!B1[5],!B1[6],B1[7] buffer IO_R.logic_op_lft_0 lc_trk_g0_0 +B8[4],B9[4],!B9[5],!B9[6],B9[7] buffer IO_R.logic_op_lft_0 lc_trk_g1_0 +!B0[5],!B0[6],B0[7],B0[8],B1[8] buffer IO_R.logic_op_lft_1 lc_trk_g0_1 +!B8[5],!B8[6],B8[7],B8[8],B9[8] buffer IO_R.logic_op_lft_1 lc_trk_g1_1 +B2[4],B3[4],!B3[5],!B3[6],B3[7] buffer IO_R.logic_op_lft_2 lc_trk_g0_2 +B10[4],B11[4],!B11[5],!B11[6],B11[7] buffer IO_R.logic_op_lft_2 lc_trk_g1_2 +!B2[5],!B2[6],B2[7],B2[8],B3[8] buffer IO_R.logic_op_lft_3 lc_trk_g0_3 +!B10[5],!B10[6],B10[7],B10[8],B11[8] buffer IO_R.logic_op_lft_3 lc_trk_g1_3 +B4[4],B5[4],!B5[5],!B5[6],B5[7] buffer IO_R.logic_op_lft_4 lc_trk_g0_4 +B12[4],B13[4],!B13[5],!B13[6],B13[7] buffer IO_R.logic_op_lft_4 lc_trk_g1_4 +!B4[5],!B4[6],B4[7],B4[8],B5[8] buffer IO_R.logic_op_lft_5 lc_trk_g0_5 +!B12[5],!B12[6],B12[7],B12[8],B13[8] buffer IO_R.logic_op_lft_5 lc_trk_g1_5 +B6[4],B7[4],!B7[5],!B7[6],B7[7] buffer IO_R.logic_op_lft_6 lc_trk_g0_6 +B14[4],B15[4],!B15[5],!B15[6],B15[7] buffer IO_R.logic_op_lft_6 lc_trk_g1_6 +!B6[5],!B6[6],B6[7],B6[8],B7[8] buffer IO_R.logic_op_lft_7 lc_trk_g0_7 +!B14[5],!B14[6],B14[7],B14[8],B15[8] buffer IO_R.logic_op_lft_7 lc_trk_g1_7 +B0[4],!B1[4],!B1[5],!B1[6],B1[7] buffer IO_R.logic_op_tnl_0 lc_trk_g0_0 +B8[4],!B9[4],!B9[5],!B9[6],B9[7] buffer IO_R.logic_op_tnl_0 lc_trk_g1_0 +!B0[5],!B0[6],B0[7],B0[8],!B1[8] buffer IO_R.logic_op_tnl_1 lc_trk_g0_1 +!B8[5],!B8[6],B8[7],B8[8],!B9[8] buffer IO_R.logic_op_tnl_1 lc_trk_g1_1 +B2[4],!B3[4],!B3[5],!B3[6],B3[7] buffer IO_R.logic_op_tnl_2 lc_trk_g0_2 +B10[4],!B11[4],!B11[5],!B11[6],B11[7] buffer IO_R.logic_op_tnl_2 lc_trk_g1_2 +!B2[5],!B2[6],B2[7],B2[8],!B3[8] buffer IO_R.logic_op_tnl_3 lc_trk_g0_3 +!B10[5],!B10[6],B10[7],B10[8],!B11[8] buffer IO_R.logic_op_tnl_3 lc_trk_g1_3 +B4[4],!B5[4],!B5[5],!B5[6],B5[7] buffer IO_R.logic_op_tnl_4 lc_trk_g0_4 +B12[4],!B13[4],!B13[5],!B13[6],B13[7] buffer IO_R.logic_op_tnl_4 lc_trk_g1_4 +!B4[5],!B4[6],B4[7],B4[8],!B5[8] buffer IO_R.logic_op_tnl_5 lc_trk_g0_5 +!B12[5],!B12[6],B12[7],B12[8],!B13[8] buffer IO_R.logic_op_tnl_5 lc_trk_g1_5 +B6[4],!B7[4],!B7[5],!B7[6],B7[7] buffer IO_R.logic_op_tnl_6 lc_trk_g0_6 +B14[4],!B15[4],!B15[5],!B15[6],B15[7] buffer IO_R.logic_op_tnl_6 lc_trk_g1_6 +!B6[5],!B6[6],B6[7],B6[8],!B7[8] buffer IO_R.logic_op_tnl_7 lc_trk_g0_7 +!B14[5],!B14[6],B14[7],B14[8],!B15[8] buffer IO_R.logic_op_tnl_7 lc_trk_g1_7 +B0[4],!B1[4],!B1[5],!B1[6],B1[7] buffer IO_T.logic_op_bnl_0 lc_trk_g0_0 +B8[4],!B9[4],!B9[5],!B9[6],B9[7] buffer IO_T.logic_op_bnl_0 lc_trk_g1_0 +!B0[5],!B0[6],B0[7],B0[8],!B1[8] buffer IO_T.logic_op_bnl_1 lc_trk_g0_1 +!B8[5],!B8[6],B8[7],B8[8],!B9[8] buffer IO_T.logic_op_bnl_1 lc_trk_g1_1 +B2[4],!B3[4],!B3[5],!B3[6],B3[7] buffer IO_T.logic_op_bnl_2 lc_trk_g0_2 +B10[4],!B11[4],!B11[5],!B11[6],B11[7] buffer IO_T.logic_op_bnl_2 lc_trk_g1_2 +!B2[5],!B2[6],B2[7],B2[8],!B3[8] buffer IO_T.logic_op_bnl_3 lc_trk_g0_3 +!B10[5],!B10[6],B10[7],B10[8],!B11[8] buffer IO_T.logic_op_bnl_3 lc_trk_g1_3 +B4[4],!B5[4],!B5[5],!B5[6],B5[7] buffer IO_T.logic_op_bnl_4 lc_trk_g0_4 +B12[4],!B13[4],!B13[5],!B13[6],B13[7] buffer IO_T.logic_op_bnl_4 lc_trk_g1_4 +!B4[5],!B4[6],B4[7],B4[8],!B5[8] buffer IO_T.logic_op_bnl_5 lc_trk_g0_5 +!B12[5],!B12[6],B12[7],B12[8],!B13[8] buffer IO_T.logic_op_bnl_5 lc_trk_g1_5 +B6[4],!B7[4],!B7[5],!B7[6],B7[7] buffer IO_T.logic_op_bnl_6 lc_trk_g0_6 +B14[4],!B15[4],!B15[5],!B15[6],B15[7] buffer IO_T.logic_op_bnl_6 lc_trk_g1_6 +!B6[5],!B6[6],B6[7],B6[8],!B7[8] buffer IO_T.logic_op_bnl_7 lc_trk_g0_7 +!B14[5],!B14[6],B14[7],B14[8],!B15[8] buffer IO_T.logic_op_bnl_7 lc_trk_g1_7 +!B0[4],!B1[4],B1[5],!B1[6],B1[7] buffer IO_T.logic_op_bnr_0 lc_trk_g0_0 +!B8[4],!B9[4],B9[5],!B9[6],B9[7] buffer IO_T.logic_op_bnr_0 lc_trk_g1_0 +B0[5],!B0[6],B0[7],!B0[8],!B1[8] buffer IO_T.logic_op_bnr_1 lc_trk_g0_1 +B8[5],!B8[6],B8[7],!B8[8],!B9[8] buffer IO_T.logic_op_bnr_1 lc_trk_g1_1 +!B2[4],!B3[4],B3[5],!B3[6],B3[7] buffer IO_T.logic_op_bnr_2 lc_trk_g0_2 +!B10[4],!B11[4],B11[5],!B11[6],B11[7] buffer IO_T.logic_op_bnr_2 lc_trk_g1_2 +B2[5],!B2[6],B2[7],!B2[8],!B3[8] buffer IO_T.logic_op_bnr_3 lc_trk_g0_3 +B10[5],!B10[6],B10[7],!B10[8],!B11[8] buffer IO_T.logic_op_bnr_3 lc_trk_g1_3 +!B4[4],!B5[4],B5[5],!B5[6],B5[7] buffer IO_T.logic_op_bnr_4 lc_trk_g0_4 +!B12[4],!B13[4],B13[5],!B13[6],B13[7] buffer IO_T.logic_op_bnr_4 lc_trk_g1_4 +B4[5],!B4[6],B4[7],!B4[8],!B5[8] buffer IO_T.logic_op_bnr_5 lc_trk_g0_5 +B12[5],!B12[6],B12[7],!B12[8],!B13[8] buffer IO_T.logic_op_bnr_5 lc_trk_g1_5 +!B6[4],!B7[4],B7[5],!B7[6],B7[7] buffer IO_T.logic_op_bnr_6 lc_trk_g0_6 +!B14[4],!B15[4],B15[5],!B15[6],B15[7] buffer IO_T.logic_op_bnr_6 lc_trk_g1_6 +B6[5],!B6[6],B6[7],!B6[8],!B7[8] buffer IO_T.logic_op_bnr_7 lc_trk_g0_7 +B14[5],!B14[6],B14[7],!B14[8],!B15[8] buffer IO_T.logic_op_bnr_7 lc_trk_g1_7 +B0[4],B1[4],!B1[5],!B1[6],B1[7] buffer IO_T.logic_op_bot_0 lc_trk_g0_0 +B8[4],B9[4],!B9[5],!B9[6],B9[7] buffer IO_T.logic_op_bot_0 lc_trk_g1_0 +!B0[5],!B0[6],B0[7],B0[8],B1[8] buffer IO_T.logic_op_bot_1 lc_trk_g0_1 +!B8[5],!B8[6],B8[7],B8[8],B9[8] buffer IO_T.logic_op_bot_1 lc_trk_g1_1 +B2[4],B3[4],!B3[5],!B3[6],B3[7] buffer IO_T.logic_op_bot_2 lc_trk_g0_2 +B10[4],B11[4],!B11[5],!B11[6],B11[7] buffer IO_T.logic_op_bot_2 lc_trk_g1_2 +!B2[5],!B2[6],B2[7],B2[8],B3[8] buffer IO_T.logic_op_bot_3 lc_trk_g0_3 +!B10[5],!B10[6],B10[7],B10[8],B11[8] buffer IO_T.logic_op_bot_3 lc_trk_g1_3 +B4[4],B5[4],!B5[5],!B5[6],B5[7] buffer IO_T.logic_op_bot_4 lc_trk_g0_4 +B12[4],B13[4],!B13[5],!B13[6],B13[7] buffer IO_T.logic_op_bot_4 lc_trk_g1_4 +!B4[5],!B4[6],B4[7],B4[8],B5[8] buffer IO_T.logic_op_bot_5 lc_trk_g0_5 +!B12[5],!B12[6],B12[7],B12[8],B13[8] buffer IO_T.logic_op_bot_5 lc_trk_g1_5 +B6[4],B7[4],!B7[5],!B7[6],B7[7] buffer IO_T.logic_op_bot_6 lc_trk_g0_6 +B14[4],B15[4],!B15[5],!B15[6],B15[7] buffer IO_T.logic_op_bot_6 lc_trk_g1_6 +!B6[5],!B6[6],B6[7],B6[8],B7[8] buffer IO_T.logic_op_bot_7 lc_trk_g0_7 +!B14[5],!B14[6],B14[7],B14[8],B15[8] buffer IO_T.logic_op_bot_7 lc_trk_g1_7 +!B8[12],!B8[13],!B8[14],!B9[12],B9[15] buffer glb_netwk_0 wire_io_cluster/io_1/inclk +!B14[12],!B14[13],!B14[14],!B15[12],B15[15] buffer glb_netwk_0 wire_io_cluster/io_1/outclk +!B8[12],!B8[13],!B8[14],B9[12],B9[15] buffer glb_netwk_1 wire_io_cluster/io_1/inclk +!B14[12],!B14[13],!B14[14],B15[12],B15[15] buffer glb_netwk_1 wire_io_cluster/io_1/outclk +B8[12],!B8[13],!B8[14],!B9[12],B9[15] buffer glb_netwk_2 wire_io_cluster/io_1/inclk +B14[12],!B14[13],!B14[14],!B15[12],B15[15] buffer glb_netwk_2 wire_io_cluster/io_1/outclk +B8[12],!B8[13],!B8[14],B9[12],B9[15] buffer glb_netwk_3 wire_io_cluster/io_1/inclk +B14[12],!B14[13],!B14[14],B15[12],B15[15] buffer glb_netwk_3 wire_io_cluster/io_1/outclk +!B8[12],!B8[13],B8[14],!B9[12],B9[15] buffer glb_netwk_4 wire_io_cluster/io_1/inclk +!B14[12],!B14[13],B14[14],!B15[12],B15[15] buffer glb_netwk_4 wire_io_cluster/io_1/outclk +!B8[12],!B8[13],B8[14],B9[12],B9[15] buffer glb_netwk_5 wire_io_cluster/io_1/inclk +!B14[12],!B14[13],B14[14],B15[12],B15[15] buffer glb_netwk_5 wire_io_cluster/io_1/outclk +B8[12],!B8[13],B8[14],!B9[12],B9[15] buffer glb_netwk_6 wire_io_cluster/io_1/inclk +B14[12],!B14[13],B14[14],!B15[12],B15[15] buffer glb_netwk_6 wire_io_cluster/io_1/outclk +B8[12],!B8[13],B8[14],B9[12],B9[15] buffer glb_netwk_7 wire_io_cluster/io_1/inclk +B14[12],!B14[13],B14[14],B15[12],B15[15] buffer glb_netwk_7 wire_io_cluster/io_1/outclk +!B4[12],!B4[13],!B5[12],B5[13] buffer lc_trk_g0_0 wire_io_cluster/io_0/D_OUT_0 +!B14[10],!B14[11],!B15[10],B15[11] buffer lc_trk_g0_0 wire_io_cluster/io_1/D_OUT_1 +!B10[10],!B10[11],!B11[10],B11[11] buffer lc_trk_g0_0 wire_io_cluster/io_1/OUT_ENB +!B8[12],B8[13],!B8[14],!B9[12],B9[15] buffer lc_trk_g0_0 wire_io_cluster/io_1/inclk +!B4[14],B4[15],!B5[14],!B5[15] buffer lc_trk_g0_1 wire_gbuf/in +!B8[10],!B8[11],!B9[10],B9[11] buffer lc_trk_g0_1 wire_io_cluster/io_0/D_OUT_1 +!B4[10],!B4[11],!B5[10],B5[11] buffer lc_trk_g0_1 wire_io_cluster/io_0/OUT_ENB +!B10[12],!B10[13],!B11[12],B11[13] buffer lc_trk_g0_1 wire_io_cluster/io_1/D_OUT_0 +!B14[12],B14[13],!B14[14],!B15[12],B15[15] buffer lc_trk_g0_1 wire_io_cluster/io_1/outclk +!B4[12],!B4[13],B5[12],B5[13] buffer lc_trk_g0_2 wire_io_cluster/io_0/D_OUT_0 +!B14[10],!B14[11],B15[10],B15[11] buffer lc_trk_g0_2 wire_io_cluster/io_1/D_OUT_1 +!B10[10],!B10[11],B11[10],B11[11] buffer lc_trk_g0_2 wire_io_cluster/io_1/OUT_ENB +!B10[14],B10[15],B11[14],!B11[15] buffer lc_trk_g0_2 wire_io_cluster/io_1/cen +B4[14],B4[15],!B5[14],!B5[15] buffer lc_trk_g0_3 wire_gbuf/in +!B8[10],!B8[11],B9[10],B9[11] buffer lc_trk_g0_3 wire_io_cluster/io_0/D_OUT_1 +!B4[10],!B4[11],B5[10],B5[11] buffer lc_trk_g0_3 wire_io_cluster/io_0/OUT_ENB +!B10[12],!B10[13],B11[12],B11[13] buffer lc_trk_g0_3 wire_io_cluster/io_1/D_OUT_0 +!B8[12],B8[13],!B8[14],B9[12],B9[15] buffer lc_trk_g0_3 wire_io_cluster/io_1/inclk +!B4[12],B4[13],!B5[12],B5[13] buffer lc_trk_g0_4 wire_io_cluster/io_0/D_OUT_0 +B14[10],!B14[11],!B15[10],B15[11] buffer lc_trk_g0_4 wire_io_cluster/io_1/D_OUT_1 +B10[10],!B10[11],!B11[10],B11[11] buffer lc_trk_g0_4 wire_io_cluster/io_1/OUT_ENB +!B14[12],B14[13],!B14[14],B15[12],B15[15] buffer lc_trk_g0_4 wire_io_cluster/io_1/outclk +!B4[14],B4[15],!B5[14],B5[15] buffer lc_trk_g0_5 wire_gbuf/in +B8[10],!B8[11],!B9[10],B9[11] buffer lc_trk_g0_5 wire_io_cluster/io_0/D_OUT_1 +B4[10],!B4[11],!B5[10],B5[11] buffer lc_trk_g0_5 wire_io_cluster/io_0/OUT_ENB +!B10[12],B10[13],!B11[12],B11[13] buffer lc_trk_g0_5 wire_io_cluster/io_1/D_OUT_0 +B10[14],B10[15],B11[14],!B11[15] buffer lc_trk_g0_5 wire_io_cluster/io_1/cen +!B4[12],B4[13],B5[12],B5[13] buffer lc_trk_g0_6 wire_io_cluster/io_0/D_OUT_0 +B14[10],!B14[11],B15[10],B15[11] buffer lc_trk_g0_6 wire_io_cluster/io_1/D_OUT_1 +B10[10],!B10[11],B11[10],B11[11] buffer lc_trk_g0_6 wire_io_cluster/io_1/OUT_ENB +B4[14],B4[15],!B5[14],B5[15] buffer lc_trk_g0_7 wire_gbuf/in +B8[10],!B8[11],B9[10],B9[11] buffer lc_trk_g0_7 wire_io_cluster/io_0/D_OUT_1 +B4[10],!B4[11],B5[10],B5[11] buffer lc_trk_g0_7 wire_io_cluster/io_0/OUT_ENB +!B10[12],B10[13],B11[12],B11[13] buffer lc_trk_g0_7 wire_io_cluster/io_1/D_OUT_0 +!B4[14],B4[15],B5[14],!B5[15] buffer lc_trk_g1_0 wire_gbuf/in +!B8[10],B8[11],!B9[10],B9[11] buffer lc_trk_g1_0 wire_io_cluster/io_0/D_OUT_1 +!B4[10],B4[11],!B5[10],B5[11] buffer lc_trk_g1_0 wire_io_cluster/io_0/OUT_ENB +B10[12],!B10[13],!B11[12],B11[13] buffer lc_trk_g1_0 wire_io_cluster/io_1/D_OUT_0 +B8[12],B8[13],!B8[14],!B9[12],B9[15] buffer lc_trk_g1_0 wire_io_cluster/io_1/inclk +B4[12],!B4[13],!B5[12],B5[13] buffer lc_trk_g1_1 wire_io_cluster/io_0/D_OUT_0 +!B14[10],B14[11],!B15[10],B15[11] buffer lc_trk_g1_1 wire_io_cluster/io_1/D_OUT_1 +!B10[10],B10[11],!B11[10],B11[11] buffer lc_trk_g1_1 wire_io_cluster/io_1/OUT_ENB +B14[12],B14[13],!B14[14],!B15[12],B15[15] buffer lc_trk_g1_1 wire_io_cluster/io_1/outclk +B4[14],B4[15],B5[14],!B5[15] buffer lc_trk_g1_2 wire_gbuf/in +!B8[10],B8[11],B9[10],B9[11] buffer lc_trk_g1_2 wire_io_cluster/io_0/D_OUT_1 +!B4[10],B4[11],B5[10],B5[11] buffer lc_trk_g1_2 wire_io_cluster/io_0/OUT_ENB +B10[12],!B10[13],B11[12],B11[13] buffer lc_trk_g1_2 wire_io_cluster/io_1/D_OUT_0 +!B10[14],B10[15],B11[14],B11[15] buffer lc_trk_g1_2 wire_io_cluster/io_1/cen +B4[12],!B4[13],B5[12],B5[13] buffer lc_trk_g1_3 wire_io_cluster/io_0/D_OUT_0 +!B14[10],B14[11],B15[10],B15[11] buffer lc_trk_g1_3 wire_io_cluster/io_1/D_OUT_1 +!B10[10],B10[11],B11[10],B11[11] buffer lc_trk_g1_3 wire_io_cluster/io_1/OUT_ENB +B8[12],B8[13],!B8[14],B9[12],B9[15] buffer lc_trk_g1_3 wire_io_cluster/io_1/inclk +!B4[14],B4[15],B5[14],B5[15] buffer lc_trk_g1_4 wire_gbuf/in +B8[10],B8[11],!B9[10],B9[11] buffer lc_trk_g1_4 wire_io_cluster/io_0/D_OUT_1 +B4[10],B4[11],!B5[10],B5[11] buffer lc_trk_g1_4 wire_io_cluster/io_0/OUT_ENB +B10[12],B10[13],!B11[12],B11[13] buffer lc_trk_g1_4 wire_io_cluster/io_1/D_OUT_0 +B14[12],B14[13],!B14[14],B15[12],B15[15] buffer lc_trk_g1_4 wire_io_cluster/io_1/outclk +B4[12],B4[13],!B5[12],B5[13] buffer lc_trk_g1_5 wire_io_cluster/io_0/D_OUT_0 +B14[10],B14[11],!B15[10],B15[11] buffer lc_trk_g1_5 wire_io_cluster/io_1/D_OUT_1 +B10[10],B10[11],!B11[10],B11[11] buffer lc_trk_g1_5 wire_io_cluster/io_1/OUT_ENB +B10[14],B10[15],B11[14],B11[15] buffer lc_trk_g1_5 wire_io_cluster/io_1/cen +B4[14],B4[15],B5[14],B5[15] buffer lc_trk_g1_6 wire_gbuf/in +B8[10],B8[11],B9[10],B9[11] buffer lc_trk_g1_6 wire_io_cluster/io_0/D_OUT_1 +B4[10],B4[11],B5[10],B5[11] buffer lc_trk_g1_6 wire_io_cluster/io_0/OUT_ENB +B10[12],B10[13],B11[12],B11[13] buffer lc_trk_g1_6 wire_io_cluster/io_1/D_OUT_0 +B4[12],B4[13],B5[12],B5[13] buffer lc_trk_g1_7 wire_io_cluster/io_0/D_OUT_0 +B14[10],B14[11],B15[10],B15[11] buffer lc_trk_g1_7 wire_io_cluster/io_1/D_OUT_1 +B10[10],B10[11],B11[10],B11[11] buffer lc_trk_g1_7 wire_io_cluster/io_1/OUT_ENB +B0[4],B1[4],B1[5],!B1[6],B1[7] buffer span12_horz_0 lc_trk_g0_0 +B8[4],B9[4],B9[5],!B9[6],B9[7] buffer span12_horz_0 lc_trk_g1_0 +B0[5],!B0[6],B0[7],B0[8],B1[8] buffer span12_horz_1 lc_trk_g0_1 +B8[5],!B8[6],B8[7],B8[8],B9[8] buffer span12_horz_1 lc_trk_g1_1 +!B2[4],!B3[4],!B3[5],B3[6],B3[7] buffer span12_horz_10 lc_trk_g0_2 +!B10[4],!B11[4],!B11[5],B11[6],B11[7] buffer span12_horz_10 lc_trk_g1_2 +!B2[5],B2[6],B2[7],!B2[8],!B3[8] buffer span12_horz_11 lc_trk_g0_3 +!B10[5],B10[6],B10[7],!B10[8],!B11[8] buffer span12_horz_11 lc_trk_g1_3 +!B4[4],!B5[4],!B5[5],B5[6],B5[7] buffer span12_horz_12 lc_trk_g0_4 +!B12[4],!B13[4],!B13[5],B13[6],B13[7] buffer span12_horz_12 lc_trk_g1_4 +!B4[5],B4[6],B4[7],!B4[8],!B5[8] buffer span12_horz_13 lc_trk_g0_5 +!B12[5],B12[6],B12[7],!B12[8],!B13[8] buffer span12_horz_13 lc_trk_g1_5 +!B6[4],!B7[4],!B7[5],B7[6],B7[7] buffer span12_horz_14 lc_trk_g0_6 +!B14[4],!B15[4],!B15[5],B15[6],B15[7] buffer span12_horz_14 lc_trk_g1_6 +!B6[5],B6[6],B6[7],!B6[8],!B7[8] buffer span12_horz_15 lc_trk_g0_7 +!B14[5],B14[6],B14[7],!B14[8],!B15[8] buffer span12_horz_15 lc_trk_g1_7 +!B0[4],B1[4],!B1[5],B1[6],B1[7] buffer span12_horz_16 lc_trk_g0_0 +!B8[4],B9[4],!B9[5],B9[6],B9[7] buffer span12_horz_16 lc_trk_g1_0 +!B0[5],B0[6],B0[7],!B0[8],B1[8] buffer span12_horz_17 lc_trk_g0_1 +!B8[5],B8[6],B8[7],!B8[8],B9[8] buffer span12_horz_17 lc_trk_g1_1 +!B2[4],B3[4],!B3[5],B3[6],B3[7] buffer span12_horz_18 lc_trk_g0_2 +!B10[4],B11[4],!B11[5],B11[6],B11[7] buffer span12_horz_18 lc_trk_g1_2 +!B2[5],B2[6],B2[7],!B2[8],B3[8] buffer span12_horz_19 lc_trk_g0_3 +!B10[5],B10[6],B10[7],!B10[8],B11[8] buffer span12_horz_19 lc_trk_g1_3 +B2[4],B3[4],B3[5],!B3[6],B3[7] buffer span12_horz_2 lc_trk_g0_2 +B10[4],B11[4],B11[5],!B11[6],B11[7] buffer span12_horz_2 lc_trk_g1_2 +!B4[4],B5[4],!B5[5],B5[6],B5[7] buffer span12_horz_20 lc_trk_g0_4 +!B12[4],B13[4],!B13[5],B13[6],B13[7] buffer span12_horz_20 lc_trk_g1_4 +!B4[5],B4[6],B4[7],!B4[8],B5[8] buffer span12_horz_21 lc_trk_g0_5 +!B12[5],B12[6],B12[7],!B12[8],B13[8] buffer span12_horz_21 lc_trk_g1_5 +!B6[4],B7[4],!B7[5],B7[6],B7[7] buffer span12_horz_22 lc_trk_g0_6 +!B14[4],B15[4],!B15[5],B15[6],B15[7] buffer span12_horz_22 lc_trk_g1_6 +!B6[5],B6[6],B6[7],!B6[8],B7[8] buffer span12_horz_23 lc_trk_g0_7 +!B14[5],B14[6],B14[7],!B14[8],B15[8] buffer span12_horz_23 lc_trk_g1_7 +B2[5],!B2[6],B2[7],B2[8],B3[8] buffer span12_horz_3 lc_trk_g0_3 +B10[5],!B10[6],B10[7],B10[8],B11[8] buffer span12_horz_3 lc_trk_g1_3 +B4[4],B5[4],B5[5],!B5[6],B5[7] buffer span12_horz_4 lc_trk_g0_4 +B12[4],B13[4],B13[5],!B13[6],B13[7] buffer span12_horz_4 lc_trk_g1_4 +B4[5],!B4[6],B4[7],B4[8],B5[8] buffer span12_horz_5 lc_trk_g0_5 +B12[5],!B12[6],B12[7],B12[8],B13[8] buffer span12_horz_5 lc_trk_g1_5 +B6[4],B7[4],B7[5],!B7[6],B7[7] buffer span12_horz_6 lc_trk_g0_6 +B14[4],B15[4],B15[5],!B15[6],B15[7] buffer span12_horz_6 lc_trk_g1_6 +B6[5],!B6[6],B6[7],B6[8],B7[8] buffer span12_horz_7 lc_trk_g0_7 +B14[5],!B14[6],B14[7],B14[8],B15[8] buffer span12_horz_7 lc_trk_g1_7 +!B0[4],!B1[4],!B1[5],B1[6],B1[7] buffer span12_horz_8 lc_trk_g0_0 +!B8[4],!B9[4],!B9[5],B9[6],B9[7] buffer span12_horz_8 lc_trk_g1_0 +!B0[5],B0[6],B0[7],!B0[8],!B1[8] buffer span12_horz_9 lc_trk_g0_1 +!B8[5],B8[6],B8[7],!B8[8],!B9[8] buffer span12_horz_9 lc_trk_g1_1 +B0[4],B1[4],B1[5],!B1[6],B1[7] buffer span12_vert_0 lc_trk_g0_0 +B8[4],B9[4],B9[5],!B9[6],B9[7] buffer span12_vert_0 lc_trk_g1_0 +B0[5],!B0[6],B0[7],B0[8],B1[8] buffer span12_vert_1 lc_trk_g0_1 +B8[5],!B8[6],B8[7],B8[8],B9[8] buffer span12_vert_1 lc_trk_g1_1 +!B2[4],!B3[4],!B3[5],B3[6],B3[7] buffer span12_vert_10 lc_trk_g0_2 +!B10[4],!B11[4],!B11[5],B11[6],B11[7] buffer span12_vert_10 lc_trk_g1_2 +!B2[5],B2[6],B2[7],!B2[8],!B3[8] buffer span12_vert_11 lc_trk_g0_3 +!B10[5],B10[6],B10[7],!B10[8],!B11[8] buffer span12_vert_11 lc_trk_g1_3 +!B4[4],!B5[4],!B5[5],B5[6],B5[7] buffer span12_vert_12 lc_trk_g0_4 +!B12[4],!B13[4],!B13[5],B13[6],B13[7] buffer span12_vert_12 lc_trk_g1_4 +!B4[5],B4[6],B4[7],!B4[8],!B5[8] buffer span12_vert_13 lc_trk_g0_5 +!B12[5],B12[6],B12[7],!B12[8],!B13[8] buffer span12_vert_13 lc_trk_g1_5 +!B6[4],!B7[4],!B7[5],B7[6],B7[7] buffer span12_vert_14 lc_trk_g0_6 +!B14[4],!B15[4],!B15[5],B15[6],B15[7] buffer span12_vert_14 lc_trk_g1_6 +!B6[5],B6[6],B6[7],!B6[8],!B7[8] buffer span12_vert_15 lc_trk_g0_7 +!B14[5],B14[6],B14[7],!B14[8],!B15[8] buffer span12_vert_15 lc_trk_g1_7 +!B0[4],B1[4],!B1[5],B1[6],B1[7] buffer span12_vert_16 lc_trk_g0_0 +!B8[4],B9[4],!B9[5],B9[6],B9[7] buffer span12_vert_16 lc_trk_g1_0 +!B0[5],B0[6],B0[7],!B0[8],B1[8] buffer span12_vert_17 lc_trk_g0_1 +!B8[5],B8[6],B8[7],!B8[8],B9[8] buffer span12_vert_17 lc_trk_g1_1 +!B2[4],B3[4],!B3[5],B3[6],B3[7] buffer span12_vert_18 lc_trk_g0_2 +!B10[4],B11[4],!B11[5],B11[6],B11[7] buffer span12_vert_18 lc_trk_g1_2 +!B2[5],B2[6],B2[7],!B2[8],B3[8] buffer span12_vert_19 lc_trk_g0_3 +!B10[5],B10[6],B10[7],!B10[8],B11[8] buffer span12_vert_19 lc_trk_g1_3 +B2[4],B3[4],B3[5],!B3[6],B3[7] buffer span12_vert_2 lc_trk_g0_2 +B10[4],B11[4],B11[5],!B11[6],B11[7] buffer span12_vert_2 lc_trk_g1_2 +!B4[4],B5[4],!B5[5],B5[6],B5[7] buffer span12_vert_20 lc_trk_g0_4 +!B12[4],B13[4],!B13[5],B13[6],B13[7] buffer span12_vert_20 lc_trk_g1_4 +!B4[5],B4[6],B4[7],!B4[8],B5[8] buffer span12_vert_21 lc_trk_g0_5 +!B12[5],B12[6],B12[7],!B12[8],B13[8] buffer span12_vert_21 lc_trk_g1_5 +!B6[4],B7[4],!B7[5],B7[6],B7[7] buffer span12_vert_22 lc_trk_g0_6 +!B14[4],B15[4],!B15[5],B15[6],B15[7] buffer span12_vert_22 lc_trk_g1_6 +!B6[5],B6[6],B6[7],!B6[8],B7[8] buffer span12_vert_23 lc_trk_g0_7 +!B14[5],B14[6],B14[7],!B14[8],B15[8] buffer span12_vert_23 lc_trk_g1_7 +B2[5],!B2[6],B2[7],B2[8],B3[8] buffer span12_vert_3 lc_trk_g0_3 +B10[5],!B10[6],B10[7],B10[8],B11[8] buffer span12_vert_3 lc_trk_g1_3 +B4[4],B5[4],B5[5],!B5[6],B5[7] buffer span12_vert_4 lc_trk_g0_4 +B12[4],B13[4],B13[5],!B13[6],B13[7] buffer span12_vert_4 lc_trk_g1_4 +B4[5],!B4[6],B4[7],B4[8],B5[8] buffer span12_vert_5 lc_trk_g0_5 +B12[5],!B12[6],B12[7],B12[8],B13[8] buffer span12_vert_5 lc_trk_g1_5 +B6[4],B7[4],B7[5],!B7[6],B7[7] buffer span12_vert_6 lc_trk_g0_6 +B14[4],B15[4],B15[5],!B15[6],B15[7] buffer span12_vert_6 lc_trk_g1_6 +B6[5],!B6[6],B6[7],B6[8],B7[8] buffer span12_vert_7 lc_trk_g0_7 +B14[5],!B14[6],B14[7],B14[8],B15[8] buffer span12_vert_7 lc_trk_g1_7 +!B0[4],!B1[4],!B1[5],B1[6],B1[7] buffer span12_vert_8 lc_trk_g0_0 +!B8[4],!B9[4],!B9[5],B9[6],B9[7] buffer span12_vert_8 lc_trk_g1_0 +!B0[5],B0[6],B0[7],!B0[8],!B1[8] buffer span12_vert_9 lc_trk_g0_1 +!B8[5],B8[6],B8[7],!B8[8],!B9[8] buffer span12_vert_9 lc_trk_g1_1 +B0[4],!B1[4],!B1[5],B1[6],B1[7] buffer span4_horz_0 lc_trk_g0_0 +B8[4],!B9[4],!B9[5],B9[6],B9[7] buffer span4_horz_0 lc_trk_g1_0 +!B0[5],B0[6],B0[7],B0[8],!B1[8] buffer span4_horz_1 lc_trk_g0_1 +!B8[5],B8[6],B8[7],B8[8],!B9[8] buffer span4_horz_1 lc_trk_g1_1 +B2[4],B3[4],!B3[5],B3[6],B3[7] buffer span4_horz_10 lc_trk_g0_2 +B10[4],B11[4],!B11[5],B11[6],B11[7] buffer span4_horz_10 lc_trk_g1_2 +!B2[5],B2[6],B2[7],B2[8],B3[8] buffer span4_horz_11 lc_trk_g0_3 +!B10[5],B10[6],B10[7],B10[8],B11[8] buffer span4_horz_11 lc_trk_g1_3 +B4[4],B5[4],!B5[5],B5[6],B5[7] buffer span4_horz_12 lc_trk_g0_4 +B12[4],B13[4],!B13[5],B13[6],B13[7] buffer span4_horz_12 lc_trk_g1_4 +!B4[5],B4[6],B4[7],B4[8],B5[8] buffer span4_horz_13 lc_trk_g0_5 +!B12[5],B12[6],B12[7],B12[8],B13[8] buffer span4_horz_13 lc_trk_g1_5 +B6[4],B7[4],!B7[5],B7[6],B7[7] buffer span4_horz_14 lc_trk_g0_6 +B14[4],B15[4],!B15[5],B15[6],B15[7] buffer span4_horz_14 lc_trk_g1_6 +!B6[5],B6[6],B6[7],B6[8],B7[8] buffer span4_horz_15 lc_trk_g0_7 +!B14[5],B14[6],B14[7],B14[8],B15[8] buffer span4_horz_15 lc_trk_g1_7 +!B0[4],!B1[4],B1[5],B1[6],B1[7] buffer span4_horz_16 lc_trk_g0_0 +!B8[4],!B9[4],B9[5],B9[6],B9[7] buffer span4_horz_16 lc_trk_g1_0 +B0[5],B0[6],B0[7],!B0[8],!B1[8] buffer span4_horz_17 lc_trk_g0_1 +B8[5],B8[6],B8[7],!B8[8],!B9[8] buffer span4_horz_17 lc_trk_g1_1 +!B2[4],!B3[4],B3[5],B3[6],B3[7] buffer span4_horz_18 lc_trk_g0_2 +!B10[4],!B11[4],B11[5],B11[6],B11[7] buffer span4_horz_18 lc_trk_g1_2 +B2[5],B2[6],B2[7],!B2[8],!B3[8] buffer span4_horz_19 lc_trk_g0_3 +B10[5],B10[6],B10[7],!B10[8],!B11[8] buffer span4_horz_19 lc_trk_g1_3 +B2[4],!B3[4],!B3[5],B3[6],B3[7] buffer span4_horz_2 lc_trk_g0_2 +B10[4],!B11[4],!B11[5],B11[6],B11[7] buffer span4_horz_2 lc_trk_g1_2 +!B4[4],!B5[4],B5[5],B5[6],B5[7] buffer span4_horz_20 lc_trk_g0_4 +!B12[4],!B13[4],B13[5],B13[6],B13[7] buffer span4_horz_20 lc_trk_g1_4 +B4[5],B4[6],B4[7],!B4[8],!B5[8] buffer span4_horz_21 lc_trk_g0_5 +B12[5],B12[6],B12[7],!B12[8],!B13[8] buffer span4_horz_21 lc_trk_g1_5 +!B6[4],!B7[4],B7[5],B7[6],B7[7] buffer span4_horz_22 lc_trk_g0_6 +!B14[4],!B15[4],B15[5],B15[6],B15[7] buffer span4_horz_22 lc_trk_g1_6 +B6[5],B6[6],B6[7],!B6[8],!B7[8] buffer span4_horz_23 lc_trk_g0_7 +B14[5],B14[6],B14[7],!B14[8],!B15[8] buffer span4_horz_23 lc_trk_g1_7 +!B0[4],B1[4],B1[5],B1[6],B1[7] buffer span4_horz_24 lc_trk_g0_0 +!B8[4],B9[4],B9[5],B9[6],B9[7] buffer span4_horz_24 lc_trk_g1_0 +B0[5],B0[6],B0[7],!B0[8],B1[8] buffer span4_horz_25 lc_trk_g0_1 +B8[5],B8[6],B8[7],!B8[8],B9[8] buffer span4_horz_25 lc_trk_g1_1 +!B2[4],B3[4],B3[5],B3[6],B3[7] buffer span4_horz_26 lc_trk_g0_2 +!B10[4],B11[4],B11[5],B11[6],B11[7] buffer span4_horz_26 lc_trk_g1_2 +B2[5],B2[6],B2[7],!B2[8],B3[8] buffer span4_horz_27 lc_trk_g0_3 +B10[5],B10[6],B10[7],!B10[8],B11[8] buffer span4_horz_27 lc_trk_g1_3 +!B4[4],B5[4],B5[5],B5[6],B5[7] buffer span4_horz_28 lc_trk_g0_4 +!B12[4],B13[4],B13[5],B13[6],B13[7] buffer span4_horz_28 lc_trk_g1_4 +B4[5],B4[6],B4[7],!B4[8],B5[8] buffer span4_horz_29 lc_trk_g0_5 +B12[5],B12[6],B12[7],!B12[8],B13[8] buffer span4_horz_29 lc_trk_g1_5 +!B2[5],B2[6],B2[7],B2[8],!B3[8] buffer span4_horz_3 lc_trk_g0_3 +!B10[5],B10[6],B10[7],B10[8],!B11[8] buffer span4_horz_3 lc_trk_g1_3 +!B6[4],B7[4],B7[5],B7[6],B7[7] buffer span4_horz_30 lc_trk_g0_6 +!B14[4],B15[4],B15[5],B15[6],B15[7] buffer span4_horz_30 lc_trk_g1_6 +B6[5],B6[6],B6[7],!B6[8],B7[8] buffer span4_horz_31 lc_trk_g0_7 +B14[5],B14[6],B14[7],!B14[8],B15[8] buffer span4_horz_31 lc_trk_g1_7 +B0[4],!B1[4],B1[5],B1[6],B1[7] buffer span4_horz_32 lc_trk_g0_0 +B8[4],!B9[4],B9[5],B9[6],B9[7] buffer span4_horz_32 lc_trk_g1_0 +B0[5],B0[6],B0[7],B0[8],!B1[8] buffer span4_horz_33 lc_trk_g0_1 +B8[5],B8[6],B8[7],B8[8],!B9[8] buffer span4_horz_33 lc_trk_g1_1 +B2[4],!B3[4],B3[5],B3[6],B3[7] buffer span4_horz_34 lc_trk_g0_2 +B10[4],!B11[4],B11[5],B11[6],B11[7] buffer span4_horz_34 lc_trk_g1_2 +B2[5],B2[6],B2[7],B2[8],!B3[8] buffer span4_horz_35 lc_trk_g0_3 +B10[5],B10[6],B10[7],B10[8],!B11[8] buffer span4_horz_35 lc_trk_g1_3 +B4[4],!B5[4],B5[5],B5[6],B5[7] buffer span4_horz_36 lc_trk_g0_4 +B12[4],!B13[4],B13[5],B13[6],B13[7] buffer span4_horz_36 lc_trk_g1_4 +B4[5],B4[6],B4[7],B4[8],!B5[8] buffer span4_horz_37 lc_trk_g0_5 +B12[5],B12[6],B12[7],B12[8],!B13[8] buffer span4_horz_37 lc_trk_g1_5 +B6[4],!B7[4],B7[5],B7[6],B7[7] buffer span4_horz_38 lc_trk_g0_6 +B14[4],!B15[4],B15[5],B15[6],B15[7] buffer span4_horz_38 lc_trk_g1_6 +B6[5],B6[6],B6[7],B6[8],!B7[8] buffer span4_horz_39 lc_trk_g0_7 +B14[5],B14[6],B14[7],B14[8],!B15[8] buffer span4_horz_39 lc_trk_g1_7 +B4[4],!B5[4],!B5[5],B5[6],B5[7] buffer span4_horz_4 lc_trk_g0_4 +B12[4],!B13[4],!B13[5],B13[6],B13[7] buffer span4_horz_4 lc_trk_g1_4 +B0[4],B1[4],B1[5],B1[6],B1[7] buffer span4_horz_40 lc_trk_g0_0 +B8[4],B9[4],B9[5],B9[6],B9[7] buffer span4_horz_40 lc_trk_g1_0 +B0[5],B0[6],B0[7],B0[8],B1[8] buffer span4_horz_41 lc_trk_g0_1 +B8[5],B8[6],B8[7],B8[8],B9[8] buffer span4_horz_41 lc_trk_g1_1 +B2[4],B3[4],B3[5],B3[6],B3[7] buffer span4_horz_42 lc_trk_g0_2 +B10[4],B11[4],B11[5],B11[6],B11[7] buffer span4_horz_42 lc_trk_g1_2 +B2[5],B2[6],B2[7],B2[8],B3[8] buffer span4_horz_43 lc_trk_g0_3 +B10[5],B10[6],B10[7],B10[8],B11[8] buffer span4_horz_43 lc_trk_g1_3 +B4[4],B5[4],B5[5],B5[6],B5[7] buffer span4_horz_44 lc_trk_g0_4 +B12[4],B13[4],B13[5],B13[6],B13[7] buffer span4_horz_44 lc_trk_g1_4 +B4[5],B4[6],B4[7],B4[8],B5[8] buffer span4_horz_45 lc_trk_g0_5 +B12[5],B12[6],B12[7],B12[8],B13[8] buffer span4_horz_45 lc_trk_g1_5 +B6[4],B7[4],B7[5],B7[6],B7[7] buffer span4_horz_46 lc_trk_g0_6 +B14[4],B15[4],B15[5],B15[6],B15[7] buffer span4_horz_46 lc_trk_g1_6 +B6[5],B6[6],B6[7],B6[8],B7[8] buffer span4_horz_47 lc_trk_g0_7 +B14[5],B14[6],B14[7],B14[8],B15[8] buffer span4_horz_47 lc_trk_g1_7 +!B4[5],B4[6],B4[7],B4[8],!B5[8] buffer span4_horz_5 lc_trk_g0_5 +!B12[5],B12[6],B12[7],B12[8],!B13[8] buffer span4_horz_5 lc_trk_g1_5 +B6[4],!B7[4],!B7[5],B7[6],B7[7] buffer span4_horz_6 lc_trk_g0_6 +B14[4],!B15[4],!B15[5],B15[6],B15[7] buffer span4_horz_6 lc_trk_g1_6 +!B6[5],B6[6],B6[7],B6[8],!B7[8] buffer span4_horz_7 lc_trk_g0_7 +!B14[5],B14[6],B14[7],B14[8],!B15[8] buffer span4_horz_7 lc_trk_g1_7 +B0[4],B1[4],!B1[5],B1[6],B1[7] buffer span4_horz_8 lc_trk_g0_0 +B8[4],B9[4],!B9[5],B9[6],B9[7] buffer span4_horz_8 lc_trk_g1_0 +!B0[5],B0[6],B0[7],B0[8],B1[8] buffer span4_horz_9 lc_trk_g0_1 +!B8[5],B8[6],B8[7],B8[8],B9[8] buffer span4_horz_9 lc_trk_g1_1 +!B0[4],B1[4],B1[5],!B1[6],B1[7] buffer span4_horz_r_0 lc_trk_g0_0 +!B8[4],B9[4],B9[5],!B9[6],B9[7] buffer span4_horz_r_0 lc_trk_g1_0 +B0[5],!B0[6],B0[7],!B0[8],B1[8] buffer span4_horz_r_1 lc_trk_g0_1 +B8[5],!B8[6],B8[7],!B8[8],B9[8] buffer span4_horz_r_1 lc_trk_g1_1 +B2[4],!B3[4],B3[5],!B3[6],B3[7] buffer span4_horz_r_10 lc_trk_g0_2 +B10[4],!B11[4],B11[5],!B11[6],B11[7] buffer span4_horz_r_10 lc_trk_g1_2 +B2[5],!B2[6],B2[7],B2[8],!B3[8] buffer span4_horz_r_11 lc_trk_g0_3 +B10[5],!B10[6],B10[7],B10[8],!B11[8] buffer span4_horz_r_11 lc_trk_g1_3 +B4[4],!B5[4],B5[5],!B5[6],B5[7] buffer span4_horz_r_12 lc_trk_g0_4 +B12[4],!B13[4],B13[5],!B13[6],B13[7] buffer span4_horz_r_12 lc_trk_g1_4 +B4[5],!B4[6],B4[7],B4[8],!B5[8] buffer span4_horz_r_13 lc_trk_g0_5 +B12[5],!B12[6],B12[7],B12[8],!B13[8] buffer span4_horz_r_13 lc_trk_g1_5 +B6[4],!B7[4],B7[5],!B7[6],B7[7] buffer span4_horz_r_14 lc_trk_g0_6 +B14[4],!B15[4],B15[5],!B15[6],B15[7] buffer span4_horz_r_14 lc_trk_g1_6 +B6[5],!B6[6],B6[7],B6[8],!B7[8] buffer span4_horz_r_15 lc_trk_g0_7 +B14[5],!B14[6],B14[7],B14[8],!B15[8] buffer span4_horz_r_15 lc_trk_g1_7 +!B2[4],B3[4],B3[5],!B3[6],B3[7] buffer span4_horz_r_2 lc_trk_g0_2 +!B10[4],B11[4],B11[5],!B11[6],B11[7] buffer span4_horz_r_2 lc_trk_g1_2 +B2[5],!B2[6],B2[7],!B2[8],B3[8] buffer span4_horz_r_3 lc_trk_g0_3 +B10[5],!B10[6],B10[7],!B10[8],B11[8] buffer span4_horz_r_3 lc_trk_g1_3 +!B4[4],B5[4],B5[5],!B5[6],B5[7] buffer span4_horz_r_4 lc_trk_g0_4 +!B12[4],B13[4],B13[5],!B13[6],B13[7] buffer span4_horz_r_4 lc_trk_g1_4 +B4[5],!B4[6],B4[7],!B4[8],B5[8] buffer span4_horz_r_5 lc_trk_g0_5 +B12[5],!B12[6],B12[7],!B12[8],B13[8] buffer span4_horz_r_5 lc_trk_g1_5 +!B6[4],B7[4],B7[5],!B7[6],B7[7] buffer span4_horz_r_6 lc_trk_g0_6 +!B14[4],B15[4],B15[5],!B15[6],B15[7] buffer span4_horz_r_6 lc_trk_g1_6 +B6[5],!B6[6],B6[7],!B6[8],B7[8] buffer span4_horz_r_7 lc_trk_g0_7 +B14[5],!B14[6],B14[7],!B14[8],B15[8] buffer span4_horz_r_7 lc_trk_g1_7 +B0[4],!B1[4],B1[5],!B1[6],B1[7] buffer span4_horz_r_8 lc_trk_g0_0 +B8[4],!B9[4],B9[5],!B9[6],B9[7] buffer span4_horz_r_8 lc_trk_g1_0 +B0[5],!B0[6],B0[7],B0[8],!B1[8] buffer span4_horz_r_9 lc_trk_g0_1 +B8[5],!B8[6],B8[7],B8[8],!B9[8] buffer span4_horz_r_9 lc_trk_g1_1 +B0[4],!B1[4],!B1[5],B1[6],B1[7] buffer span4_vert_0 lc_trk_g0_0 +B8[4],!B9[4],!B9[5],B9[6],B9[7] buffer span4_vert_0 lc_trk_g1_0 +!B0[5],B0[6],B0[7],B0[8],!B1[8] buffer span4_vert_1 lc_trk_g0_1 +!B8[5],B8[6],B8[7],B8[8],!B9[8] buffer span4_vert_1 lc_trk_g1_1 +B2[4],B3[4],!B3[5],B3[6],B3[7] buffer span4_vert_10 lc_trk_g0_2 +B10[4],B11[4],!B11[5],B11[6],B11[7] buffer span4_vert_10 lc_trk_g1_2 +!B2[5],B2[6],B2[7],B2[8],B3[8] buffer span4_vert_11 lc_trk_g0_3 +!B10[5],B10[6],B10[7],B10[8],B11[8] buffer span4_vert_11 lc_trk_g1_3 +B4[4],B5[4],!B5[5],B5[6],B5[7] buffer span4_vert_12 lc_trk_g0_4 +B12[4],B13[4],!B13[5],B13[6],B13[7] buffer span4_vert_12 lc_trk_g1_4 +!B4[5],B4[6],B4[7],B4[8],B5[8] buffer span4_vert_13 lc_trk_g0_5 +!B12[5],B12[6],B12[7],B12[8],B13[8] buffer span4_vert_13 lc_trk_g1_5 +B6[4],B7[4],!B7[5],B7[6],B7[7] buffer span4_vert_14 lc_trk_g0_6 +B14[4],B15[4],!B15[5],B15[6],B15[7] buffer span4_vert_14 lc_trk_g1_6 +!B6[5],B6[6],B6[7],B6[8],B7[8] buffer span4_vert_15 lc_trk_g0_7 +!B14[5],B14[6],B14[7],B14[8],B15[8] buffer span4_vert_15 lc_trk_g1_7 +!B0[4],!B1[4],B1[5],B1[6],B1[7] buffer span4_vert_16 lc_trk_g0_0 +!B8[4],!B9[4],B9[5],B9[6],B9[7] buffer span4_vert_16 lc_trk_g1_0 +B0[5],B0[6],B0[7],!B0[8],!B1[8] buffer span4_vert_17 lc_trk_g0_1 +B8[5],B8[6],B8[7],!B8[8],!B9[8] buffer span4_vert_17 lc_trk_g1_1 +!B2[4],!B3[4],B3[5],B3[6],B3[7] buffer span4_vert_18 lc_trk_g0_2 +!B10[4],!B11[4],B11[5],B11[6],B11[7] buffer span4_vert_18 lc_trk_g1_2 +B2[5],B2[6],B2[7],!B2[8],!B3[8] buffer span4_vert_19 lc_trk_g0_3 +B10[5],B10[6],B10[7],!B10[8],!B11[8] buffer span4_vert_19 lc_trk_g1_3 +B2[4],!B3[4],!B3[5],B3[6],B3[7] buffer span4_vert_2 lc_trk_g0_2 +B10[4],!B11[4],!B11[5],B11[6],B11[7] buffer span4_vert_2 lc_trk_g1_2 +!B4[4],!B5[4],B5[5],B5[6],B5[7] buffer span4_vert_20 lc_trk_g0_4 +!B12[4],!B13[4],B13[5],B13[6],B13[7] buffer span4_vert_20 lc_trk_g1_4 +B4[5],B4[6],B4[7],!B4[8],!B5[8] buffer span4_vert_21 lc_trk_g0_5 +B12[5],B12[6],B12[7],!B12[8],!B13[8] buffer span4_vert_21 lc_trk_g1_5 +!B6[4],!B7[4],B7[5],B7[6],B7[7] buffer span4_vert_22 lc_trk_g0_6 +!B14[4],!B15[4],B15[5],B15[6],B15[7] buffer span4_vert_22 lc_trk_g1_6 +B6[5],B6[6],B6[7],!B6[8],!B7[8] buffer span4_vert_23 lc_trk_g0_7 +B14[5],B14[6],B14[7],!B14[8],!B15[8] buffer span4_vert_23 lc_trk_g1_7 +!B0[4],B1[4],B1[5],B1[6],B1[7] buffer span4_vert_24 lc_trk_g0_0 +!B8[4],B9[4],B9[5],B9[6],B9[7] buffer span4_vert_24 lc_trk_g1_0 +B0[5],B0[6],B0[7],!B0[8],B1[8] buffer span4_vert_25 lc_trk_g0_1 +B8[5],B8[6],B8[7],!B8[8],B9[8] buffer span4_vert_25 lc_trk_g1_1 +!B2[4],B3[4],B3[5],B3[6],B3[7] buffer span4_vert_26 lc_trk_g0_2 +!B10[4],B11[4],B11[5],B11[6],B11[7] buffer span4_vert_26 lc_trk_g1_2 +B2[5],B2[6],B2[7],!B2[8],B3[8] buffer span4_vert_27 lc_trk_g0_3 +B10[5],B10[6],B10[7],!B10[8],B11[8] buffer span4_vert_27 lc_trk_g1_3 +!B4[4],B5[4],B5[5],B5[6],B5[7] buffer span4_vert_28 lc_trk_g0_4 +!B12[4],B13[4],B13[5],B13[6],B13[7] buffer span4_vert_28 lc_trk_g1_4 +B4[5],B4[6],B4[7],!B4[8],B5[8] buffer span4_vert_29 lc_trk_g0_5 +B12[5],B12[6],B12[7],!B12[8],B13[8] buffer span4_vert_29 lc_trk_g1_5 +!B2[5],B2[6],B2[7],B2[8],!B3[8] buffer span4_vert_3 lc_trk_g0_3 +!B10[5],B10[6],B10[7],B10[8],!B11[8] buffer span4_vert_3 lc_trk_g1_3 +!B6[4],B7[4],B7[5],B7[6],B7[7] buffer span4_vert_30 lc_trk_g0_6 +!B14[4],B15[4],B15[5],B15[6],B15[7] buffer span4_vert_30 lc_trk_g1_6 +B6[5],B6[6],B6[7],!B6[8],B7[8] buffer span4_vert_31 lc_trk_g0_7 +B14[5],B14[6],B14[7],!B14[8],B15[8] buffer span4_vert_31 lc_trk_g1_7 +B0[4],!B1[4],B1[5],B1[6],B1[7] buffer span4_vert_32 lc_trk_g0_0 +B8[4],!B9[4],B9[5],B9[6],B9[7] buffer span4_vert_32 lc_trk_g1_0 +B0[5],B0[6],B0[7],B0[8],!B1[8] buffer span4_vert_33 lc_trk_g0_1 +B8[5],B8[6],B8[7],B8[8],!B9[8] buffer span4_vert_33 lc_trk_g1_1 +B2[4],!B3[4],B3[5],B3[6],B3[7] buffer span4_vert_34 lc_trk_g0_2 +B10[4],!B11[4],B11[5],B11[6],B11[7] buffer span4_vert_34 lc_trk_g1_2 +B2[5],B2[6],B2[7],B2[8],!B3[8] buffer span4_vert_35 lc_trk_g0_3 +B10[5],B10[6],B10[7],B10[8],!B11[8] buffer span4_vert_35 lc_trk_g1_3 +B4[4],!B5[4],B5[5],B5[6],B5[7] buffer span4_vert_36 lc_trk_g0_4 +B12[4],!B13[4],B13[5],B13[6],B13[7] buffer span4_vert_36 lc_trk_g1_4 +B4[5],B4[6],B4[7],B4[8],!B5[8] buffer span4_vert_37 lc_trk_g0_5 +B12[5],B12[6],B12[7],B12[8],!B13[8] buffer span4_vert_37 lc_trk_g1_5 +B6[4],!B7[4],B7[5],B7[6],B7[7] buffer span4_vert_38 lc_trk_g0_6 +B14[4],!B15[4],B15[5],B15[6],B15[7] buffer span4_vert_38 lc_trk_g1_6 +B6[5],B6[6],B6[7],B6[8],!B7[8] buffer span4_vert_39 lc_trk_g0_7 +B14[5],B14[6],B14[7],B14[8],!B15[8] buffer span4_vert_39 lc_trk_g1_7 +B4[4],!B5[4],!B5[5],B5[6],B5[7] buffer span4_vert_4 lc_trk_g0_4 +B12[4],!B13[4],!B13[5],B13[6],B13[7] buffer span4_vert_4 lc_trk_g1_4 +B0[4],B1[4],B1[5],B1[6],B1[7] buffer span4_vert_40 lc_trk_g0_0 +B8[4],B9[4],B9[5],B9[6],B9[7] buffer span4_vert_40 lc_trk_g1_0 +B0[5],B0[6],B0[7],B0[8],B1[8] buffer span4_vert_41 lc_trk_g0_1 +B8[5],B8[6],B8[7],B8[8],B9[8] buffer span4_vert_41 lc_trk_g1_1 +B2[4],B3[4],B3[5],B3[6],B3[7] buffer span4_vert_42 lc_trk_g0_2 +B10[4],B11[4],B11[5],B11[6],B11[7] buffer span4_vert_42 lc_trk_g1_2 +B2[5],B2[6],B2[7],B2[8],B3[8] buffer span4_vert_43 lc_trk_g0_3 +B10[5],B10[6],B10[7],B10[8],B11[8] buffer span4_vert_43 lc_trk_g1_3 +B4[4],B5[4],B5[5],B5[6],B5[7] buffer span4_vert_44 lc_trk_g0_4 +B12[4],B13[4],B13[5],B13[6],B13[7] buffer span4_vert_44 lc_trk_g1_4 +B4[5],B4[6],B4[7],B4[8],B5[8] buffer span4_vert_45 lc_trk_g0_5 +B12[5],B12[6],B12[7],B12[8],B13[8] buffer span4_vert_45 lc_trk_g1_5 +B6[4],B7[4],B7[5],B7[6],B7[7] buffer span4_vert_46 lc_trk_g0_6 +B14[4],B15[4],B15[5],B15[6],B15[7] buffer span4_vert_46 lc_trk_g1_6 +B6[5],B6[6],B6[7],B6[8],B7[8] buffer span4_vert_47 lc_trk_g0_7 +B14[5],B14[6],B14[7],B14[8],B15[8] buffer span4_vert_47 lc_trk_g1_7 +!B4[5],B4[6],B4[7],B4[8],!B5[8] buffer span4_vert_5 lc_trk_g0_5 +!B12[5],B12[6],B12[7],B12[8],!B13[8] buffer span4_vert_5 lc_trk_g1_5 +B6[4],!B7[4],!B7[5],B7[6],B7[7] buffer span4_vert_6 lc_trk_g0_6 +B14[4],!B15[4],!B15[5],B15[6],B15[7] buffer span4_vert_6 lc_trk_g1_6 +!B6[5],B6[6],B6[7],B6[8],!B7[8] buffer span4_vert_7 lc_trk_g0_7 +!B14[5],B14[6],B14[7],B14[8],!B15[8] buffer span4_vert_7 lc_trk_g1_7 +B0[4],B1[4],!B1[5],B1[6],B1[7] buffer span4_vert_8 lc_trk_g0_0 +B8[4],B9[4],!B9[5],B9[6],B9[7] buffer span4_vert_8 lc_trk_g1_0 +!B0[5],B0[6],B0[7],B0[8],B1[8] buffer span4_vert_9 lc_trk_g0_1 +!B8[5],B8[6],B8[7],B8[8],B9[8] buffer span4_vert_9 lc_trk_g1_1 +!B0[4],B1[4],B1[5],!B1[6],B1[7] buffer span4_vert_b_0 lc_trk_g0_0 +!B8[4],B9[4],B9[5],!B9[6],B9[7] buffer span4_vert_b_0 lc_trk_g1_0 +B0[5],!B0[6],B0[7],!B0[8],B1[8] buffer span4_vert_b_1 lc_trk_g0_1 +B8[5],!B8[6],B8[7],!B8[8],B9[8] buffer span4_vert_b_1 lc_trk_g1_1 +B2[4],!B3[4],B3[5],!B3[6],B3[7] buffer span4_vert_b_10 lc_trk_g0_2 +B10[4],!B11[4],B11[5],!B11[6],B11[7] buffer span4_vert_b_10 lc_trk_g1_2 +B2[5],!B2[6],B2[7],B2[8],!B3[8] buffer span4_vert_b_11 lc_trk_g0_3 +B10[5],!B10[6],B10[7],B10[8],!B11[8] buffer span4_vert_b_11 lc_trk_g1_3 +B4[4],!B5[4],B5[5],!B5[6],B5[7] buffer span4_vert_b_12 lc_trk_g0_4 +B12[4],!B13[4],B13[5],!B13[6],B13[7] buffer span4_vert_b_12 lc_trk_g1_4 +B4[5],!B4[6],B4[7],B4[8],!B5[8] buffer span4_vert_b_13 lc_trk_g0_5 +B12[5],!B12[6],B12[7],B12[8],!B13[8] buffer span4_vert_b_13 lc_trk_g1_5 +B6[4],!B7[4],B7[5],!B7[6],B7[7] buffer span4_vert_b_14 lc_trk_g0_6 +B14[4],!B15[4],B15[5],!B15[6],B15[7] buffer span4_vert_b_14 lc_trk_g1_6 +B6[5],!B6[6],B6[7],B6[8],!B7[8] buffer span4_vert_b_15 lc_trk_g0_7 +B14[5],!B14[6],B14[7],B14[8],!B15[8] buffer span4_vert_b_15 lc_trk_g1_7 +!B2[4],B3[4],B3[5],!B3[6],B3[7] buffer span4_vert_b_2 lc_trk_g0_2 +!B10[4],B11[4],B11[5],!B11[6],B11[7] buffer span4_vert_b_2 lc_trk_g1_2 +B2[5],!B2[6],B2[7],!B2[8],B3[8] buffer span4_vert_b_3 lc_trk_g0_3 +B10[5],!B10[6],B10[7],!B10[8],B11[8] buffer span4_vert_b_3 lc_trk_g1_3 +!B4[4],B5[4],B5[5],!B5[6],B5[7] buffer span4_vert_b_4 lc_trk_g0_4 +!B12[4],B13[4],B13[5],!B13[6],B13[7] buffer span4_vert_b_4 lc_trk_g1_4 +B4[5],!B4[6],B4[7],!B4[8],B5[8] buffer span4_vert_b_5 lc_trk_g0_5 +B12[5],!B12[6],B12[7],!B12[8],B13[8] buffer span4_vert_b_5 lc_trk_g1_5 +!B6[4],B7[4],B7[5],!B7[6],B7[7] buffer span4_vert_b_6 lc_trk_g0_6 +!B14[4],B15[4],B15[5],!B15[6],B15[7] buffer span4_vert_b_6 lc_trk_g1_6 +B6[5],!B6[6],B6[7],!B6[8],B7[8] buffer span4_vert_b_7 lc_trk_g0_7 +B14[5],!B14[6],B14[7],!B14[8],B15[8] buffer span4_vert_b_7 lc_trk_g1_7 +B0[4],!B1[4],B1[5],!B1[6],B1[7] buffer span4_vert_b_8 lc_trk_g0_0 +B8[4],!B9[4],B9[5],!B9[6],B9[7] buffer span4_vert_b_8 lc_trk_g1_0 +B0[5],!B0[6],B0[7],B0[8],!B1[8] buffer span4_vert_b_9 lc_trk_g0_1 +B8[5],!B8[6],B8[7],B8[8],!B9[8] buffer span4_vert_b_9 lc_trk_g1_1 +B1[17] buffer wire_io_cluster/io_0/D_IN_0 span12_horz_0 +B5[17] buffer wire_io_cluster/io_0/D_IN_0 span12_horz_16 +B2[17] buffer wire_io_cluster/io_0/D_IN_0 span12_horz_8 +B1[17] buffer wire_io_cluster/io_0/D_IN_0 span12_vert_0 +B5[17] buffer wire_io_cluster/io_0/D_IN_0 span12_vert_16 +B2[17] buffer wire_io_cluster/io_0/D_IN_0 span12_vert_8 +B1[0] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_0 +B0[0] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_16 +B0[1] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_24 +B1[2] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_32 +B3[0] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_40 +B1[1] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_8 +B3[1] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_r_0 +B3[2] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_r_12 +B2[0] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_r_4 +B2[1] buffer wire_io_cluster/io_0/D_IN_0 span4_horz_r_8 +B1[0] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_0 +B0[0] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_16 +B0[1] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_24 +B1[2] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_32 +B3[0] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_40 +B1[1] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_8 +B3[1] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_b_0 +B3[2] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_b_12 +B2[0] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_b_4 +B2[1] buffer wire_io_cluster/io_0/D_IN_0 span4_vert_b_8 +B7[17] buffer wire_io_cluster/io_0/D_IN_1 span12_horz_10 +B6[16] buffer wire_io_cluster/io_0/D_IN_1 span12_horz_18 +B7[16] buffer wire_io_cluster/io_0/D_IN_1 span12_horz_2 +B7[17] buffer wire_io_cluster/io_0/D_IN_1 span12_vert_10 +B6[16] buffer wire_io_cluster/io_0/D_IN_1 span12_vert_18 +B7[16] buffer wire_io_cluster/io_0/D_IN_1 span12_vert_2 +B5[1] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_10 +B4[0] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_18 +B5[0] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_2 +B4[1] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_26 +B5[2] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_34 +B7[0] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_42 +B7[1] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_r_1 +B7[2] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_r_13 +B6[0] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_r_5 +B6[1] buffer wire_io_cluster/io_0/D_IN_1 span4_horz_r_9 +B4[0] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_18 +B5[0] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_2 +B4[1] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_26 +B5[2] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_34 +B7[0] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_42 +B7[1] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_b_1 +B7[2] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_b_13 +B6[0] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_b_5 +B6[1] buffer wire_io_cluster/io_0/D_IN_1 span4_vert_b_9 +B9[17] buffer wire_io_cluster/io_1/D_IN_0 span12_horz_12 +B8[16] buffer wire_io_cluster/io_1/D_IN_0 span12_horz_20 +B9[16] buffer wire_io_cluster/io_1/D_IN_0 span12_horz_4 +B9[17] buffer wire_io_cluster/io_1/D_IN_0 span12_vert_12 +B8[16] buffer wire_io_cluster/io_1/D_IN_0 span12_vert_20 +B9[16] buffer wire_io_cluster/io_1/D_IN_0 span12_vert_4 +B9[1] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_12 +B8[0] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_20 +B8[1] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_28 +B9[2] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_36 +B9[0] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_4 +B11[0] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_44 +B10[1] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_r_10 +B11[2] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_r_14 +B11[1] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_r_2 +B10[0] buffer wire_io_cluster/io_1/D_IN_0 span4_horz_r_6 +B9[1] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_12 +B8[0] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_20 +B8[1] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_28 +B9[2] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_36 +B9[0] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_4 +B11[0] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_44 +B10[1] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_b_10 +B11[2] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_b_14 +B11[1] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_b_2 +B10[0] buffer wire_io_cluster/io_1/D_IN_0 span4_vert_b_6 +B12[17] buffer wire_io_cluster/io_1/D_IN_1 span12_horz_14 +B15[17] buffer wire_io_cluster/io_1/D_IN_1 span12_horz_22 +B11[17] buffer wire_io_cluster/io_1/D_IN_1 span12_horz_6 +B12[17] buffer wire_io_cluster/io_1/D_IN_1 span12_vert_14 +B15[17] buffer wire_io_cluster/io_1/D_IN_1 span12_vert_22 +B11[17] buffer wire_io_cluster/io_1/D_IN_1 span12_vert_6 +B13[1] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_14 +B12[0] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_22 +B12[1] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_30 +B13[2] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_38 +B13[0] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_6 +B14[1] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_r_11 +B15[2] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_r_15 +B15[1] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_r_3 +B14[0] buffer wire_io_cluster/io_1/D_IN_1 span4_horz_r_7 +B13[1] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_14 +B12[0] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_22 +B12[1] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_30 +B13[2] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_38 +B15[0] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_46 +B13[0] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_6 +B14[1] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_b_11 +B15[2] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_b_15 +B15[1] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_b_3 +B14[0] buffer wire_io_cluster/io_1/D_IN_1 span4_vert_b_7 +B1[11],B1[12] routing span4_horz_1 span4_horz_25 +B1[13],B1[14] routing span4_horz_1 span4_vert_b_0 +B0[11],B0[12] routing span4_horz_1 span4_vert_t_12 +B7[11],B7[12] routing span4_horz_13 span4_horz_37 +B7[13],B7[14] routing span4_horz_13 span4_vert_b_2 +B6[11],B6[12] routing span4_horz_13 span4_vert_t_14 +B13[11],B13[12] routing span4_horz_19 span4_horz_43 +B13[13],B13[14] routing span4_horz_19 span4_vert_b_3 +B12[11],B12[12] routing span4_horz_19 span4_vert_t_15 +B0[13],!B0[14] routing span4_horz_25 span4_horz_1 +B1[13],!B1[14] routing span4_horz_25 span4_vert_b_0 +!B0[11],B0[12] routing span4_horz_25 span4_vert_t_12 +B2[13],!B2[14] routing span4_horz_31 span4_horz_7 +B3[13],!B3[14] routing span4_horz_31 span4_vert_b_1 +!B2[11],B2[12] routing span4_horz_31 span4_vert_t_13 +B6[13],!B6[14] routing span4_horz_37 span4_horz_13 +B7[13],!B7[14] routing span4_horz_37 span4_vert_b_2 +!B6[11],B6[12] routing span4_horz_37 span4_vert_t_14 +B12[13],!B12[14] routing span4_horz_43 span4_horz_19 +B13[13],!B13[14] routing span4_horz_43 span4_vert_b_3 +!B12[11],B12[12] routing span4_horz_43 span4_vert_t_15 +B3[11],B3[12] routing span4_horz_7 span4_horz_31 +B3[13],B3[14] routing span4_horz_7 span4_vert_b_1 +B2[11],B2[12] routing span4_horz_7 span4_vert_t_13 +!B1[13],B1[14] routing span4_horz_l_12 span4_horz_r_0 +!B0[13],B0[14] routing span4_horz_l_12 span4_vert_1 +B1[11],!B1[12] routing span4_horz_l_12 span4_vert_25 +!B3[13],B3[14] routing span4_horz_l_13 span4_horz_r_1 +B3[11],!B3[12] routing span4_horz_l_13 span4_vert_31 +!B2[13],B2[14] routing span4_horz_l_13 span4_vert_7 +!B7[13],B7[14] routing span4_horz_l_14 span4_horz_r_2 +!B6[13],B6[14] routing span4_horz_l_14 span4_vert_13 +B7[11],!B7[12] routing span4_horz_l_14 span4_vert_37 +!B13[13],B13[14] routing span4_horz_l_15 span4_horz_r_3 +!B12[13],B12[14] routing span4_horz_l_15 span4_vert_19 +B13[11],!B13[12] routing span4_horz_l_15 span4_vert_43 +B0[11],!B0[12] routing span4_horz_r_0 span4_horz_l_12 +B0[13],B0[14] routing span4_horz_r_0 span4_vert_1 +!B1[11],B1[12] routing span4_horz_r_0 span4_vert_25 +B2[11],!B2[12] routing span4_horz_r_1 span4_horz_l_13 +!B3[11],B3[12] routing span4_horz_r_1 span4_vert_31 +B2[13],B2[14] routing span4_horz_r_1 span4_vert_7 +B6[11],!B6[12] routing span4_horz_r_2 span4_horz_l_14 +B6[13],B6[14] routing span4_horz_r_2 span4_vert_13 +!B7[11],B7[12] routing span4_horz_r_2 span4_vert_37 +B12[11],!B12[12] routing span4_horz_r_3 span4_horz_l_15 +B12[13],B12[14] routing span4_horz_r_3 span4_vert_19 +!B13[11],B13[12] routing span4_horz_r_3 span4_vert_43 +B0[11],B0[12] routing span4_vert_1 span4_horz_l_12 +B1[13],B1[14] routing span4_vert_1 span4_horz_r_0 +B1[11],B1[12] routing span4_vert_1 span4_vert_25 +B6[11],B6[12] routing span4_vert_13 span4_horz_l_14 +B7[13],B7[14] routing span4_vert_13 span4_horz_r_2 +B7[11],B7[12] routing span4_vert_13 span4_vert_37 +B12[11],B12[12] routing span4_vert_19 span4_horz_l_15 +B13[13],B13[14] routing span4_vert_19 span4_horz_r_3 +B13[11],B13[12] routing span4_vert_19 span4_vert_43 +!B0[11],B0[12] routing span4_vert_25 span4_horz_l_12 +B1[13],!B1[14] routing span4_vert_25 span4_horz_r_0 +B0[13],!B0[14] routing span4_vert_25 span4_vert_1 +!B2[11],B2[12] routing span4_vert_31 span4_horz_l_13 +B3[13],!B3[14] routing span4_vert_31 span4_horz_r_1 +B2[13],!B2[14] routing span4_vert_31 span4_vert_7 +!B6[11],B6[12] routing span4_vert_37 span4_horz_l_14 +B7[13],!B7[14] routing span4_vert_37 span4_horz_r_2 +B6[13],!B6[14] routing span4_vert_37 span4_vert_13 +!B12[11],B12[12] routing span4_vert_43 span4_horz_l_15 +B13[13],!B13[14] routing span4_vert_43 span4_horz_r_3 +B12[13],!B12[14] routing span4_vert_43 span4_vert_19 +B2[11],B2[12] routing span4_vert_7 span4_horz_l_13 +B3[13],B3[14] routing span4_vert_7 span4_horz_r_1 +B3[11],B3[12] routing span4_vert_7 span4_vert_31 +B0[13],B0[14] routing span4_vert_b_0 span4_horz_1 +!B1[11],B1[12] routing span4_vert_b_0 span4_horz_25 +B0[11],!B0[12] routing span4_vert_b_0 span4_vert_t_12 +!B3[11],B3[12] routing span4_vert_b_1 span4_horz_31 +B2[13],B2[14] routing span4_vert_b_1 span4_horz_7 +B2[11],!B2[12] routing span4_vert_b_1 span4_vert_t_13 +B6[13],B6[14] routing span4_vert_b_2 span4_horz_13 +!B7[11],B7[12] routing span4_vert_b_2 span4_horz_37 +B6[11],!B6[12] routing span4_vert_b_2 span4_vert_t_14 +B12[13],B12[14] routing span4_vert_b_3 span4_horz_19 +!B13[11],B13[12] routing span4_vert_b_3 span4_horz_43 +B12[11],!B12[12] routing span4_vert_b_3 span4_vert_t_15 +!B0[13],B0[14] routing span4_vert_t_12 span4_horz_1 +B1[11],!B1[12] routing span4_vert_t_12 span4_horz_25 +!B1[13],B1[14] routing span4_vert_t_12 span4_vert_b_0 +B3[11],!B3[12] routing span4_vert_t_13 span4_horz_31 +!B2[13],B2[14] routing span4_vert_t_13 span4_horz_7 +!B3[13],B3[14] routing span4_vert_t_13 span4_vert_b_1 +!B6[13],B6[14] routing span4_vert_t_14 span4_horz_13 +B7[11],!B7[12] routing span4_vert_t_14 span4_horz_37 +!B7[13],B7[14] routing span4_vert_t_14 span4_vert_b_2 +!B12[13],B12[14] routing span4_vert_t_15 span4_horz_19 +B13[11],!B13[12] routing span4_vert_t_15 span4_horz_43 +!B13[13],B13[14] routing span4_vert_t_15 span4_vert_b_3 +""" +database_logic_txt = """ +B0[1] ColBufCtrl LH_colbuf_cntl_0 B0[1] +B9[7] ColBufCtrl LH_colbuf_cntl_0 B9[7] +B1[2] ColBufCtrl LH_colbuf_cntl_1 B1[2] +B8[7] ColBufCtrl LH_colbuf_cntl_1 B8[7] +B11[7] ColBufCtrl LH_colbuf_cntl_2 B11[7] +B5[2] ColBufCtrl LH_colbuf_cntl_2 B5[2] +B10[7] ColBufCtrl LH_colbuf_cntl_3 B10[7] +B7[2] ColBufCtrl LH_colbuf_cntl_3 B7[2] +B13[7] ColBufCtrl LH_colbuf_cntl_4 B13[7] +B9[2] ColBufCtrl LH_colbuf_cntl_4 B9[2] +B11[2] ColBufCtrl LH_colbuf_cntl_5 B11[2] +B12[7] ColBufCtrl LH_colbuf_cntl_5 B12[7] +B13[2] ColBufCtrl LH_colbuf_cntl_6 B13[2] +B15[7] ColBufCtrl LH_colbuf_cntl_6 B15[7] +B14[7] ColBufCtrl LH_colbuf_cntl_7 B14[7] +B15[2] ColBufCtrl LH_colbuf_cntl_7 B15[2] +B0[36],B0[37],B0[38],B0[39],B0[40],B0[41],B0[42],B0[43],B0[44],B0[45],B1[36],B1[37],B1[38],B1[39],B1[40],B1[41],B1[42],B1[43],B1[44],B1[45] LC_0 +B2[36],B2[37],B2[38],B2[39],B2[40],B2[41],B2[42],B2[43],B2[44],B2[45],B3[36],B3[37],B3[38],B3[39],B3[40],B3[41],B3[42],B3[43],B3[44],B3[45] LC_1 +B4[36],B4[37],B4[38],B4[39],B4[40],B4[41],B4[42],B4[43],B4[44],B4[45],B5[36],B5[37],B5[38],B5[39],B5[40],B5[41],B5[42],B5[43],B5[44],B5[45] LC_2 +B6[36],B6[37],B6[38],B6[39],B6[40],B6[41],B6[42],B6[43],B6[44],B6[45],B7[36],B7[37],B7[38],B7[39],B7[40],B7[41],B7[42],B7[43],B7[44],B7[45] LC_3 +B8[36],B8[37],B8[38],B8[39],B8[40],B8[41],B8[42],B8[43],B8[44],B8[45],B9[36],B9[37],B9[38],B9[39],B9[40],B9[41],B9[42],B9[43],B9[44],B9[45] LC_4 +B10[36],B10[37],B10[38],B10[39],B10[40],B10[41],B10[42],B10[43],B10[44],B10[45],B11[36],B11[37],B11[38],B11[39],B11[40],B11[41],B11[42],B11[43],B11[44],B11[45] LC_5 +B12[36],B12[37],B12[38],B12[39],B12[40],B12[41],B12[42],B12[43],B12[44],B12[45],B13[36],B13[37],B13[38],B13[39],B13[40],B13[41],B13[42],B13[43],B13[44],B13[45] LC_6 +B14[36],B14[37],B14[38],B14[39],B14[40],B14[41],B14[42],B14[43],B14[44],B14[45],B15[36],B15[37],B15[38],B15[39],B15[40],B15[41],B15[42],B15[43],B15[44],B15[45] LC_7 +B0[0] NegClk +B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer bnl_op_0 lc_trk_g2_0 +B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer bnl_op_0 lc_trk_g3_0 +!B8[15],!B8[16],B8[17],B8[18],B9[18] buffer bnl_op_1 lc_trk_g2_1 +!B12[15],!B12[16],B12[17],B12[18],B13[18] buffer bnl_op_1 lc_trk_g3_1 +B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer bnl_op_2 lc_trk_g2_2 +B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer bnl_op_2 lc_trk_g3_2 +B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer bnl_op_3 lc_trk_g2_3 +B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer bnl_op_3 lc_trk_g3_3 +B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer bnl_op_4 lc_trk_g2_4 +B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer bnl_op_4 lc_trk_g3_4 +!B10[15],!B10[16],B10[17],B10[18],B11[18] buffer bnl_op_5 lc_trk_g2_5 +!B14[15],!B14[16],B14[17],B14[18],B15[18] buffer bnl_op_5 lc_trk_g3_5 +B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer bnl_op_6 lc_trk_g2_6 +B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer bnl_op_6 lc_trk_g3_6 +B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer bnl_op_7 lc_trk_g2_7 +B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer bnl_op_7 lc_trk_g3_7 +B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer bnr_op_0 lc_trk_g0_0 +B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer bnr_op_0 lc_trk_g1_0 +!B0[15],!B0[16],B0[17],B0[18],B1[18] buffer bnr_op_1 lc_trk_g0_1 +!B4[15],!B4[16],B4[17],B4[18],B5[18] buffer bnr_op_1 lc_trk_g1_1 +B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer bnr_op_2 lc_trk_g0_2 +B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer bnr_op_2 lc_trk_g1_2 +B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer bnr_op_3 lc_trk_g0_3 +B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer bnr_op_3 lc_trk_g1_3 +B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer bnr_op_4 lc_trk_g0_4 +B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer bnr_op_4 lc_trk_g1_4 +!B2[15],!B2[16],B2[17],B2[18],B3[18] buffer bnr_op_5 lc_trk_g0_5 +!B6[15],!B6[16],B6[17],B6[18],B7[18] buffer bnr_op_5 lc_trk_g1_5 +B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer bnr_op_6 lc_trk_g0_6 +B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer bnr_op_6 lc_trk_g1_6 +B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer bnr_op_7 lc_trk_g0_7 +B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7 +!B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer bot_op_0 lc_trk_g0_0 +!B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer bot_op_0 lc_trk_g1_0 +B0[15],!B0[16],B0[17],!B0[18],!B1[18] buffer bot_op_1 lc_trk_g0_1 +B4[15],!B4[16],B4[17],!B4[18],!B5[18] buffer bot_op_1 lc_trk_g1_1 +!B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer bot_op_2 lc_trk_g0_2 +!B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer bot_op_2 lc_trk_g1_2 +!B0[21],B0[22],!B0[23],B0[24],!B1[21] buffer bot_op_3 lc_trk_g0_3 +!B4[21],B4[22],!B4[23],B4[24],!B5[21] buffer bot_op_3 lc_trk_g1_3 +!B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer bot_op_4 lc_trk_g0_4 +!B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer bot_op_4 lc_trk_g1_4 +B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer bot_op_5 lc_trk_g0_5 +B6[15],!B6[16],B6[17],!B6[18],!B7[18] buffer bot_op_5 lc_trk_g1_5 +!B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer bot_op_6 lc_trk_g0_6 +!B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer bot_op_6 lc_trk_g1_6 +!B2[21],B2[22],!B2[23],B2[24],!B3[21] buffer bot_op_7 lc_trk_g0_7 +!B6[21],B6[22],!B6[23],B6[24],!B7[21] buffer bot_op_7 lc_trk_g1_7 +!B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer glb2local_0 lc_trk_g0_4 +!B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer glb2local_1 lc_trk_g0_5 +!B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6 +!B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer glb2local_3 lc_trk_g0_7 +!B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_0 glb2local_0 +!B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_0 glb2local_1 +!B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_0 glb2local_2 +!B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_0 wire_logic_cluster/lc_7/clk +!B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_0 wire_logic_cluster/lc_7/s_r +!B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0 +!B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1 +!B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2 +!B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3 +!B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_1 wire_logic_cluster/lc_7/cen +!B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_1 wire_logic_cluster/lc_7/clk +B6[0],B6[1],!B7[0],!B7[1] buffer glb_netwk_2 glb2local_0 +B8[0],B8[1],!B9[0],!B9[1] buffer glb_netwk_2 glb2local_1 +B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_2 glb2local_2 +B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_2 glb2local_3 +B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_logic_cluster/lc_7/clk +!B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_2 wire_logic_cluster/lc_7/s_r +B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0 +B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_3 glb2local_1 +B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_3 glb2local_2 +B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_3 glb2local_3 +!B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_3 wire_logic_cluster/lc_7/cen +B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_3 wire_logic_cluster/lc_7/clk +!B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_4 glb2local_0 +!B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_4 glb2local_1 +!B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_4 glb2local_2 +!B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_4 glb2local_3 +!B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 wire_logic_cluster/lc_7/clk +B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_logic_cluster/lc_7/s_r +!B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0 +!B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_5 glb2local_1 +!B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2 +!B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3 +B4[0],B4[1],!B5[0],!B5[1] buffer glb_netwk_5 wire_logic_cluster/lc_7/cen +!B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_logic_cluster/lc_7/clk +B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_6 glb2local_0 +B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_6 glb2local_1 +B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2 +B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_6 glb2local_3 +B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_6 wire_logic_cluster/lc_7/clk +B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_logic_cluster/lc_7/s_r +B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_7 glb2local_0 +B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_7 glb2local_1 +B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_7 glb2local_2 +B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_7 glb2local_3 +B4[0],B4[1],B5[0],!B5[1] buffer glb_netwk_7 wire_logic_cluster/lc_7/cen +B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_logic_cluster/lc_7/clk +!B0[35],B1[32],!B1[33],!B1[34],!B1[35] buffer lc_trk_g0_0 input_2_0 +!B4[35],B5[32],!B5[33],!B5[34],!B5[35] buffer lc_trk_g0_0 input_2_2 +!B8[35],B9[32],!B9[33],!B9[34],!B9[35] buffer lc_trk_g0_0 input_2_4 +!B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_0 input_2_6 +!B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 wire_logic_cluster/lc_0/in_0 +!B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g0_0 wire_logic_cluster/lc_1/in_1 +!B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_0 wire_logic_cluster/lc_2/in_0 +!B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_logic_cluster/lc_3/in_1 +!B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_0 wire_logic_cluster/lc_4/in_0 +!B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g0_0 wire_logic_cluster/lc_5/in_1 +!B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_0 wire_logic_cluster/lc_6/in_0 +!B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g0_0 wire_logic_cluster/lc_7/clk +!B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g0_0 wire_logic_cluster/lc_7/in_1 +!B2[35],B3[32],!B3[33],!B3[34],!B3[35] buffer lc_trk_g0_1 input_2_1 +!B6[35],B7[32],!B7[33],!B7[34],!B7[35] buffer lc_trk_g0_1 input_2_3 +!B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_1 input_2_5 +!B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_1 input_2_7 +!B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g0_1 wire_logic_cluster/lc_0/in_1 +!B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_1 wire_logic_cluster/lc_1/in_0 +!B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_logic_cluster/lc_2/in_1 +!B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_1 wire_logic_cluster/lc_3/in_0 +!B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_logic_cluster/lc_4/in_1 +!B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_1 wire_logic_cluster/lc_5/in_0 +!B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_logic_cluster/lc_6/in_1 +!B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_1 wire_logic_cluster/lc_7/in_0 +!B0[35],B1[32],!B1[33],!B1[34],B1[35] buffer lc_trk_g0_2 input_2_0 +!B4[35],B5[32],!B5[33],!B5[34],B5[35] buffer lc_trk_g0_2 input_2_2 +!B8[35],B9[32],!B9[33],!B9[34],B9[35] buffer lc_trk_g0_2 input_2_4 +!B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_2 input_2_6 +!B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_2 wire_logic_cluster/lc_0/in_0 +!B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_logic_cluster/lc_1/in_1 +!B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_logic_cluster/lc_1/in_3 +!B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_2 wire_logic_cluster/lc_2/in_0 +!B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_logic_cluster/lc_3/in_1 +!B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_logic_cluster/lc_3/in_3 +!B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_2 wire_logic_cluster/lc_4/in_0 +!B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_logic_cluster/lc_5/in_1 +!B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_logic_cluster/lc_5/in_3 +!B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_2 wire_logic_cluster/lc_6/in_0 +!B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g0_2 wire_logic_cluster/lc_7/cen +!B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_logic_cluster/lc_7/in_1 +!B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_logic_cluster/lc_7/in_3 +!B2[35],B3[32],!B3[33],!B3[34],B3[35] buffer lc_trk_g0_3 input_2_1 +!B6[35],B7[32],!B7[33],!B7[34],B7[35] buffer lc_trk_g0_3 input_2_3 +!B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_3 input_2_5 +!B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_3 input_2_7 +!B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_logic_cluster/lc_0/in_1 +!B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_logic_cluster/lc_0/in_3 +!B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_3 wire_logic_cluster/lc_1/in_0 +!B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_logic_cluster/lc_2/in_1 +!B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_logic_cluster/lc_2/in_3 +!B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_3 wire_logic_cluster/lc_3/in_0 +!B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_logic_cluster/lc_4/in_1 +!B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_logic_cluster/lc_4/in_3 +!B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_3 wire_logic_cluster/lc_5/in_0 +!B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_logic_cluster/lc_6/in_1 +!B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_logic_cluster/lc_6/in_3 +!B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_3 wire_logic_cluster/lc_7/in_0 +B0[35],B1[32],!B1[33],!B1[34],!B1[35] buffer lc_trk_g0_4 input_2_0 +B4[35],B5[32],!B5[33],!B5[34],!B5[35] buffer lc_trk_g0_4 input_2_2 +B8[35],B9[32],!B9[33],!B9[34],!B9[35] buffer lc_trk_g0_4 input_2_4 +B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_4 input_2_6 +B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_4 wire_logic_cluster/lc_0/in_0 +!B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_logic_cluster/lc_1/in_1 +B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_logic_cluster/lc_1/in_3 +B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_4 wire_logic_cluster/lc_2/in_0 +!B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_logic_cluster/lc_3/in_1 +B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_logic_cluster/lc_3/in_3 +B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_4 wire_logic_cluster/lc_4/in_0 +!B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_logic_cluster/lc_5/in_1 +B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_logic_cluster/lc_5/in_3 +B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_4 wire_logic_cluster/lc_6/in_0 +!B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_logic_cluster/lc_7/in_1 +B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_logic_cluster/lc_7/in_3 +!B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_logic_cluster/lc_7/s_r +B2[35],B3[32],!B3[33],!B3[34],!B3[35] buffer lc_trk_g0_5 input_2_1 +B6[35],B7[32],!B7[33],!B7[34],!B7[35] buffer lc_trk_g0_5 input_2_3 +B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_5 input_2_5 +B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_5 input_2_7 +!B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g0_5 wire_logic_cluster/lc_0/in_1 +B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_logic_cluster/lc_0/in_3 +B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_5 wire_logic_cluster/lc_1/in_0 +!B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_logic_cluster/lc_2/in_1 +B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_logic_cluster/lc_2/in_3 +B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_5 wire_logic_cluster/lc_3/in_0 +!B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_logic_cluster/lc_4/in_1 +B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_logic_cluster/lc_4/in_3 +B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_5 wire_logic_cluster/lc_5/in_0 +!B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_logic_cluster/lc_6/in_1 +B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_logic_cluster/lc_6/in_3 +B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_5 wire_logic_cluster/lc_7/in_0 +B0[35],B1[32],!B1[33],!B1[34],B1[35] buffer lc_trk_g0_6 input_2_0 +B4[35],B5[32],!B5[33],!B5[34],B5[35] buffer lc_trk_g0_6 input_2_2 +B8[35],B9[32],!B9[33],!B9[34],B9[35] buffer lc_trk_g0_6 input_2_4 +B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_6 input_2_6 +B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_6 wire_logic_cluster/lc_0/in_0 +!B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g0_6 wire_logic_cluster/lc_1/in_1 +B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_logic_cluster/lc_1/in_3 +B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_6 wire_logic_cluster/lc_2/in_0 +!B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g0_6 wire_logic_cluster/lc_3/in_1 +B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_logic_cluster/lc_3/in_3 +B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_6 wire_logic_cluster/lc_4/in_0 +!B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_logic_cluster/lc_5/in_1 +B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_6 wire_logic_cluster/lc_5/in_3 +B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_6 wire_logic_cluster/lc_6/in_0 +!B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_logic_cluster/lc_7/in_1 +B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_logic_cluster/lc_7/in_3 +B2[35],B3[32],!B3[33],!B3[34],B3[35] buffer lc_trk_g0_7 input_2_1 +B6[35],B7[32],!B7[33],!B7[34],B7[35] buffer lc_trk_g0_7 input_2_3 +B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_7 input_2_5 +B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_7 input_2_7 +!B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_logic_cluster/lc_0/in_1 +B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_logic_cluster/lc_0/in_3 +B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_7 wire_logic_cluster/lc_1/in_0 +!B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_logic_cluster/lc_2/in_1 +B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_logic_cluster/lc_2/in_3 +B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_7 wire_logic_cluster/lc_3/in_0 +!B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_logic_cluster/lc_4/in_1 +B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_logic_cluster/lc_4/in_3 +B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_7 wire_logic_cluster/lc_5/in_0 +!B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_logic_cluster/lc_6/in_1 +B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_logic_cluster/lc_6/in_3 +B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_7 wire_logic_cluster/lc_7/in_0 +!B2[35],B3[32],!B3[33],B3[34],!B3[35] buffer lc_trk_g1_0 input_2_1 +!B6[35],B7[32],!B7[33],B7[34],!B7[35] buffer lc_trk_g1_0 input_2_3 +!B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_0 input_2_5 +!B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_0 input_2_7 +B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_logic_cluster/lc_0/in_1 +!B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_logic_cluster/lc_0/in_3 +!B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_0 wire_logic_cluster/lc_1/in_0 +B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_logic_cluster/lc_2/in_1 +!B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_logic_cluster/lc_2/in_3 +!B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_0 wire_logic_cluster/lc_3/in_0 +B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_logic_cluster/lc_4/in_1 +!B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_logic_cluster/lc_4/in_3 +!B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_0 wire_logic_cluster/lc_5/in_0 +B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_logic_cluster/lc_6/in_1 +!B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_logic_cluster/lc_6/in_3 +!B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_0 wire_logic_cluster/lc_7/in_0 +!B0[35],B1[32],!B1[33],B1[34],!B1[35] buffer lc_trk_g1_1 input_2_0 +!B4[35],B5[32],!B5[33],B5[34],!B5[35] buffer lc_trk_g1_1 input_2_2 +!B8[35],B9[32],!B9[33],B9[34],!B9[35] buffer lc_trk_g1_1 input_2_4 +!B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_1 input_2_6 +!B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_1 wire_logic_cluster/lc_0/in_0 +B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_logic_cluster/lc_1/in_1 +!B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_1 wire_logic_cluster/lc_1/in_3 +!B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_1 wire_logic_cluster/lc_2/in_0 +B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g1_1 wire_logic_cluster/lc_3/in_1 +!B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_logic_cluster/lc_3/in_3 +!B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_1 wire_logic_cluster/lc_4/in_0 +B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_logic_cluster/lc_5/in_1 +!B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_logic_cluster/lc_5/in_3 +!B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_1 wire_logic_cluster/lc_6/in_0 +!B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g1_1 wire_logic_cluster/lc_7/clk +B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_logic_cluster/lc_7/in_1 +!B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_logic_cluster/lc_7/in_3 +!B2[35],B3[32],!B3[33],B3[34],B3[35] buffer lc_trk_g1_2 input_2_1 +!B6[35],B7[32],!B7[33],B7[34],B7[35] buffer lc_trk_g1_2 input_2_3 +!B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_2 input_2_5 +!B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_2 input_2_7 +B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_logic_cluster/lc_0/in_1 +!B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_logic_cluster/lc_0/in_3 +!B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_2 wire_logic_cluster/lc_1/in_0 +B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_logic_cluster/lc_2/in_1 +!B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_logic_cluster/lc_2/in_3 +!B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_2 wire_logic_cluster/lc_3/in_0 +B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_logic_cluster/lc_4/in_1 +!B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_logic_cluster/lc_4/in_3 +!B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_2 wire_logic_cluster/lc_5/in_0 +B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_logic_cluster/lc_6/in_1 +!B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_logic_cluster/lc_6/in_3 +!B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_2 wire_logic_cluster/lc_7/in_0 +!B0[35],B1[32],!B1[33],B1[34],B1[35] buffer lc_trk_g1_3 input_2_0 +!B4[35],B5[32],!B5[33],B5[34],B5[35] buffer lc_trk_g1_3 input_2_2 +!B8[35],B9[32],!B9[33],B9[34],B9[35] buffer lc_trk_g1_3 input_2_4 +!B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_3 input_2_6 +!B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_3 wire_logic_cluster/lc_0/in_0 +B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_logic_cluster/lc_1/in_1 +!B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_logic_cluster/lc_1/in_3 +!B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_3 wire_logic_cluster/lc_2/in_0 +B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_logic_cluster/lc_3/in_1 +!B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_logic_cluster/lc_3/in_3 +!B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_3 wire_logic_cluster/lc_4/in_0 +B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_logic_cluster/lc_5/in_1 +!B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_logic_cluster/lc_5/in_3 +!B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_3 wire_logic_cluster/lc_6/in_0 +!B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g1_3 wire_logic_cluster/lc_7/cen +B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_logic_cluster/lc_7/in_1 +!B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_logic_cluster/lc_7/in_3 +B2[35],B3[32],!B3[33],B3[34],!B3[35] buffer lc_trk_g1_4 input_2_1 +B6[35],B7[32],!B7[33],B7[34],!B7[35] buffer lc_trk_g1_4 input_2_3 +B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_4 input_2_5 +B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_4 input_2_7 +B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g1_4 wire_logic_cluster/lc_0/in_1 +B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_4 wire_logic_cluster/lc_0/in_3 +B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_4 wire_logic_cluster/lc_1/in_0 +B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g1_4 wire_logic_cluster/lc_2/in_1 +B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_4 wire_logic_cluster/lc_2/in_3 +B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_4 wire_logic_cluster/lc_3/in_0 +B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g1_4 wire_logic_cluster/lc_4/in_1 +B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_4 wire_logic_cluster/lc_4/in_3 +B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_4 wire_logic_cluster/lc_5/in_0 +B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g1_4 wire_logic_cluster/lc_6/in_1 +B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_4 wire_logic_cluster/lc_6/in_3 +B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_4 wire_logic_cluster/lc_7/in_0 +B0[35],B1[32],!B1[33],B1[34],!B1[35] buffer lc_trk_g1_5 input_2_0 +B4[35],B5[32],!B5[33],B5[34],!B5[35] buffer lc_trk_g1_5 input_2_2 +B8[35],B9[32],!B9[33],B9[34],!B9[35] buffer lc_trk_g1_5 input_2_4 +B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_5 input_2_6 +B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_5 wire_logic_cluster/lc_0/in_0 +B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_logic_cluster/lc_1/in_1 +B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_logic_cluster/lc_1/in_3 +B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_5 wire_logic_cluster/lc_2/in_0 +B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_logic_cluster/lc_3/in_1 +B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_logic_cluster/lc_3/in_3 +B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_5 wire_logic_cluster/lc_4/in_0 +B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_logic_cluster/lc_5/in_1 +B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_logic_cluster/lc_5/in_3 +B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_5 wire_logic_cluster/lc_6/in_0 +B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_logic_cluster/lc_7/in_1 +B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_logic_cluster/lc_7/in_3 +!B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_logic_cluster/lc_7/s_r +B2[35],B3[32],!B3[33],B3[34],B3[35] buffer lc_trk_g1_6 input_2_1 +B6[35],B7[32],!B7[33],B7[34],B7[35] buffer lc_trk_g1_6 input_2_3 +B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_6 input_2_5 +B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_6 input_2_7 +B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g1_6 wire_logic_cluster/lc_0/in_1 +B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_logic_cluster/lc_0/in_3 +B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_6 wire_logic_cluster/lc_1/in_0 +B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_logic_cluster/lc_2/in_1 +B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_logic_cluster/lc_2/in_3 +B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_6 wire_logic_cluster/lc_3/in_0 +B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_logic_cluster/lc_4/in_1 +B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_logic_cluster/lc_4/in_3 +B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_6 wire_logic_cluster/lc_5/in_0 +B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_logic_cluster/lc_6/in_1 +B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_logic_cluster/lc_6/in_3 +B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_6 wire_logic_cluster/lc_7/in_0 +B0[35],B1[32],!B1[33],B1[34],B1[35] buffer lc_trk_g1_7 input_2_0 +B4[35],B5[32],!B5[33],B5[34],B5[35] buffer lc_trk_g1_7 input_2_2 +B8[35],B9[32],!B9[33],B9[34],B9[35] buffer lc_trk_g1_7 input_2_4 +B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_7 input_2_6 +B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_7 wire_logic_cluster/lc_0/in_0 +B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_logic_cluster/lc_1/in_1 +B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_logic_cluster/lc_1/in_3 +B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_7 wire_logic_cluster/lc_2/in_0 +B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_logic_cluster/lc_3/in_1 +B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_logic_cluster/lc_3/in_3 +B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_7 wire_logic_cluster/lc_4/in_0 +B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_logic_cluster/lc_5/in_1 +B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_logic_cluster/lc_5/in_3 +B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_7 wire_logic_cluster/lc_6/in_0 +B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_logic_cluster/lc_7/in_1 +B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_logic_cluster/lc_7/in_3 +!B0[35],B1[32],B1[33],!B1[34],!B1[35] buffer lc_trk_g2_0 input_2_0 +!B4[35],B5[32],B5[33],!B5[34],!B5[35] buffer lc_trk_g2_0 input_2_2 +!B8[35],B9[32],B9[33],!B9[34],!B9[35] buffer lc_trk_g2_0 input_2_4 +!B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_0 input_2_6 +!B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 wire_logic_cluster/lc_0/in_0 +!B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_logic_cluster/lc_1/in_1 +!B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_logic_cluster/lc_1/in_3 +!B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_0 wire_logic_cluster/lc_2/in_0 +!B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_logic_cluster/lc_3/in_1 +!B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_0 wire_logic_cluster/lc_3/in_3 +!B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_0 wire_logic_cluster/lc_4/in_0 +!B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_logic_cluster/lc_5/in_1 +!B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_0 wire_logic_cluster/lc_5/in_3 +!B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_0 wire_logic_cluster/lc_6/in_0 +B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_logic_cluster/lc_7/clk +!B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_logic_cluster/lc_7/in_1 +!B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_logic_cluster/lc_7/in_3 +!B2[35],B3[32],B3[33],!B3[34],!B3[35] buffer lc_trk_g2_1 input_2_1 +!B6[35],B7[32],B7[33],!B7[34],!B7[35] buffer lc_trk_g2_1 input_2_3 +!B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_1 input_2_5 +!B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_1 input_2_7 +!B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g2_1 wire_logic_cluster/lc_0/in_1 +!B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_logic_cluster/lc_0/in_3 +!B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_1 wire_logic_cluster/lc_1/in_0 +!B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_logic_cluster/lc_2/in_1 +!B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_logic_cluster/lc_2/in_3 +!B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_1 wire_logic_cluster/lc_3/in_0 +!B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_logic_cluster/lc_4/in_1 +!B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_logic_cluster/lc_4/in_3 +!B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_1 wire_logic_cluster/lc_5/in_0 +!B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_logic_cluster/lc_6/in_1 +!B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_logic_cluster/lc_6/in_3 +!B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_1 wire_logic_cluster/lc_7/in_0 +!B0[35],B1[32],B1[33],!B1[34],B1[35] buffer lc_trk_g2_2 input_2_0 +!B4[35],B5[32],B5[33],!B5[34],B5[35] buffer lc_trk_g2_2 input_2_2 +!B8[35],B9[32],B9[33],!B9[34],B9[35] buffer lc_trk_g2_2 input_2_4 +!B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_2 input_2_6 +!B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_2 wire_logic_cluster/lc_0/in_0 +!B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g2_2 wire_logic_cluster/lc_1/in_1 +!B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_2 wire_logic_cluster/lc_1/in_3 +!B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_2 wire_logic_cluster/lc_2/in_0 +!B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_logic_cluster/lc_3/in_1 +!B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_2 wire_logic_cluster/lc_3/in_3 +!B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_2 wire_logic_cluster/lc_4/in_0 +!B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_logic_cluster/lc_5/in_1 +!B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_2 wire_logic_cluster/lc_5/in_3 +!B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_2 wire_logic_cluster/lc_6/in_0 +B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_logic_cluster/lc_7/cen +!B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_logic_cluster/lc_7/in_1 +!B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_2 wire_logic_cluster/lc_7/in_3 +!B2[35],B3[32],B3[33],!B3[34],B3[35] buffer lc_trk_g2_3 input_2_1 +!B6[35],B7[32],B7[33],!B7[34],B7[35] buffer lc_trk_g2_3 input_2_3 +!B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_3 input_2_5 +!B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_3 input_2_7 +!B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_logic_cluster/lc_0/in_1 +!B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_logic_cluster/lc_0/in_3 +!B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_3 wire_logic_cluster/lc_1/in_0 +!B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_logic_cluster/lc_2/in_1 +!B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_logic_cluster/lc_2/in_3 +!B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_3 wire_logic_cluster/lc_3/in_0 +!B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_logic_cluster/lc_4/in_1 +!B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_logic_cluster/lc_4/in_3 +!B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_3 wire_logic_cluster/lc_5/in_0 +!B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_logic_cluster/lc_6/in_1 +!B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_logic_cluster/lc_6/in_3 +!B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_3 wire_logic_cluster/lc_7/in_0 +B0[35],B1[32],B1[33],!B1[34],!B1[35] buffer lc_trk_g2_4 input_2_0 +B4[35],B5[32],B5[33],!B5[34],!B5[35] buffer lc_trk_g2_4 input_2_2 +B8[35],B9[32],B9[33],!B9[34],!B9[35] buffer lc_trk_g2_4 input_2_4 +B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_4 input_2_6 +B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_4 wire_logic_cluster/lc_0/in_0 +!B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_logic_cluster/lc_1/in_1 +B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_logic_cluster/lc_1/in_3 +B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_4 wire_logic_cluster/lc_2/in_0 +!B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_logic_cluster/lc_3/in_1 +B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_logic_cluster/lc_3/in_3 +B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_4 wire_logic_cluster/lc_4/in_0 +!B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_logic_cluster/lc_5/in_1 +B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_4 wire_logic_cluster/lc_5/in_3 +B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_4 wire_logic_cluster/lc_6/in_0 +!B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_logic_cluster/lc_7/in_1 +B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_logic_cluster/lc_7/in_3 +B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_logic_cluster/lc_7/s_r +B2[35],B3[32],B3[33],!B3[34],!B3[35] buffer lc_trk_g2_5 input_2_1 +B6[35],B7[32],B7[33],!B7[34],!B7[35] buffer lc_trk_g2_5 input_2_3 +B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_5 input_2_5 +B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_5 input_2_7 +!B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g2_5 wire_logic_cluster/lc_0/in_1 +B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_logic_cluster/lc_0/in_3 +B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_5 wire_logic_cluster/lc_1/in_0 +!B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_logic_cluster/lc_2/in_1 +B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_5 wire_logic_cluster/lc_2/in_3 +B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_5 wire_logic_cluster/lc_3/in_0 +!B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_logic_cluster/lc_4/in_1 +B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_logic_cluster/lc_4/in_3 +B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_5 wire_logic_cluster/lc_5/in_0 +!B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_logic_cluster/lc_6/in_1 +B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_logic_cluster/lc_6/in_3 +B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_5 wire_logic_cluster/lc_7/in_0 +B0[35],B1[32],B1[33],!B1[34],B1[35] buffer lc_trk_g2_6 input_2_0 +B4[35],B5[32],B5[33],!B5[34],B5[35] buffer lc_trk_g2_6 input_2_2 +B8[35],B9[32],B9[33],!B9[34],B9[35] buffer lc_trk_g2_6 input_2_4 +B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_6 input_2_6 +B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_6 wire_logic_cluster/lc_0/in_0 +!B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_logic_cluster/lc_1/in_1 +B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_logic_cluster/lc_1/in_3 +B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_6 wire_logic_cluster/lc_2/in_0 +!B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g2_6 wire_logic_cluster/lc_3/in_1 +B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_6 wire_logic_cluster/lc_3/in_3 +B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_6 wire_logic_cluster/lc_4/in_0 +!B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g2_6 wire_logic_cluster/lc_5/in_1 +B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_6 wire_logic_cluster/lc_5/in_3 +B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_6 wire_logic_cluster/lc_6/in_0 +!B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g2_6 wire_logic_cluster/lc_7/in_1 +B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_logic_cluster/lc_7/in_3 +B2[35],B3[32],B3[33],!B3[34],B3[35] buffer lc_trk_g2_7 input_2_1 +B6[35],B7[32],B7[33],!B7[34],B7[35] buffer lc_trk_g2_7 input_2_3 +B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_7 input_2_5 +B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_7 input_2_7 +!B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g2_7 wire_logic_cluster/lc_0/in_1 +B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_logic_cluster/lc_0/in_3 +B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_7 wire_logic_cluster/lc_1/in_0 +!B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_logic_cluster/lc_2/in_1 +B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_logic_cluster/lc_2/in_3 +B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_7 wire_logic_cluster/lc_3/in_0 +!B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_logic_cluster/lc_4/in_1 +B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_logic_cluster/lc_4/in_3 +B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_7 wire_logic_cluster/lc_5/in_0 +!B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g2_7 wire_logic_cluster/lc_6/in_1 +B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_logic_cluster/lc_6/in_3 +B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_7 wire_logic_cluster/lc_7/in_0 +!B2[35],B3[32],B3[33],B3[34],!B3[35] buffer lc_trk_g3_0 input_2_1 +!B6[35],B7[32],B7[33],B7[34],!B7[35] buffer lc_trk_g3_0 input_2_3 +!B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_0 input_2_5 +!B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_0 input_2_7 +B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g3_0 wire_logic_cluster/lc_0/in_1 +!B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_0 wire_logic_cluster/lc_0/in_3 +!B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_0 wire_logic_cluster/lc_1/in_0 +B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_logic_cluster/lc_2/in_1 +!B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_logic_cluster/lc_2/in_3 +!B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_0 wire_logic_cluster/lc_3/in_0 +B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g3_0 wire_logic_cluster/lc_4/in_1 +!B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_0 wire_logic_cluster/lc_4/in_3 +!B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_0 wire_logic_cluster/lc_5/in_0 +B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_logic_cluster/lc_6/in_1 +!B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_logic_cluster/lc_6/in_3 +!B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_0 wire_logic_cluster/lc_7/in_0 +!B0[35],B1[32],B1[33],B1[34],!B1[35] buffer lc_trk_g3_1 input_2_0 +!B4[35],B5[32],B5[33],B5[34],!B5[35] buffer lc_trk_g3_1 input_2_2 +!B8[35],B9[32],B9[33],B9[34],!B9[35] buffer lc_trk_g3_1 input_2_4 +!B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_1 input_2_6 +!B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_1 wire_logic_cluster/lc_0/in_0 +B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g3_1 wire_logic_cluster/lc_1/in_1 +!B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_1 wire_logic_cluster/lc_1/in_3 +!B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_1 wire_logic_cluster/lc_2/in_0 +B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g3_1 wire_logic_cluster/lc_3/in_1 +!B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_1 wire_logic_cluster/lc_3/in_3 +!B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_1 wire_logic_cluster/lc_4/in_0 +B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g3_1 wire_logic_cluster/lc_5/in_1 +!B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_1 wire_logic_cluster/lc_5/in_3 +!B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_1 wire_logic_cluster/lc_6/in_0 +B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g3_1 wire_logic_cluster/lc_7/clk +B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g3_1 wire_logic_cluster/lc_7/in_1 +!B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_1 wire_logic_cluster/lc_7/in_3 +!B2[35],B3[32],B3[33],B3[34],B3[35] buffer lc_trk_g3_2 input_2_1 +!B6[35],B7[32],B7[33],B7[34],B7[35] buffer lc_trk_g3_2 input_2_3 +!B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_2 input_2_5 +!B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_2 input_2_7 +B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g3_2 wire_logic_cluster/lc_0/in_1 +!B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_logic_cluster/lc_0/in_3 +!B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_2 wire_logic_cluster/lc_1/in_0 +B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_logic_cluster/lc_2/in_1 +!B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_logic_cluster/lc_2/in_3 +!B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_2 wire_logic_cluster/lc_3/in_0 +B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_logic_cluster/lc_4/in_1 +!B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_logic_cluster/lc_4/in_3 +!B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_2 wire_logic_cluster/lc_5/in_0 +B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_logic_cluster/lc_6/in_1 +!B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_logic_cluster/lc_6/in_3 +!B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_2 wire_logic_cluster/lc_7/in_0 +!B0[35],B1[32],B1[33],B1[34],B1[35] buffer lc_trk_g3_3 input_2_0 +!B4[35],B5[32],B5[33],B5[34],B5[35] buffer lc_trk_g3_3 input_2_2 +!B8[35],B9[32],B9[33],B9[34],B9[35] buffer lc_trk_g3_3 input_2_4 +!B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_3 input_2_6 +!B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_3 wire_logic_cluster/lc_0/in_0 +B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g3_3 wire_logic_cluster/lc_1/in_1 +!B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_logic_cluster/lc_1/in_3 +!B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_3 wire_logic_cluster/lc_2/in_0 +B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_logic_cluster/lc_3/in_1 +!B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_3 wire_logic_cluster/lc_3/in_3 +!B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_3 wire_logic_cluster/lc_4/in_0 +B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_logic_cluster/lc_5/in_1 +!B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_3 wire_logic_cluster/lc_5/in_3 +!B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_3 wire_logic_cluster/lc_6/in_0 +B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g3_3 wire_logic_cluster/lc_7/cen +B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g3_3 wire_logic_cluster/lc_7/in_1 +!B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_logic_cluster/lc_7/in_3 +B2[35],B3[32],B3[33],B3[34],!B3[35] buffer lc_trk_g3_4 input_2_1 +B6[35],B7[32],B7[33],B7[34],!B7[35] buffer lc_trk_g3_4 input_2_3 +B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_4 input_2_5 +B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_4 input_2_7 +B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g3_4 wire_logic_cluster/lc_0/in_1 +B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_logic_cluster/lc_0/in_3 +B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_4 wire_logic_cluster/lc_1/in_0 +B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_logic_cluster/lc_2/in_1 +B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_logic_cluster/lc_2/in_3 +B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_4 wire_logic_cluster/lc_3/in_0 +B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_logic_cluster/lc_4/in_1 +B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_logic_cluster/lc_4/in_3 +B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_4 wire_logic_cluster/lc_5/in_0 +B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_logic_cluster/lc_6/in_1 +B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_logic_cluster/lc_6/in_3 +B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_4 wire_logic_cluster/lc_7/in_0 +B0[35],B1[32],B1[33],B1[34],!B1[35] buffer lc_trk_g3_5 input_2_0 +B4[35],B5[32],B5[33],B5[34],!B5[35] buffer lc_trk_g3_5 input_2_2 +B8[35],B9[32],B9[33],B9[34],!B9[35] buffer lc_trk_g3_5 input_2_4 +B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_5 input_2_6 +B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_5 wire_logic_cluster/lc_0/in_0 +B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g3_5 wire_logic_cluster/lc_1/in_1 +B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_logic_cluster/lc_1/in_3 +B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_5 wire_logic_cluster/lc_2/in_0 +B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g3_5 wire_logic_cluster/lc_3/in_1 +B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_5 wire_logic_cluster/lc_3/in_3 +B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_5 wire_logic_cluster/lc_4/in_0 +B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_logic_cluster/lc_5/in_1 +B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_logic_cluster/lc_5/in_3 +B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_5 wire_logic_cluster/lc_6/in_0 +B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_logic_cluster/lc_7/in_1 +B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_logic_cluster/lc_7/in_3 +B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g3_5 wire_logic_cluster/lc_7/s_r +B2[35],B3[32],B3[33],B3[34],B3[35] buffer lc_trk_g3_6 input_2_1 +B6[35],B7[32],B7[33],B7[34],B7[35] buffer lc_trk_g3_6 input_2_3 +B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_6 input_2_5 +B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_6 input_2_7 +B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g3_6 wire_logic_cluster/lc_0/in_1 +B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_logic_cluster/lc_0/in_3 +B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_6 wire_logic_cluster/lc_1/in_0 +B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_logic_cluster/lc_2/in_1 +B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_logic_cluster/lc_2/in_3 +B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_6 wire_logic_cluster/lc_3/in_0 +B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_logic_cluster/lc_4/in_1 +B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_logic_cluster/lc_4/in_3 +B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_6 wire_logic_cluster/lc_5/in_0 +B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_logic_cluster/lc_6/in_1 +B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_logic_cluster/lc_6/in_3 +B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_6 wire_logic_cluster/lc_7/in_0 +B0[35],B1[32],B1[33],B1[34],B1[35] buffer lc_trk_g3_7 input_2_0 +B4[35],B5[32],B5[33],B5[34],B5[35] buffer lc_trk_g3_7 input_2_2 +B8[35],B9[32],B9[33],B9[34],B9[35] buffer lc_trk_g3_7 input_2_4 +B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_7 input_2_6 +B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_7 wire_logic_cluster/lc_0/in_0 +B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_logic_cluster/lc_1/in_1 +B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_logic_cluster/lc_1/in_3 +B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_7 wire_logic_cluster/lc_2/in_0 +B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_logic_cluster/lc_3/in_1 +B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_logic_cluster/lc_3/in_3 +B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_7 wire_logic_cluster/lc_4/in_0 +B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_logic_cluster/lc_5/in_1 +B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_7 wire_logic_cluster/lc_5/in_3 +B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_7 wire_logic_cluster/lc_6/in_0 +B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g3_7 wire_logic_cluster/lc_7/in_1 +B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_logic_cluster/lc_7/in_3 +B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer lft_op_0 lc_trk_g0_0 +B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer lft_op_0 lc_trk_g1_0 +B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer lft_op_1 lc_trk_g0_1 +B4[15],!B4[16],B4[17],B4[18],!B5[18] buffer lft_op_1 lc_trk_g1_1 +B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer lft_op_2 lc_trk_g0_2 +B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer lft_op_2 lc_trk_g1_2 +B0[21],B0[22],!B0[23],B0[24],!B1[21] buffer lft_op_3 lc_trk_g0_3 +B4[21],B4[22],!B4[23],B4[24],!B5[21] buffer lft_op_3 lc_trk_g1_3 +B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer lft_op_4 lc_trk_g0_4 +B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer lft_op_4 lc_trk_g1_4 +B2[15],!B2[16],B2[17],B2[18],!B3[18] buffer lft_op_5 lc_trk_g0_5 +B6[15],!B6[16],B6[17],B6[18],!B7[18] buffer lft_op_5 lc_trk_g1_5 +B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer lft_op_6 lc_trk_g0_6 +B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer lft_op_6 lc_trk_g1_6 +B2[21],B2[22],!B2[23],B2[24],!B3[21] buffer lft_op_7 lc_trk_g0_7 +B6[21],B6[22],!B6[23],B6[24],!B7[21] buffer lft_op_7 lc_trk_g1_7 +B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer rgt_op_0 lc_trk_g2_0 +B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer rgt_op_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],B8[18],!B9[18] buffer rgt_op_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],B12[18],!B13[18] buffer rgt_op_1 lc_trk_g3_1 +B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer rgt_op_2 lc_trk_g2_2 +B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer rgt_op_2 lc_trk_g3_2 +B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer rgt_op_3 lc_trk_g2_3 +B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer rgt_op_3 lc_trk_g3_3 +B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer rgt_op_4 lc_trk_g2_4 +B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer rgt_op_4 lc_trk_g3_4 +B10[15],!B10[16],B10[17],B10[18],!B11[18] buffer rgt_op_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],B14[18],!B15[18] buffer rgt_op_5 lc_trk_g3_5 +B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer rgt_op_6 lc_trk_g2_6 +B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer rgt_op_6 lc_trk_g3_6 +B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer rgt_op_7 lc_trk_g2_7 +B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer rgt_op_7 lc_trk_g3_7 +!B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp12_h_l_12 lc_trk_g0_7 +!B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp12_h_l_12 lc_trk_g1_7 +!B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp12_h_l_14 lc_trk_g0_1 +!B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_l_14 lc_trk_g1_1 +!B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp12_h_l_16 lc_trk_g0_3 +!B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp12_h_l_16 lc_trk_g1_3 +!B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_l_17 lc_trk_g0_2 +!B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp12_h_l_17 lc_trk_g1_2 +B10[2] buffer sp12_h_l_17 sp4_h_r_21 +!B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp12_h_l_18 lc_trk_g0_5 +!B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp12_h_l_18 lc_trk_g1_5 +!B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_l_21 lc_trk_g0_6 +!B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_l_21 lc_trk_g1_6 +B14[2] buffer sp12_h_l_21 sp4_h_l_10 +B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_l_3 lc_trk_g0_4 +B6[14],B7[14],B7[15],!B7[16],B7[17] buffer sp12_h_l_3 lc_trk_g1_4 +B15[19] buffer sp12_h_l_3 sp4_h_r_14 +B2[21],B2[22],!B2[23],B2[24],B3[21] buffer sp12_h_l_4 lc_trk_g0_7 +B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_l_4 lc_trk_g1_7 +B2[25],B3[22],!B3[23],B3[24],B3[25] buffer sp12_h_l_5 lc_trk_g0_6 +B6[25],B7[22],!B7[23],B7[24],B7[25] buffer sp12_h_l_5 lc_trk_g1_6 +B14[19] buffer sp12_h_l_5 sp4_h_l_2 +B0[14],B1[14],B1[15],!B1[16],B1[17] buffer sp12_h_r_0 lc_trk_g0_0 +B4[14],B5[14],B5[15],!B5[16],B5[17] buffer sp12_h_r_0 lc_trk_g1_0 +B13[19] buffer sp12_h_r_0 sp4_h_l_1 +B0[15],!B0[16],B0[17],B0[18],B1[18] buffer sp12_h_r_1 lc_trk_g0_1 +B4[15],!B4[16],B4[17],B4[18],B5[18] buffer sp12_h_r_1 lc_trk_g1_1 +!B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_r_10 lc_trk_g0_2 +!B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_r_10 lc_trk_g1_2 +B3[1] buffer sp12_h_r_10 sp4_h_l_4 +!B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp12_h_r_11 lc_trk_g0_3 +!B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp12_h_r_11 lc_trk_g1_3 +!B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_12 lc_trk_g0_4 +!B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_12 lc_trk_g1_4 +B4[2] buffer sp12_h_r_12 sp4_h_l_7 +!B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_r_13 lc_trk_g0_5 +!B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_r_13 lc_trk_g1_5 +!B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_r_14 lc_trk_g0_6 +!B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_r_14 lc_trk_g1_6 +B6[2] buffer sp12_h_r_14 sp4_h_r_19 +!B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_16 lc_trk_g0_0 +!B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_16 lc_trk_g1_0 +B8[2] buffer sp12_h_r_16 sp4_h_l_9 +B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_r_2 lc_trk_g0_2 +B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_r_2 lc_trk_g1_2 +B12[19] buffer sp12_h_r_2 sp4_h_r_13 +!B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_20 lc_trk_g0_4 +!B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_20 lc_trk_g1_4 +B12[2] buffer sp12_h_r_20 sp4_h_l_11 +!B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_r_23 lc_trk_g0_7 +!B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_r_23 lc_trk_g1_7 +B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_r_3 lc_trk_g0_3 +B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_r_3 lc_trk_g1_3 +B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_r_5 lc_trk_g0_5 +B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_r_5 lc_trk_g1_5 +!B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_8 lc_trk_g0_0 +!B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_8 lc_trk_g1_0 +B0[2] buffer sp12_h_r_8 sp4_h_l_5 +!B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp12_h_r_9 lc_trk_g0_1 +!B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_r_9 lc_trk_g1_1 +B8[14],B9[14],B9[15],!B9[16],B9[17] buffer sp12_v_b_0 lc_trk_g2_0 +B12[14],B13[14],B13[15],!B13[16],B13[17] buffer sp12_v_b_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],B8[18],B9[18] buffer sp12_v_b_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],B12[18],B13[18] buffer sp12_v_b_1 lc_trk_g3_1 +B1[19] buffer sp12_v_b_1 sp4_v_t_1 +!B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp12_v_b_11 lc_trk_g2_3 +!B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_b_11 lc_trk_g3_3 +B4[19] buffer sp12_v_b_11 sp4_v_b_17 +!B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_12 lc_trk_g2_4 +!B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_12 lc_trk_g3_4 +!B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp12_v_b_14 lc_trk_g2_6 +!B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp12_v_b_14 lc_trk_g3_6 +!B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_16 lc_trk_g2_0 +!B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_b_16 lc_trk_g3_0 +!B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp12_v_b_18 lc_trk_g2_2 +!B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp12_v_b_18 lc_trk_g3_2 +!B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp12_v_b_19 lc_trk_g2_3 +!B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp12_v_b_19 lc_trk_g3_3 +B8[19] buffer sp12_v_b_19 sp4_v_b_21 +!B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_20 lc_trk_g2_4 +!B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_20 lc_trk_g3_4 +!B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp12_v_b_21 lc_trk_g2_5 +!B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp12_v_b_21 lc_trk_g3_5 +B11[19] buffer sp12_v_b_21 sp4_v_b_22 +!B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp12_v_b_23 lc_trk_g2_7 +!B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp12_v_b_23 lc_trk_g3_7 +B10[19] buffer sp12_v_b_23 sp4_v_b_23 +B10[25],B11[22],!B11[23],B11[24],B11[25] buffer sp12_v_b_6 lc_trk_g2_6 +B14[25],B15[22],!B15[23],B15[24],B15[25] buffer sp12_v_b_6 lc_trk_g3_6 +B10[21],B10[22],!B10[23],B10[24],B11[21] buffer sp12_v_b_7 lc_trk_g2_7 +B14[21],B14[22],!B14[23],B14[24],B15[21] buffer sp12_v_b_7 lc_trk_g3_7 +B2[19] buffer sp12_v_b_7 sp4_v_b_15 +!B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_8 lc_trk_g2_0 +!B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_b_8 lc_trk_g3_0 +B8[21],B8[22],!B8[23],B8[24],B9[21] buffer sp12_v_t_0 lc_trk_g2_3 +B12[21],B12[22],!B12[23],B12[24],B13[21] buffer sp12_v_t_0 lc_trk_g3_3 +B0[19] buffer sp12_v_t_0 sp4_v_b_13 +B8[25],B9[22],!B9[23],B9[24],B9[25] buffer sp12_v_t_1 lc_trk_g2_2 +B12[25],B13[22],!B13[23],B13[24],B13[25] buffer sp12_v_t_1 lc_trk_g3_2 +!B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp12_v_t_10 lc_trk_g2_5 +!B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp12_v_t_10 lc_trk_g3_5 +B7[19] buffer sp12_v_t_10 sp4_v_b_18 +!B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp12_v_t_12 lc_trk_g2_7 +!B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp12_v_t_12 lc_trk_g3_7 +B6[19] buffer sp12_v_t_12 sp4_v_b_19 +!B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp12_v_t_14 lc_trk_g2_1 +!B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp12_v_t_14 lc_trk_g3_1 +B9[19] buffer sp12_v_t_14 sp4_v_t_9 +B10[15],!B10[16],B10[17],B10[18],B11[18] buffer sp12_v_t_2 lc_trk_g2_5 +B14[15],!B14[16],B14[17],B14[18],B15[18] buffer sp12_v_t_2 lc_trk_g3_5 +B3[19] buffer sp12_v_t_2 sp4_v_t_3 +!B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_t_21 lc_trk_g2_6 +!B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_t_21 lc_trk_g3_6 +B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_t_3 lc_trk_g2_4 +B14[14],B15[14],B15[15],!B15[16],B15[17] buffer sp12_v_t_3 lc_trk_g3_4 +!B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp12_v_t_6 lc_trk_g2_1 +!B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp12_v_t_6 lc_trk_g3_1 +B5[19] buffer sp12_v_t_6 sp4_v_t_5 +!B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_t_9 lc_trk_g2_2 +!B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp12_v_t_9 lc_trk_g3_2 +B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_1 lc_trk_g0_4 +B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_1 lc_trk_g1_4 +B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_l_10 lc_trk_g0_7 +B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_l_10 lc_trk_g1_7 +B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_l_11 lc_trk_g0_6 +B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_l_11 lc_trk_g1_6 +!B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_l_15 lc_trk_g2_2 +!B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_l_15 lc_trk_g3_2 +B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_l_16 lc_trk_g2_5 +B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_l_16 lc_trk_g3_5 +!B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_l_17 lc_trk_g2_4 +!B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_l_17 lc_trk_g3_4 +B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_h_l_2 lc_trk_g0_7 +B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_l_2 lc_trk_g1_7 +B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_21 lc_trk_g2_0 +B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_21 lc_trk_g3_0 +B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_h_l_24 lc_trk_g2_5 +B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_h_l_24 lc_trk_g3_5 +B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_l_34 lc_trk_g2_7 +B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_l_34 lc_trk_g3_7 +B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_h_l_4 lc_trk_g0_1 +B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_h_l_4 lc_trk_g1_1 +B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_l_5 lc_trk_g0_0 +B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_l_5 lc_trk_g1_0 +B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_l_7 lc_trk_g0_2 +B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_l_7 lc_trk_g1_2 +B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_9 lc_trk_g0_4 +B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_9 lc_trk_g1_4 +!B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_0 lc_trk_g0_0 +!B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_0 lc_trk_g1_0 +B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp4_h_r_1 lc_trk_g0_1 +B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp4_h_r_1 lc_trk_g1_1 +B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_h_r_10 lc_trk_g0_2 +B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_h_r_10 lc_trk_g1_2 +B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_h_r_11 lc_trk_g0_3 +B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_h_r_11 lc_trk_g1_3 +B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_h_r_13 lc_trk_g0_5 +B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_h_r_13 lc_trk_g1_5 +B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_h_r_14 lc_trk_g0_6 +B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_h_r_14 lc_trk_g1_6 +B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_19 lc_trk_g0_3 +B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_19 lc_trk_g1_3 +!B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_2 lc_trk_g0_2 +!B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_2 lc_trk_g1_2 +B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_r_21 lc_trk_g0_5 +B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_r_21 lc_trk_g1_5 +!B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_24 lc_trk_g2_0 +!B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_24 lc_trk_g3_0 +B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp4_h_r_25 lc_trk_g2_1 +B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp4_h_r_25 lc_trk_g3_1 +!B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_27 lc_trk_g2_3 +!B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_27 lc_trk_g3_3 +!B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_3 lc_trk_g0_3 +!B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_3 lc_trk_g1_3 +!B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_30 lc_trk_g2_6 +!B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_30 lc_trk_g3_6 +!B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_31 lc_trk_g2_7 +!B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_31 lc_trk_g3_7 +B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_h_r_33 lc_trk_g2_1 +B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_h_r_33 lc_trk_g3_1 +B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_h_r_34 lc_trk_g2_2 +B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_h_r_34 lc_trk_g3_2 +B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_r_35 lc_trk_g2_3 +B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_r_35 lc_trk_g3_3 +B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_36 lc_trk_g2_4 +B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_36 lc_trk_g3_4 +B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_r_38 lc_trk_g2_6 +B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_r_38 lc_trk_g3_6 +B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_r_39 lc_trk_g2_7 +B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_r_39 lc_trk_g3_7 +!B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_4 lc_trk_g0_4 +!B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_4 lc_trk_g1_4 +B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_40 lc_trk_g2_0 +B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_40 lc_trk_g3_0 +B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_h_r_41 lc_trk_g2_1 +B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_h_r_41 lc_trk_g3_1 +B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_r_42 lc_trk_g2_2 +B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_r_42 lc_trk_g3_2 +B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_43 lc_trk_g2_3 +B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_43 lc_trk_g3_3 +B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_44 lc_trk_g2_4 +B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_44 lc_trk_g3_4 +B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_h_r_45 lc_trk_g2_5 +B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_h_r_45 lc_trk_g3_5 +B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_46 lc_trk_g2_6 +B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_46 lc_trk_g3_6 +B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp4_h_r_5 lc_trk_g0_5 +B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5 +!B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_6 lc_trk_g0_6 +!B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_6 lc_trk_g1_6 +!B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_7 lc_trk_g0_7 +!B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_7 lc_trk_g1_7 +B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_8 lc_trk_g0_0 +B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_8 lc_trk_g1_0 +B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_h_r_9 lc_trk_g0_1 +B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_h_r_9 lc_trk_g1_1 +!B4[14],!B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_0 lc_trk_g1_0 +!B4[15],!B4[16],B4[17],!B4[18],!B5[18] buffer sp4_r_v_b_1 lc_trk_g1_1 +!B8[25],B9[22],!B9[23],!B9[24],!B9[25] buffer sp4_r_v_b_10 lc_trk_g2_2 +!B8[21],B8[22],!B8[23],!B8[24],!B9[21] buffer sp4_r_v_b_11 lc_trk_g2_3 +!B10[14],!B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_12 lc_trk_g2_4 +!B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer sp4_r_v_b_13 lc_trk_g2_5 +!B10[25],B11[22],!B11[23],!B11[24],!B11[25] buffer sp4_r_v_b_14 lc_trk_g2_6 +!B10[21],B10[22],!B10[23],!B10[24],!B11[21] buffer sp4_r_v_b_15 lc_trk_g2_7 +!B12[14],!B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_16 lc_trk_g3_0 +!B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer sp4_r_v_b_17 lc_trk_g3_1 +!B12[25],B13[22],!B13[23],!B13[24],!B13[25] buffer sp4_r_v_b_18 lc_trk_g3_2 +!B12[21],B12[22],!B12[23],!B12[24],!B13[21] buffer sp4_r_v_b_19 lc_trk_g3_3 +!B4[25],B5[22],!B5[23],!B5[24],!B5[25] buffer sp4_r_v_b_2 lc_trk_g1_2 +!B14[14],!B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_20 lc_trk_g3_4 +!B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer sp4_r_v_b_21 lc_trk_g3_5 +!B14[25],B15[22],!B15[23],!B15[24],!B15[25] buffer sp4_r_v_b_22 lc_trk_g3_6 +!B14[21],B14[22],!B14[23],!B14[24],!B15[21] buffer sp4_r_v_b_23 lc_trk_g3_7 +!B0[14],!B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_24 lc_trk_g0_0 +!B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_24 lc_trk_g1_0 +!B0[15],!B0[16],B0[17],!B0[18],!B1[18] buffer sp4_r_v_b_25 lc_trk_g0_1 +!B4[15],!B4[16],B4[17],!B4[18],B5[18] buffer sp4_r_v_b_25 lc_trk_g1_1 +!B0[25],B1[22],!B1[23],!B1[24],!B1[25] buffer sp4_r_v_b_26 lc_trk_g0_2 +!B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer sp4_r_v_b_26 lc_trk_g1_2 +!B0[21],B0[22],!B0[23],!B0[24],!B1[21] buffer sp4_r_v_b_27 lc_trk_g0_3 +!B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer sp4_r_v_b_27 lc_trk_g1_3 +!B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer sp4_r_v_b_28 lc_trk_g0_4 +!B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_28 lc_trk_g1_4 +!B2[15],!B2[16],B2[17],!B2[18],B3[18] buffer sp4_r_v_b_29 lc_trk_g0_5 +!B6[15],!B6[16],B6[17],!B6[18],B7[18] buffer sp4_r_v_b_29 lc_trk_g1_5 +!B4[21],B4[22],!B4[23],!B4[24],!B5[21] buffer sp4_r_v_b_3 lc_trk_g1_3 +!B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer sp4_r_v_b_30 lc_trk_g0_6 +!B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer sp4_r_v_b_30 lc_trk_g1_6 +!B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer sp4_r_v_b_31 lc_trk_g0_7 +!B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer sp4_r_v_b_31 lc_trk_g1_7 +!B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer sp4_r_v_b_32 lc_trk_g0_3 +!B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_32 lc_trk_g2_0 +!B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer sp4_r_v_b_33 lc_trk_g0_2 +!B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer sp4_r_v_b_33 lc_trk_g2_1 +!B0[15],!B0[16],B0[17],!B0[18],B1[18] buffer sp4_r_v_b_34 lc_trk_g0_1 +!B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer sp4_r_v_b_34 lc_trk_g2_2 +!B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_35 lc_trk_g0_0 +!B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer sp4_r_v_b_35 lc_trk_g2_3 +!B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_36 lc_trk_g2_4 +!B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer sp4_r_v_b_37 lc_trk_g2_5 +!B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer sp4_r_v_b_38 lc_trk_g2_6 +!B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer sp4_r_v_b_39 lc_trk_g2_7 +!B6[14],!B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_4 lc_trk_g1_4 +!B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_40 lc_trk_g3_0 +!B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer sp4_r_v_b_41 lc_trk_g3_1 +!B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer sp4_r_v_b_42 lc_trk_g3_2 +!B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer sp4_r_v_b_43 lc_trk_g3_3 +!B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_44 lc_trk_g3_4 +!B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer sp4_r_v_b_45 lc_trk_g3_5 +!B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer sp4_r_v_b_46 lc_trk_g3_6 +!B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer sp4_r_v_b_47 lc_trk_g3_7 +!B6[15],!B6[16],B6[17],!B6[18],!B7[18] buffer sp4_r_v_b_5 lc_trk_g1_5 +!B6[25],B7[22],!B7[23],!B7[24],!B7[25] buffer sp4_r_v_b_6 lc_trk_g1_6 +!B6[21],B6[22],!B6[23],!B6[24],!B7[21] buffer sp4_r_v_b_7 lc_trk_g1_7 +!B8[14],!B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_8 lc_trk_g2_0 +!B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer sp4_r_v_b_9 lc_trk_g2_1 +B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_0 lc_trk_g0_0 +B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_0 lc_trk_g1_0 +!B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_v_b_1 lc_trk_g0_1 +!B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_v_b_1 lc_trk_g1_1 +B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp4_v_b_10 lc_trk_g0_2 +B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp4_v_b_10 lc_trk_g1_2 +B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp4_v_b_11 lc_trk_g0_3 +B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp4_v_b_11 lc_trk_g1_3 +!B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_v_b_13 lc_trk_g0_5 +!B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_v_b_13 lc_trk_g1_5 +B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp4_v_b_15 lc_trk_g0_7 +B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp4_v_b_15 lc_trk_g1_7 +B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp4_v_b_17 lc_trk_g0_1 +B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp4_v_b_17 lc_trk_g1_1 +!B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_v_b_18 lc_trk_g0_2 +!B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_v_b_18 lc_trk_g1_2 +!B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_v_b_19 lc_trk_g0_3 +!B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_v_b_19 lc_trk_g1_3 +B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp4_v_b_2 lc_trk_g0_2 +B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp4_v_b_2 lc_trk_g1_2 +B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp4_v_b_21 lc_trk_g0_5 +B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp4_v_b_21 lc_trk_g1_5 +!B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_v_b_22 lc_trk_g0_6 +!B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_v_b_22 lc_trk_g1_6 +!B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_v_b_23 lc_trk_g0_7 +!B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_v_b_23 lc_trk_g1_7 +B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_b_24 lc_trk_g2_0 +B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_b_24 lc_trk_g3_0 +B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp4_v_b_26 lc_trk_g2_2 +B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp4_v_b_26 lc_trk_g3_2 +B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp4_v_b_3 lc_trk_g0_3 +B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp4_v_b_3 lc_trk_g1_3 +B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp4_v_b_30 lc_trk_g2_6 +B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp4_v_b_30 lc_trk_g3_6 +!B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_v_b_33 lc_trk_g2_1 +!B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_v_b_33 lc_trk_g3_1 +B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_b_36 lc_trk_g2_4 +B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_b_36 lc_trk_g3_4 +!B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_v_b_37 lc_trk_g2_5 +!B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_v_b_37 lc_trk_g3_5 +B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp4_v_b_38 lc_trk_g2_6 +B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp4_v_b_38 lc_trk_g3_6 +B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_4 lc_trk_g0_4 +B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_4 lc_trk_g1_4 +!B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_v_b_42 lc_trk_g2_2 +!B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_v_b_42 lc_trk_g3_2 +!B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_v_b_46 lc_trk_g2_6 +!B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_v_b_46 lc_trk_g3_6 +!B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_v_b_47 lc_trk_g2_7 +!B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_v_b_47 lc_trk_g3_7 +!B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_v_b_5 lc_trk_g0_5 +!B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_v_b_5 lc_trk_g1_5 +B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp4_v_b_6 lc_trk_g0_6 +B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp4_v_b_6 lc_trk_g1_6 +B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp4_v_b_7 lc_trk_g0_7 +B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp4_v_b_7 lc_trk_g1_7 +B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_8 lc_trk_g0_0 +B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_8 lc_trk_g1_0 +!B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_v_b_9 lc_trk_g0_1 +!B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_v_b_9 lc_trk_g1_1 +B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_t_1 lc_trk_g0_4 +B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_t_1 lc_trk_g1_4 +!B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_v_t_12 lc_trk_g2_1 +!B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_v_t_12 lc_trk_g3_1 +B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp4_v_t_14 lc_trk_g2_3 +B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp4_v_t_14 lc_trk_g3_3 +!B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_v_t_16 lc_trk_g2_5 +!B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_v_t_16 lc_trk_g3_5 +B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_t_17 lc_trk_g2_4 +B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_t_17 lc_trk_g3_4 +B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp4_v_t_18 lc_trk_g2_7 +B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp4_v_t_18 lc_trk_g3_7 +B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_21 lc_trk_g2_0 +B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_21 lc_trk_g3_0 +B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp4_v_t_22 lc_trk_g2_3 +B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp4_v_t_22 lc_trk_g3_3 +B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp4_v_t_23 lc_trk_g2_2 +B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp4_v_t_23 lc_trk_g3_2 +B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp4_v_t_26 lc_trk_g2_7 +B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp4_v_t_26 lc_trk_g3_7 +B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp4_v_t_28 lc_trk_g2_1 +B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp4_v_t_28 lc_trk_g3_1 +!B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_v_t_29 lc_trk_g2_0 +!B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_v_t_29 lc_trk_g3_0 +B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp4_v_t_3 lc_trk_g0_6 +B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp4_v_t_3 lc_trk_g1_6 +!B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_v_t_30 lc_trk_g2_3 +!B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_t_30 lc_trk_g3_3 +B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp4_v_t_32 lc_trk_g2_5 +B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp4_v_t_32 lc_trk_g3_5 +!B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_t_33 lc_trk_g2_4 +!B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_t_33 lc_trk_g3_4 +!B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_v_t_5 lc_trk_g0_0 +!B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_v_t_5 lc_trk_g1_0 +!B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_v_t_9 lc_trk_g0_4 +!B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_v_t_9 lc_trk_g1_4 +!B8[14],B9[14],B9[15],!B9[16],B9[17] buffer tnl_op_0 lc_trk_g2_0 +!B12[14],B13[14],B13[15],!B13[16],B13[17] buffer tnl_op_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer tnl_op_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer tnl_op_1 lc_trk_g3_1 +!B8[25],B9[22],!B9[23],B9[24],B9[25] buffer tnl_op_2 lc_trk_g2_2 +!B12[25],B13[22],!B13[23],B13[24],B13[25] buffer tnl_op_2 lc_trk_g3_2 +!B8[21],B8[22],!B8[23],B8[24],B9[21] buffer tnl_op_3 lc_trk_g2_3 +!B12[21],B12[22],!B12[23],B12[24],B13[21] buffer tnl_op_3 lc_trk_g3_3 +!B10[14],B11[14],B11[15],!B11[16],B11[17] buffer tnl_op_4 lc_trk_g2_4 +!B14[14],B15[14],B15[15],!B15[16],B15[17] buffer tnl_op_4 lc_trk_g3_4 +B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer tnl_op_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer tnl_op_5 lc_trk_g3_5 +!B10[25],B11[22],!B11[23],B11[24],B11[25] buffer tnl_op_6 lc_trk_g2_6 +!B14[25],B15[22],!B15[23],B15[24],B15[25] buffer tnl_op_6 lc_trk_g3_6 +!B10[21],B10[22],!B10[23],B10[24],B11[21] buffer tnl_op_7 lc_trk_g2_7 +!B14[21],B14[22],!B14[23],B14[24],B15[21] buffer tnl_op_7 lc_trk_g3_7 +!B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer tnr_op_0 lc_trk_g2_0 +!B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer tnr_op_0 lc_trk_g3_0 +B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer tnr_op_1 lc_trk_g2_1 +B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer tnr_op_1 lc_trk_g3_1 +!B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer tnr_op_2 lc_trk_g2_2 +!B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer tnr_op_2 lc_trk_g3_2 +!B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer tnr_op_3 lc_trk_g2_3 +!B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer tnr_op_3 lc_trk_g3_3 +!B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer tnr_op_4 lc_trk_g2_4 +!B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer tnr_op_4 lc_trk_g3_4 +B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer tnr_op_5 lc_trk_g2_5 +B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer tnr_op_5 lc_trk_g3_5 +!B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer tnr_op_6 lc_trk_g2_6 +!B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer tnr_op_6 lc_trk_g3_6 +!B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer tnr_op_7 lc_trk_g2_7 +!B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer tnr_op_7 lc_trk_g3_7 +!B0[14],B1[14],B1[15],!B1[16],B1[17] buffer top_op_0 lc_trk_g0_0 +!B4[14],B5[14],B5[15],!B5[16],B5[17] buffer top_op_0 lc_trk_g1_0 +B0[15],!B0[16],B0[17],!B0[18],B1[18] buffer top_op_1 lc_trk_g0_1 +B4[15],!B4[16],B4[17],!B4[18],B5[18] buffer top_op_1 lc_trk_g1_1 +!B0[25],B1[22],!B1[23],B1[24],B1[25] buffer top_op_2 lc_trk_g0_2 +!B4[25],B5[22],!B5[23],B5[24],B5[25] buffer top_op_2 lc_trk_g1_2 +!B0[21],B0[22],!B0[23],B0[24],B1[21] buffer top_op_3 lc_trk_g0_3 +!B4[21],B4[22],!B4[23],B4[24],B5[21] buffer top_op_3 lc_trk_g1_3 +!B2[14],B3[14],B3[15],!B3[16],B3[17] buffer top_op_4 lc_trk_g0_4 +!B6[14],B7[14],B7[15],!B7[16],B7[17] buffer top_op_4 lc_trk_g1_4 +B2[15],!B2[16],B2[17],!B2[18],B3[18] buffer top_op_5 lc_trk_g0_5 +B6[15],!B6[16],B6[17],!B6[18],B7[18] buffer top_op_5 lc_trk_g1_5 +!B2[25],B3[22],!B3[23],B3[24],B3[25] buffer top_op_6 lc_trk_g0_6 +!B6[25],B7[22],!B7[23],B7[24],B7[25] buffer top_op_6 lc_trk_g1_6 +!B2[21],B2[22],!B2[23],B2[24],B3[21] buffer top_op_7 lc_trk_g0_7 +!B6[21],B6[22],!B6[23],B6[24],B7[21] buffer top_op_7 lc_trk_g1_7 +!B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer wire_logic_cluster/carry_in_mux/cout wire_logic_cluster/lc_0/in_3 +!B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer wire_logic_cluster/lc_0/cout wire_logic_cluster/lc_1/in_3 +B2[50] buffer wire_logic_cluster/lc_0/out input_2_1 +B0[14],!B1[14],!B1[15],!B1[16],B1[17] buffer wire_logic_cluster/lc_0/out lc_trk_g0_0 +B4[14],!B5[14],!B5[15],!B5[16],B5[17] buffer wire_logic_cluster/lc_0/out lc_trk_g1_0 +B8[14],!B9[14],!B9[15],!B9[16],B9[17] buffer wire_logic_cluster/lc_0/out lc_trk_g2_0 +B12[14],!B13[14],!B13[15],!B13[16],B13[17] buffer wire_logic_cluster/lc_0/out lc_trk_g3_0 +B0[47] buffer wire_logic_cluster/lc_0/out sp12_h_r_8 +B0[51] buffer wire_logic_cluster/lc_0/out sp12_v_b_0 +B0[52] buffer wire_logic_cluster/lc_0/out sp12_v_b_16 +B1[47] buffer wire_logic_cluster/lc_0/out sp4_h_l_21 +B0[46] buffer wire_logic_cluster/lc_0/out sp4_h_l_5 +B1[46] buffer wire_logic_cluster/lc_0/out sp4_h_r_0 +B1[52] buffer wire_logic_cluster/lc_0/out sp4_r_v_b_1 +B0[53] buffer wire_logic_cluster/lc_0/out sp4_r_v_b_17 +B1[53] buffer wire_logic_cluster/lc_0/out sp4_r_v_b_33 +B0[48] buffer wire_logic_cluster/lc_0/out sp4_v_b_0 +B1[51] buffer wire_logic_cluster/lc_0/out sp4_v_t_21 +B1[48] buffer wire_logic_cluster/lc_0/out sp4_v_t_5 +!B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer wire_logic_cluster/lc_1/cout wire_logic_cluster/lc_2/in_3 +B4[50] buffer wire_logic_cluster/lc_1/out input_2_2 +!B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer wire_logic_cluster/lc_1/out lc_trk_g0_1 +!B4[15],!B4[16],B4[17],B4[18],!B5[18] buffer wire_logic_cluster/lc_1/out lc_trk_g1_1 +!B8[15],!B8[16],B8[17],B8[18],!B9[18] buffer wire_logic_cluster/lc_1/out lc_trk_g2_1 +!B12[15],!B12[16],B12[17],B12[18],!B13[18] buffer wire_logic_cluster/lc_1/out lc_trk_g3_1 +B2[47] buffer wire_logic_cluster/lc_1/out sp12_h_r_10 +B2[52] buffer wire_logic_cluster/lc_1/out sp12_v_b_18 +B2[51] buffer wire_logic_cluster/lc_1/out sp12_v_t_1 +B2[46] buffer wire_logic_cluster/lc_1/out sp4_h_l_7 +B3[46] buffer wire_logic_cluster/lc_1/out sp4_h_r_2 +B3[47] buffer wire_logic_cluster/lc_1/out sp4_h_r_34 +B2[53] buffer wire_logic_cluster/lc_1/out sp4_r_v_b_19 +B3[52] buffer wire_logic_cluster/lc_1/out sp4_r_v_b_3 +B3[53] buffer wire_logic_cluster/lc_1/out sp4_r_v_b_35 +B3[48] buffer wire_logic_cluster/lc_1/out sp4_v_b_18 +B2[48] buffer wire_logic_cluster/lc_1/out sp4_v_b_2 +B3[51] buffer wire_logic_cluster/lc_1/out sp4_v_t_23 +!B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer wire_logic_cluster/lc_2/cout wire_logic_cluster/lc_3/in_3 +B6[50] buffer wire_logic_cluster/lc_2/out input_2_3 +B0[25],B1[22],!B1[23],!B1[24],!B1[25] buffer wire_logic_cluster/lc_2/out lc_trk_g0_2 +B4[25],B5[22],!B5[23],!B5[24],!B5[25] buffer wire_logic_cluster/lc_2/out lc_trk_g1_2 +B8[25],B9[22],!B9[23],!B9[24],!B9[25] buffer wire_logic_cluster/lc_2/out lc_trk_g2_2 +B12[25],B13[22],!B13[23],!B13[24],!B13[25] buffer wire_logic_cluster/lc_2/out lc_trk_g3_2 +B4[47] buffer wire_logic_cluster/lc_2/out sp12_h_r_12 +B4[52] buffer wire_logic_cluster/lc_2/out sp12_v_b_20 +B4[51] buffer wire_logic_cluster/lc_2/out sp12_v_t_3 +B4[46] buffer wire_logic_cluster/lc_2/out sp4_h_l_9 +B5[47] buffer wire_logic_cluster/lc_2/out sp4_h_r_36 +B5[46] buffer wire_logic_cluster/lc_2/out sp4_h_r_4 +B4[53] buffer wire_logic_cluster/lc_2/out sp4_r_v_b_21 +B5[53] buffer wire_logic_cluster/lc_2/out sp4_r_v_b_37 +B5[52] buffer wire_logic_cluster/lc_2/out sp4_r_v_b_5 +B5[51] buffer wire_logic_cluster/lc_2/out sp4_v_b_36 +B4[48] buffer wire_logic_cluster/lc_2/out sp4_v_b_4 +B5[48] buffer wire_logic_cluster/lc_2/out sp4_v_t_9 +!B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer wire_logic_cluster/lc_3/cout wire_logic_cluster/lc_4/in_3 +B8[50] buffer wire_logic_cluster/lc_3/out input_2_4 +B0[21],B0[22],!B0[23],!B0[24],!B1[21] buffer wire_logic_cluster/lc_3/out lc_trk_g0_3 +B4[21],B4[22],!B4[23],!B4[24],!B5[21] buffer wire_logic_cluster/lc_3/out lc_trk_g1_3 +B8[21],B8[22],!B8[23],!B8[24],!B9[21] buffer wire_logic_cluster/lc_3/out lc_trk_g2_3 +B12[21],B12[22],!B12[23],!B12[24],!B13[21] buffer wire_logic_cluster/lc_3/out lc_trk_g3_3 +B6[47] buffer wire_logic_cluster/lc_3/out sp12_h_r_14 +B6[51] buffer wire_logic_cluster/lc_3/out sp12_v_b_6 +B6[52] buffer wire_logic_cluster/lc_3/out sp12_v_t_21 +B6[46] buffer wire_logic_cluster/lc_3/out sp4_h_l_11 +B7[47] buffer wire_logic_cluster/lc_3/out sp4_h_r_38 +B7[46] buffer wire_logic_cluster/lc_3/out sp4_h_r_6 +B6[53] buffer wire_logic_cluster/lc_3/out sp4_r_v_b_23 +B7[53] buffer wire_logic_cluster/lc_3/out sp4_r_v_b_39 +B7[52] buffer wire_logic_cluster/lc_3/out sp4_r_v_b_7 +B7[48] buffer wire_logic_cluster/lc_3/out sp4_v_b_22 +B7[51] buffer wire_logic_cluster/lc_3/out sp4_v_b_38 +B6[48] buffer wire_logic_cluster/lc_3/out sp4_v_b_6 +!B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer wire_logic_cluster/lc_4/cout wire_logic_cluster/lc_5/in_3 +B10[50] buffer wire_logic_cluster/lc_4/out input_2_5 +B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer wire_logic_cluster/lc_4/out lc_trk_g0_4 +B6[14],!B7[14],!B7[15],!B7[16],B7[17] buffer wire_logic_cluster/lc_4/out lc_trk_g1_4 +B10[14],!B11[14],!B11[15],!B11[16],B11[17] buffer wire_logic_cluster/lc_4/out lc_trk_g2_4 +B14[14],!B15[14],!B15[15],!B15[16],B15[17] buffer wire_logic_cluster/lc_4/out lc_trk_g3_4 +B8[47] buffer wire_logic_cluster/lc_4/out sp12_h_r_0 +B8[48] buffer wire_logic_cluster/lc_4/out sp12_h_r_16 +B8[52] buffer wire_logic_cluster/lc_4/out sp12_v_b_8 +B8[46] buffer wire_logic_cluster/lc_4/out sp4_h_r_24 +B9[47] buffer wire_logic_cluster/lc_4/out sp4_h_r_40 +B9[46] buffer wire_logic_cluster/lc_4/out sp4_h_r_8 +B8[53] buffer wire_logic_cluster/lc_4/out sp4_r_v_b_25 +B9[53] buffer wire_logic_cluster/lc_4/out sp4_r_v_b_41 +B9[52] buffer wire_logic_cluster/lc_4/out sp4_r_v_b_9 +B9[51] buffer wire_logic_cluster/lc_4/out sp4_v_b_24 +B9[48] buffer wire_logic_cluster/lc_4/out sp4_v_b_8 +B8[51] buffer wire_logic_cluster/lc_4/out sp4_v_t_29 +!B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer wire_logic_cluster/lc_5/cout wire_logic_cluster/lc_6/in_3 +B12[50] buffer wire_logic_cluster/lc_5/out input_2_6 +!B2[15],!B2[16],B2[17],B2[18],!B3[18] buffer wire_logic_cluster/lc_5/out lc_trk_g0_5 +!B6[15],!B6[16],B6[17],B6[18],!B7[18] buffer wire_logic_cluster/lc_5/out lc_trk_g1_5 +!B10[15],!B10[16],B10[17],B10[18],!B11[18] buffer wire_logic_cluster/lc_5/out lc_trk_g2_5 +!B14[15],!B14[16],B14[17],B14[18],!B15[18] buffer wire_logic_cluster/lc_5/out lc_trk_g3_5 +B10[48] buffer wire_logic_cluster/lc_5/out sp12_h_l_17 +B10[47] buffer wire_logic_cluster/lc_5/out sp12_h_r_2 +B10[52] buffer wire_logic_cluster/lc_5/out sp12_v_t_9 +B10[46] buffer wire_logic_cluster/lc_5/out sp4_h_l_15 +B11[46] buffer wire_logic_cluster/lc_5/out sp4_h_r_10 +B11[47] buffer wire_logic_cluster/lc_5/out sp4_h_r_42 +B11[52] buffer wire_logic_cluster/lc_5/out sp4_r_v_b_11 +B10[53] buffer wire_logic_cluster/lc_5/out sp4_r_v_b_27 +B11[53] buffer wire_logic_cluster/lc_5/out sp4_r_v_b_43 +B11[48] buffer wire_logic_cluster/lc_5/out sp4_v_b_10 +B11[51] buffer wire_logic_cluster/lc_5/out sp4_v_b_26 +B10[51] buffer wire_logic_cluster/lc_5/out sp4_v_b_42 +!B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer wire_logic_cluster/lc_6/cout wire_logic_cluster/lc_7/in_3 +B14[50] buffer wire_logic_cluster/lc_6/out input_2_7 +B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer wire_logic_cluster/lc_6/out lc_trk_g0_6 +B6[25],B7[22],!B7[23],!B7[24],!B7[25] buffer wire_logic_cluster/lc_6/out lc_trk_g1_6 +B10[25],B11[22],!B11[23],!B11[24],!B11[25] buffer wire_logic_cluster/lc_6/out lc_trk_g2_6 +B14[25],B15[22],!B15[23],!B15[24],!B15[25] buffer wire_logic_cluster/lc_6/out lc_trk_g3_6 +B12[47] buffer wire_logic_cluster/lc_6/out sp12_h_l_3 +B12[48] buffer wire_logic_cluster/lc_6/out sp12_h_r_20 +B12[52] buffer wire_logic_cluster/lc_6/out sp12_v_b_12 +B13[46] buffer wire_logic_cluster/lc_6/out sp4_h_l_1 +B12[46] buffer wire_logic_cluster/lc_6/out sp4_h_l_17 +B13[47] buffer wire_logic_cluster/lc_6/out sp4_h_r_44 +B13[52] buffer wire_logic_cluster/lc_6/out sp4_r_v_b_13 +B12[53] buffer wire_logic_cluster/lc_6/out sp4_r_v_b_29 +B13[53] buffer wire_logic_cluster/lc_6/out sp4_r_v_b_45 +B13[48] buffer wire_logic_cluster/lc_6/out sp4_v_t_1 +B13[51] buffer wire_logic_cluster/lc_6/out sp4_v_t_17 +B12[51] buffer wire_logic_cluster/lc_6/out sp4_v_t_33 +B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer wire_logic_cluster/lc_7/out lc_trk_g0_7 +B6[21],B6[22],!B6[23],!B6[24],!B7[21] buffer wire_logic_cluster/lc_7/out lc_trk_g1_7 +B10[21],B10[22],!B10[23],!B10[24],!B11[21] buffer wire_logic_cluster/lc_7/out lc_trk_g2_7 +B14[21],B14[22],!B14[23],!B14[24],!B15[21] buffer wire_logic_cluster/lc_7/out lc_trk_g3_7 +B14[48] buffer wire_logic_cluster/lc_7/out sp12_h_l_21 +B14[47] buffer wire_logic_cluster/lc_7/out sp12_h_l_5 +B14[52] buffer wire_logic_cluster/lc_7/out sp12_v_b_14 +B15[46] buffer wire_logic_cluster/lc_7/out sp4_h_r_14 +B14[46] buffer wire_logic_cluster/lc_7/out sp4_h_r_30 +B15[47] buffer wire_logic_cluster/lc_7/out sp4_h_r_46 +B15[52] buffer wire_logic_cluster/lc_7/out sp4_r_v_b_15 +B14[53] buffer wire_logic_cluster/lc_7/out sp4_r_v_b_31 +B15[53] buffer wire_logic_cluster/lc_7/out sp4_r_v_b_47 +B15[51] buffer wire_logic_cluster/lc_7/out sp4_v_b_30 +B14[51] buffer wire_logic_cluster/lc_7/out sp4_v_b_46 +B15[48] buffer wire_logic_cluster/lc_7/out sp4_v_t_3 +!B12[3],B13[3] routing sp12_h_l_22 sp12_h_r_1 +!B8[3],B9[3] routing sp12_h_l_22 sp12_v_b_1 +!B14[3],B15[3] routing sp12_h_l_22 sp12_v_t_22 +!B4[3],B5[3] routing sp12_h_l_23 sp12_h_r_0 +!B0[3],B1[3] routing sp12_h_l_23 sp12_v_b_0 +!B6[3],B7[3] routing sp12_h_l_23 sp12_v_t_23 +B2[3],B3[3] routing sp12_h_r_0 sp12_h_l_23 +B0[3],B1[3] routing sp12_h_r_0 sp12_v_b_0 +B6[3],B7[3] routing sp12_h_r_0 sp12_v_t_23 +B10[3],B11[3] routing sp12_h_r_1 sp12_h_l_22 +B8[3],B9[3] routing sp12_h_r_1 sp12_v_b_1 +B14[3],B15[3] routing sp12_h_r_1 sp12_v_t_22 +!B2[3],B3[3] routing sp12_v_b_0 sp12_h_l_23 +B4[3],B5[3] routing sp12_v_b_0 sp12_h_r_0 +B6[3],!B7[3] routing sp12_v_b_0 sp12_v_t_23 +!B10[3],B11[3] routing sp12_v_b_1 sp12_h_l_22 +B12[3],B13[3] routing sp12_v_b_1 sp12_h_r_1 +B14[3],!B15[3] routing sp12_v_b_1 sp12_v_t_22 +B10[3],!B11[3] routing sp12_v_t_22 sp12_h_l_22 +B12[3],!B13[3] routing sp12_v_t_22 sp12_h_r_1 +B8[3],!B9[3] routing sp12_v_t_22 sp12_v_b_1 +B2[3],!B3[3] routing sp12_v_t_23 sp12_h_l_23 +B4[3],!B5[3] routing sp12_v_t_23 sp12_h_r_0 +B0[3],!B1[3] routing sp12_v_t_23 sp12_v_b_0 +B0[8],!B0[9],!B0[10] routing sp4_h_l_36 sp4_h_r_1 +!B4[8],B4[9],B4[10] routing sp4_h_l_36 sp4_h_r_4 +!B12[5],B13[4],B13[6] routing sp4_h_l_36 sp4_h_r_9 +B1[8],B1[9],!B1[10] routing sp4_h_l_36 sp4_v_b_1 +B9[8],B9[9],B9[10] routing sp4_h_l_36 sp4_v_b_7 +B3[8],!B3[9],!B3[10] routing sp4_h_l_36 sp4_v_t_36 +!B10[4],B10[6],!B11[5] routing sp4_h_l_36 sp4_v_t_43 +!B0[5],!B1[4],B1[6] routing sp4_h_l_37 sp4_h_r_0 +B4[5],B5[4],!B5[6] routing sp4_h_l_37 sp4_h_r_3 +!B8[12],B9[11],B9[13] routing sp4_h_l_37 sp4_h_r_8 +B0[4],!B0[6],B1[5] routing sp4_h_l_37 sp4_v_b_0 +B8[4],B8[6],B9[5] routing sp4_h_l_37 sp4_v_b_6 +!B2[4],!B2[6],B3[5] routing sp4_h_l_37 sp4_v_t_37 +B6[11],!B6[13],!B7[12] routing sp4_h_l_37 sp4_v_t_40 +!B12[12],B13[11],B13[13] routing sp4_h_l_38 sp4_h_r_11 +!B4[5],!B5[4],B5[6] routing sp4_h_l_38 sp4_h_r_3 +B8[5],B9[4],!B9[6] routing sp4_h_l_38 sp4_h_r_6 +B4[4],!B4[6],B5[5] routing sp4_h_l_38 sp4_v_b_3 +B12[4],B12[6],B13[5] routing sp4_h_l_38 sp4_v_b_9 +!B6[4],!B6[6],B7[5] routing sp4_h_l_38 sp4_v_t_38 +B10[11],!B10[13],!B11[12] routing sp4_h_l_38 sp4_v_t_45 +B12[8],!B12[9],B12[10] routing sp4_h_l_39 sp4_h_r_10 +!B0[12],B1[11],!B1[13] routing sp4_h_l_39 sp4_h_r_2 +B4[12],!B5[11],B5[13] routing sp4_h_l_39 sp4_h_r_5 +!B0[11],B0[13],B1[12] routing sp4_h_l_39 sp4_v_b_2 +B8[11],B8[13],B9[12] routing sp4_h_l_39 sp4_v_b_8 +!B2[11],!B2[13],B3[12] routing sp4_h_l_39 sp4_v_t_39 +!B11[8],!B11[9],B11[10] routing sp4_h_l_39 sp4_v_t_42 +B0[8],!B0[9],B0[10] routing sp4_h_l_40 sp4_h_r_1 +!B4[12],B5[11],!B5[13] routing sp4_h_l_40 sp4_h_r_5 +B8[12],!B9[11],B9[13] routing sp4_h_l_40 sp4_h_r_8 +B12[11],B12[13],B13[12] routing sp4_h_l_40 sp4_v_b_11 +!B4[11],B4[13],B5[12] routing sp4_h_l_40 sp4_v_b_5 +!B6[11],!B6[13],B7[12] routing sp4_h_l_40 sp4_v_t_40 +!B15[8],!B15[9],B15[10] routing sp4_h_l_40 sp4_v_t_47 +!B0[5],B1[4],B1[6] routing sp4_h_l_41 sp4_h_r_0 +B4[8],!B4[9],!B4[10] routing sp4_h_l_41 sp4_h_r_4 +!B8[8],B8[9],B8[10] routing sp4_h_l_41 sp4_h_r_7 +B13[8],B13[9],B13[10] routing sp4_h_l_41 sp4_v_b_10 +B5[8],B5[9],!B5[10] routing sp4_h_l_41 sp4_v_b_4 +B7[8],!B7[9],!B7[10] routing sp4_h_l_41 sp4_v_t_41 +!B14[4],B14[6],!B15[5] routing sp4_h_l_41 sp4_v_t_44 +!B12[8],B12[9],B12[10] routing sp4_h_l_42 sp4_h_r_10 +!B4[5],B5[4],B5[6] routing sp4_h_l_42 sp4_h_r_3 +B8[8],!B8[9],!B8[10] routing sp4_h_l_42 sp4_h_r_7 +B1[8],B1[9],B1[10] routing sp4_h_l_42 sp4_v_b_1 +B9[8],B9[9],!B9[10] routing sp4_h_l_42 sp4_v_b_7 +!B2[4],B2[6],!B3[5] routing sp4_h_l_42 sp4_v_t_37 +B11[8],!B11[9],!B11[10] routing sp4_h_l_42 sp4_v_t_42 +!B0[12],B1[11],B1[13] routing sp4_h_l_43 sp4_h_r_2 +!B8[5],!B9[4],B9[6] routing sp4_h_l_43 sp4_h_r_6 +B12[5],B13[4],!B13[6] routing sp4_h_l_43 sp4_h_r_9 +B0[4],B0[6],B1[5] routing sp4_h_l_43 sp4_v_b_0 +B8[4],!B8[6],B9[5] routing sp4_h_l_43 sp4_v_b_6 +!B10[4],!B10[6],B11[5] routing sp4_h_l_43 sp4_v_t_43 +B14[11],!B14[13],!B15[12] routing sp4_h_l_43 sp4_v_t_46 +B0[5],B1[4],!B1[6] routing sp4_h_l_44 sp4_h_r_0 +!B4[12],B5[11],B5[13] routing sp4_h_l_44 sp4_h_r_5 +!B12[5],!B13[4],B13[6] routing sp4_h_l_44 sp4_h_r_9 +B4[4],B4[6],B5[5] routing sp4_h_l_44 sp4_v_b_3 +B12[4],!B12[6],B13[5] routing sp4_h_l_44 sp4_v_b_9 +B2[11],!B2[13],!B3[12] routing sp4_h_l_44 sp4_v_t_39 +!B14[4],!B14[6],B15[5] routing sp4_h_l_44 sp4_v_t_44 +B12[12],!B13[11],B13[13] routing sp4_h_l_45 sp4_h_r_11 +B4[8],!B4[9],B4[10] routing sp4_h_l_45 sp4_h_r_4 +!B8[12],B9[11],!B9[13] routing sp4_h_l_45 sp4_h_r_8 +B0[11],B0[13],B1[12] routing sp4_h_l_45 sp4_v_b_2 +!B8[11],B8[13],B9[12] routing sp4_h_l_45 sp4_v_b_8 +!B3[8],!B3[9],B3[10] routing sp4_h_l_45 sp4_v_t_36 +!B10[11],!B10[13],B11[12] routing sp4_h_l_45 sp4_v_t_45 +!B12[12],B13[11],!B13[13] routing sp4_h_l_46 sp4_h_r_11 +B0[12],!B1[11],B1[13] routing sp4_h_l_46 sp4_h_r_2 +B8[8],!B8[9],B8[10] routing sp4_h_l_46 sp4_h_r_7 +!B12[11],B12[13],B13[12] routing sp4_h_l_46 sp4_v_b_11 +B4[11],B4[13],B5[12] routing sp4_h_l_46 sp4_v_b_5 +!B7[8],!B7[9],B7[10] routing sp4_h_l_46 sp4_v_t_41 +!B14[11],!B14[13],B15[12] routing sp4_h_l_46 sp4_v_t_46 +!B0[8],B0[9],B0[10] routing sp4_h_l_47 sp4_h_r_1 +B12[8],!B12[9],!B12[10] routing sp4_h_l_47 sp4_h_r_10 +!B8[5],B9[4],B9[6] routing sp4_h_l_47 sp4_h_r_6 +B13[8],B13[9],!B13[10] routing sp4_h_l_47 sp4_v_b_10 +B5[8],B5[9],B5[10] routing sp4_h_l_47 sp4_v_b_4 +!B6[4],B6[6],!B7[5] routing sp4_h_l_47 sp4_v_t_38 +B15[8],!B15[9],!B15[10] routing sp4_h_l_47 sp4_v_t_47 +!B2[5],!B3[4],B3[6] routing sp4_h_r_0 sp4_h_l_37 +B6[5],B7[4],!B7[6] routing sp4_h_r_0 sp4_h_l_38 +!B10[12],B11[11],B11[13] routing sp4_h_r_0 sp4_h_l_45 +!B0[4],!B0[6],B1[5] routing sp4_h_r_0 sp4_v_b_0 +B4[11],!B4[13],!B5[12] routing sp4_h_r_0 sp4_v_b_5 +B2[4],!B2[6],B3[5] routing sp4_h_r_0 sp4_v_t_37 +B10[4],B10[6],B11[5] routing sp4_h_r_0 sp4_v_t_43 +B2[8],!B2[9],!B2[10] routing sp4_h_r_1 sp4_h_l_36 +!B6[8],B6[9],B6[10] routing sp4_h_r_1 sp4_h_l_41 +!B14[5],B15[4],B15[6] routing sp4_h_r_1 sp4_h_l_44 +B1[8],!B1[9],!B1[10] routing sp4_h_r_1 sp4_v_b_1 +!B8[4],B8[6],!B9[5] routing sp4_h_r_1 sp4_v_b_6 +B3[8],B3[9],!B3[10] routing sp4_h_r_1 sp4_v_t_36 +B11[8],B11[9],B11[10] routing sp4_h_r_1 sp4_v_t_42 +!B2[8],B2[9],B2[10] routing sp4_h_r_10 sp4_h_l_36 +!B10[5],B11[4],B11[6] routing sp4_h_r_10 sp4_h_l_43 +B14[8],!B14[9],!B14[10] routing sp4_h_r_10 sp4_h_l_47 +B13[8],!B13[9],!B13[10] routing sp4_h_r_10 sp4_v_b_10 +!B4[4],B4[6],!B5[5] routing sp4_h_r_10 sp4_v_b_3 +B7[8],B7[9],B7[10] routing sp4_h_r_10 sp4_v_t_41 +B15[8],B15[9],!B15[10] routing sp4_h_r_10 sp4_v_t_47 +B2[12],!B3[11],B3[13] routing sp4_h_r_11 sp4_h_l_39 +B10[8],!B10[9],B10[10] routing sp4_h_r_11 sp4_h_l_42 +!B14[12],B15[11],!B15[13] routing sp4_h_r_11 sp4_h_l_46 +!B12[11],!B12[13],B13[12] routing sp4_h_r_11 sp4_v_b_11 +!B5[8],!B5[9],B5[10] routing sp4_h_r_11 sp4_v_b_4 +B6[11],B6[13],B7[12] routing sp4_h_r_11 sp4_v_t_40 +!B14[11],B14[13],B15[12] routing sp4_h_r_11 sp4_v_t_46 +!B2[12],B3[11],!B3[13] routing sp4_h_r_2 sp4_h_l_39 +B6[12],!B7[11],B7[13] routing sp4_h_r_2 sp4_h_l_40 +B14[8],!B14[9],B14[10] routing sp4_h_r_2 sp4_h_l_47 +!B0[11],!B0[13],B1[12] routing sp4_h_r_2 sp4_v_b_2 +!B9[8],!B9[9],B9[10] routing sp4_h_r_2 sp4_v_b_7 +!B2[11],B2[13],B3[12] routing sp4_h_r_2 sp4_v_t_39 +B10[11],B10[13],B11[12] routing sp4_h_r_2 sp4_v_t_45 +!B6[5],!B7[4],B7[6] routing sp4_h_r_3 sp4_h_l_38 +B10[5],B11[4],!B11[6] routing sp4_h_r_3 sp4_h_l_43 +!B14[12],B15[11],B15[13] routing sp4_h_r_3 sp4_h_l_46 +!B4[4],!B4[6],B5[5] routing sp4_h_r_3 sp4_v_b_3 +B8[11],!B8[13],!B9[12] routing sp4_h_r_3 sp4_v_b_8 +B6[4],!B6[6],B7[5] routing sp4_h_r_3 sp4_v_t_38 +B14[4],B14[6],B15[5] routing sp4_h_r_3 sp4_v_t_44 +!B2[5],B3[4],B3[6] routing sp4_h_r_4 sp4_h_l_37 +B6[8],!B6[9],!B6[10] routing sp4_h_r_4 sp4_h_l_41 +!B10[8],B10[9],B10[10] routing sp4_h_r_4 sp4_h_l_42 +B5[8],!B5[9],!B5[10] routing sp4_h_r_4 sp4_v_b_4 +!B12[4],B12[6],!B13[5] routing sp4_h_r_4 sp4_v_b_9 +B7[8],B7[9],!B7[10] routing sp4_h_r_4 sp4_v_t_41 +B15[8],B15[9],B15[10] routing sp4_h_r_4 sp4_v_t_47 +B2[8],!B2[9],B2[10] routing sp4_h_r_5 sp4_h_l_36 +!B6[12],B7[11],!B7[13] routing sp4_h_r_5 sp4_h_l_40 +B10[12],!B11[11],B11[13] routing sp4_h_r_5 sp4_h_l_45 +!B13[8],!B13[9],B13[10] routing sp4_h_r_5 sp4_v_b_10 +!B4[11],!B4[13],B5[12] routing sp4_h_r_5 sp4_v_b_5 +!B6[11],B6[13],B7[12] routing sp4_h_r_5 sp4_v_t_40 +B14[11],B14[13],B15[12] routing sp4_h_r_5 sp4_v_t_46 +!B2[12],B3[11],B3[13] routing sp4_h_r_6 sp4_h_l_39 +!B10[5],!B11[4],B11[6] routing sp4_h_r_6 sp4_h_l_43 +B14[5],B15[4],!B15[6] routing sp4_h_r_6 sp4_h_l_44 +B12[11],!B12[13],!B13[12] routing sp4_h_r_6 sp4_v_b_11 +!B8[4],!B8[6],B9[5] routing sp4_h_r_6 sp4_v_b_6 +B2[4],B2[6],B3[5] routing sp4_h_r_6 sp4_v_t_37 +B10[4],!B10[6],B11[5] routing sp4_h_r_6 sp4_v_t_43 +!B6[5],B7[4],B7[6] routing sp4_h_r_7 sp4_h_l_38 +B10[8],!B10[9],!B10[10] routing sp4_h_r_7 sp4_h_l_42 +!B14[8],B14[9],B14[10] routing sp4_h_r_7 sp4_h_l_47 +!B0[4],B0[6],!B1[5] routing sp4_h_r_7 sp4_v_b_0 +B9[8],!B9[9],!B9[10] routing sp4_h_r_7 sp4_v_b_7 +B3[8],B3[9],B3[10] routing sp4_h_r_7 sp4_v_t_36 +B11[8],B11[9],!B11[10] routing sp4_h_r_7 sp4_v_t_42 +B6[8],!B6[9],B6[10] routing sp4_h_r_8 sp4_h_l_41 +!B10[12],B11[11],!B11[13] routing sp4_h_r_8 sp4_h_l_45 +B14[12],!B15[11],B15[13] routing sp4_h_r_8 sp4_h_l_46 +!B1[8],!B1[9],B1[10] routing sp4_h_r_8 sp4_v_b_1 +!B8[11],!B8[13],B9[12] routing sp4_h_r_8 sp4_v_b_8 +B2[11],B2[13],B3[12] routing sp4_h_r_8 sp4_v_t_39 +!B10[11],B10[13],B11[12] routing sp4_h_r_8 sp4_v_t_45 +B2[5],B3[4],!B3[6] routing sp4_h_r_9 sp4_h_l_37 +!B6[12],B7[11],B7[13] routing sp4_h_r_9 sp4_h_l_40 +!B14[5],!B15[4],B15[6] routing sp4_h_r_9 sp4_h_l_44 +B0[11],!B0[13],!B1[12] routing sp4_h_r_9 sp4_v_b_2 +!B12[4],!B12[6],B13[5] routing sp4_h_r_9 sp4_v_b_9 +B6[4],B6[6],B7[5] routing sp4_h_r_9 sp4_v_t_38 +B14[4],!B14[6],B15[5] routing sp4_h_r_9 sp4_v_t_44 +B2[5],!B3[4],!B3[6] routing sp4_v_b_0 sp4_h_l_37 +!B6[12],!B7[11],B7[13] routing sp4_v_b_0 sp4_h_l_40 +B0[5],!B1[4],B1[6] routing sp4_v_b_0 sp4_h_r_0 +B8[5],B9[4],B9[6] routing sp4_v_b_0 sp4_h_r_6 +B2[4],!B2[6],!B3[5] routing sp4_v_b_0 sp4_v_t_37 +!B6[4],B6[6],B7[5] routing sp4_v_b_0 sp4_v_t_38 +B10[11],B10[13],!B11[12] routing sp4_v_b_0 sp4_v_t_45 +!B2[8],B2[9],!B2[10] routing sp4_v_b_1 sp4_h_l_36 +!B10[5],B11[4],!B11[6] routing sp4_v_b_1 sp4_h_l_43 +B0[8],B0[9],!B0[10] routing sp4_v_b_1 sp4_h_r_1 +B8[8],B8[9],B8[10] routing sp4_v_b_1 sp4_h_r_7 +!B3[8],B3[9],!B3[10] routing sp4_v_b_1 sp4_v_t_36 +B7[8],!B7[9],B7[10] routing sp4_v_b_1 sp4_v_t_41 +B14[4],B14[6],!B15[5] routing sp4_v_b_1 sp4_v_t_44 +!B6[5],B7[4],!B7[6] routing sp4_v_b_10 sp4_h_l_38 +!B14[8],B14[9],!B14[10] routing sp4_v_b_10 sp4_h_l_47 +B12[8],B12[9],!B12[10] routing sp4_v_b_10 sp4_h_r_10 +B4[8],B4[9],B4[10] routing sp4_v_b_10 sp4_h_r_4 +B3[8],!B3[9],B3[10] routing sp4_v_b_10 sp4_v_t_36 +B10[4],B10[6],!B11[5] routing sp4_v_b_10 sp4_v_t_43 +!B15[8],B15[9],!B15[10] routing sp4_v_b_10 sp4_v_t_47 +!B6[8],!B6[9],B6[10] routing sp4_v_b_11 sp4_h_l_41 +B14[12],!B15[11],!B15[13] routing sp4_v_b_11 sp4_h_l_46 +B12[12],B13[11],!B13[13] routing sp4_v_b_11 sp4_h_r_11 +B4[12],B5[11],B5[13] routing sp4_v_b_11 sp4_h_r_5 +B2[11],!B2[13],B3[12] routing sp4_v_b_11 sp4_v_t_39 +!B11[8],B11[9],B11[10] routing sp4_v_b_11 sp4_v_t_42 +!B14[11],B14[13],!B15[12] routing sp4_v_b_11 sp4_v_t_46 +B2[12],!B3[11],!B3[13] routing sp4_v_b_2 sp4_h_l_39 +!B10[8],!B10[9],B10[10] routing sp4_v_b_2 sp4_h_l_42 +B0[12],B1[11],!B1[13] routing sp4_v_b_2 sp4_h_r_2 +B8[12],B9[11],B9[13] routing sp4_v_b_2 sp4_h_r_8 +!B2[11],B2[13],!B3[12] routing sp4_v_b_2 sp4_v_t_39 +B6[11],!B6[13],B7[12] routing sp4_v_b_2 sp4_v_t_40 +!B15[8],B15[9],B15[10] routing sp4_v_b_2 sp4_v_t_47 +B6[5],!B7[4],!B7[6] routing sp4_v_b_3 sp4_h_l_38 +!B10[12],!B11[11],B11[13] routing sp4_v_b_3 sp4_h_l_45 +B4[5],!B5[4],B5[6] routing sp4_v_b_3 sp4_h_r_3 +B12[5],B13[4],B13[6] routing sp4_v_b_3 sp4_h_r_9 +B6[4],!B6[6],!B7[5] routing sp4_v_b_3 sp4_v_t_38 +!B10[4],B10[6],B11[5] routing sp4_v_b_3 sp4_v_t_43 +B14[11],B14[13],!B15[12] routing sp4_v_b_3 sp4_v_t_46 +!B6[8],B6[9],!B6[10] routing sp4_v_b_4 sp4_h_l_41 +!B14[5],B15[4],!B15[6] routing sp4_v_b_4 sp4_h_l_44 +B12[8],B12[9],B12[10] routing sp4_v_b_4 sp4_h_r_10 +B4[8],B4[9],!B4[10] routing sp4_v_b_4 sp4_h_r_4 +B2[4],B2[6],!B3[5] routing sp4_v_b_4 sp4_v_t_37 +!B7[8],B7[9],!B7[10] routing sp4_v_b_4 sp4_v_t_41 +B11[8],!B11[9],B11[10] routing sp4_v_b_4 sp4_v_t_42 +B6[12],!B7[11],!B7[13] routing sp4_v_b_5 sp4_h_l_40 +!B14[8],!B14[9],B14[10] routing sp4_v_b_5 sp4_h_l_47 +B12[12],B13[11],B13[13] routing sp4_v_b_5 sp4_h_r_11 +B4[12],B5[11],!B5[13] routing sp4_v_b_5 sp4_h_r_5 +!B3[8],B3[9],B3[10] routing sp4_v_b_5 sp4_v_t_36 +!B6[11],B6[13],!B7[12] routing sp4_v_b_5 sp4_v_t_40 +B10[11],!B10[13],B11[12] routing sp4_v_b_5 sp4_v_t_45 +B10[5],!B11[4],!B11[6] routing sp4_v_b_6 sp4_h_l_43 +!B14[12],!B15[11],B15[13] routing sp4_v_b_6 sp4_h_l_46 +B0[5],B1[4],B1[6] routing sp4_v_b_6 sp4_h_r_0 +B8[5],!B9[4],B9[6] routing sp4_v_b_6 sp4_h_r_6 +B2[11],B2[13],!B3[12] routing sp4_v_b_6 sp4_v_t_39 +B10[4],!B10[6],!B11[5] routing sp4_v_b_6 sp4_v_t_43 +!B14[4],B14[6],B15[5] routing sp4_v_b_6 sp4_v_t_44 +!B2[5],B3[4],!B3[6] routing sp4_v_b_7 sp4_h_l_37 +!B10[8],B10[9],!B10[10] routing sp4_v_b_7 sp4_h_l_42 +B0[8],B0[9],B0[10] routing sp4_v_b_7 sp4_h_r_1 +B8[8],B8[9],!B8[10] routing sp4_v_b_7 sp4_h_r_7 +B6[4],B6[6],!B7[5] routing sp4_v_b_7 sp4_v_t_38 +!B11[8],B11[9],!B11[10] routing sp4_v_b_7 sp4_v_t_42 +B15[8],!B15[9],B15[10] routing sp4_v_b_7 sp4_v_t_47 +!B2[8],!B2[9],B2[10] routing sp4_v_b_8 sp4_h_l_36 +B10[12],!B11[11],!B11[13] routing sp4_v_b_8 sp4_h_l_45 +B0[12],B1[11],B1[13] routing sp4_v_b_8 sp4_h_r_2 +B8[12],B9[11],!B9[13] routing sp4_v_b_8 sp4_h_r_8 +!B7[8],B7[9],B7[10] routing sp4_v_b_8 sp4_v_t_41 +!B10[11],B10[13],!B11[12] routing sp4_v_b_8 sp4_v_t_45 +B14[11],!B14[13],B15[12] routing sp4_v_b_8 sp4_v_t_46 +!B2[12],!B3[11],B3[13] routing sp4_v_b_9 sp4_h_l_39 +B14[5],!B15[4],!B15[6] routing sp4_v_b_9 sp4_h_l_44 +B4[5],B5[4],B5[6] routing sp4_v_b_9 sp4_h_r_3 +B12[5],!B13[4],B13[6] routing sp4_v_b_9 sp4_h_r_9 +!B2[4],B2[6],B3[5] routing sp4_v_b_9 sp4_v_t_37 +B6[11],B6[13],!B7[12] routing sp4_v_b_9 sp4_v_t_40 +B14[4],!B14[6],!B15[5] routing sp4_v_b_9 sp4_v_t_44 +B2[8],B2[9],!B2[10] routing sp4_v_t_36 sp4_h_l_36 +B10[8],B10[9],B10[10] routing sp4_v_t_36 sp4_h_l_42 +!B0[8],B0[9],!B0[10] routing sp4_v_t_36 sp4_h_r_1 +!B8[5],B9[4],!B9[6] routing sp4_v_t_36 sp4_h_r_6 +!B1[8],B1[9],!B1[10] routing sp4_v_t_36 sp4_v_b_1 +B5[8],!B5[9],B5[10] routing sp4_v_t_36 sp4_v_b_4 +B12[4],B12[6],!B13[5] routing sp4_v_t_36 sp4_v_b_9 +B2[5],!B3[4],B3[6] routing sp4_v_t_37 sp4_h_l_37 +B10[5],B11[4],B11[6] routing sp4_v_t_37 sp4_h_l_43 +B0[5],!B1[4],!B1[6] routing sp4_v_t_37 sp4_h_r_0 +!B4[12],!B5[11],B5[13] routing sp4_v_t_37 sp4_h_r_5 +B0[4],!B0[6],!B1[5] routing sp4_v_t_37 sp4_v_b_0 +!B4[4],B4[6],B5[5] routing sp4_v_t_37 sp4_v_b_3 +B8[11],B8[13],!B9[12] routing sp4_v_t_37 sp4_v_b_8 +B6[5],!B7[4],B7[6] routing sp4_v_t_38 sp4_h_l_38 +B14[5],B15[4],B15[6] routing sp4_v_t_38 sp4_h_l_44 +B4[5],!B5[4],!B5[6] routing sp4_v_t_38 sp4_h_r_3 +!B8[12],!B9[11],B9[13] routing sp4_v_t_38 sp4_h_r_8 +B12[11],B12[13],!B13[12] routing sp4_v_t_38 sp4_v_b_11 +B4[4],!B4[6],!B5[5] routing sp4_v_t_38 sp4_v_b_3 +!B8[4],B8[6],B9[5] routing sp4_v_t_38 sp4_v_b_6 +B2[12],B3[11],!B3[13] routing sp4_v_t_39 sp4_h_l_39 +B10[12],B11[11],B11[13] routing sp4_v_t_39 sp4_h_l_45 +B0[12],!B1[11],!B1[13] routing sp4_v_t_39 sp4_h_r_2 +!B8[8],!B8[9],B8[10] routing sp4_v_t_39 sp4_h_r_7 +!B13[8],B13[9],B13[10] routing sp4_v_t_39 sp4_v_b_10 +!B0[11],B0[13],!B1[12] routing sp4_v_t_39 sp4_v_b_2 +B4[11],!B4[13],B5[12] routing sp4_v_t_39 sp4_v_b_5 +B6[12],B7[11],!B7[13] routing sp4_v_t_40 sp4_h_l_40 +B14[12],B15[11],B15[13] routing sp4_v_t_40 sp4_h_l_46 +!B12[8],!B12[9],B12[10] routing sp4_v_t_40 sp4_h_r_10 +B4[12],!B5[11],!B5[13] routing sp4_v_t_40 sp4_h_r_5 +!B1[8],B1[9],B1[10] routing sp4_v_t_40 sp4_v_b_1 +!B4[11],B4[13],!B5[12] routing sp4_v_t_40 sp4_v_b_5 +B8[11],!B8[13],B9[12] routing sp4_v_t_40 sp4_v_b_8 +B6[8],B6[9],!B6[10] routing sp4_v_t_41 sp4_h_l_41 +B14[8],B14[9],B14[10] routing sp4_v_t_41 sp4_h_l_47 +!B4[8],B4[9],!B4[10] routing sp4_v_t_41 sp4_h_r_4 +!B12[5],B13[4],!B13[6] routing sp4_v_t_41 sp4_h_r_9 +B0[4],B0[6],!B1[5] routing sp4_v_t_41 sp4_v_b_0 +!B5[8],B5[9],!B5[10] routing sp4_v_t_41 sp4_v_b_4 +B9[8],!B9[9],B9[10] routing sp4_v_t_41 sp4_v_b_7 +B2[8],B2[9],B2[10] routing sp4_v_t_42 sp4_h_l_36 +B10[8],B10[9],!B10[10] routing sp4_v_t_42 sp4_h_l_42 +!B0[5],B1[4],!B1[6] routing sp4_v_t_42 sp4_h_r_0 +!B8[8],B8[9],!B8[10] routing sp4_v_t_42 sp4_h_r_7 +B13[8],!B13[9],B13[10] routing sp4_v_t_42 sp4_v_b_10 +B4[4],B4[6],!B5[5] routing sp4_v_t_42 sp4_v_b_3 +!B9[8],B9[9],!B9[10] routing sp4_v_t_42 sp4_v_b_7 +B2[5],B3[4],B3[6] routing sp4_v_t_43 sp4_h_l_37 +B10[5],!B11[4],B11[6] routing sp4_v_t_43 sp4_h_l_43 +!B12[12],!B13[11],B13[13] routing sp4_v_t_43 sp4_h_r_11 +B8[5],!B9[4],!B9[6] routing sp4_v_t_43 sp4_h_r_6 +B0[11],B0[13],!B1[12] routing sp4_v_t_43 sp4_v_b_2 +B8[4],!B8[6],!B9[5] routing sp4_v_t_43 sp4_v_b_6 +!B12[4],B12[6],B13[5] routing sp4_v_t_43 sp4_v_b_9 +B6[5],B7[4],B7[6] routing sp4_v_t_44 sp4_h_l_38 +B14[5],!B15[4],B15[6] routing sp4_v_t_44 sp4_h_l_44 +!B0[12],!B1[11],B1[13] routing sp4_v_t_44 sp4_h_r_2 +B12[5],!B13[4],!B13[6] routing sp4_v_t_44 sp4_h_r_9 +!B0[4],B0[6],B1[5] routing sp4_v_t_44 sp4_v_b_0 +B4[11],B4[13],!B5[12] routing sp4_v_t_44 sp4_v_b_5 +B12[4],!B12[6],!B13[5] routing sp4_v_t_44 sp4_v_b_9 +B2[12],B3[11],B3[13] routing sp4_v_t_45 sp4_h_l_39 +B10[12],B11[11],!B11[13] routing sp4_v_t_45 sp4_h_l_45 +!B0[8],!B0[9],B0[10] routing sp4_v_t_45 sp4_h_r_1 +B8[12],!B9[11],!B9[13] routing sp4_v_t_45 sp4_h_r_8 +B12[11],!B12[13],B13[12] routing sp4_v_t_45 sp4_v_b_11 +!B5[8],B5[9],B5[10] routing sp4_v_t_45 sp4_v_b_4 +!B8[11],B8[13],!B9[12] routing sp4_v_t_45 sp4_v_b_8 +B6[12],B7[11],B7[13] routing sp4_v_t_46 sp4_h_l_40 +B14[12],B15[11],!B15[13] routing sp4_v_t_46 sp4_h_l_46 +B12[12],!B13[11],!B13[13] routing sp4_v_t_46 sp4_h_r_11 +!B4[8],!B4[9],B4[10] routing sp4_v_t_46 sp4_h_r_4 +!B12[11],B12[13],!B13[12] routing sp4_v_t_46 sp4_v_b_11 +B0[11],!B0[13],B1[12] routing sp4_v_t_46 sp4_v_b_2 +!B9[8],B9[9],B9[10] routing sp4_v_t_46 sp4_v_b_7 +B6[8],B6[9],B6[10] routing sp4_v_t_47 sp4_h_l_41 +B14[8],B14[9],!B14[10] routing sp4_v_t_47 sp4_h_l_47 +!B12[8],B12[9],!B12[10] routing sp4_v_t_47 sp4_h_r_10 +!B4[5],B5[4],!B5[6] routing sp4_v_t_47 sp4_h_r_3 +B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1 +!B13[8],B13[9],!B13[10] routing sp4_v_t_47 sp4_v_b_10 +B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6 +""" +database_ram_txt = """ +B6[7] Cascade MEMT_LC00_inmux00_bram_cbit_7 +B4[7] Cascade MEMT_LC01_inmux00_bram_cbit_5 +B7[7] Cascade MEMT_LC01_inmux00_bram_cbit_6 +B6[7] Cascade MEMT_LC01_inmux00_bram_cbit_7 +B5[7] Cascade MEMT_LC02_inmux00_bram_cbit_4 +B4[7] Cascade MEMT_LC02_inmux00_bram_cbit_5 +B5[7] Cascade MEMT_LC03_inmux00_bram_cbit_4 +B4[7] Cascade MEMT_LC03_inmux00_bram_cbit_5 +B7[7] Cascade MEMT_LC03_inmux00_bram_cbit_6 +B6[7] Cascade MEMT_LC03_inmux00_bram_cbit_7 +B5[7] Cascade MEMT_LC04_inmux00_bram_cbit_4 +B4[7] Cascade MEMT_LC04_inmux00_bram_cbit_5 +B7[7] Cascade MEMT_LC04_inmux00_bram_cbit_6 +B6[7] Cascade MEMT_LC04_inmux00_bram_cbit_7 +B7[7] Cascade MEMT_LC05_inmux00_bram_cbit_6 +B6[7] Cascade MEMT_LC05_inmux00_bram_cbit_7 +B5[7] Cascade MEMT_LC07_inmux00_bram_cbit_4 +B4[7] Cascade MEMT_LC07_inmux00_bram_cbit_5 +B0[1] ColBufCtrl MEMB_colbuf_cntl_0 B0[1] +B1[2] ColBufCtrl MEMB_colbuf_cntl_1 B1[2] +B11[7] ColBufCtrl MEMB_colbuf_cntl_2 B11[7] +B5[2] ColBufCtrl MEMB_colbuf_cntl_2 B5[2] +B7[2] ColBufCtrl MEMB_colbuf_cntl_3 B7[2] +B13[7] ColBufCtrl MEMB_colbuf_cntl_4 B13[7] +B9[2] ColBufCtrl MEMB_colbuf_cntl_4 B9[2] +B11[2] ColBufCtrl MEMB_colbuf_cntl_5 B11[2] +B13[2] ColBufCtrl MEMB_colbuf_cntl_6 B13[2] +B15[2] ColBufCtrl MEMB_colbuf_cntl_7 B15[2] +B11[7] ColBufCtrl MEMT_colbuf_cntl_2 B11[7] +B1[7] RamConfig MEMB_Power_Up_Control +B12[19] buffer sp12_h_l_1 sp4_h_r_13 +B6[2] buffer sp12_h_l_13 sp4_h_r_19 +B8[2] buffer sp12_h_l_15 sp4_h_l_9 +B10[2] buffer sp12_h_l_17 sp4_h_r_21 +B14[2] buffer sp12_h_l_21 sp4_h_l_10 +B15[19] buffer sp12_h_l_3 sp4_h_l_3 +B14[19] buffer sp12_h_l_5 sp4_h_l_2 +B14[19] buffer sp12_h_l_5 sp4_h_r_15 +B3[1] buffer sp12_h_l_9 sp4_h_r_17 +B13[19] buffer sp12_h_r_0 sp4_h_l_1 +B13[19] buffer sp12_h_r_0 sp4_h_r_12 +B3[1] buffer sp12_h_r_10 sp4_h_r_17 +B4[2] buffer sp12_h_r_12 sp4_h_l_7 +B4[2] buffer sp12_h_r_12 sp4_h_r_18 +B6[2] buffer sp12_h_r_14 sp4_h_l_6 +B8[2] buffer sp12_h_r_16 sp4_h_r_20 +B10[2] buffer sp12_h_r_18 sp4_h_l_8 +B12[19] buffer sp12_h_r_2 sp4_h_r_13 +B12[2] buffer sp12_h_r_20 sp4_h_l_11 +B12[2] buffer sp12_h_r_20 sp4_h_r_22 +B14[2] buffer sp12_h_r_22 sp4_h_r_23 +B0[2] buffer sp12_h_r_8 sp4_h_l_5 +B0[2] buffer sp12_h_r_8 sp4_h_r_16 +B1[19] buffer sp12_v_b_1 sp4_v_b_12 +B1[19] buffer sp12_v_b_1 sp4_v_t_1 +B4[19] buffer sp12_v_b_11 sp4_v_b_17 +B7[19] buffer sp12_v_b_13 sp4_v_t_7 +B9[19] buffer sp12_v_b_17 sp4_v_b_20 +B8[19] buffer sp12_v_b_19 sp4_v_t_8 +B11[19] buffer sp12_v_b_21 sp4_v_b_22 +B10[19] buffer sp12_v_b_23 sp4_v_t_10 +B0[19] buffer sp12_v_b_3 sp4_v_b_13 +B3[19] buffer sp12_v_b_5 sp4_v_b_14 +B2[19] buffer sp12_v_b_7 sp4_v_t_2 +B5[19] buffer sp12_v_b_9 sp4_v_b_16 +B0[19] buffer sp12_v_t_0 sp4_v_b_13 +B7[19] buffer sp12_v_t_10 sp4_v_t_7 +B6[19] buffer sp12_v_t_12 sp4_v_b_19 +B6[19] buffer sp12_v_t_12 sp4_v_t_6 +B9[19] buffer sp12_v_t_14 sp4_v_b_20 +B8[19] buffer sp12_v_t_16 sp4_v_t_8 +B11[19] buffer sp12_v_t_18 sp4_v_t_11 +B10[19] buffer sp12_v_t_20 sp4_v_b_23 +B2[19] buffer sp12_v_t_4 sp4_v_t_2 +B4[19] buffer sp12_v_t_8 sp4_v_t_4 +!B12[3],B13[3] routing sp12_h_l_22 sp12_h_r_1 +!B8[3],B9[3] routing sp12_h_l_22 sp12_v_b_1 +!B14[3],B15[3] routing sp12_h_l_22 sp12_v_t_22 +!B4[3],B5[3] routing sp12_h_l_23 sp12_h_r_0 +!B0[3],B1[3] routing sp12_h_l_23 sp12_v_b_0 +!B6[3],B7[3] routing sp12_h_l_23 sp12_v_t_23 +B2[3],B3[3] routing sp12_h_r_0 sp12_h_l_23 +B0[3],B1[3] routing sp12_h_r_0 sp12_v_b_0 +B6[3],B7[3] routing sp12_h_r_0 sp12_v_t_23 +B10[3],B11[3] routing sp12_h_r_1 sp12_h_l_22 +B8[3],B9[3] routing sp12_h_r_1 sp12_v_b_1 +B14[3],B15[3] routing sp12_h_r_1 sp12_v_t_22 +!B2[3],B3[3] routing sp12_v_b_0 sp12_h_l_23 +B4[3],B5[3] routing sp12_v_b_0 sp12_h_r_0 +B6[3],!B7[3] routing sp12_v_b_0 sp12_v_t_23 +!B10[3],B11[3] routing sp12_v_b_1 sp12_h_l_22 +B12[3],B13[3] routing sp12_v_b_1 sp12_h_r_1 +B14[3],!B15[3] routing sp12_v_b_1 sp12_v_t_22 +B10[3],!B11[3] routing sp12_v_t_22 sp12_h_l_22 +B12[3],!B13[3] routing sp12_v_t_22 sp12_h_r_1 +B8[3],!B9[3] routing sp12_v_t_22 sp12_v_b_1 +B2[3],!B3[3] routing sp12_v_t_23 sp12_h_l_23 +B4[3],!B5[3] routing sp12_v_t_23 sp12_h_r_0 +B0[3],!B1[3] routing sp12_v_t_23 sp12_v_b_0 +B0[8],!B0[9],!B0[10] routing sp4_h_l_36 sp4_h_r_1 +!B4[8],B4[9],B4[10] routing sp4_h_l_36 sp4_h_r_4 +!B12[5],B13[4],B13[6] routing sp4_h_l_36 sp4_h_r_9 +B1[8],B1[9],!B1[10] routing sp4_h_l_36 sp4_v_b_1 +B9[8],B9[9],B9[10] routing sp4_h_l_36 sp4_v_b_7 +B3[8],!B3[9],!B3[10] routing sp4_h_l_36 sp4_v_t_36 +!B10[4],B10[6],!B11[5] routing sp4_h_l_36 sp4_v_t_43 +!B0[5],!B1[4],B1[6] routing sp4_h_l_37 sp4_h_r_0 +B4[5],B5[4],!B5[6] routing sp4_h_l_37 sp4_h_r_3 +!B8[12],B9[11],B9[13] routing sp4_h_l_37 sp4_h_r_8 +B0[4],!B0[6],B1[5] routing sp4_h_l_37 sp4_v_b_0 +B8[4],B8[6],B9[5] routing sp4_h_l_37 sp4_v_b_6 +!B2[4],!B2[6],B3[5] routing sp4_h_l_37 sp4_v_t_37 +B6[11],!B6[13],!B7[12] routing sp4_h_l_37 sp4_v_t_40 +!B12[12],B13[11],B13[13] routing sp4_h_l_38 sp4_h_r_11 +!B4[5],!B5[4],B5[6] routing sp4_h_l_38 sp4_h_r_3 +B8[5],B9[4],!B9[6] routing sp4_h_l_38 sp4_h_r_6 +B4[4],!B4[6],B5[5] routing sp4_h_l_38 sp4_v_b_3 +B12[4],B12[6],B13[5] routing sp4_h_l_38 sp4_v_b_9 +!B6[4],!B6[6],B7[5] routing sp4_h_l_38 sp4_v_t_38 +B10[11],!B10[13],!B11[12] routing sp4_h_l_38 sp4_v_t_45 +B12[8],!B12[9],B12[10] routing sp4_h_l_39 sp4_h_r_10 +!B0[12],B1[11],!B1[13] routing sp4_h_l_39 sp4_h_r_2 +B4[12],!B5[11],B5[13] routing sp4_h_l_39 sp4_h_r_5 +!B0[11],B0[13],B1[12] routing sp4_h_l_39 sp4_v_b_2 +B8[11],B8[13],B9[12] routing sp4_h_l_39 sp4_v_b_8 +!B2[11],!B2[13],B3[12] routing sp4_h_l_39 sp4_v_t_39 +!B11[8],!B11[9],B11[10] routing sp4_h_l_39 sp4_v_t_42 +B0[8],!B0[9],B0[10] routing sp4_h_l_40 sp4_h_r_1 +!B4[12],B5[11],!B5[13] routing sp4_h_l_40 sp4_h_r_5 +B8[12],!B9[11],B9[13] routing sp4_h_l_40 sp4_h_r_8 +B12[11],B12[13],B13[12] routing sp4_h_l_40 sp4_v_b_11 +!B4[11],B4[13],B5[12] routing sp4_h_l_40 sp4_v_b_5 +!B6[11],!B6[13],B7[12] routing sp4_h_l_40 sp4_v_t_40 +!B15[8],!B15[9],B15[10] routing sp4_h_l_40 sp4_v_t_47 +!B0[5],B1[4],B1[6] routing sp4_h_l_41 sp4_h_r_0 +B4[8],!B4[9],!B4[10] routing sp4_h_l_41 sp4_h_r_4 +!B8[8],B8[9],B8[10] routing sp4_h_l_41 sp4_h_r_7 +B13[8],B13[9],B13[10] routing sp4_h_l_41 sp4_v_b_10 +B5[8],B5[9],!B5[10] routing sp4_h_l_41 sp4_v_b_4 +B7[8],!B7[9],!B7[10] routing sp4_h_l_41 sp4_v_t_41 +!B14[4],B14[6],!B15[5] routing sp4_h_l_41 sp4_v_t_44 +!B12[8],B12[9],B12[10] routing sp4_h_l_42 sp4_h_r_10 +!B4[5],B5[4],B5[6] routing sp4_h_l_42 sp4_h_r_3 +B8[8],!B8[9],!B8[10] routing sp4_h_l_42 sp4_h_r_7 +B1[8],B1[9],B1[10] routing sp4_h_l_42 sp4_v_b_1 +B9[8],B9[9],!B9[10] routing sp4_h_l_42 sp4_v_b_7 +!B2[4],B2[6],!B3[5] routing sp4_h_l_42 sp4_v_t_37 +B11[8],!B11[9],!B11[10] routing sp4_h_l_42 sp4_v_t_42 +!B0[12],B1[11],B1[13] routing sp4_h_l_43 sp4_h_r_2 +!B8[5],!B9[4],B9[6] routing sp4_h_l_43 sp4_h_r_6 +B12[5],B13[4],!B13[6] routing sp4_h_l_43 sp4_h_r_9 +B0[4],B0[6],B1[5] routing sp4_h_l_43 sp4_v_b_0 +B8[4],!B8[6],B9[5] routing sp4_h_l_43 sp4_v_b_6 +!B10[4],!B10[6],B11[5] routing sp4_h_l_43 sp4_v_t_43 +B14[11],!B14[13],!B15[12] routing sp4_h_l_43 sp4_v_t_46 +B0[5],B1[4],!B1[6] routing sp4_h_l_44 sp4_h_r_0 +!B4[12],B5[11],B5[13] routing sp4_h_l_44 sp4_h_r_5 +!B12[5],!B13[4],B13[6] routing sp4_h_l_44 sp4_h_r_9 +B4[4],B4[6],B5[5] routing sp4_h_l_44 sp4_v_b_3 +B12[4],!B12[6],B13[5] routing sp4_h_l_44 sp4_v_b_9 +B2[11],!B2[13],!B3[12] routing sp4_h_l_44 sp4_v_t_39 +!B14[4],!B14[6],B15[5] routing sp4_h_l_44 sp4_v_t_44 +B12[12],!B13[11],B13[13] routing sp4_h_l_45 sp4_h_r_11 +B4[8],!B4[9],B4[10] routing sp4_h_l_45 sp4_h_r_4 +!B8[12],B9[11],!B9[13] routing sp4_h_l_45 sp4_h_r_8 +B0[11],B0[13],B1[12] routing sp4_h_l_45 sp4_v_b_2 +!B8[11],B8[13],B9[12] routing sp4_h_l_45 sp4_v_b_8 +!B3[8],!B3[9],B3[10] routing sp4_h_l_45 sp4_v_t_36 +!B10[11],!B10[13],B11[12] routing sp4_h_l_45 sp4_v_t_45 +!B12[12],B13[11],!B13[13] routing sp4_h_l_46 sp4_h_r_11 +B0[12],!B1[11],B1[13] routing sp4_h_l_46 sp4_h_r_2 +B8[8],!B8[9],B8[10] routing sp4_h_l_46 sp4_h_r_7 +!B12[11],B12[13],B13[12] routing sp4_h_l_46 sp4_v_b_11 +B4[11],B4[13],B5[12] routing sp4_h_l_46 sp4_v_b_5 +!B7[8],!B7[9],B7[10] routing sp4_h_l_46 sp4_v_t_41 +!B14[11],!B14[13],B15[12] routing sp4_h_l_46 sp4_v_t_46 +!B0[8],B0[9],B0[10] routing sp4_h_l_47 sp4_h_r_1 +B12[8],!B12[9],!B12[10] routing sp4_h_l_47 sp4_h_r_10 +!B8[5],B9[4],B9[6] routing sp4_h_l_47 sp4_h_r_6 +B13[8],B13[9],!B13[10] routing sp4_h_l_47 sp4_v_b_10 +B5[8],B5[9],B5[10] routing sp4_h_l_47 sp4_v_b_4 +!B6[4],B6[6],!B7[5] routing sp4_h_l_47 sp4_v_t_38 +B15[8],!B15[9],!B15[10] routing sp4_h_l_47 sp4_v_t_47 +!B2[5],!B3[4],B3[6] routing sp4_h_r_0 sp4_h_l_37 +B6[5],B7[4],!B7[6] routing sp4_h_r_0 sp4_h_l_38 +!B10[12],B11[11],B11[13] routing sp4_h_r_0 sp4_h_l_45 +!B0[4],!B0[6],B1[5] routing sp4_h_r_0 sp4_v_b_0 +B4[11],!B4[13],!B5[12] routing sp4_h_r_0 sp4_v_b_5 +B2[4],!B2[6],B3[5] routing sp4_h_r_0 sp4_v_t_37 +B10[4],B10[6],B11[5] routing sp4_h_r_0 sp4_v_t_43 +B2[8],!B2[9],!B2[10] routing sp4_h_r_1 sp4_h_l_36 +!B6[8],B6[9],B6[10] routing sp4_h_r_1 sp4_h_l_41 +!B14[5],B15[4],B15[6] routing sp4_h_r_1 sp4_h_l_44 +B1[8],!B1[9],!B1[10] routing sp4_h_r_1 sp4_v_b_1 +!B8[4],B8[6],!B9[5] routing sp4_h_r_1 sp4_v_b_6 +B3[8],B3[9],!B3[10] routing sp4_h_r_1 sp4_v_t_36 +B11[8],B11[9],B11[10] routing sp4_h_r_1 sp4_v_t_42 +!B2[8],B2[9],B2[10] routing sp4_h_r_10 sp4_h_l_36 +!B10[5],B11[4],B11[6] routing sp4_h_r_10 sp4_h_l_43 +B14[8],!B14[9],!B14[10] routing sp4_h_r_10 sp4_h_l_47 +B13[8],!B13[9],!B13[10] routing sp4_h_r_10 sp4_v_b_10 +!B4[4],B4[6],!B5[5] routing sp4_h_r_10 sp4_v_b_3 +B7[8],B7[9],B7[10] routing sp4_h_r_10 sp4_v_t_41 +B15[8],B15[9],!B15[10] routing sp4_h_r_10 sp4_v_t_47 +B2[12],!B3[11],B3[13] routing sp4_h_r_11 sp4_h_l_39 +B10[8],!B10[9],B10[10] routing sp4_h_r_11 sp4_h_l_42 +!B14[12],B15[11],!B15[13] routing sp4_h_r_11 sp4_h_l_46 +!B12[11],!B12[13],B13[12] routing sp4_h_r_11 sp4_v_b_11 +!B5[8],!B5[9],B5[10] routing sp4_h_r_11 sp4_v_b_4 +B6[11],B6[13],B7[12] routing sp4_h_r_11 sp4_v_t_40 +!B14[11],B14[13],B15[12] routing sp4_h_r_11 sp4_v_t_46 +!B2[12],B3[11],!B3[13] routing sp4_h_r_2 sp4_h_l_39 +B6[12],!B7[11],B7[13] routing sp4_h_r_2 sp4_h_l_40 +B14[8],!B14[9],B14[10] routing sp4_h_r_2 sp4_h_l_47 +!B0[11],!B0[13],B1[12] routing sp4_h_r_2 sp4_v_b_2 +!B9[8],!B9[9],B9[10] routing sp4_h_r_2 sp4_v_b_7 +!B2[11],B2[13],B3[12] routing sp4_h_r_2 sp4_v_t_39 +B10[11],B10[13],B11[12] routing sp4_h_r_2 sp4_v_t_45 +!B6[5],!B7[4],B7[6] routing sp4_h_r_3 sp4_h_l_38 +B10[5],B11[4],!B11[6] routing sp4_h_r_3 sp4_h_l_43 +!B14[12],B15[11],B15[13] routing sp4_h_r_3 sp4_h_l_46 +!B4[4],!B4[6],B5[5] routing sp4_h_r_3 sp4_v_b_3 +B8[11],!B8[13],!B9[12] routing sp4_h_r_3 sp4_v_b_8 +B6[4],!B6[6],B7[5] routing sp4_h_r_3 sp4_v_t_38 +B14[4],B14[6],B15[5] routing sp4_h_r_3 sp4_v_t_44 +!B2[5],B3[4],B3[6] routing sp4_h_r_4 sp4_h_l_37 +B6[8],!B6[9],!B6[10] routing sp4_h_r_4 sp4_h_l_41 +!B10[8],B10[9],B10[10] routing sp4_h_r_4 sp4_h_l_42 +B5[8],!B5[9],!B5[10] routing sp4_h_r_4 sp4_v_b_4 +!B12[4],B12[6],!B13[5] routing sp4_h_r_4 sp4_v_b_9 +B7[8],B7[9],!B7[10] routing sp4_h_r_4 sp4_v_t_41 +B15[8],B15[9],B15[10] routing sp4_h_r_4 sp4_v_t_47 +B2[8],!B2[9],B2[10] routing sp4_h_r_5 sp4_h_l_36 +!B6[12],B7[11],!B7[13] routing sp4_h_r_5 sp4_h_l_40 +B10[12],!B11[11],B11[13] routing sp4_h_r_5 sp4_h_l_45 +!B13[8],!B13[9],B13[10] routing sp4_h_r_5 sp4_v_b_10 +!B4[11],!B4[13],B5[12] routing sp4_h_r_5 sp4_v_b_5 +!B6[11],B6[13],B7[12] routing sp4_h_r_5 sp4_v_t_40 +B14[11],B14[13],B15[12] routing sp4_h_r_5 sp4_v_t_46 +!B2[12],B3[11],B3[13] routing sp4_h_r_6 sp4_h_l_39 +!B10[5],!B11[4],B11[6] routing sp4_h_r_6 sp4_h_l_43 +B14[5],B15[4],!B15[6] routing sp4_h_r_6 sp4_h_l_44 +B12[11],!B12[13],!B13[12] routing sp4_h_r_6 sp4_v_b_11 +!B8[4],!B8[6],B9[5] routing sp4_h_r_6 sp4_v_b_6 +B2[4],B2[6],B3[5] routing sp4_h_r_6 sp4_v_t_37 +B10[4],!B10[6],B11[5] routing sp4_h_r_6 sp4_v_t_43 +!B6[5],B7[4],B7[6] routing sp4_h_r_7 sp4_h_l_38 +B10[8],!B10[9],!B10[10] routing sp4_h_r_7 sp4_h_l_42 +!B14[8],B14[9],B14[10] routing sp4_h_r_7 sp4_h_l_47 +!B0[4],B0[6],!B1[5] routing sp4_h_r_7 sp4_v_b_0 +B9[8],!B9[9],!B9[10] routing sp4_h_r_7 sp4_v_b_7 +B3[8],B3[9],B3[10] routing sp4_h_r_7 sp4_v_t_36 +B11[8],B11[9],!B11[10] routing sp4_h_r_7 sp4_v_t_42 +B6[8],!B6[9],B6[10] routing sp4_h_r_8 sp4_h_l_41 +!B10[12],B11[11],!B11[13] routing sp4_h_r_8 sp4_h_l_45 +B14[12],!B15[11],B15[13] routing sp4_h_r_8 sp4_h_l_46 +!B1[8],!B1[9],B1[10] routing sp4_h_r_8 sp4_v_b_1 +!B8[11],!B8[13],B9[12] routing sp4_h_r_8 sp4_v_b_8 +B2[11],B2[13],B3[12] routing sp4_h_r_8 sp4_v_t_39 +!B10[11],B10[13],B11[12] routing sp4_h_r_8 sp4_v_t_45 +B2[5],B3[4],!B3[6] routing sp4_h_r_9 sp4_h_l_37 +!B6[12],B7[11],B7[13] routing sp4_h_r_9 sp4_h_l_40 +!B14[5],!B15[4],B15[6] routing sp4_h_r_9 sp4_h_l_44 +B0[11],!B0[13],!B1[12] routing sp4_h_r_9 sp4_v_b_2 +!B12[4],!B12[6],B13[5] routing sp4_h_r_9 sp4_v_b_9 +B6[4],B6[6],B7[5] routing sp4_h_r_9 sp4_v_t_38 +B14[4],!B14[6],B15[5] routing sp4_h_r_9 sp4_v_t_44 +B2[5],!B3[4],!B3[6] routing sp4_v_b_0 sp4_h_l_37 +!B6[12],!B7[11],B7[13] routing sp4_v_b_0 sp4_h_l_40 +B0[5],!B1[4],B1[6] routing sp4_v_b_0 sp4_h_r_0 +B8[5],B9[4],B9[6] routing sp4_v_b_0 sp4_h_r_6 +B2[4],!B2[6],!B3[5] routing sp4_v_b_0 sp4_v_t_37 +!B6[4],B6[6],B7[5] routing sp4_v_b_0 sp4_v_t_38 +B10[11],B10[13],!B11[12] routing sp4_v_b_0 sp4_v_t_45 +!B2[8],B2[9],!B2[10] routing sp4_v_b_1 sp4_h_l_36 +!B10[5],B11[4],!B11[6] routing sp4_v_b_1 sp4_h_l_43 +B0[8],B0[9],!B0[10] routing sp4_v_b_1 sp4_h_r_1 +B8[8],B8[9],B8[10] routing sp4_v_b_1 sp4_h_r_7 +!B3[8],B3[9],!B3[10] routing sp4_v_b_1 sp4_v_t_36 +B7[8],!B7[9],B7[10] routing sp4_v_b_1 sp4_v_t_41 +B14[4],B14[6],!B15[5] routing sp4_v_b_1 sp4_v_t_44 +!B6[5],B7[4],!B7[6] routing sp4_v_b_10 sp4_h_l_38 +!B14[8],B14[9],!B14[10] routing sp4_v_b_10 sp4_h_l_47 +B12[8],B12[9],!B12[10] routing sp4_v_b_10 sp4_h_r_10 +B4[8],B4[9],B4[10] routing sp4_v_b_10 sp4_h_r_4 +B3[8],!B3[9],B3[10] routing sp4_v_b_10 sp4_v_t_36 +B10[4],B10[6],!B11[5] routing sp4_v_b_10 sp4_v_t_43 +!B15[8],B15[9],!B15[10] routing sp4_v_b_10 sp4_v_t_47 +!B6[8],!B6[9],B6[10] routing sp4_v_b_11 sp4_h_l_41 +B14[12],!B15[11],!B15[13] routing sp4_v_b_11 sp4_h_l_46 +B12[12],B13[11],!B13[13] routing sp4_v_b_11 sp4_h_r_11 +B4[12],B5[11],B5[13] routing sp4_v_b_11 sp4_h_r_5 +B2[11],!B2[13],B3[12] routing sp4_v_b_11 sp4_v_t_39 +!B11[8],B11[9],B11[10] routing sp4_v_b_11 sp4_v_t_42 +!B14[11],B14[13],!B15[12] routing sp4_v_b_11 sp4_v_t_46 +B2[12],!B3[11],!B3[13] routing sp4_v_b_2 sp4_h_l_39 +!B10[8],!B10[9],B10[10] routing sp4_v_b_2 sp4_h_l_42 +B0[12],B1[11],!B1[13] routing sp4_v_b_2 sp4_h_r_2 +B8[12],B9[11],B9[13] routing sp4_v_b_2 sp4_h_r_8 +!B2[11],B2[13],!B3[12] routing sp4_v_b_2 sp4_v_t_39 +B6[11],!B6[13],B7[12] routing sp4_v_b_2 sp4_v_t_40 +!B15[8],B15[9],B15[10] routing sp4_v_b_2 sp4_v_t_47 +B6[5],!B7[4],!B7[6] routing sp4_v_b_3 sp4_h_l_38 +!B10[12],!B11[11],B11[13] routing sp4_v_b_3 sp4_h_l_45 +B4[5],!B5[4],B5[6] routing sp4_v_b_3 sp4_h_r_3 +B12[5],B13[4],B13[6] routing sp4_v_b_3 sp4_h_r_9 +B6[4],!B6[6],!B7[5] routing sp4_v_b_3 sp4_v_t_38 +!B10[4],B10[6],B11[5] routing sp4_v_b_3 sp4_v_t_43 +B14[11],B14[13],!B15[12] routing sp4_v_b_3 sp4_v_t_46 +!B6[8],B6[9],!B6[10] routing sp4_v_b_4 sp4_h_l_41 +!B14[5],B15[4],!B15[6] routing sp4_v_b_4 sp4_h_l_44 +B12[8],B12[9],B12[10] routing sp4_v_b_4 sp4_h_r_10 +B4[8],B4[9],!B4[10] routing sp4_v_b_4 sp4_h_r_4 +B2[4],B2[6],!B3[5] routing sp4_v_b_4 sp4_v_t_37 +!B7[8],B7[9],!B7[10] routing sp4_v_b_4 sp4_v_t_41 +B11[8],!B11[9],B11[10] routing sp4_v_b_4 sp4_v_t_42 +B6[12],!B7[11],!B7[13] routing sp4_v_b_5 sp4_h_l_40 +!B14[8],!B14[9],B14[10] routing sp4_v_b_5 sp4_h_l_47 +B12[12],B13[11],B13[13] routing sp4_v_b_5 sp4_h_r_11 +B4[12],B5[11],!B5[13] routing sp4_v_b_5 sp4_h_r_5 +!B3[8],B3[9],B3[10] routing sp4_v_b_5 sp4_v_t_36 +!B6[11],B6[13],!B7[12] routing sp4_v_b_5 sp4_v_t_40 +B10[11],!B10[13],B11[12] routing sp4_v_b_5 sp4_v_t_45 +B10[5],!B11[4],!B11[6] routing sp4_v_b_6 sp4_h_l_43 +!B14[12],!B15[11],B15[13] routing sp4_v_b_6 sp4_h_l_46 +B0[5],B1[4],B1[6] routing sp4_v_b_6 sp4_h_r_0 +B8[5],!B9[4],B9[6] routing sp4_v_b_6 sp4_h_r_6 +B2[11],B2[13],!B3[12] routing sp4_v_b_6 sp4_v_t_39 +B10[4],!B10[6],!B11[5] routing sp4_v_b_6 sp4_v_t_43 +!B14[4],B14[6],B15[5] routing sp4_v_b_6 sp4_v_t_44 +!B2[5],B3[4],!B3[6] routing sp4_v_b_7 sp4_h_l_37 +!B10[8],B10[9],!B10[10] routing sp4_v_b_7 sp4_h_l_42 +B0[8],B0[9],B0[10] routing sp4_v_b_7 sp4_h_r_1 +B8[8],B8[9],!B8[10] routing sp4_v_b_7 sp4_h_r_7 +B6[4],B6[6],!B7[5] routing sp4_v_b_7 sp4_v_t_38 +!B11[8],B11[9],!B11[10] routing sp4_v_b_7 sp4_v_t_42 +B15[8],!B15[9],B15[10] routing sp4_v_b_7 sp4_v_t_47 +!B2[8],!B2[9],B2[10] routing sp4_v_b_8 sp4_h_l_36 +B10[12],!B11[11],!B11[13] routing sp4_v_b_8 sp4_h_l_45 +B0[12],B1[11],B1[13] routing sp4_v_b_8 sp4_h_r_2 +B8[12],B9[11],!B9[13] routing sp4_v_b_8 sp4_h_r_8 +!B7[8],B7[9],B7[10] routing sp4_v_b_8 sp4_v_t_41 +!B10[11],B10[13],!B11[12] routing sp4_v_b_8 sp4_v_t_45 +B14[11],!B14[13],B15[12] routing sp4_v_b_8 sp4_v_t_46 +!B2[12],!B3[11],B3[13] routing sp4_v_b_9 sp4_h_l_39 +B14[5],!B15[4],!B15[6] routing sp4_v_b_9 sp4_h_l_44 +B4[5],B5[4],B5[6] routing sp4_v_b_9 sp4_h_r_3 +B12[5],!B13[4],B13[6] routing sp4_v_b_9 sp4_h_r_9 +!B2[4],B2[6],B3[5] routing sp4_v_b_9 sp4_v_t_37 +B6[11],B6[13],!B7[12] routing sp4_v_b_9 sp4_v_t_40 +B14[4],!B14[6],!B15[5] routing sp4_v_b_9 sp4_v_t_44 +B2[8],B2[9],!B2[10] routing sp4_v_t_36 sp4_h_l_36 +B10[8],B10[9],B10[10] routing sp4_v_t_36 sp4_h_l_42 +!B0[8],B0[9],!B0[10] routing sp4_v_t_36 sp4_h_r_1 +!B8[5],B9[4],!B9[6] routing sp4_v_t_36 sp4_h_r_6 +!B1[8],B1[9],!B1[10] routing sp4_v_t_36 sp4_v_b_1 +B5[8],!B5[9],B5[10] routing sp4_v_t_36 sp4_v_b_4 +B12[4],B12[6],!B13[5] routing sp4_v_t_36 sp4_v_b_9 +B2[5],!B3[4],B3[6] routing sp4_v_t_37 sp4_h_l_37 +B10[5],B11[4],B11[6] routing sp4_v_t_37 sp4_h_l_43 +B0[5],!B1[4],!B1[6] routing sp4_v_t_37 sp4_h_r_0 +!B4[12],!B5[11],B5[13] routing sp4_v_t_37 sp4_h_r_5 +B0[4],!B0[6],!B1[5] routing sp4_v_t_37 sp4_v_b_0 +!B4[4],B4[6],B5[5] routing sp4_v_t_37 sp4_v_b_3 +B8[11],B8[13],!B9[12] routing sp4_v_t_37 sp4_v_b_8 +B6[5],!B7[4],B7[6] routing sp4_v_t_38 sp4_h_l_38 +B14[5],B15[4],B15[6] routing sp4_v_t_38 sp4_h_l_44 +B4[5],!B5[4],!B5[6] routing sp4_v_t_38 sp4_h_r_3 +!B8[12],!B9[11],B9[13] routing sp4_v_t_38 sp4_h_r_8 +B12[11],B12[13],!B13[12] routing sp4_v_t_38 sp4_v_b_11 +B4[4],!B4[6],!B5[5] routing sp4_v_t_38 sp4_v_b_3 +!B8[4],B8[6],B9[5] routing sp4_v_t_38 sp4_v_b_6 +B2[12],B3[11],!B3[13] routing sp4_v_t_39 sp4_h_l_39 +B10[12],B11[11],B11[13] routing sp4_v_t_39 sp4_h_l_45 +B0[12],!B1[11],!B1[13] routing sp4_v_t_39 sp4_h_r_2 +!B8[8],!B8[9],B8[10] routing sp4_v_t_39 sp4_h_r_7 +!B13[8],B13[9],B13[10] routing sp4_v_t_39 sp4_v_b_10 +!B0[11],B0[13],!B1[12] routing sp4_v_t_39 sp4_v_b_2 +B4[11],!B4[13],B5[12] routing sp4_v_t_39 sp4_v_b_5 +B6[12],B7[11],!B7[13] routing sp4_v_t_40 sp4_h_l_40 +B14[12],B15[11],B15[13] routing sp4_v_t_40 sp4_h_l_46 +!B12[8],!B12[9],B12[10] routing sp4_v_t_40 sp4_h_r_10 +B4[12],!B5[11],!B5[13] routing sp4_v_t_40 sp4_h_r_5 +!B1[8],B1[9],B1[10] routing sp4_v_t_40 sp4_v_b_1 +!B4[11],B4[13],!B5[12] routing sp4_v_t_40 sp4_v_b_5 +B8[11],!B8[13],B9[12] routing sp4_v_t_40 sp4_v_b_8 +B6[8],B6[9],!B6[10] routing sp4_v_t_41 sp4_h_l_41 +B14[8],B14[9],B14[10] routing sp4_v_t_41 sp4_h_l_47 +!B4[8],B4[9],!B4[10] routing sp4_v_t_41 sp4_h_r_4 +!B12[5],B13[4],!B13[6] routing sp4_v_t_41 sp4_h_r_9 +B0[4],B0[6],!B1[5] routing sp4_v_t_41 sp4_v_b_0 +!B5[8],B5[9],!B5[10] routing sp4_v_t_41 sp4_v_b_4 +B9[8],!B9[9],B9[10] routing sp4_v_t_41 sp4_v_b_7 +B2[8],B2[9],B2[10] routing sp4_v_t_42 sp4_h_l_36 +B10[8],B10[9],!B10[10] routing sp4_v_t_42 sp4_h_l_42 +!B0[5],B1[4],!B1[6] routing sp4_v_t_42 sp4_h_r_0 +!B8[8],B8[9],!B8[10] routing sp4_v_t_42 sp4_h_r_7 +B13[8],!B13[9],B13[10] routing sp4_v_t_42 sp4_v_b_10 +B4[4],B4[6],!B5[5] routing sp4_v_t_42 sp4_v_b_3 +!B9[8],B9[9],!B9[10] routing sp4_v_t_42 sp4_v_b_7 +B2[5],B3[4],B3[6] routing sp4_v_t_43 sp4_h_l_37 +B10[5],!B11[4],B11[6] routing sp4_v_t_43 sp4_h_l_43 +!B12[12],!B13[11],B13[13] routing sp4_v_t_43 sp4_h_r_11 +B8[5],!B9[4],!B9[6] routing sp4_v_t_43 sp4_h_r_6 +B0[11],B0[13],!B1[12] routing sp4_v_t_43 sp4_v_b_2 +B8[4],!B8[6],!B9[5] routing sp4_v_t_43 sp4_v_b_6 +!B12[4],B12[6],B13[5] routing sp4_v_t_43 sp4_v_b_9 +B6[5],B7[4],B7[6] routing sp4_v_t_44 sp4_h_l_38 +B14[5],!B15[4],B15[6] routing sp4_v_t_44 sp4_h_l_44 +!B0[12],!B1[11],B1[13] routing sp4_v_t_44 sp4_h_r_2 +B12[5],!B13[4],!B13[6] routing sp4_v_t_44 sp4_h_r_9 +!B0[4],B0[6],B1[5] routing sp4_v_t_44 sp4_v_b_0 +B4[11],B4[13],!B5[12] routing sp4_v_t_44 sp4_v_b_5 +B12[4],!B12[6],!B13[5] routing sp4_v_t_44 sp4_v_b_9 +B2[12],B3[11],B3[13] routing sp4_v_t_45 sp4_h_l_39 +B10[12],B11[11],!B11[13] routing sp4_v_t_45 sp4_h_l_45 +!B0[8],!B0[9],B0[10] routing sp4_v_t_45 sp4_h_r_1 +B8[12],!B9[11],!B9[13] routing sp4_v_t_45 sp4_h_r_8 +B12[11],!B12[13],B13[12] routing sp4_v_t_45 sp4_v_b_11 +!B5[8],B5[9],B5[10] routing sp4_v_t_45 sp4_v_b_4 +!B8[11],B8[13],!B9[12] routing sp4_v_t_45 sp4_v_b_8 +B6[12],B7[11],B7[13] routing sp4_v_t_46 sp4_h_l_40 +B14[12],B15[11],!B15[13] routing sp4_v_t_46 sp4_h_l_46 +B12[12],!B13[11],!B13[13] routing sp4_v_t_46 sp4_h_r_11 +!B4[8],!B4[9],B4[10] routing sp4_v_t_46 sp4_h_r_4 +!B12[11],B12[13],!B13[12] routing sp4_v_t_46 sp4_v_b_11 +B0[11],!B0[13],B1[12] routing sp4_v_t_46 sp4_v_b_2 +!B9[8],B9[9],B9[10] routing sp4_v_t_46 sp4_v_b_7 +B6[8],B6[9],B6[10] routing sp4_v_t_47 sp4_h_l_41 +B14[8],B14[9],!B14[10] routing sp4_v_t_47 sp4_h_l_47 +!B12[8],B12[9],!B12[10] routing sp4_v_t_47 sp4_h_r_10 +!B4[5],B5[4],!B5[6] routing sp4_v_t_47 sp4_h_r_3 +B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1 +!B13[8],B13[9],!B13[10] routing sp4_v_t_47 sp4_v_b_10 +B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6 +""" +pinloc_txt = """ +10 0 11 0 +101 13 13 0 +1 0 14 1 +102 13 13 1 +104 13 14 0 +105 13 14 1 +106 13 15 0 +107 13 15 1 +11 0 10 1 +112 12 17 1 +113 12 17 0 +114 11 17 1 +115 11 17 0 +116 10 17 1 +117 10 17 0 +118 9 17 1 +119 9 17 0 +12 0 10 0 +120 8 17 1 +121 8 17 0 +122 7 17 1 +128 7 17 0 +129 6 17 1 +134 5 17 1 +135 5 17 0 +136 4 17 1 +137 4 17 0 +138 3 17 1 +139 3 17 0 +141 2 17 1 +142 2 17 0 +143 1 17 1 +144 1 17 0 +19 0 9 1 +20 0 9 0 +2 0 14 0 +21 0 8 1 +22 0 8 0 +23 0 6 1 +24 0 6 0 +25 0 5 1 +26 0 5 0 +28 0 4 1 +29 0 4 0 +3 0 13 1 +31 0 3 1 +32 0 3 0 +33 0 2 1 +34 0 2 0 +37 1 0 0 +38 1 0 1 +39 2 0 0 +4 0 13 0 +41 2 0 1 +42 3 0 0 +43 3 0 1 +44 4 0 0 +45 4 0 1 +47 5 0 0 +48 5 0 1 +49 6 0 1 +50 7 0 0 +52 6 0 0 +56 7 0 1 +58 8 0 0 +60 8 0 1 +61 9 0 0 +62 9 0 1 +63 10 0 0 +64 10 0 1 +67 11 0 0 +68 11 0 1 +70 12 0 0 +7 0 12 1 +71 12 0 1 +73 13 1 0 +74 13 1 1 +75 13 2 0 +76 13 2 1 +78 13 3 1 +79 13 4 0 +8 0 12 0 +80 13 4 1 +81 13 6 0 +87 13 6 1 +88 13 7 0 +9 0 11 1 +90 13 7 1 +91 13 8 0 +93 13 8 1 +94 13 9 0 +95 13 9 1 +96 13 11 0 +97 13 11 1 +98 13 12 0 +99 13 12 1 +""" -- cgit v1.2.3