From cd0e6cfa8e594255b9640f644a97d9d549e62093 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 30 Dec 2016 14:29:44 +0100
Subject: Added icestick rs232 demo

---
 examples/icestick/.gitignore   |  4 +++
 examples/icestick/icestick.pcf |  2 ++
 examples/icestick/rs232demo.v  | 59 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 65 insertions(+)
 create mode 100644 examples/icestick/rs232demo.v

(limited to 'examples')

diff --git a/examples/icestick/.gitignore b/examples/icestick/.gitignore
index c1fa30b..539898f 100644
--- a/examples/icestick/.gitignore
+++ b/examples/icestick/.gitignore
@@ -2,3 +2,7 @@ example.bin
 example.blif
 example.asc
 example.rpt
+rs232demo.bin
+rs232demo.blif
+rs232demo.asc
+rs232demo.rpt
diff --git a/examples/icestick/icestick.pcf b/examples/icestick/icestick.pcf
index a1693eb..49cb382 100644
--- a/examples/icestick/icestick.pcf
+++ b/examples/icestick/icestick.pcf
@@ -1,3 +1,5 @@
+set_io --warn-no-port RX 9
+set_io --warn-no-port TX 8
 set_io LED1 99
 set_io LED2 98
 set_io LED3 97
diff --git a/examples/icestick/rs232demo.v b/examples/icestick/rs232demo.v
new file mode 100644
index 0000000..fc7a770
--- /dev/null
+++ b/examples/icestick/rs232demo.v
@@ -0,0 +1,59 @@
+module top (
+	input  clk,
+	input  RX,
+	output TX,
+	output reg LED1,
+	output reg LED2,
+	output reg LED3,
+	output reg LED4,
+	output reg LED5
+);
+	parameter integer BAUD_RATE = 9600;
+	parameter integer CLOCK_FREQ_HZ = 12000000;
+	localparam integer HALF_PERIOD = CLOCK_FREQ_HZ / (2 * BAUD_RATE);
+
+	reg [9:0] buffer;
+	reg buffer_valid;
+
+	reg [$clog2(3*HALF_PERIOD):0] cycle_cnt;
+	reg [3:0] bit_cnt = 0;
+	reg [0:0] state = 0;
+
+	always @(posedge clk) begin
+		buffer_valid <= 0;
+		case (state)
+			0: begin
+				if (!RX) begin
+					cycle_cnt <= HALF_PERIOD;
+					bit_cnt <= 0;
+					state <= 1;
+				end
+			end
+			1: begin
+				if (cycle_cnt == 2*HALF_PERIOD) begin
+					cycle_cnt <= 0;
+					buffer[bit_cnt] <= RX;
+					bit_cnt <= bit_cnt + 1;
+					if (bit_cnt == 9) begin
+						buffer_valid <= 1;
+						state <= 0;
+					end
+				end else begin
+					cycle_cnt <= cycle_cnt + 1;
+				end
+			end
+		endcase
+	end
+
+	always @(posedge clk) begin
+		if (buffer_valid) begin
+			if (buffer[8:1] == "1") LED1 <= !LED1;
+			if (buffer[8:1] == "2") LED2 <= !LED2;
+			if (buffer[8:1] == "3") LED3 <= !LED3;
+			if (buffer[8:1] == "4") LED4 <= !LED4;
+			if (buffer[8:1] == "5") LED5 <= !LED5;
+		end
+	end
+
+	assign TX = RX;
+endmodule
-- 
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