From d1e16d54ad7dd6bb7334494450917107615d0ef2 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 2 Oct 2015 14:06:54 +0200 Subject: Converted docs to proper HTML5 --- docs/format.html | 34 +++- docs/index.html | 39 ++-- docs/io_tile.html | 561 ++++++++++++++++++++++++++------------------------- docs/logic_tile.html | 315 ++++++++++++++--------------- docs/ram_tile.html | 79 ++++---- 5 files changed, 528 insertions(+), 500 deletions(-) (limited to 'docs') diff --git a/docs/format.html b/docs/format.html index 75397e0..8c21c00 100644 --- a/docs/format.html +++ b/docs/format.html @@ -1,4 +1,18 @@ + + + Project IceStorm – Bitstream File Format Documentation +

Project IceStorm – Bitstream File Format Documentation

@@ -31,8 +45,7 @@ follows the command in case of the CRAM and BRAM commands. The following commands are known:

- +

Opcode Description

0 payload=0: CRAM Data
payload=3: BRAM Data
@@ -53,10 +66,9 @@ The following commands are known: payload=16: Enable cold boot
payload=32: Enable warm boot

-

Opcode	Description
0	payload=0: CRAM Data payload=3: BRAM Data @@ -53,10 +66,9 @@ The following commands are known: payload=16: Enable cold boot payload=32: Enable warm boot

-Use iceunpack -vv to display the commands as they are interpreted by the tool. +Use iceunpack -vv to display the commands as they are interpreted by the tool.

@@ -72,7 +84,7 @@ Most bytes in the bitstream are SRAM data bytes that should be written to the va in the FPGA. The following sequence is used to program an SRAM cell:

Set bank width (opcode 6)
Set bank height (opcode 7)
Set bank offset (opcode 8)
CRAM or BRAM Data Command
(width * height / 8) data bytes
two zero bytes

The bank width and height parameters reflect the width and height of the SRAM bank. A large SRAM can @@ -104,7 +116,8 @@ The ordering of the data bits is in MSB first row-major order.

Organization of the CRAM

The chip is organized into four quadrants. Each CRAM memory bank contains the configuration bits for one quadrant. @@ -129,14 +142,14 @@ RAM tiles are 42 bits wide. (Notice the two slightly smaller columns for the RAM

The IO tiles on the top and bottom of the chip use a strange permutation pattern for their bits. It can be seen in the picture that their columns are spread out horizontally. What cannot be seen in the picture is the columns also are not in order and the bit -positions are vertically permuted as well. The CramIndexConverter class in icepack.cc encapsulates the calculations +positions are vertically permuted as well. The CramIndexConverter class in icepack.cc encapsulates the calculations that are neccessary to convert between tile-relative bit addresses and CRAM bank-relative bit addresses.

The black pixels in the image correspond to CRAM bits that are not associated with any IO, LOGIC or RAM tile. -Some of them are unused, others are used by hard IPs or other global resources. The iceunpack tool reports -such bits, when set, with the ".extra_bit bank x y" statement in the ASCII output format. +Some of them are unused, others are used by hard IPs or other global resources. The iceunpack tool reports +such bits, when set, with the ".extra_bit bank x y" statement in the ASCII output format.

Organization of the BRAM

@@ -152,3 +165,4 @@ The CRC is a 16 bit CRC. The (truncated) polynomial is 0x1021 (CRC-16-CCITT). Th the CRC to 0xFFFF. No zero padding is performed.

+ diff --git a/docs/index.html b/docs/index.html index 17b99a7..a400fef 100644 --- a/docs/index.html +++ b/docs/index.html @@ -1,4 +1,7 @@ + + Project IceStorm +

Project IceStorm

@@ -102,16 +105,16 @@ after updating your IceStorm installation.

IcePack/IceUnpack

-The iceunpack program converts an iCE40 .bin file into the IceBox ASCII format -that has blocks of 0 and 1 for the config bits for each tile in the chip. The -icepack program converts such an ASCII file back to an iCE40 .bin file. +The iceunpack program converts an iCE40 .bin file into the IceBox ASCII format +that has blocks of 0 and 1 for the config bits for each tile in the chip. The +icepack program converts such an ASCII file back to an iCE40 .bin file.

IceBox

A python library and various tools for working with IceBox ASCII files and accessing -the device database. For example icebox_vlog converts our ASCII file +the device database. For example icebox_vlog converts our ASCII file dump of a bitstream into a Verilog file that implements an equivalent circuit.

@@ -130,7 +133,7 @@ A tool for packing multiple bitstream files into one iCE40 multiboot image file.

ChipDB

-The IceStorm Makefile builds and installs two files: chipdb-1k.txt and chipdb-8k.txt. +The IceStorm Makefile builds and installs two files: chipdb-1k.txt and chipdb-8k.txt. This files contain all the relevant information for arachne-pnr to place&route a design and create an IceBox ASCII file for the placed and routed design.

@@ -163,8 +166,8 @@ The FPGA fabric is divided into tiles. There are IO, RAM and LOGIC tiles.

-The iceunpack program can be used to convert the bitstream into an ASCII file -that has a block of 0 and 1 characters for each tile. For example: +The iceunpack program can be used to convert the bitstream into an ASCII file +that has a block of 0 and 1 characters for each tile. For example:

.logic_tile 12 12
@@ -186,12 +189,12 @@ that has a block of 0 and 1 characters for each tile. For exam
 000000000000000000000000000101010000101010100000000000

-This bits are referred to as By[x] in the documentation. For example, B0 is the first -line, B0[0] the first bit in the first line, and B15[53] the last bit in the last line. +This bits are referred to as By[x] in the documentation. For example, B0 is the first +line, B0[0] the first bit in the first line, and B15[53] the last bit in the last line.

-The icebox_explain program can be used to turn this block of config bits into a description of the cell +The icebox_explain program can be used to turn this block of config bits into a description of the cell configuration:

@@ -205,16 +208,16 @@ buffer sp12_h_r_20 local_g1_4

IceBox contains a database of the wires and configuration bits that can be found in iCE40 tiles. This database can be accessed via the IceBox Python API. But IceBox is a large hack. So it is recommended to only use the IceBox API -to export this database into a format that fits the target application. See icebox_chipdb for +to export this database into a format that fits the target application. See icebox_chipdb for an example program that does that.

The recommended approach for learning how to use this documentation is to synthesize very simple circuits using Yosys and Arachne-pnr, run the icestorm -tool icebox_explain on the resulting bitstream files, and analyze the +tool icebox_explain on the resulting bitstream files, and analyze the results using the HTML export of the database mentioned above. -icebox_vlog can be used to convert the bitstream to Verilog. The +icebox_vlog can be used to convert the bitstream to Verilog. The output file of this tool will also outline the signal paths in comments added to the generated Verilog code.

@@ -243,7 +246,7 @@ $ icepack example.txt example.bin

-We would get something like the following icebox_explain output: +We would get something like the following icebox_explain output:

$ icebox_explain example.txt
@@ -280,7 +283,7 @@ buffer neigh_op_lft_0 local_g0_0
 buffer sp4_h_r_24 local_g3_0

-And something like the following icebox_vlog output: +And something like the following icebox_vlog output:

$ icebox_vlog -p example.pcf example.txt
@@ -353,9 +356,7 @@ Links to related projects. Contact me at clifford@clifford.at if you have an int
 ICEd = an Arduino Style Board, with ICE FPGA
 
 
-
 

-
 
 
 In papers and reports, please refer to Project IceStorm as follows: Clifford Wolf, Mathias Lasser. Project IceStorm. http://www.clifford.at/icestorm/,
@@ -368,11 +369,11 @@ e.g. using the following BibTeX code:
 	howpublished = "\url{http://www.clifford.at/icestorm/}"
 }

Documentation mostly by Clifford Wolf <clifford@clifford.at> in 2015. Based on research by Mathias Lasser and Clifford Wolf.
Buy an iCEstick from Lattice and see what you can do with the information provided here. Buy a few because you might break some..

+ + diff --git a/docs/io_tile.html b/docs/io_tile.html index 53ee497..8c1555f 100644 --- a/docs/io_tile.html +++ b/docs/io_tile.html @@ -1,4 +1,27 @@ + + + Project IceStorm – IO Tile Documentation +

Project IceStorm – IO Tile Documentation

@@ -9,31 +32,31 @@ This is work in progress.

Span-4 and Span-12 Wires

The image on the right shows the span-wires of a left (or right) io cell (click to enlarge).

-A left/right io cell has 16 connections named span4_vert_t_0 to span4_vert_t_15 on its top edge and -16 connections named span4_vert_b_0 to span4_vert_b_15 on its bottom edge. The nets span4_vert_t_0 -to span4_vert_t_11 are connected to span4_vert_b_4 to span4_vert_b_15. The span-4 and span-12 wires -of the adjacent logic cell are connected to the nets span4_horz_0 to span4_horz_47 and span12_horz_0 -to span12_horz_23. +A left/right io cell has 16 connections named span4_vert_t_0 to span4_vert_t_15 on its top edge and +16 connections named span4_vert_b_0 to span4_vert_b_15 on its bottom edge. The nets span4_vert_t_0 +to span4_vert_t_11 are connected to span4_vert_b_4 to span4_vert_b_15. The span-4 and span-12 wires +of the adjacent logic cell are connected to the nets span4_horz_0 to span4_horz_47 and span12_horz_0 +to span12_horz_23.

-A top/bottom io cell has 16 connections named span4_vert_l_0 to span4_vert_l_15 on its top edge and -16 connections named span4_vert_r_0 to span4_vert_r_15 on its bottom edge. The nets span4_vert_l_0 -to span4_vert_l_11 are connected to span4_vert_r_4 to span4_vert_r_15. The span-4 and span-12 wires -of the adjacent logic cell are connected to the nets span4_vert_0 to span4_vert_47 and span12_vert_0 -to span12_vert_23. +A top/bottom io cell has 16 connections named span4_vert_l_0 to span4_vert_l_15 on its top edge and +16 connections named span4_vert_r_0 to span4_vert_r_15 on its bottom edge. The nets span4_vert_l_0 +to span4_vert_l_11 are connected to span4_vert_r_4 to span4_vert_r_15. The span-4 and span-12 wires +of the adjacent logic cell are connected to the nets span4_vert_0 to span4_vert_47 and span12_vert_0 +to span12_vert_23.

The vertical span4 wires of left/right io cells are connected "around the corner" to the horizontal span4 wires of the top/bottom -io cells. For example span4_vert_b_0 of IO cell (0 1) is connected to span4_horz_l_0 (span4_horz_r_4) +io cells. For example span4_vert_b_0 of IO cell (0 1) is connected to span4_horz_l_0 (span4_horz_r_4) of IO cell (1 0).

@@ -45,26 +68,24 @@ connecting IO tiles to each other are not pairwise crossed out.

IO Blocks

-Each IO tile contains two IO blocks. Each IO block essentially implements the SB_IO +Each IO tile contains two IO blocks. Each IO block essentially implements the SB_IO primitive from the Lattice iCE Technology Library. Some inputs are shared between the two IO blocks. The following table lists how the -wires in the logic tile map to the SB_IO primitive ports: +wires in the logic tile map to the SB_IO primitive ports:

- +
- - - - - - - - - + + + + + + + + +

SB_IO Port IO Block 0 IO Block 1
D_IN_0 io_0/D_IN_0 io_1/D_IN_0
D_IN_1 io_0/D_IN_1 io_1/D_IN_1
D_OUT_0 io_0/D_OUT_0 io_1/D_OUT_0
D_OUT_1 io_0/D_OUT_1 io_1/D_OUT_1
OUTPUT_ENABLE io_0/OUT_ENB io_1/OUT_ENB
CLOCK_ENABLE io_global/cen
INPUT_CLK io_global/inclk
OUTPUT_CLK io_global/outclk
LATCH_INPUT_VALUE io_global/latch
D_IN_0 io_0/D_IN_0 io_1/D_IN_0
D_IN_1 io_0/D_IN_1 io_1/D_IN_1
D_OUT_0 io_0/D_OUT_0 io_1/D_OUT_0
D_OUT_1 io_0/D_OUT_1 io_1/D_OUT_1
OUTPUT_ENABLE io_0/OUT_ENB io_1/OUT_ENB
CLOCK_ENABLE io_global/cen
INPUT_CLK io_global/inclk
OUTPUT_CLK io_global/outclk
LATCH_INPUT_VALUE io_global/latch

-

SB_IO Port	IO Block 0	IO Block 1
D_IN_0	`io_0/D_IN_0`	`io_1/D_IN_0`
D_IN_1	`io_0/D_IN_1`	`io_1/D_IN_1`
D_OUT_0	`io_0/D_OUT_0`	`io_1/D_OUT_0`
D_OUT_1	`io_0/D_OUT_1`	`io_1/D_OUT_1`
OUTPUT_ENABLE	`io_0/OUT_ENB`	`io_1/OUT_ENB`
CLOCK_ENABLE	`io_global/cen`
INPUT_CLK	`io_global/inclk`
OUTPUT_CLK	`io_global/outclk`
LATCH_INPUT_VALUE	`io_global/latch`
D_IN_0	io_0/D_IN_0	io_1/D_IN_0
D_IN_1	io_0/D_IN_1	io_1/D_IN_1
D_OUT_0	io_0/D_OUT_0	io_1/D_OUT_0
D_OUT_1	io_0/D_OUT_1	io_1/D_OUT_1
OUTPUT_ENABLE	io_0/OUT_ENB	io_1/OUT_ENB
CLOCK_ENABLE	io_global/cen
INPUT_CLK	io_global/inclk
OUTPUT_CLK	io_global/outclk
LATCH_INPUT_VALUE	io_global/latch

Like the inputs to logic cells, the inputs to IO blocks are routed to the IO block via a two-stage process. A signal @@ -72,36 +93,34 @@ is first routed to one of 16 local tracks in the IO tile and then from the local

-The io_global/latch signal is shared among all IO tiles on an edge of the chip and is driven by fabout -from one dedicated IO tile on that edge. For the HX1K chips the tiles driving the io_global/latch signal are: +The io_global/latch signal is shared among all IO tiles on an edge of the chip and is driven by fabout +from one dedicated IO tile on that edge. For the HX1K chips the tiles driving the io_global/latch signal are: (0, 7), (13, 10), (5, 0), and (8, 17)

-A logic tile sends the output of its eight logic cells to its neighbour tiles. An IO tile does the same thing with the four D_IN -signals created by its two IO blocks. The D_IN signals map to logic function indices as follows: +A logic tile sends the output of its eight logic cells to its neighbour tiles. An IO tile does the same thing with the four D_IN +signals created by its two IO blocks. The D_IN signals map to logic function indices as follows:

- +
- - - - - - - - + + + + + + + +

Function Index D_IN Wire
0 io_0/D_IN_0
1 io_0/D_IN_1
2 io_1/D_IN_0
3 io_1/D_IN_1
4 io_0/D_IN_0
5 io_0/D_IN_1
6 io_1/D_IN_0
7 io_1/D_IN_1
0 io_0/D_IN_0
1 io_0/D_IN_1
2 io_1/D_IN_0
3 io_1/D_IN_1
4 io_0/D_IN_0
5 io_0/D_IN_1
6 io_1/D_IN_0
7 io_1/D_IN_1

-

Function Index	D_IN Wire
0	`io_0/D_IN_0`
1	`io_0/D_IN_1`
2	`io_1/D_IN_0`
3	`io_1/D_IN_1`
4	`io_0/D_IN_0`
5	`io_0/D_IN_1`
6	`io_1/D_IN_0`
7	`io_1/D_IN_1`
0	io_0/D_IN_0
1	io_0/D_IN_1
2	io_1/D_IN_0
3	io_1/D_IN_1
4	io_0/D_IN_0
5	io_0/D_IN_1
6	io_1/D_IN_0
7	io_1/D_IN_1

-For example the signal io_1/D_IN_0 in IO tile (0, 5) can be seen as neigh_op_lft_2 and neigh_op_lft_6 in LOGIC tile (1, 5). +For example the signal io_1/D_IN_0 in IO tile (0, 5) can be seen as neigh_op_lft_2 and neigh_op_lft_6 in LOGIC tile (1, 5).

-Each IO Tile has 2 NegClk configuration bits, suggesting that the +Each IO Tile has 2 NegClk configuration bits, suggesting that the clock signals can be inverted independently for the the two IO blocks in the tile. However, the Lattice tools refuse to pack to IO blocks with different block polarity into the same IO tile. In our tests we only managed to either set or clear @@ -109,159 +128,157 @@ both NegClk bits.

-Each IO block has two IoCtrl IE bits that enable the input buffers and -two IoCtrl REN bits that enable the pull up resistors. Both bits are active +Each IO block has two IoCtrl IE bits that enable the input buffers and +two IoCtrl REN bits that enable the pull up resistors. Both bits are active low, i.e. an unused IO tile will have both IE bits set and both REN bits cleared (the default behavior is to enable pullup resistors on all unused pins). Note that -icebox_explain.py will ignore all IO tiles that only have the two IoCtrl -IE bits set. +icebox_explain.py will ignore all IO tiles that only have the two IoCtrl +IE bits set.

-However, the IoCtrl IE_0/IE_1 and IoCtrl REN_0/REN_1 do not +However, the IoCtrl IE_0/IE_1 and IoCtrl REN_0/REN_1 do not necessarily configure the IO PIN that are connected to the IO block in the same tile, and if they do the numbers (0/1) do not necessarily match. As a general rule, the pins on the right and bottom side of the chips match up with the IO blocks and for the pins on the left and top side the numbers must be swapped. But in some cases the IO block -and the set of IE/REN are not even located in the same tile. The following -table lists the correlation between IO blocks and IE/REN bits for the +and the set of IE/REN are not even located in the same tile. The following +table lists the correlation between IO blocks and IE/REN bits for the 1K chip:

- - + + + + + + + + + + + + + + + +
+ +
- +
- - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + +

IO Block IE/REN Block
0 14 1 0 14 0
0 14 0 0 14 1
0 13 1 0 13 0
0 13 0 0 13 1
0 12 1 0 12 0
0 12 0 0 12 1
0 11 1 0 11 0
0 11 0 0 11 1
0 10 1 0 10 0
0 10 0 0 10 1
0 9 1 0 9 0
0 9 0 0 9 1
0 8 1 0 8 0
0 8 0 0 8 1
0 6 1 0 6 0
0 6 0 0 6 1
0 5 1 0 5 0
0 5 0 0 5 1
0 4 1 0 4 0
0 4 0 0 4 1
0 3 1 0 3 0
0 3 0 0 3 1
0 2 1 0 2 0
0 2 0 0 2 1
0 14 1 0 14 0
0 14 0 0 14 1
0 13 1 0 13 0
0 13 0 0 13 1
0 12 1 0 12 0
0 12 0 0 12 1
0 11 1 0 11 0
0 11 0 0 11 1
0 10 1 0 10 0
0 10 0 0 10 1
0 9 1 0 9 0
0 9 0 0 9 1
0 8 1 0 8 0
0 8 0 0 8 1
0 6 1 0 6 0
0 6 0 0 6 1
0 5 1 0 5 0
0 5 0 0 5 1
0 4 1 0 4 0
0 4 0 0 4 1
0 3 1 0 3 0
0 3 0 0 3 1
0 2 1 0 2 0
0 2 0 0 2 1

- + - +
- - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + +

IO Block IE/REN Block
1 0 0 1 0 0
1 0 1 1 0 1
2 0 0 2 0 0
2 0 1 2 0 1
3 0 0 3 0 0
3 0 1 3 0 1
4 0 0 4 0 0
4 0 1 4 0 1
5 0 0 5 0 0
5 0 1 5 0 1
6 0 1 6 0 0
7 0 0 6 0 1
6 0 0 7 0 0
7 0 1 7 0 1
8 0 0 8 0 0
8 0 1 8 0 1
9 0 0 9 0 0
9 0 1 9 0 1
10 0 0 10 0 0
10 0 1 10 0 1
11 0 0 11 0 0
11 0 1 11 0 1
12 0 0 12 0 0
12 0 1 12 0 1
1 0 0 1 0 0
1 0 1 1 0 1
2 0 0 2 0 0
2 0 1 2 0 1
3 0 0 3 0 0
3 0 1 3 0 1
4 0 0 4 0 0
4 0 1 4 0 1
5 0 0 5 0 0
5 0 1 5 0 1
6 0 1 6 0 0
7 0 0 6 0 1
6 0 0 7 0 0
7 0 1 7 0 1
8 0 0 8 0 0
8 0 1 8 0 1
9 0 0 9 0 0
9 0 1 9 0 1
10 0 0 10 0 0
10 0 1 10 0 1
11 0 0 11 0 0
11 0 1 11 0 1
12 0 0 12 0 0
12 0 1 12 0 1

- + - +
- - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + +

IO Block IE/REN Block
13 1 0 13 1 0
13 1 1 13 1 1
13 2 0 13 2 0
13 2 1 13 2 1
13 3 1 13 3 1
13 4 0 13 4 0
13 4 1 13 4 1
13 6 0 13 6 0
13 6 1 13 6 1
13 7 0 13 7 0
13 7 1 13 7 1
13 8 0 13 8 0
13 8 1 13 8 1
13 9 0 13 9 0
13 9 1 13 9 1
13 11 0 13 10 0
13 11 1 13 10 1
13 12 0 13 11 0
13 12 1 13 11 1
13 13 0 13 13 0
13 13 1 13 13 1
13 14 0 13 14 0
13 14 1 13 14 1
13 15 0 13 15 0
13 15 1 13 15 1
13 1 0 13 1 0
13 1 1 13 1 1
13 2 0 13 2 0
13 2 1 13 2 1
13 3 1 13 3 1
13 4 0 13 4 0
13 4 1 13 4 1
13 6 0 13 6 0
13 6 1 13 6 1
13 7 0 13 7 0
13 7 1 13 7 1
13 8 0 13 8 0
13 8 1 13 8 1
13 9 0 13 9 0
13 9 1 13 9 1
13 11 0 13 10 0
13 11 1 13 10 1
13 12 0 13 11 0
13 12 1 13 11 1
13 13 0 13 13 0
13 13 1 13 13 1
13 14 0 13 14 0
13 14 1 13 14 1
13 15 0 13 15 0
13 15 1 13 15 1

- + - +
- - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + +

IO Block IE/REN Block
12 17 1 12 17 1
12 17 0 12 17 0
11 17 1 11 17 1
11 17 0 11 17 0
10 17 1 9 17 1
10 17 0 9 17 0
9 17 1 10 17 1
9 17 0 10 17 0
8 17 1 8 17 1
8 17 0 8 17 0
7 17 1 7 17 1
7 17 0 7 17 0
6 17 1 6 17 1
5 17 1 5 17 1
5 17 0 5 17 0
4 17 1 4 17 1
4 17 0 4 17 0
3 17 1 3 17 1
3 17 0 3 17 0
2 17 1 2 17 1
2 17 0 2 17 0
1 17 1 1 17 1
1 17 0 1 17 0
12 17 1 12 17 1
12 17 0 12 17 0
11 17 1 11 17 1
11 17 0 11 17 0
10 17 1 9 17 1
10 17 0 9 17 0
9 17 1 10 17 1
9 17 0 10 17 0
8 17 1 8 17 1
8 17 0 8 17 0
7 17 1 7 17 1
7 17 0 7 17 0
6 17 1 6 17 1
5 17 1 5 17 1
5 17 0 5 17 0
4 17 1 4 17 1
4 17 0 4 17 0
3 17 1 3 17 1
3 17 0 3 17 0
2 17 1 2 17 1
2 17 0 2 17 0
1 17 1 1 17 1
1 17 0 1 17 0

-

When an input pin pair is used as LVDS pair (IO standard -SB_LVDS_INPUT, bank 3 / left edge only), then the four bits -IoCtrl IE_0/IE_1 and IoCtrl REN_0/REN_1 are all set, as well -as the IoCtrl LVDS bit. +SB_LVDS_INPUT, bank 3 / left edge only), then the four bits +IoCtrl IE_0/IE_1 and IoCtrl REN_0/REN_1 are all set, as well +as the IoCtrl LVDS bit.

-In the iCE 8k devices the IoCtrl IE bits are active high. So an unused +In the iCE 8k devices the IoCtrl IE bits are active high. So an unused IO tile on an 8k chip has all bits cleared.
@@ -276,55 +293,51 @@ tile are used. In IceBox nomenclature such bits are called "extra bits".
The following table lists which pins / IO blocks may be used to drive -which global net, and what .extra statements in the IceBox ASCII file +which global net, and what .extra statements in the IceBox ASCII file format to represent the corresponding configuration bits:
-
- +
- - - - - - - - + + + + + + + +

Glb Net Pin
(HX1K-TQ144) IO Tile +
Block # IceBox Statement
0 93 13 8 1 .extra_bit 0 330 142
1 21 0 8 1 .extra_bit 0 331 142
2 128 7 17 0 .extra_bit 1 330 143
3 50 7 0 0 .extra_bit 1 331 143
4 20 0 9 0 .extra_bit 1 330 142
5 94 13 9 0 .extra_bit 1 331 142
6 49 6 0 1 .extra_bit 0 330 143
7 129 6 17 1 .extra_bit 0 331 143
0 93 13 8 1 .extra_bit 0 330 142
1 21 0 8 1 .extra_bit 0 331 142
2 128 7 17 0 .extra_bit 1 330 143
3 50 7 0 0 .extra_bit 1 331 143
4 20 0 9 0 .extra_bit 1 330 142
5 94 13 9 0 .extra_bit 1 331 142
6 49 6 0 1 .extra_bit 0 330 143
7 129 6 17 1 .extra_bit 0 331 143

-

Signals internal to the FPGA can also be routed to the global nets. This is done by routing the signal -to the fabout net on an IO tile. The same set of I/O tiles is used for this, but in this +to the fabout net on an IO tile. The same set of I/O tiles is used for this, but in this case each of the I/O tiles corresponds to a different global net:
-
- +
- - - - - - - - + + + + + + + + - - - - - - - - + + + + + + + +

Glb Net 0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7

IO Tile 7 0 7 17 13 9 0 9 6 17 6 0 0 8 13 8
7 0 7 17 13 9 0 9 6 17 6 0 0 8 13 8

-
-
+

Column Buffer Control Bits
@@ -344,147 +357,142 @@ IO columns.
Warmboot

-The SB_WARMBOOT primitive in iCE40 FPGAs has three inputs and no outputs. The three inputs of that cell -are driven by the fabout signal from three IO tiles. In HX1K chips the tiles connected to the -SB_WARMBOOT primitive are: +The SB_WARMBOOT primitive in iCE40 FPGAs has three inputs and no outputs. The three inputs of that cell +are driven by the fabout signal from three IO tiles. In HX1K chips the tiles connected to the +SB_WARMBOOT primitive are:
-
- +
- - - + + +

Warmboot Pin IO Tile
BOOT 12 0
S0 13 1
S1 13 2
BOOT 12 0
S0 13 1
S1 13 2

-

PLL Cores

-The PLL primitives in iCE40 FPGAs are configured using the PLLCONFIG_* +The PLL primitives in iCE40 FPGAs are configured using the PLLCONFIG_* bits in the IO tiles. The configuration for a single PLL cell is spread out over many IO tiles. For example, the PLL cell in the 1K chip are configured as follows (bits listed from LSB to MSB):
-
-
+ +
- +
- - - + + - - - + + - - - - + - - + - + - + -

IO Tile Config Bit SB_PLL40_* Parameter
0 3 PLLCONFIG_5 Select PLL Type:
+
0 3 PLLCONFIG_5 Select PLL Type:
000 = DISABLED
010 = SB_PLL40_PAD
100 = SB_PLL40_2_PAD
110 = SB_PLL40_2F_PAD
011 = SB_PLL40_CORE
111 = SB_PLL40_2F_CORE
0 5 PLLCONFIG_1
0 5 PLLCONFIG_3
0 5 PLLCONFIG_1
0 5 PLLCONFIG_3
0 5 PLLCONFIG_5 FEEDBACK_PATH
+
0 5 PLLCONFIG_5 FEEDBACK_PATH
000 = "DELAY"
001 = "SIMPLE"
010 = "PHASE_AND_DELAY"
110 = "EXTERNAL"
0 2 PLLCONFIG_9
0 3 PLLCONFIG_1
0 2 PLLCONFIG_9
0 3 PLLCONFIG_1
0 4 PLLCONFIG_4 DELAY_ADJUSTMENT_MODE_FEEDBACK
+
0 4 PLLCONFIG_4 DELAY_ADJUSTMENT_MODE_FEEDBACK
0 = "FIXED"
1 = "DYNAMIC"
0 4 PLLCONFIG_9 DELAY_ADJUSTMENT_MODE_RELATIVE
+
0 4 PLLCONFIG_9 DELAY_ADJUSTMENT_MODE_RELATIVE
0 = "FIXED"
1 = "DYNAMIC"
0 3 PLLCONFIG_6 PLLOUT_SELECT PLLOUT_SELECT_PORTA
+
0 3 PLLCONFIG_6 PLLOUT_SELECT
PLLOUT_SELECT_PORTA
00 = "GENCLK"
01 = "GENCLK_HALF"
10 = "SHIFTREG_90deg"
11 = "SHIFTREG_0deg"
0 3 PLLCONFIG_7
0 3 PLLCONFIG_7
0 3 PLLCONFIG_2 PLLOUT_SELECT_PORTB
+
0 3 PLLCONFIG_2 PLLOUT_SELECT_PORTB
00 = "GENCLK"
01 = "GENCLK_HALF"
10 = "SHIFTREG_90deg"
11 = "SHIFTREG_0deg"
0 3 PLLCONFIG_3
0 3 PLLCONFIG_3
0 3 PLLCONFIG_4 SHIFTREG_DIV_MODE
0 3 PLLCONFIG_4 SHIFTREG_DIV_MODE
0 3 PLLCONFIG_8 TEST_MODE
0 3 PLLCONFIG_8 TEST_MODE
+
- +
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

IO Tile Config Bit SB_PLL40_* Parameter
0 3 PLLCONFIG_9 FDA_FEEDBACK
0 4 PLLCONFIG_1
0 4 PLLCONFIG_2
0 4 PLLCONFIG_3
0 5 PLLCONFIG_5 FDA_RELATIVE
0 4 PLLCONFIG_6
0 4 PLLCONFIG_7
0 4 PLLCONFIG_8
0 1 PLLCONFIG_1 DIVR
0 1 PLLCONFIG_2
0 1 PLLCONFIG_3
0 1 PLLCONFIG_4
0 1 PLLCONFIG_5 DIVF
0 1 PLLCONFIG_6
0 1 PLLCONFIG_7
0 1 PLLCONFIG_8
0 1 PLLCONFIG_9
0 2 PLLCONFIG_1
0 2 PLLCONFIG_2
0 2 PLLCONFIG_3 DIVQ
0 2 PLLCONFIG_4
0 2 PLLCONFIG_5
0 2 PLLCONFIG_6 FILTER_RANGE
0 2 PLLCONFIG_7
0 2 PLLCONFIG_8
0 3 PLLCONFIG_9 FDA_FEEDBACK
0 4 PLLCONFIG_1
0 4 PLLCONFIG_2
0 4 PLLCONFIG_3
0 5 PLLCONFIG_5 FDA_RELATIVE
0 4 PLLCONFIG_6
0 4 PLLCONFIG_7
0 4 PLLCONFIG_8
0 1 PLLCONFIG_1 DIVR
0 1 PLLCONFIG_2
0 1 PLLCONFIG_3
0 1 PLLCONFIG_4
0 1 PLLCONFIG_5 DIVF
0 1 PLLCONFIG_6
0 1 PLLCONFIG_7
0 1 PLLCONFIG_8
0 1 PLLCONFIG_9
0 2 PLLCONFIG_1
0 2 PLLCONFIG_2
0 2 PLLCONFIG_3 DIVQ
0 2 PLLCONFIG_4
0 2 PLLCONFIG_5
0 2 PLLCONFIG_6 FILTER_RANGE
0 2 PLLCONFIG_7
0 2 PLLCONFIG_8

-

-The PLL inputs are routed to the PLL via the fabout signal from various IO tiles. The non-clock -PLL outputs are routed via otherwise unused neigh_op_* signals in fabric corners. For example in case +The PLL inputs are routed to the PLL via the fabout signal from various IO tiles. The non-clock +PLL outputs are routed via otherwise unused neigh_op_* signals in fabric corners. For example in case of the 1k chip:
-
- +
- - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + +

Tile Net-Segment SB_PLL40_* Port Name
0 1 fabout REFERENCECLK
0 2 fabout EXTFEEDBACK
0 4 fabout DYNAMICDELAY
0 5 fabout
0 6 fabout
0 10 fabout
0 11 fabout
0 12 fabout
0 13 fabout
0 14 fabout
1 1 neigh_op_bnl_1 LOCK
1 0 fabout BYPASS
2 0 fabout RESETB
5 0 fabout LATCHINPUTVALUE
12 1 neigh_op_bnl_1 SDO
4 0 fabout SDI
5 0 fabout SCLK
0 1 fabout REFERENCECLK
0 2 fabout EXTFEEDBACK
0 4 fabout DYNAMICDELAY
0 5 fabout
0 6 fabout
0 10 fabout
0 11 fabout
0 12 fabout
0 13 fabout
0 14 fabout
1 1 neigh_op_bnl_1 LOCK
1 0 fabout BYPASS
2 0 fabout RESETB
5 0 fabout LATCHINPUTVALUE
12 1 neigh_op_bnl_1 SDO
4 0 fabout SDI
5 0 fabout SCLK

-

The PLL clock outputs are fed directly into the input path of certain IO tiles. @@ -494,3 +502,4 @@ PIOs can only be used as output Pins by the FPGA fabric when the PLL ports are being used.
+ diff --git a/docs/logic_tile.html b/docs/logic_tile.html index 6404a80..67524bb 100644 --- a/docs/logic_tile.html +++ b/docs/logic_tile.html @@ -1,4 +1,18 @@ + + + Project IceStorm – LOGIC Tile Documentation +
Project IceStorm – LOGIC Tile Documentation

@@ -15,9 +29,9 @@ The span-4 and span-12 wires are the main interconnect resource in

-The bits marked routing in the bitstream do enable switches (transfer gates) that can +The bits marked routing in the bitstream do enable switches (transfer gates) that can be used to connect wire segments bidirectionally to each other in order to create larger -segments. The bits marked buffer in the bitstream enable tristate buffers that drive +segments. The bits marked buffer in the bitstream enable tristate buffers that drive the signal in one direction from one wire to another. Both types of bits exist for routing between span-wires. See the auto generated documentation for the LOGIC Tile configuration bits for details.
@@ -28,21 +42,21 @@ Only directional tristate buffers are used to route signals between the span-wir
Span-4 Horizontal
-
+

The image on the right shows the horizontal span-4 wires of a logic or ram cell (click to enlarge).

-On the left side of the cell there are 48 connections named sp4_h_l_0 to sp4_h_l_47. The lower 36 of those -wires are connected to sp4_h_r_12 to sp4_h_r_47 on the right side of the cell. (IceStorm normalizes this -wire names to sp4_h_r_0 to sp4_h_r_35. Note: the Lattice tools use a different normalization scheme +On the left side of the cell there are 48 connections named sp4_h_l_0 to sp4_h_l_47. The lower 36 of those +wires are connected to sp4_h_r_12 to sp4_h_r_47 on the right side of the cell. (IceStorm normalizes this +wire names to sp4_h_r_0 to sp4_h_r_35. Note: the Lattice tools use a different normalization scheme for this wire names.) The wires connecting the left and right horizontal span-4 ports are pairwise crossed-out.

-The wires sp4_h_l_36 to sp4_h_l_47 terminate in the cell, so do the wires sp4_h_r_0 to sp4_h_r_11. +The wires sp4_h_l_36 to sp4_h_l_47 terminate in the cell, so do the wires sp4_h_r_0 to sp4_h_r_11.

@@ -51,55 +65,51 @@ both ends of the wire.

-For example, the wire sp4_h_r_0 in cell (x, y) has the following names: +For example, the wire sp4_h_r_0 in cell (x, y) has the following names:
-
- +
- - - - - + + + + +

Cell Coordinates sp4_h_l_* wire name sp4_h_r_* wire name
x, y - sp4_h_r_0
x+1, y sp4_h_l_0 sp4_h_r_13
x+2, y sp4_h_l_13 sp4_h_r_24
x+3, y sp4_h_l_24 sp4_h_r_37
x+4, y sp4_h_l_37 -
x, y - sp4_h_r_0
x+1, y sp4_h_l_0 sp4_h_r_13
x+2, y sp4_h_l_13 sp4_h_r_24
x+3, y sp4_h_l_24 sp4_h_r_37
x+4, y sp4_h_l_37 -

-

Span-4 Vertical
-
+

The image on the right shows the vertical span-4 wires of a logic or ram cell (click to enlarge).

-Similar to the horizontal span-4 wires there are 48 connections on the top (sp4_v_t_0 to sp4_v_t_47) and -48 connections on the bottom (sp4_v_b_0 to sp4_v_b_47). The wires sp4_v_t_0 to sp4_v_t_35 -are connected to sp4_v_b_12 to sp4_v_b_47 (with pairwise crossing out). Wire names are normalized -to sp4_v_b_12 to sp4_v_b_47. +Similar to the horizontal span-4 wires there are 48 connections on the top (sp4_v_t_0 to sp4_v_t_47) and +48 connections on the bottom (sp4_v_b_0 to sp4_v_b_47). The wires sp4_v_t_0 to sp4_v_t_35 +are connected to sp4_v_b_12 to sp4_v_b_47 (with pairwise crossing out). Wire names are normalized +to sp4_v_b_12 to sp4_v_b_47.

-But in addition to that, each cell also has access to sp4_v_b_0 to sp4_v_b_47 of its right neighbour. -This are the wires sp4_r_v_b_0 to sp4_r_v_b_47. So over all a single vertical span-4 wire -connects 9 cells. For example, the wire sp4_v_b_0 in cell (x, y) has the following names: +But in addition to that, each cell also has access to sp4_v_b_0 to sp4_v_b_47 of its right neighbour. +This are the wires sp4_r_v_b_0 to sp4_r_v_b_47. So over all a single vertical span-4 wire +connects 9 cells. For example, the wire sp4_v_b_0 in cell (x, y) has the following names:
-
- +
- - - - - - - - - + + + + + + + + +

Cell Coordinates sp4_v_t_* wire name sp4_v_b_* wire name sp4_r_v_b_* wire name
x, y - sp4_v_b_0 -
x, y-1 sp4_v_t_0 sp4_v_b_13 -
x, y-2 sp4_v_t_13 sp4_v_b_24 -
x, y-3 sp4_v_t_24 sp4_v_b_37 -
x, y-4 sp4_v_t_37 - -
x-1, y - - sp4_r_v_b_0
x-1, y-1 - - sp4_r_v_b_13
x-1, y-2 - - sp4_r_v_b_24
x-1, y-3 - - sp4_r_v_b_37
x, y - sp4_v_b_0 -
x, y-1 sp4_v_t_0 sp4_v_b_13 -
x, y-2 sp4_v_t_13 sp4_v_b_24 -
x, y-3 sp4_v_t_24 sp4_v_b_37 -
x, y-4 sp4_v_t_37 - -
x-1, y - - sp4_r_v_b_0
x-1, y-1 - - sp4_r_v_b_13
x-1, y-2 - - sp4_r_v_b_24
x-1, y-3 - - sp4_r_v_b_37

-

Span-12 Horizontal and Vertical
@@ -108,21 +118,21 @@ Similar to the span-4 wires there are also longer horizontal and vertical span-1

-There are 24 connections sp12_v_t_0 to sp12_v_t_23 on the top of the -cell and 24 connections sp12_v_b_0 to sp12_v_b_23 on the bottom of the -cell. The wires sp12_v_t_0 to sp12_v_t_21 are connected to -sp12_v_b_2 to sp12_v_b_23 (with pairwise crossing out). The connections -sp12_v_b_0, sp12_v_b_1, sp12_v_t_22, and sp12_v_t_23 -terminate in the cell. Wire names are normalized to sp12_v_b_2 to sp12_v_b_23. +There are 24 connections sp12_v_t_0 to sp12_v_t_23 on the top of the +cell and 24 connections sp12_v_b_0 to sp12_v_b_23 on the bottom of the +cell. The wires sp12_v_t_0 to sp12_v_t_21 are connected to +sp12_v_b_2 to sp12_v_b_23 (with pairwise crossing out). The connections +sp12_v_b_0, sp12_v_b_1, sp12_v_t_22, and sp12_v_t_23 +terminate in the cell. Wire names are normalized to sp12_v_b_2 to sp12_v_b_23.

-There are also 24 connections sp12_h_l_0 to sp12_h_l_23 on the left of the -cell and 24 connections sp12_h_r_0 to sp12_h_r_23 on the right of the -cell. The wires sp12_h_l_0 to sp12_h_l_21 are connected to -sp12_h_r_2 to sp12_h_r_23 (with pairwise crossing out). The connections -sp12_h_r_0, sp12_h_r_1, sp12_h_l_22, and sp12_h_l_23 -terminate in the cell. Wire names are normalized to sp12_v_r_2 to sp12_h_r_23. +There are also 24 connections sp12_h_l_0 to sp12_h_l_23 on the left of the +cell and 24 connections sp12_h_r_0 to sp12_h_r_23 on the right of the +cell. The wires sp12_h_l_0 to sp12_h_l_21 are connected to +sp12_h_r_2 to sp12_h_r_23 (with pairwise crossing out). The connections +sp12_h_r_0, sp12_h_r_1, sp12_h_l_22, and sp12_h_l_23 +terminate in the cell. Wire names are normalized to sp12_v_r_2 to sp12_h_r_23.

Local Tracks
@@ -135,7 +145,7 @@ signals from the local tracks can be routed to the logic cell inputs.
Each logic tile has 32 local tracks. They are organized in 4 groups of 8 wires each: -local_g0_0 to local_g3_7. +local_g0_0 to local_g3_7.

@@ -146,71 +156,59 @@ mix of 16 signals for each local track.
The buffer driving the local track has 5 configuration bits. One enable bit and 4 bits that select -the input wire. For example for local_g0_0 (copy&paste from the bitstream doku): +the input wire. For example for local_g0_0 (copy&paste from the bitstream doku):
-
- - - - - - +
B0[14] B1[14] B1[15] B1[16] B1[17]
+ - - - - - - - - - - - - - - - - -
B0[14] B1[14] B1[15] B1[16] B1[17] Function Source-Net Destination-Net
0 0 0 0 1 buffer sp4_r_v_b_24 local_g0_0
0 0 0 1 1 buffer sp12_h_r_8 local_g0_0
0 0 1 0 1 buffer neigh_op_bot_0 local_g0_0
0 0 1 1 1 buffer sp4_v_b_16 local_g0_0
0 1 0 0 1 buffer sp4_r_v_b_35 local_g0_0
0 1 0 1 1 buffer sp12_h_r_16 local_g0_0
0 1 1 0 1 buffer neigh_op_top_0 local_g0_0
0 1 1 1 1 buffer sp4_h_r_0 local_g0_0
1 0 0 0 1 buffer lutff_0/out local_g0_0
1 0 0 1 1 buffer sp4_v_b_0 local_g0_0
1 0 1 0 1 buffer neigh_op_lft_0 local_g0_0
1 0 1 1 1 buffer sp4_h_r_8 local_g0_0
1 1 0 0 1 buffer neigh_op_bnr_0 local_g0_0
1 1 0 1 1 buffer sp4_v_b_8 local_g0_0
1 1 1 0 1 buffer sp12_h_r_0 local_g0_0
1 1 1 1 1 buffer sp4_h_r_16 local_g0_0
-
+
0 0 0 0 1 buffer sp4_r_v_b_24 local_g0_0
0 0 0 1 1 buffer sp12_h_r_8 local_g0_0
0 0 1 0 1 buffer neigh_op_bot_0 local_g0_0
0 0 1 1 1 buffer sp4_v_b_16 local_g0_0
0 1 0 0 1 buffer sp4_r_v_b_35 local_g0_0
0 1 0 1 1 buffer sp12_h_r_16 local_g0_0
0 1 1 0 1 buffer neigh_op_top_0 local_g0_0
0 1 1 1 1 buffer sp4_h_r_0 local_g0_0
1 0 0 0 1 buffer lutff_0/out local_g0_0
1 0 0 1 1 buffer sp4_v_b_0 local_g0_0
1 0 1 0 1 buffer neigh_op_lft_0 local_g0_0
1 0 1 1 1 buffer sp4_h_r_8 local_g0_0
1 1 0 0 1 buffer neigh_op_bnr_0 local_g0_0
1 1 0 1 1 buffer sp4_v_b_8 local_g0_0
1 1 1 0 1 buffer sp12_h_r_0 local_g0_0
1 1 1 1 1 buffer sp4_h_r_16 local_g0_0

Then the signals on the local tracks can be routed to the input pins of the logic cells. Like before, not every local track can be routed to every logic cell input pin. Instead there is a different mix -of 16 local track for each logic cell input. For example for lutff_0/in_0: +of 16 local track for each logic cell input. For example for lutff_0/in_0:

- - - - - - +
B0[26] B1[26] B1[27] B1[28] B1[29]
+ - - - - - - - - - - - - - - - - -
B0[26] B1[26] B1[27] B1[28] B1[29] Function Source-Net Destination-Net
0 0 0 0 1 buffer local_g0_0 lutff_0/in_0
0 0 0 1 1 buffer local_g2_0 lutff_0/in_0
0 0 1 0 1 buffer local_g1_1 lutff_0/in_0
0 0 1 1 1 buffer local_g3_1 lutff_0/in_0
0 1 0 0 1 buffer local_g0_2 lutff_0/in_0
0 1 0 1 1 buffer local_g2_2 lutff_0/in_0
0 1 1 0 1 buffer local_g1_3 lutff_0/in_0
0 1 1 1 1 buffer local_g3_3 lutff_0/in_0
1 0 0 0 1 buffer local_g0_4 lutff_0/in_0
1 0 0 1 1 buffer local_g2_4 lutff_0/in_0
1 0 1 0 1 buffer local_g1_5 lutff_0/in_0
1 0 1 1 1 buffer local_g3_5 lutff_0/in_0
1 1 0 0 1 buffer local_g0_6 lutff_0/in_0
1 1 0 1 1 buffer local_g2_6 lutff_0/in_0
1 1 1 0 1 buffer local_g1_7 lutff_0/in_0
1 1 1 1 1 buffer local_g3_7 lutff_0/in_0
-

B0[26]	B1[26]	B1[27]	B1[28]	B1[29]	Function	Source-Net	Destination-Net
0	0	0	0	1	buffer	`local_g0_0`	`lutff_0/in_0`
0	0	0	1	1	buffer	`local_g2_0`	`lutff_0/in_0`
0	0	1	0	1	buffer	`local_g1_1`	`lutff_0/in_0`
0	0	1	1	1	buffer	`local_g3_1`	`lutff_0/in_0`
0	1	0	0	1	buffer	`local_g0_2`	`lutff_0/in_0`
0	1	0	1	1	buffer	`local_g2_2`	`lutff_0/in_0`
0	1	1	0	1	buffer	`local_g1_3`	`lutff_0/in_0`
0	1	1	1	1	buffer	`local_g3_3`	`lutff_0/in_0`
1	0	0	0	1	buffer	`local_g0_4`	`lutff_0/in_0`
1	0	0	1	1	buffer	`local_g2_4`	`lutff_0/in_0`
1	0	1	0	1	buffer	`local_g1_5`	`lutff_0/in_0`
1	0	1	1	1	buffer	`local_g3_5`	`lutff_0/in_0`
1	1	0	0	1	buffer	`local_g0_6`	`lutff_0/in_0`
1	1	0	1	1	buffer	`local_g2_6`	`lutff_0/in_0`
1	1	1	0	1	buffer	`local_g1_7`	`lutff_0/in_0`
1	1	1	1	1	buffer	`local_g3_7`	`lutff_0/in_0`

- -

-The 8 global nets on the iCE40 can be routed to the local track via the glb2local_0 to glb2local_3 +00001bufferlocal_g0_0lutff_0/in_0 +00011bufferlocal_g2_0lutff_0/in_0 +00101bufferlocal_g1_1lutff_0/in_0 +00111bufferlocal_g3_1lutff_0/in_0 +01001bufferlocal_g0_2lutff_0/in_0 +01011bufferlocal_g2_2lutff_0/in_0 +01101bufferlocal_g1_3lutff_0/in_0 +01111bufferlocal_g3_3lutff_0/in_0 +10001bufferlocal_g0_4lutff_0/in_0 +10011bufferlocal_g2_4lutff_0/in_0 +10101bufferlocal_g1_5lutff_0/in_0 +10111bufferlocal_g3_5lutff_0/in_0 +11001bufferlocal_g0_6lutff_0/in_0 +11011bufferlocal_g2_6lutff_0/in_0 +11101bufferlocal_g1_7lutff_0/in_0 +11111bufferlocal_g3_7lutff_0/in_0 + + +

+The 8 global nets on the iCE40 can be routed to the local track via the glb2local_0 to glb2local_3 nets using a similar two-stage process. The logic block clock-enable and set-reset inputs can be driven directly from one of 4 global nets or from one of 4 local tracks. The logic block clock input can be driven from any of the global nets and from a few local tracks. See the bitstream documentation for details. @@ -227,97 +225,93 @@ or asynchronous exist for each logic cell individually.

-Each LUT i has four input wires lutff_i/in_0 to lutff_i/in_3. Input -lutff_i/in_3 can be configured to be driven by the carry output of the previous logic cell, -or by carry_in_mux in case of i=0. Input lutff_i/in_2 can be configured to +Each LUT i has four input wires lutff_i/in_0 to lutff_i/in_3. Input +lutff_i/in_3 can be configured to be driven by the carry output of the previous logic cell, +or by carry_in_mux in case of i=0. Input lutff_i/in_2 can be configured to be driven by the output of the previous LUT for i>0. The LUT uses its 4 input signals to -calculate lutff_i/out. +calculate lutff_i/out.

-The carry unit calculates lutff_i/cout = lutff_i/in_1 + lutff_i/in_2 + lutff_(i-1)/cout > 1. In case of i=0, carry_in_mux is used as third input. carry_in_mux can be configured to be constant 0, 1 or the lutff_7/cout signal from the logic tile below. +The carry unit calculates lutff_i/cout = lutff_i/in_1 + lutff_i/in_2 + lutff_(i-1)/cout > 1. In case of i=0, carry_in_mux is used as third input. carry_in_mux can be configured to be constant 0, 1 or the lutff_7/cout signal from the logic tile below.

Part of the functionality described above is documented as part of the routing -bitstream documentation (see the buffers for lutff_ inputs). The NegClk -bit switches all 8 FFs in the tile to negative edge mode. The CarryInSet -bit drives the carry_in_mux high (it defaults to low when not driven via the buffer from -carry_in). +bitstream documentation (see the buffers for lutff_ inputs). The NegClk +bit switches all 8 FFs in the tile to negative edge mode. The CarryInSet +bit drives the carry_in_mux high (it defaults to low when not driven via the buffer from +carry_in).

-The remaining functions of the logic cell are configured via the LC_i bits. This +The remaining functions of the logic cell are configured via the LC_i bits. This are 20 bit per logic cell. We have arbitrarily labeled those bits as follows:

- +
- - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + +

Label LC_0 LC_1 LC_2 LC_3 LC_4 LC_5 LC_6 LC_7
LC_i[0] B0[36] B2[36] B4[36] B6[36] B8[36] B10[36] B12[36] B14[36]
LC_i[1] B0[37] B2[37] B4[37] B6[37] B8[37] B10[37] B12[37] B14[37]
LC_i[2] B0[38] B2[38] B4[38] B6[38] B8[38] B10[38] B12[38] B14[38]
LC_i[3] B0[39] B2[39] B4[39] B6[39] B8[39] B10[39] B12[39] B14[39]
LC_i[4] B0[40] B2[40] B4[40] B6[40] B8[40] B10[40] B12[40] B14[40]
LC_i[5] B0[41] B2[41] B4[41] B6[41] B8[41] B10[41] B12[41] B14[41]
LC_i[6] B0[42] B2[42] B4[42] B6[42] B8[42] B10[42] B12[42] B14[42]
LC_i[7] B0[43] B2[43] B4[43] B6[43] B8[43] B10[43] B12[43] B14[43]
LC_i[8] B0[44] B2[44] B4[44] B6[44] B8[44] B10[44] B12[44] B14[44]
LC_i[9] B0[45] B2[45] B4[45] B6[45] B8[45] B10[45] B12[45] B14[45]
LC_i[10] B1[36] B3[36] B5[36] B7[36] B9[36] B11[36] B13[36] B15[36]
LC_i[11] B1[37] B3[37] B5[37] B7[37] B9[37] B11[37] B13[37] B15[37]
LC_i[12] B1[38] B3[38] B5[38] B7[38] B9[38] B11[38] B13[38] B15[38]
LC_i[13] B1[39] B3[39] B5[39] B7[39] B9[39] B11[39] B13[39] B15[39]
LC_i[14] B1[40] B3[40] B5[40] B7[40] B9[40] B11[40] B13[40] B15[40]
LC_i[15] B1[41] B3[41] B5[41] B7[41] B9[41] B11[41] B13[41] B15[41]
LC_i[16] B1[42] B3[42] B5[42] B7[42] B9[42] B11[42] B13[42] B15[42]
LC_i[17] B1[43] B3[43] B5[43] B7[43] B9[43] B11[43] B13[43] B15[43]
LC_i[18] B1[44] B3[44] B5[44] B7[44] B9[44] B11[44] B13[44] B15[44]
LC_i[19] B1[45] B3[45] B5[45] B7[45] B9[45] B11[45] B13[45] B15[45]
LC_i[0] B0[36] B2[36] B4[36] B6[36] B8[36] B10[36] B12[36] B14[36]
LC_i[1] B0[37] B2[37] B4[37] B6[37] B8[37] B10[37] B12[37] B14[37]
LC_i[2] B0[38] B2[38] B4[38] B6[38] B8[38] B10[38] B12[38] B14[38]
LC_i[3] B0[39] B2[39] B4[39] B6[39] B8[39] B10[39] B12[39] B14[39]
LC_i[4] B0[40] B2[40] B4[40] B6[40] B8[40] B10[40] B12[40] B14[40]
LC_i[5] B0[41] B2[41] B4[41] B6[41] B8[41] B10[41] B12[41] B14[41]
LC_i[6] B0[42] B2[42] B4[42] B6[42] B8[42] B10[42] B12[42] B14[42]
LC_i[7] B0[43] B2[43] B4[43] B6[43] B8[43] B10[43] B12[43] B14[43]
LC_i[8] B0[44] B2[44] B4[44] B6[44] B8[44] B10[44] B12[44] B14[44]
LC_i[9] B0[45] B2[45] B4[45] B6[45] B8[45] B10[45] B12[45] B14[45]
LC_i[10] B1[36] B3[36] B5[36] B7[36] B9[36] B11[36] B13[36] B15[36]
LC_i[11] B1[37] B3[37] B5[37] B7[37] B9[37] B11[37] B13[37] B15[37]
LC_i[12] B1[38] B3[38] B5[38] B7[38] B9[38] B11[38] B13[38] B15[38]
LC_i[13] B1[39] B3[39] B5[39] B7[39] B9[39] B11[39] B13[39] B15[39]
LC_i[14] B1[40] B3[40] B5[40] B7[40] B9[40] B11[40] B13[40] B15[40]
LC_i[15] B1[41] B3[41] B5[41] B7[41] B9[41] B11[41] B13[41] B15[41]
LC_i[16] B1[42] B3[42] B5[42] B7[42] B9[42] B11[42] B13[42] B15[42]
LC_i[17] B1[43] B3[43] B5[43] B7[43] B9[43] B11[43] B13[43] B15[43]
LC_i[18] B1[44] B3[44] B5[44] B7[44] B9[44] B11[44] B13[44] B15[44]
LC_i[19] B1[45] B3[45] B5[45] B7[45] B9[45] B11[45] B13[45] B15[45]

-

Label	LC_0	LC_1	LC_2	LC_3	LC_4	LC_5	LC_6	LC_7
LC_i[0]	B0[36]	B2[36]	B4[36]	B6[36]	B8[36]	B10[36]	B12[36]	B14[36]
LC_i[1]	B0[37]	B2[37]	B4[37]	B6[37]	B8[37]	B10[37]	B12[37]	B14[37]
LC_i[2]	B0[38]	B2[38]	B4[38]	B6[38]	B8[38]	B10[38]	B12[38]	B14[38]
LC_i[3]	B0[39]	B2[39]	B4[39]	B6[39]	B8[39]	B10[39]	B12[39]	B14[39]
LC_i[4]	B0[40]	B2[40]	B4[40]	B6[40]	B8[40]	B10[40]	B12[40]	B14[40]
LC_i[5]	B0[41]	B2[41]	B4[41]	B6[41]	B8[41]	B10[41]	B12[41]	B14[41]
LC_i[6]	B0[42]	B2[42]	B4[42]	B6[42]	B8[42]	B10[42]	B12[42]	B14[42]
LC_i[7]	B0[43]	B2[43]	B4[43]	B6[43]	B8[43]	B10[43]	B12[43]	B14[43]
LC_i[8]	B0[44]	B2[44]	B4[44]	B6[44]	B8[44]	B10[44]	B12[44]	B14[44]
LC_i[9]	B0[45]	B2[45]	B4[45]	B6[45]	B8[45]	B10[45]	B12[45]	B14[45]
LC_i[10]	B1[36]	B3[36]	B5[36]	B7[36]	B9[36]	B11[36]	B13[36]	B15[36]
LC_i[11]	B1[37]	B3[37]	B5[37]	B7[37]	B9[37]	B11[37]	B13[37]	B15[37]
LC_i[12]	B1[38]	B3[38]	B5[38]	B7[38]	B9[38]	B11[38]	B13[38]	B15[38]
LC_i[13]	B1[39]	B3[39]	B5[39]	B7[39]	B9[39]	B11[39]	B13[39]	B15[39]
LC_i[14]	B1[40]	B3[40]	B5[40]	B7[40]	B9[40]	B11[40]	B13[40]	B15[40]
LC_i[15]	B1[41]	B3[41]	B5[41]	B7[41]	B9[41]	B11[41]	B13[41]	B15[41]
LC_i[16]	B1[42]	B3[42]	B5[42]	B7[42]	B9[42]	B11[42]	B13[42]	B15[42]
LC_i[17]	B1[43]	B3[43]	B5[43]	B7[43]	B9[43]	B11[43]	B13[43]	B15[43]
LC_i[18]	B1[44]	B3[44]	B5[44]	B7[44]	B9[44]	B11[44]	B13[44]	B15[44]
LC_i[19]	B1[45]	B3[45]	B5[45]	B7[45]	B9[45]	B11[45]	B13[45]	B15[45]
LC_i[0]	B0[36]	B2[36]	B4[36]	B6[36]	B8[36]	B10[36]	B12[36]	B14[36]
LC_i[1]	B0[37]	B2[37]	B4[37]	B6[37]	B8[37]	B10[37]	B12[37]	B14[37]
LC_i[2]	B0[38]	B2[38]	B4[38]	B6[38]	B8[38]	B10[38]	B12[38]	B14[38]
LC_i[3]	B0[39]	B2[39]	B4[39]	B6[39]	B8[39]	B10[39]	B12[39]	B14[39]
LC_i[4]	B0[40]	B2[40]	B4[40]	B6[40]	B8[40]	B10[40]	B12[40]	B14[40]
LC_i[5]	B0[41]	B2[41]	B4[41]	B6[41]	B8[41]	B10[41]	B12[41]	B14[41]
LC_i[6]	B0[42]	B2[42]	B4[42]	B6[42]	B8[42]	B10[42]	B12[42]	B14[42]
LC_i[7]	B0[43]	B2[43]	B4[43]	B6[43]	B8[43]	B10[43]	B12[43]	B14[43]
LC_i[8]	B0[44]	B2[44]	B4[44]	B6[44]	B8[44]	B10[44]	B12[44]	B14[44]
LC_i[9]	B0[45]	B2[45]	B4[45]	B6[45]	B8[45]	B10[45]	B12[45]	B14[45]
LC_i[10]	B1[36]	B3[36]	B5[36]	B7[36]	B9[36]	B11[36]	B13[36]	B15[36]
LC_i[11]	B1[37]	B3[37]	B5[37]	B7[37]	B9[37]	B11[37]	B13[37]	B15[37]
LC_i[12]	B1[38]	B3[38]	B5[38]	B7[38]	B9[38]	B11[38]	B13[38]	B15[38]
LC_i[13]	B1[39]	B3[39]	B5[39]	B7[39]	B9[39]	B11[39]	B13[39]	B15[39]
LC_i[14]	B1[40]	B3[40]	B5[40]	B7[40]	B9[40]	B11[40]	B13[40]	B15[40]
LC_i[15]	B1[41]	B3[41]	B5[41]	B7[41]	B9[41]	B11[41]	B13[41]	B15[41]
LC_i[16]	B1[42]	B3[42]	B5[42]	B7[42]	B9[42]	B11[42]	B13[42]	B15[42]
LC_i[17]	B1[43]	B3[43]	B5[43]	B7[43]	B9[43]	B11[43]	B13[43]	B15[43]
LC_i[18]	B1[44]	B3[44]	B5[44]	B7[44]	B9[44]	B11[44]	B13[44]	B15[44]
LC_i[19]	B1[45]	B3[45]	B5[45]	B7[45]	B9[45]	B11[45]	B13[45]	B15[45]

-LC_i[8] is the CarryEnable bit. This bit must be set if the carry logic is used. +LC_i[8] is the CarryEnable bit. This bit must be set if the carry logic is used.

-LC_i[9] is the DffEnable bit. It enables the output flip-flop for the LUT. +LC_i[9] is the DffEnable bit. It enables the output flip-flop for the LUT.

-LC_i[18] is the Set_NoReset bit. When this bit is set then the set/reset signal will set, not reset the flip-flop. +LC_i[18] is the Set_NoReset bit. When this bit is set then the set/reset signal will set, not reset the flip-flop.

-LC_i[19] is the AsyncSetReset bit. When this bit is set then the set/reset signal is asynchronous to the clock. +LC_i[19] is the AsyncSetReset bit. When this bit is set then the set/reset signal is asynchronous to the clock.

The LUT implements the following truth table:

- +
- - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + +

in_3 in_2 in_1 in_0 out
0 0 0 0 LC_i[4]
0 0 0 1 LC_i[14]
0 0 1 0 LC_i[15]
0 0 1 1 LC_i[5]
0 1 0 0 LC_i[6]
0 1 0 1 LC_i[16]
0 1 1 0 LC_i[17]
0 1 1 1 LC_i[7]
1 0 0 0 LC_i[3]
1 0 0 1 LC_i[13]
1 0 1 0 LC_i[12]
1 0 1 1 LC_i[2]
1 1 0 0 LC_i[1]
1 1 0 1 LC_i[11]
1 1 1 0 LC_i[10]
1 1 1 1 LC_i[0]
0 0 0 0 LC_i[4]
0 0 0 1 LC_i[14]
0 0 1 0 LC_i[15]
0 0 1 1 LC_i[5]
0 1 0 0 LC_i[6]
0 1 0 1 LC_i[16]
0 1 1 0 LC_i[17]
0 1 1 1 LC_i[7]
1 0 0 0 LC_i[3]
1 0 0 1 LC_i[13]
1 0 1 0 LC_i[12]
1 0 1 1 LC_i[2]
1 1 0 0 LC_i[1]
1 1 0 1 LC_i[11]
1 1 1 0 LC_i[10]
1 1 1 1 LC_i[0]

-

in_3	in_2	in_1	in_0	out
0	0	0	0	`LC_i[4]`
0	0	0	1	`LC_i[14]`
0	0	1	0	`LC_i[15]`
0	0	1	1	`LC_i[5]`
0	1	0	0	`LC_i[6]`
0	1	0	1	`LC_i[16]`
0	1	1	0	`LC_i[17]`
0	1	1	1	`LC_i[7]`
1	0	0	0	`LC_i[3]`
1	0	0	1	`LC_i[13]`
1	0	1	0	`LC_i[12]`
1	0	1	1	`LC_i[2]`
1	1	0	0	`LC_i[1]`
1	1	0	1	`LC_i[11]`
1	1	1	0	`LC_i[10]`
1	1	1	1	`LC_i[0]`
0	0	0	0	LC_i[4]
0	0	0	1	LC_i[14]
0	0	1	0	LC_i[15]
0	0	1	1	LC_i[5]
0	1	0	0	LC_i[6]
0	1	0	1	LC_i[16]
0	1	1	0	LC_i[17]
0	1	1	1	LC_i[7]
1	0	0	0	LC_i[3]
1	0	0	1	LC_i[13]
1	0	1	0	LC_i[12]
1	0	1	1	LC_i[2]
1	1	0	0	LC_i[1]
1	1	0	1	LC_i[11]
1	1	1	0	LC_i[10]
1	1	1	1	LC_i[0]

LUT inputs that are not connected to anything are driven low. The set/reset @@ -325,3 +319,4 @@ signal is also driven low if not connected to any other driver, and the clock enable signal is driven high when left unconnected.

+ diff --git a/docs/ram_tile.html b/docs/ram_tile.html index 3121f57..73bda8d 100644 --- a/docs/ram_tile.html +++ b/docs/ram_tile.html @@ -1,4 +1,18 @@ + + + Project IceStorm – RAM Tile Documentation +

Project IceStorm – RAM Tile Documentation

@@ -21,75 +35,70 @@ tiles without logic cells in them. A pair or RAM tiles (odd and even y-coordinates) provides an interface to a block ram cell. Like with LOGIC tiles, signals entering the RAM tile have to be routed over local tracks to the block ram inputs. Tiles with odd y-coordinates are "bottom" RAM Tiles (RAMB Tiles), and tiles with even y-coordinates -are "top" RAM Tiles (RAMT Tiles). Each pair of RAMB/RAMT tiles implements a SB_RAM40_4K cell. The +are "top" RAM Tiles (RAMT Tiles). Each pair of RAMB/RAMT tiles implements a SB_RAM40_4K cell. The cell ports are spread out over the two tiles as follows:

- +
- - - - - - - - - - - + + + + + + + + + + +

SB_RAM40_4K RAMB Tile RAMT Tile
RDATA[15:0] RDATA[7:0] RDATA[15:8]
RADDR[10:0] - RADDR[10:0]
WADDR[10:0] WADDR[10:0] -
MASK[15:0] MASK[7:0] MASK[15:8]
WDATA[15:0] WDATA[7:0] WDATA[15:8]
RCLKE - RCLKE
RCLK - RCLK
RE - RE
WCLKE WCLKE -
WCLK WCLK -
WE WE -
RDATA[15:0] RDATA[7:0] RDATA[15:8]
RADDR[10:0] - RADDR[10:0]
WADDR[10:0] WADDR[10:0] -
MASK[15:0] MASK[7:0] MASK[15:8]
WDATA[15:0] WDATA[7:0] WDATA[15:8]
RCLKE - RCLKE
RCLK - RCLK
RE - RE
WCLKE WCLKE -
WCLK WCLK -
WE WE -

-

SB_RAM40_4K	RAMB Tile	RAMT Tile
`RDATA[15:0]`	`RDATA[7:0]`	`RDATA[15:8]`
`RADDR[10:0]`	`-`	`RADDR[10:0]`
`WADDR[10:0]`	`WADDR[10:0]`	`-`
`MASK[15:0]`	`MASK[7:0]`	`MASK[15:8]`
`WDATA[15:0]`	`WDATA[7:0]`	`WDATA[15:8]`
`RCLKE`	`-`	`RCLKE`
`RCLK`	`-`	`RCLK`
`RE`	`-`	`RE`
`WCLKE`	`WCLKE`	`-`
`WCLK`	`WCLK`	`-`
`WE`	`WE`	`-`
RDATA[15:0]	RDATA[7:0]	RDATA[15:8]
RADDR[10:0]	-	RADDR[10:0]
WADDR[10:0]	WADDR[10:0]	-
MASK[15:0]	MASK[7:0]	MASK[15:8]
WDATA[15:0]	WDATA[7:0]	WDATA[15:8]
RCLKE	-	RCLKE
RCLK	-	RCLK
RE	-	RE
WCLKE	WCLKE	-
WCLK	WCLK	-
WE	WE	-

-The configuration bit RamConfig PowerUp in the RAMB tile enables the memory. This bit -is active-low in 1k chips, i.e. an unused RAM block has only this bit set. Note that icebox_explain.py -will ignore all RAMB tiles that only have the RamConfig PowerUp bit set. +The configuration bit RamConfig PowerUp in the RAMB tile enables the memory. This bit +is active-low in 1k chips, i.e. an unused RAM block has only this bit set. Note that icebox_explain.py +will ignore all RAMB tiles that only have the RamConfig PowerUp bit set.

-In 8k chips the RamConfig PowerUp bit is active-high. So an unused RAM block has all bits cleared +In 8k chips the RamConfig PowerUp bit is active-high. So an unused RAM block has all bits cleared in the 8k config bitstream.

-The RamConfig CBIT_* bits in the RAMT tile configure the read/write width of the -memory. Those bits map to the SB_RAM40_4K cell parameters as follows: +The RamConfig CBIT_* bits in the RAMT tile configure the read/write width of the +memory. Those bits map to the SB_RAM40_4K cell parameters as follows:

- +
- - - - + + + +

SB_RAM40_4K RAMT Config Bit
WRITE_MODE[0] RamConfig CBIT_0
WRITE_MODE[1] RamConfig CBIT_1
READ_MODE[0] RamConfig CBIT_2
READ_MODE[1] RamConfig CBIT_3
WRITE_MODE[0] RamConfig CBIT_0
WRITE_MODE[1] RamConfig CBIT_1
READ_MODE[0] RamConfig CBIT_2
READ_MODE[1] RamConfig CBIT_3

-

SB_RAM40_4K	RAMT Config Bit
`WRITE_MODE[0]`	`RamConfig CBIT_0`
`WRITE_MODE[1]`	`RamConfig CBIT_1`
`READ_MODE[0]`	`RamConfig CBIT_2`
`READ_MODE[1]`	`RamConfig CBIT_3`
WRITE_MODE[0]	RamConfig CBIT_0
WRITE_MODE[1]	RamConfig CBIT_1
READ_MODE[0]	RamConfig CBIT_2
READ_MODE[1]	RamConfig CBIT_3

The read/write mode selects the width of the read/write port:

- +

MODE DATA Width Used WDATA/RDATA Bits

0 16 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0

1 8 14, 12, 10, 8, 6, 4, 2, 0

2 4 13, 9, 5, 1

3 2 11, 3

-

MODE	DATA Width	Used WDATA/RDATA Bits
0	16	15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
1	8	14, 12, 10, 8, 6, 4, 2, 0
2	4	13, 9, 5, 1
3	2	11, 3

-The NegClk bit in the RAMB tile negates the polarity of the WCLK port, -and the NegClk bit in the RAMT tile negates the polarity of the RCLK port. +The NegClk bit in the RAMB tile negates the polarity of the WCLK port, +and the NegClk bit in the RAMT tile negates the polarity of the RCLK port.

A logic tile sends the output of its eight logic cells to its neighbour tiles. A RAM tile does the same thing -with the RDATA outputs. Each RAMB tile exports its RDATA[7:0] outputs and each RAMT tile -exports its RDATA[15:8] outputs via this mechanism. +with the RDATA outputs. Each RAMB tile exports its RDATA[7:0] outputs and each RAMT tile +exports its RDATA[15:8] outputs via this mechanism.

+ -- cgit v1.2.3