From 7b73086ade468f460ca7e00e69e07b2dc3ea5f8b Mon Sep 17 00:00:00 2001 From: Cotton Seed Date: Sat, 29 Aug 2015 12:53:18 -0400 Subject: Renamed wire_gbuf/in -> fabout in docs. --- docs/io_tile.html | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) (limited to 'docs') diff --git a/docs/io_tile.html b/docs/io_tile.html index 3cbc045..53ee497 100644 --- a/docs/io_tile.html +++ b/docs/io_tile.html @@ -72,7 +72,7 @@ is first routed to one of 16 local tracks in the IO tile and then from the local

-The io_global/latch signal is shared among all IO tiles on an edge of the chip and is driven by wire_gbuf/in +The io_global/latch signal is shared among all IO tiles on an edge of the chip and is driven by fabout from one dedicated IO tile on that edge. For the HX1K chips the tiles driving the io_global/latch signal are: (0, 7), (13, 10), (5, 0), and (8, 17)

@@ -297,7 +297,7 @@ format to represent the corresponding configuration bits:

Signals internal to the FPGA can also be routed to the global nets. This is done by routing the signal -to the wire_gbuf/in net on an IO tile. The same set of I/O tiles is used for this, but in this +to the fabout net on an IO tile. The same set of I/O tiles is used for this, but in this case each of the I/O tiles corresponds to a different global net:

@@ -345,7 +345,7 @@ IO columns.

The SB_WARMBOOT primitive in iCE40 FPGAs has three inputs and no outputs. The three inputs of that cell -are driven by the wire_gbuf/in signal from three IO tiles. In HX1K chips the tiles connected to the +are driven by the fabout signal from three IO tiles. In HX1K chips the tiles connected to the SB_WARMBOOT primitive are:

@@ -458,7 +458,7 @@ follows (bits listed from LSB to MSB):

-The PLL inputs are routed to the PLL via the wire_gbuf/in signal from various IO tiles. The non-clock +The PLL inputs are routed to the PLL via the fabout signal from various IO tiles. The non-clock PLL outputs are routed via otherwise unused neigh_op_* signals in fabric corners. For example in case of the 1k chip:

@@ -466,23 +466,23 @@ of the 1k chip:

- - - - - - - - - - + + + + + + + + + + - - - + + + - - + +
TileNet-SegmentSB_PLL40_* Port Name
0 1wire_gbuf/inREFERENCECLK
0 2wire_gbuf/inEXTFEEDBACK
0 4wire_gbuf/inDYNAMICDELAY
0 5wire_gbuf/in
0 6wire_gbuf/in
0 10wire_gbuf/in
0 11wire_gbuf/in
0 12wire_gbuf/in
0 13wire_gbuf/in
0 14wire_gbuf/in
0 1faboutREFERENCECLK
0 2faboutEXTFEEDBACK
0 4faboutDYNAMICDELAY
0 5fabout
0 6fabout
0 10fabout
0 11fabout
0 12fabout
0 13fabout
0 14fabout
1 1neigh_op_bnl_1LOCK
1 0wire_gbuf/inBYPASS
2 0wire_gbuf/inRESETB
5 0wire_gbuf/inLATCHINPUTVALUE
1 0faboutBYPASS
2 0faboutRESETB
5 0faboutLATCHINPUTVALUE
12 1neigh_op_bnl_1SDO
4 0wire_gbuf/inSDI
5 0wire_gbuf/inSCLK
4 0faboutSDI
5 0faboutSCLK

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