From db87f484660dab833ea534e7d37c9c55417d5239 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 24 Nov 2017 15:50:16 +0000 Subject: Documented I2C/SPI/LEDDA_IP --- docs/ultraplus.html | 152 +++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 150 insertions(+), 2 deletions(-) (limited to 'docs') diff --git a/docs/ultraplus.html b/docs/ultraplus.html index da109b5..e01d038 100644 --- a/docs/ultraplus.html +++ b/docs/ultraplus.html @@ -1,19 +1,36 @@ Project IceStorm – UltraPlus Features Documentation @@ -264,4 +281,135 @@ can be used as an open-drain IO using the standard IO cell.

100kΩ
(default)!cf_bit_35
!B6[15]!cf_bit_39
!B12[15] + +

Hard IP

+ +

The UltraPlus devices contain three types of Hard IP: I2C (SB_I2C), SPI (SB_SPI), and LED PWM generation +(SB_LEDDA_IP). The connections and configurations for each of these blocks are documented below.

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
SignalI2C
(0, 31, 0)		I2C
(25, 31, 0)
SBACKO(0, 30, slf_op_6)(25, 30, slf_op_6)
SBADRI0(0, 30, lutff_1/in_0)(25, 30, lutff_1/in_0)
SBADRI1(0, 30, lutff_2/in_0)(25, 30, lutff_2/in_0)
SBADRI2(0, 30, lutff_3/in_0)(25, 30, lutff_3/in_0)
SBADRI3(0, 30, lutff_4/in_0)(25, 30, lutff_4/in_0)
SBADRI4(0, 30, lutff_5/in_0)(25, 30, lutff_5/in_0)
SBADRI5(0, 30, lutff_6/in_0)(25, 30, lutff_6/in_0)
SBADRI6(0, 30, lutff_7/in_0)(25, 30, lutff_7/in_0)
SBADRI7(0, 29, lutff_2/in_0)(25, 29, lutff_2/in_0)
SBCLKI(0, 30, clk)(25, 30, clk)
SBDATI0(0, 29, lutff_5/in_0)(25, 29, lutff_5/in_0)
SBDATI1(0, 29, lutff_6/in_0)(25, 29, lutff_6/in_0)
SBDATI2(0, 29, lutff_7/in_0)(25, 29, lutff_7/in_0)
SBDATI3(0, 30, lutff_0/in_3)(25, 30, lutff_0/in_3)
SBDATI4(0, 30, lutff_5/in_1)(25, 30, lutff_5/in_1)
SBDATI5(0, 30, lutff_6/in_1)(25, 30, lutff_6/in_1)
SBDATI6(0, 30, lutff_7/in_1)(25, 30, lutff_7/in_1)
SBDATI7(0, 30, lutff_0/in_0)(25, 30, lutff_0/in_0)
SBDATO0(0, 29, slf_op_6)(25, 29, slf_op_6)
SBDATO1(0, 29, slf_op_7)(25, 29, slf_op_7)
SBDATO2(0, 30, slf_op_0)(25, 30, slf_op_0)
SBDATO3(0, 30, slf_op_1)(25, 30, slf_op_1)
SBDATO4(0, 30, slf_op_2)(25, 30, slf_op_2)
SBDATO5(0, 30, slf_op_3)(25, 30, slf_op_3)
SBDATO6(0, 30, slf_op_4)(25, 30, slf_op_4)
SBDATO7(0, 30, slf_op_5)(25, 30, slf_op_5)
SBRWI(0, 29, lutff_4/in_0)(25, 29, lutff_4/in_0)
SBSTBI(0, 29, lutff_3/in_0)(25, 29, lutff_3/in_0)
I2CIRQ(0, 30, slf_op_7)(25, 30, slf_op_7)
I2CWKUP(0, 29, slf_op_5)(25, 29, slf_op_5)
SCLI(0, 29, lutff_2/in_1)(25, 29, lutff_2/in_1)
SCLO(0, 29, slf_op_3)(25, 29, slf_op_3)
SCLOE(0, 29, slf_op_4)(25, 29, slf_op_4)
SDAI(0, 29, lutff_1/in_1)(25, 29, lutff_1/in_1)
SDAO(0, 29, slf_op_1)(25, 29, slf_op_1)
SDAOE(0, 29, slf_op_2)(25, 29, slf_op_2)
I2C_ENABLE_0(13, 31, cbit2usealt_in_0)(19, 31, cbit2usealt_in_0)
I2C_ENABLE_1(12, 31, cbit2usealt_in_1)(19, 31, cbit2usealt_in_1)
SDA_INPUT_DELAYED(12, 31, SDA_input_delay)(19, 31, SDA_input_delay)
SDA_OUTPUT_DELAYED(12, 31, SDA_output_delay)(19, 31, SDA_output_delay)
+ +		 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
SignalSPI
(0, 0, 0)		SPI
(25, 0, 1)
SBACKO(0, 20, slf_op_1)(25, 20, slf_op_1)
SBADRI0(0, 19, lutff_1/in_1)(25, 19, lutff_1/in_1)
SBADRI1(0, 19, lutff_2/in_1)(25, 19, lutff_2/in_1)
SBADRI2(0, 20, lutff_0/in_3)(25, 20, lutff_0/in_3)
SBADRI3(0, 20, lutff_1/in_3)(25, 20, lutff_1/in_3)
SBADRI4(0, 20, lutff_2/in_3)(25, 20, lutff_2/in_3)
SBADRI5(0, 20, lutff_3/in_3)(25, 20, lutff_3/in_3)
SBADRI6(0, 20, lutff_4/in_3)(25, 20, lutff_4/in_3)
SBADRI7(0, 20, lutff_5/in_3)(25, 20, lutff_5/in_3)
SBCLKI(0, 20, clk)(25, 20, clk)
SBDATI0(0, 19, lutff_1/in_3)(25, 19, lutff_1/in_3)
SBDATI1(0, 19, lutff_2/in_3)(25, 19, lutff_2/in_3)
SBDATI2(0, 19, lutff_3/in_3)(25, 19, lutff_3/in_3)
SBDATI3(0, 19, lutff_4/in_3)(25, 19, lutff_4/in_3)
SBDATI4(0, 19, lutff_5/in_3)(25, 19, lutff_5/in_3)
SBDATI5(0, 19, lutff_6/in_3)(25, 19, lutff_6/in_3)
SBDATI6(0, 19, lutff_7/in_3)(25, 19, lutff_7/in_3)
SBDATI7(0, 19, lutff_0/in_1)(25, 19, lutff_0/in_1)
SBDATO0(0, 19, slf_op_1)(25, 19, slf_op_1)
SBDATO1(0, 19, slf_op_2)(25, 19, slf_op_2)
SBDATO2(0, 19, slf_op_3)(25, 19, slf_op_3)
SBDATO3(0, 19, slf_op_4)(25, 19, slf_op_4)
SBDATO4(0, 19, slf_op_5)(25, 19, slf_op_5)
SBDATO5(0, 19, slf_op_6)(25, 19, slf_op_6)
SBDATO6(0, 19, slf_op_7)(25, 19, slf_op_7)
SBDATO7(0, 20, slf_op_0)(25, 20, slf_op_0)
SBRWI(0, 19, lutff_0/in_3)(25, 19, lutff_0/in_3)
SBSTBI(0, 20, lutff_6/in_3)(25, 20, lutff_6/in_3)
MCSNO0(0, 21, slf_op_2)(25, 21, slf_op_2)
MCSNO1(0, 21, slf_op_4)(25, 21, slf_op_4)
MCSNO2(0, 21, slf_op_7)(25, 21, slf_op_7)
MCSNO3(0, 22, slf_op_1)(25, 22, slf_op_1)
MCSNOE0(0, 21, slf_op_3)(25, 21, slf_op_3)
MCSNOE1(0, 21, slf_op_5)(25, 21, slf_op_5)
MCSNOE2(0, 22, slf_op_0)(25, 22, slf_op_0)
MCSNOE3(0, 22, slf_op_2)(25, 22, slf_op_2)
MI(0, 22, lutff_0/in_1)(25, 22, lutff_0/in_1)
MO(0, 20, slf_op_6)(25, 20, slf_op_6)
MOE(0, 20, slf_op_7)(25, 20, slf_op_7)
SCKI(0, 22, lutff_1/in_1)(25, 22, lutff_1/in_1)
SCKO(0, 21, slf_op_0)(25, 21, slf_op_0)
SCKOE(0, 21, slf_op_1)(25, 21, slf_op_1)
SCSNI(0, 22, lutff_2/in_1)(25, 22, lutff_2/in_1)
SI(0, 22, lutff_7/in_3)(25, 22, lutff_7/in_3)
SO(0, 20, slf_op_4)(25, 20, slf_op_4)
SOE(0, 20, slf_op_5)(25, 20, slf_op_5)
SPIIRQ(0, 20, slf_op_2)(25, 20, slf_op_2)
SPIWKUP(0, 20, slf_op_3)(25, 20, slf_op_3)
+		 + + + + + + + + + + + + + + + + + + + + + + +
SignalLEDDA_IP
(0, 31, 2)
LEDDADDR0(0, 28, lutff_4/in_0)
LEDDADDR1(0, 28, lutff_5/in_0)
LEDDADDR2(0, 28, lutff_6/in_0)
LEDDADDR3(0, 28, lutff_7/in_0)
LEDDCLK(0, 29, clk)
LEDDCS(0, 28, lutff_2/in_0)
LEDDDAT0(0, 28, lutff_2/in_1)
LEDDDAT1(0, 28, lutff_3/in_1)
LEDDDAT2(0, 28, lutff_4/in_1)
LEDDDAT3(0, 28, lutff_5/in_1)
LEDDDAT4(0, 28, lutff_6/in_1)
LEDDDAT5(0, 28, lutff_7/in_1)
LEDDDAT6(0, 28, lutff_0/in_0)
LEDDDAT7(0, 28, lutff_1/in_0)
LEDDDEN(0, 28, lutff_1/in_1)
LEDDEXE(0, 28, lutff_0/in_1)
LEDDON(0, 29, slf_op_0)
PWMOUT0(0, 28, slf_op_4)
PWMOUT1(0, 28, slf_op_5)
PWMOUT2(0, 28, slf_op_6)
+
+

+ +

The I2C "glitch filter" is a seperate module from the I2C interface IP and needs to be reverse engineered seperately. + -- cgit v1.2.3 From 3c490702694f66b5ceba31dc50538bd14f8019f4 Mon Sep 17 00:00:00 2001 From: David Shah Date: Sat, 25 Nov 2017 10:20:54 +0000 Subject: Add note about glitch filter --- docs/ultraplus.html | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'docs') diff --git a/docs/ultraplus.html b/docs/ultraplus.html index e01d038..694b82d 100644 --- a/docs/ultraplus.html +++ b/docs/ultraplus.html @@ -285,7 +285,8 @@ can be used as an open-drain IO using the standard IO cell.

Hard IP

The UltraPlus devices contain three types of Hard IP: I2C (SB_I2C), SPI (SB_SPI), and LED PWM generation -(SB_LEDDA_IP). The connections and configurations for each of these blocks are documented below.

+(SB_LEDDA_IP). The connections and configurations for each of these blocks are documented below. Names in italics are parameters rather than actual bits, +where multiple bits are used to enable an IP they are labeled as _ENABLE_0, _ENABLE_1, etc.

@@ -410,6 +411,15 @@ can be used as an open-drain IO using the standard IO cell.

SignalI2C
(0, 31, 0)		I2C
(25, 31, 0)

-

The I2C "glitch filter" is a seperate module from the I2C interface IP and needs to be reverse engineered seperately. +

The I2C "glitch filter" (referred to as SB_FILTER_50NS) is a seperate module from the I2C interface IP, with connections as shown below: + + + + + + + + +
SignalSB_FILTER_50NS
(25, 31, 2)		SB_FILTER_50NS
(25, 31, 3)
FILTERIN(25, 27, lutff_1/in_0)(25, 27, lutff_0/in_0)
FILTEROUT(25, 27, slf_op_2)(25, 27, slf_op_1)
ENABLE_0(25, 30, CBIT_2)(25, 30, CBIT_5)
ENABLE_1(25, 30, CBIT_3)(25, 30, CBIT_6)
ENABLE_2(25, 30, CBIT_4)(25, 30, CBIT_7)
-- cgit v1.2.3