From 1dc402804a7f1087ae5b7ca01364b1427d6a2a0d Mon Sep 17 00:00:00 2001 From: John McMaster Date: Mon, 9 Apr 2018 16:27:03 -0700 Subject: docs: spelling/grammer Signed-off-by: John McMaster --- docs/logic_tile.html | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'docs/logic_tile.html') diff --git a/docs/logic_tile.html b/docs/logic_tile.html index 982b25d..ab9adc7 100644 --- a/docs/logic_tile.html +++ b/docs/logic_tile.html @@ -29,7 +29,7 @@ The span-4 and span-12 wires are the main interconnect resource in

-The bits marked routing in the bitstream do enable switches (transfer gates) that can +The bits marked routing in the bitstream enable switches (transfer gates) that can be used to connect wire segments bidirectionally to each other in order to create larger segments. The bits marked buffer in the bitstream enable tristate buffers that drive the signal in one direction from one wire to another. Both types of bits exist for routing between @@ -56,7 +56,7 @@ for this wire names.) The wires connecting the left and right horizontal span-4

-The wires sp4_h_l_36 to sp4_h_l_47 terminate in the cell, so do the wires sp4_h_r_0 to sp4_h_r_11. +The wires sp4_h_l_36 to sp4_h_l_47 terminate in the cell as do the wires sp4_h_r_0 to sp4_h_r_11.

@@ -150,7 +150,7 @@ Each logic tile has 32 local tracks. They are organized in 4 groups of 8 wires e

The span wires, global signals, and neighbour outputs can be routed to the local tracks. But not -every of those signals can be routed to every of the local tracks. Instead there is a different +all of those signals can be routed to all of the local tracks. Instead there is a different mix of 16 signals for each local track.

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