From d1e16d54ad7dd6bb7334494450917107615d0ef2 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 2 Oct 2015 14:06:54 +0200 Subject: Converted docs to proper HTML5 --- docs/index.html | 39 ++++++++++++++++++++------------------- 1 file changed, 20 insertions(+), 19 deletions(-) (limited to 'docs/index.html') diff --git a/docs/index.html b/docs/index.html index 17b99a7..a400fef 100644 --- a/docs/index.html +++ b/docs/index.html @@ -1,4 +1,7 @@ + + Project IceStorm +

Project IceStorm

@@ -102,16 +105,16 @@ after updating your IceStorm installation.

IcePack/IceUnpack

-The iceunpack program converts an iCE40 .bin file into the IceBox ASCII format -that has blocks of 0 and 1 for the config bits for each tile in the chip. The -icepack program converts such an ASCII file back to an iCE40 .bin file. +The iceunpack program converts an iCE40 .bin file into the IceBox ASCII format +that has blocks of 0 and 1 for the config bits for each tile in the chip. The +icepack program converts such an ASCII file back to an iCE40 .bin file.

IceBox

A python library and various tools for working with IceBox ASCII files and accessing -the device database. For example icebox_vlog converts our ASCII file +the device database. For example icebox_vlog converts our ASCII file dump of a bitstream into a Verilog file that implements an equivalent circuit.

@@ -130,7 +133,7 @@ A tool for packing multiple bitstream files into one iCE40 multiboot image file.

ChipDB

-The IceStorm Makefile builds and installs two files: chipdb-1k.txt and chipdb-8k.txt. +The IceStorm Makefile builds and installs two files: chipdb-1k.txt and chipdb-8k.txt. This files contain all the relevant information for arachne-pnr to place&route a design and create an IceBox ASCII file for the placed and routed design.

@@ -163,8 +166,8 @@ The FPGA fabric is divided into tiles. There are IO, RAM and LOGIC tiles.

-The iceunpack program can be used to convert the bitstream into an ASCII file -that has a block of 0 and 1 characters for each tile. For example: +The iceunpack program can be used to convert the bitstream into an ASCII file +that has a block of 0 and 1 characters for each tile. For example:

.logic_tile 12 12
@@ -186,12 +189,12 @@ that has a block of 0 and 1 characters for each tile. For exam
 000000000000000000000000000101010000101010100000000000

-This bits are referred to as By[x] in the documentation. For example, B0 is the first -line, B0[0] the first bit in the first line, and B15[53] the last bit in the last line. +This bits are referred to as By[x] in the documentation. For example, B0 is the first +line, B0[0] the first bit in the first line, and B15[53] the last bit in the last line.

-The icebox_explain program can be used to turn this block of config bits into a description of the cell +The icebox_explain program can be used to turn this block of config bits into a description of the cell configuration:

@@ -205,16 +208,16 @@ buffer sp12_h_r_20 local_g1_4

IceBox contains a database of the wires and configuration bits that can be found in iCE40 tiles. This database can be accessed via the IceBox Python API. But IceBox is a large hack. So it is recommended to only use the IceBox API -to export this database into a format that fits the target application. See icebox_chipdb for +to export this database into a format that fits the target application. See icebox_chipdb for an example program that does that.

The recommended approach for learning how to use this documentation is to synthesize very simple circuits using Yosys and Arachne-pnr, run the icestorm -tool icebox_explain on the resulting bitstream files, and analyze the +tool icebox_explain on the resulting bitstream files, and analyze the results using the HTML export of the database mentioned above. -icebox_vlog can be used to convert the bitstream to Verilog. The +icebox_vlog can be used to convert the bitstream to Verilog. The output file of this tool will also outline the signal paths in comments added to the generated Verilog code.

@@ -243,7 +246,7 @@ $ icepack example.txt example.bin

-We would get something like the following icebox_explain output: +We would get something like the following icebox_explain output:

$ icebox_explain example.txt
@@ -280,7 +283,7 @@ buffer neigh_op_lft_0 local_g0_0
 buffer sp4_h_r_24 local_g3_0

-And something like the following icebox_vlog output: +And something like the following icebox_vlog output:

$ icebox_vlog -p example.pcf example.txt
@@ -353,9 +356,7 @@ Links to related projects. Contact me at clifford@clifford.at if you have an int
 ICEd = an Arduino Style Board, with ICE FPGA
 
 
-
 

-
 
 
 In papers and reports, please refer to Project IceStorm as follows: Clifford Wolf, Mathias Lasser. Project IceStorm. http://www.clifford.at/icestorm/,
@@ -368,11 +369,11 @@ e.g. using the following BibTeX code:
 	howpublished = "\url{http://www.clifford.at/icestorm/}"
 }

Documentation mostly by Clifford Wolf <clifford@clifford.at> in 2015. Based on research by Mathias Lasser and Clifford Wolf.
Buy an iCEstick from Lattice and see what you can do with the information provided here. Buy a few because you might break some..

+ + -- cgit v1.2.3