From fbe038923e51b19665e09ef4f447d3736d42755f Mon Sep 17 00:00:00 2001
From: Clifford Wolf
+2015-07-19: Released support for 8k chips. Moved IceStorm sourcecode to GitHub. This documentation is auto-generated by icebox_html.py from IceBox.Project IceStorm
2015-05-27: We have a working fully Open Source flow with Yosys and Arachne-pnr! Video: http://youtu.be/yUiNlmvVOq8
2015-04-13: Complete rewrite of IceUnpack, added IcePack, some major documentation updates
2015-03-22: First public release and short YouTube video demonstrating our work: http://youtu.be/u1ZHcSNDQMM
diff --git a/icebox/icebox_html.py b/icebox/icebox_html.py
index dbd2e5d..53cbdb2 100755
--- a/icebox/icebox_html.py
+++ b/icebox/icebox_html.py
@@ -22,7 +22,9 @@ import icebox
import getopt, sys, os, re
chipname = "iCE40 HX1K"
+chipdbfile = "chipdb-1k.txt"
outdir = None
+mode8k = False
tx, ty = 0, 0
def usage():
@@ -30,10 +32,11 @@ def usage():
print(" -x tile_x_coordinate")
print(" -y tile_y_coordinate")
print(" -d outdir")
+ print(" -8")
sys.exit(0)
try:
- opts, args = getopt.getopt(sys.argv[1:], "x:y:d:")
+ opts, args = getopt.getopt(sys.argv[1:], "x:y:d:8")
except:
usage()
@@ -44,6 +47,10 @@ for o, a in opts:
ty = int(a)
elif o == "-d":
outdir = a
+ elif o == "-8":
+ mode8k = True
+ chipname = "iCE40 HX8K"
+ chipdbfile = "chipdb-8k.txt"
else:
usage()
@@ -51,29 +58,56 @@ if len(args) != 0:
usage()
ic = icebox.iceconfig()
-ic.setup_empty_1k()
mktiles = set()
-for x in range(1, 13):
- mktiles.add((x, 0))
- mktiles.add((x, 17))
+if mode8k:
+ ic.setup_empty_8k()
-for x in range(0, 6) + range(8, 14):
- mktiles.add((x, 1))
- mktiles.add((x, 16))
+ for x in range(1, 3) + range(8-2, 8+3) + range(15, 19) + range(25-2, 25+3) + range(33-2, 33):
+ mktiles.add((x, 0))
+ mktiles.add((x, 33))
-for x in range(0, 5) + range(9, 14):
- mktiles.add((x, 2))
- mktiles.add((x, 15))
+ for x in range(0, 3) + range(8-1, 8+2) + range(25-1, 25+2) + range(33-2, 34):
+ mktiles.add((x, 1))
+ mktiles.add((x, 32))
-for y in range(7, 11):
- mktiles.add((0, y))
- mktiles.add((13, y))
+ for x in range(0, 2) + range(8-1, 8+2) + range(25-1, 25+2) + range(34-2, 34):
+ mktiles.add((x, 2))
+ mktiles.add((x, 31))
-for x in range(6, 8):
- for y in range(8, 10):
- mktiles.add((x, y))
+ for x in [0, 33]:
+ mktiles.add((x, 15))
+ mktiles.add((x, 16))
+ mktiles.add((x, 17))
+ mktiles.add((x, 18))
+
+ for x in [16, 17]:
+ mktiles.add((x, 16))
+ mktiles.add((x, 17))
+
+else:
+ ic.setup_empty_1k()
+
+ for x in range(1, 13):
+ mktiles.add((x, 0))
+ mktiles.add((x, 17))
+
+ for x in range(0, 6) + range(8, 14):
+ mktiles.add((x, 1))
+ mktiles.add((x, 16))
+
+ for x in range(0, 5) + range(9, 14):
+ mktiles.add((x, 2))
+ mktiles.add((x, 15))
+
+ for y in range(7, 11):
+ mktiles.add((0, y))
+ mktiles.add((13, y))
+
+ for x in range(6, 8):
+ for y in range(8, 10):
+ mktiles.add((x, y))
expand_count=[0]
@@ -96,7 +130,7 @@ def print_index():
and providing simple tools for analyzing and creating bitstream files. This is work in progress.""")
print("""
-A machine-readable form of the database can be downloaded here.
The iCE40 FPGA fabric is organized into tiles. The configuration bits themself have the same meaning in all tiles of the same type. But the way the tiles @@ -112,7 +146,12 @@ in iCE40 FPGAs.
""") for y in range(ic.max_y, -1, -1): print("