From ec3ad586835ec13cd5b3c32f6c2b7580247c562b Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 29 Nov 2017 12:37:40 +0000 Subject: Figure out missing SPI config bits, and add to chipdb --- icebox/icebox.py | 8 ++++++++ icefuzz/tests/ip/up5k_I2C_data.txt | 4 ++-- icefuzz/tests/ip/up5k_SPI_data.txt | 8 ++++++++ 3 files changed, 18 insertions(+), 2 deletions(-) diff --git a/icebox/icebox.py b/icebox/icebox.py index 25e01e4..37f7767 100644 --- a/icebox/icebox.py +++ b/icebox/icebox.py @@ -4862,6 +4862,10 @@ extra_cells_db = { "SOE": (0, 20, "slf_op_5"), "SPIIRQ": (0, 20, "slf_op_2"), "SPIWKUP": (0, 20, "slf_op_3"), + "SPI_ENABLE_0": (7, 0, "cbit2usealt_in_0"), + "SPI_ENABLE_1": (7, 0, "cbit2usealt_in_1"), + "SPI_ENABLE_2": (6, 0, "cbit2usealt_in_0"), + "SPI_ENABLE_3": (6, 0, "cbit2usealt_in_1"), }, ("SPI", (25, 0, 1)): { "MCSNO0": (25, 21, "slf_op_2"), @@ -4912,6 +4916,10 @@ extra_cells_db = { "SOE": (25, 20, "slf_op_5"), "SPIIRQ": (25, 20, "slf_op_2"), "SPIWKUP": (25, 20, "slf_op_3"), + "SPI_ENABLE_0": (23, 0, "cbit2usealt_in_0"), + "SPI_ENABLE_1": (24, 0, "cbit2usealt_in_0"), + "SPI_ENABLE_2": (23, 0, "cbit2usealt_in_1"), + "SPI_ENABLE_3": (24, 0, "cbit2usealt_in_1"), }, ("LEDDA_IP", (0, 31, 2)): { "LEDDADDR0": (0, 28, "lutff_4/in_0"), diff --git a/icefuzz/tests/ip/up5k_I2C_data.txt b/icefuzz/tests/ip/up5k_I2C_data.txt index a891b0c..f433663 100644 --- a/icefuzz/tests/ip/up5k_I2C_data.txt +++ b/icefuzz/tests/ip/up5k_I2C_data.txt @@ -43,8 +43,8 @@ ("I2C", (25, 31, 0)): { "I2CIRQ": (25, 30, "slf_op_7"), "I2CWKUP": (25, 29, "slf_op_5"), - "I2C_ENABLE_0": (19, 31, "cbit2usealt_in_0"), - "I2C_ENABLE_1": (19, 31, "cbit2usealt_in_1"), + "I2C_ENABLE_0": (19, 31, "cbit2usealt_in_1"), + "I2C_ENABLE_1": (19, 31, "cbit2usealt_in_0"), "SBACKO": (25, 30, "slf_op_6"), "SBADRI0": (25, 30, "lutff_1/in_0"), "SBADRI1": (25, 30, "lutff_2/in_0"), diff --git a/icefuzz/tests/ip/up5k_SPI_data.txt b/icefuzz/tests/ip/up5k_SPI_data.txt index 149c93a..be4be44 100644 --- a/icefuzz/tests/ip/up5k_SPI_data.txt +++ b/icefuzz/tests/ip/up5k_SPI_data.txt @@ -47,6 +47,10 @@ "SOE": (0, 20, "slf_op_5"), "SPIIRQ": (0, 20, "slf_op_2"), "SPIWKUP": (0, 20, "slf_op_3"), + "SPI_ENABLE_0": (7, 0, "cbit2usealt_in_0"), + "SPI_ENABLE_1": (7, 0, "cbit2usealt_in_1"), + "SPI_ENABLE_2": (6, 0, "cbit2usealt_in_0"), + "SPI_ENABLE_3": (6, 0, "cbit2usealt_in_1"), }, ("SPI", (25, 0, 1)): { "MCSNO0": (25, 21, "slf_op_2"), @@ -97,4 +101,8 @@ "SOE": (25, 20, "slf_op_5"), "SPIIRQ": (25, 20, "slf_op_2"), "SPIWKUP": (25, 20, "slf_op_3"), + "SPI_ENABLE_0": (23, 0, "cbit2usealt_in_0"), + "SPI_ENABLE_1": (24, 0, "cbit2usealt_in_0"), + "SPI_ENABLE_2": (23, 0, "cbit2usealt_in_1"), + "SPI_ENABLE_3": (24, 0, "cbit2usealt_in_1"), }, -- cgit v1.2.3 From 0932c559a781c261c6d7f10f54faeb27aef4b702 Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 4 Dec 2017 14:23:58 +0000 Subject: Misc routing tweaks --- icebox/icebox.py | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/icebox/icebox.py b/icebox/icebox.py index 37f7767..13f8641 100644 --- a/icebox/icebox.py +++ b/icebox/icebox.py @@ -419,7 +419,7 @@ class iceconfig: def do_direction(name, nx, ny): if (0 < nx < self.max_x or self.is_ultra()) and 0 < ny < self.max_y: neighbours.add((nx, ny, "neigh_op_%s_%d" % (name, func))) - if nx in (0, self.max_x) and 0 < ny < self.max_y and nx != x: + if nx in (0, self.max_x) and 0 < ny < self.max_y and nx != x and (not self.is_ultra()): neighbours.add((nx, ny, "logic_op_%s_%d" % (name, func))) if ny in (0, self.max_y) and 0 < nx < self.max_x and ny != y: neighbours.add((nx, ny, "logic_op_%s_%d" % (name, func))) @@ -463,7 +463,7 @@ class iceconfig: else: assert False - elif pos == "x" and npos in ("l", "r", "t", "b"): + elif pos == "x" and ((npos in ("t", "b")) or ((not self.is_ultra()) and (npos in ("l", "r")))): if func in (0, 4): return (nx, ny, "io_0/D_IN_0") if func in (1, 5): return (nx, ny, "io_0/D_IN_1") if func in (2, 6): return (nx, ny, "io_1/D_IN_0") @@ -650,7 +650,7 @@ class iceconfig: vert_net = netname.replace("_l_", "_t_").replace("_r_", "_b_").replace("_horz_", "_vert_") horz_net = netname.replace("_t_", "_l_").replace("_b_", "_r_").replace("_vert_", "_horz_") - if self.is_ultra(): + if self.is_ultra(): # Might have sp4 not span4 here vert_net = vert_net.replace("_h_", "_v_") horz_net = horz_net.replace("_v_", "_h_") @@ -1194,6 +1194,8 @@ def pos_follow_net(pos, direction, netname, is_ultra): if direction == "t": n = re.sub("_t_", "_b_", n) n = sp12v_normalize(n) + elif direction == "T" and pos in ("l", "r"): + pass else: n = re.sub("_t_", "_", n) n = re.sub("sp12_v_", "span12_vert_", n) @@ -1204,6 +1206,8 @@ def pos_follow_net(pos, direction, netname, is_ultra): if direction == "b": n = re.sub("_b_", "_t_", n) n = sp12v_normalize(n) + elif direction == "B" and pos in ("l", "r"): + pass else: n = re.sub("_b_", "_", n) n = re.sub("sp12_v_", "span12_vert_", n) -- cgit v1.2.3 From 9e81ac7786d7633b7d1c204318f1559bca300643 Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 4 Dec 2017 17:37:14 +0000 Subject: New UltraPlus corner tracing algorithm --- icebox/icebox.py | 173 +++++++++++++++++++++++++++---------------------------- 1 file changed, 86 insertions(+), 87 deletions(-) diff --git a/icebox/icebox.py b/icebox/icebox.py index 13f8641..ed27d1b 100644 --- a/icebox/icebox.py +++ b/icebox/icebox.py @@ -507,34 +507,52 @@ class iceconfig: return funcnets + def ultraplus_follow_corner(self, corner, direction, netname): + m = re.match("span4_(horz|vert)_([lrtb])_(\d+)$", netname) + if not m: + return None + cur_edge = m.group(2) + cur_index = int(m.group(3)) + if direction not in corner: + return None + if direction != cur_edge: + return None + h_idx, v_idx = self.ultraplus_trace_corner_idx(corner, cur_index) + if h_idx is None and (direction == "b" or direction == "t"): + return None + if v_idx is None and (direction == "l" or direction == "r"): + return None + if corner == "bl" and direction == "l": + return (0, 1, sp4v_normalize("sp4_v_b_%d" % v_idx)) + if corner == "bl" and direction == "b": + return (1, 0, ultra_span4_horz_normalize("span4_horz_l_%d" % h_idx)) + if corner == "br" and direction == "r": + return (self.max_x, 1, sp4v_normalize("sp4_v_b_%d" % v_idx)) + if corner == "br" and direction == "b": + return (self.max_x-1, 0, ultra_span4_horz_normalize("span4_horz_r_%d" % h_idx)) + if corner == "tl" and direction == "l": + return (0, self.max_y-1, sp4v_normalize("sp4_v_t_%d" % v_idx)) + if corner == "tl" and direction == "t": + return (1, self.max_y, ultra_span4_horz_normalize("span4_horz_l_%d" % h_idx)) + if corner == "tr" and direction == "r": + return (self.max_x, self.max_y-1, sp4v_normalize("sp4_v_t_%d" % v_idx)) + if corner == "tr" and direction == "t": + return (self.max_x-1, self.max_y, ultra_span4_horz_normalize("span4_horz_r_%d" % h_idx)) + assert False #UltraPlus corner routing: given the corner name and net index, #return a tuple containing H and V indexes, or none if NA - def ultraplus_trace_corner(self, corner, idx): + def ultraplus_trace_corner_idx(self, corner, idx): h_idx = None v_idx = None - if corner == "bl": - if idx >= 4: - v_idx = idx + 28 - if idx >= 32 and idx < 48: - h_idx = idx - 28 - elif corner == "tl": - #TODO: bounds check for v_idx case? - if idx >= 4: - v_idx = (idx + 8) ^ 1 - if idx >= 12 and idx < 28: - h_idx = (idx ^ 1) - 8 - elif corner == "tr": - #TODO: bounds check for v_idx case? - if idx <= 16: - v_idx = (idx + 12) ^ 1 - if idx >= 12 and idx < 28: - h_idx = (idx ^ 1) - 12 - elif corner == "br": - #TODO: bounds check for v_idx case? - if idx <= 16: + if corner == "bl" or corner == "br": + if idx < 16: v_idx = idx + 32 - if idx >= 32 and idx < 48: #check + if idx >= 32 and idx < 48: h_idx = idx - 32 + elif corner == "tl" or corner == "tr": + if idx >= 0 and idx < 16: + v_idx = idx + h_idx = idx return (h_idx, v_idx) def get_corner(self, x, y): @@ -551,7 +569,7 @@ class iceconfig: corner += "r" else: corner += "x" - return corner + return corner def follow_net(self, netspec): x, y, netname = netspec @@ -608,37 +626,16 @@ class iceconfig: if direction == "b": s = (x, y-1, n) if s[0] in (0, self.max_x) and s[1] in (0, self.max_y): - if re.match("span4_(vert|horz)_[lrtb]_\d+$", n): - m = re.match("span4_(vert|horz)_([lrtb])_\d+$", n) - #We ignore L and T edges when performing the Ultra/UltraPlus corner algorithm - if self.is_ultra() and (m.group(2) == "l" or m.group(2) == "t"): + if self.is_ultra(): + s = self.ultraplus_follow_corner(self.get_corner(s[0], s[1]), direction, n) + if s is None: continue + elif re.match("span4_(vert|horz)_[lrtb]_\d+$", n) and not self.is_ultra(): + m = re.match("span4_(vert|horz)_([lrtb])_\d+$", n) + vert_net = n.replace("_l_", "_t_").replace("_r_", "_b_").replace("_horz_", "_vert_") horz_net = n.replace("_t_", "_l_").replace("_b_", "_r_").replace("_vert_", "_horz_") - - if self.is_ultra(): #Convert between span4 and sp4, and perform U/UP corner tracing - m = re.match("span4_vert_([lrtb])_(\d+)$", vert_net) - assert m - idx = int(m.group(2)) - h_idx, v_idx = self.ultraplus_trace_corner(self.get_corner(s[0], s[1]), idx) - if v_idx is None: - if (s[0] == 0 and s[1] == 0 and direction == "l") or (s[0] == self.max_x and s[1] == self.max_y and direction == "r"): - continue #Not routed, skip - else: - vert_net = "sp4_v_%s_%d" % (m.group(1), v_idx) - - m = re.match("span4_horz_([lrtb])_(\d+)$", horz_net) - assert m - idx = int(m.group(2)) - h_idx, v_idx = self.ultraplus_trace_corner(self.get_corner(s[0], s[1]), idx) - if h_idx is None: - if (s[0] == 0 and s[1] == 0 and direction == "b") or (s[0] == self.max_x and s[1] == self.max_y and direction == "t"): - continue #Not routed, skip - else: - horz_net = "span4_horz_%s_%d" % (m.group(1), h_idx) - - - + if s[0] == 0 and s[1] == 0: if direction == "l": s = (0, 1, vert_net) if direction == "b": s = (1, 0, horz_net) @@ -649,30 +646,6 @@ class iceconfig: vert_net = netname.replace("_l_", "_t_").replace("_r_", "_b_").replace("_horz_", "_vert_") horz_net = netname.replace("_t_", "_l_").replace("_b_", "_r_").replace("_vert_", "_horz_") - - if self.is_ultra(): - # Might have sp4 not span4 here - vert_net = vert_net.replace("_h_", "_v_") - horz_net = horz_net.replace("_v_", "_h_") - m = re.match("(span4_vert|sp4_v)_([lrtb])_(\d+)$", vert_net) - assert m - idx = int(m.group(3)) - h_idx, v_idx = self.ultraplus_trace_corner(self.get_corner(s[0], s[1]), idx) - if v_idx is None: - if (s[0] == 0 and s[1] == self.max_y and direction == "l") or (s[0] == self.max_x and s[1] == 0 and direction == "r"): - continue - else: - vert_net = "sp4_v_%s_%d" % (m.group(2), v_idx) - - m = re.match("(span4_horz|sp4_h)_([lrtb])_(\d+)$", horz_net) - assert m - idx = int(m.group(3)) - h_idx, v_idx = self.ultraplus_trace_corner(self.get_corner(s[0], s[1]), idx) - if h_idx is None: - if (s[0] == 0 and s[1] == self.max_y and direction == "t") or (s[0] == self.max_x and s[1] == 0 and direction == "b"): - continue - else: - horz_net = "span4_horz_%s_%d" % (m.group(2), h_idx) if s[0] == 0 and s[1] == self.max_y: if direction == "l": s = (0, self.max_y-1, vert_net) @@ -1008,7 +981,34 @@ def sp4h_normalize(netname, edge=""): return "sp4_h_r_%d" % ((cur_index+12)^1) return netname - +# "Normalization" of span4 (not just sp4) is needed during Ultra/UltraPlus +# corner tracing +def ultra_span4_horz_normalize(netname, edge=""): + m = re.match("span4_horz_([rl])_(\d+)$", netname) + assert m + if not m: return None + cur_edge = m.group(1) + cur_index = int(m.group(2)) + if cur_edge == edge: + return netname + if edge == "": + if cur_edge == "l" and cur_index < 12: + return "span4_horz_r_%d" % (cur_index + 4) + else: + return netname + elif edge == "l" and cur_edge == "r": + if cur_index < 4: + return None + else: + cur_index -= 4 + return "span4_horz_l_%d" % cur_index + elif edge == "r" and cur_edge == "l": + if cur_index < 12: + return "span4_horz_r_%d" % (cur_index + 4) + else: + return None + assert False + def sp4v_normalize(netname, edge=""): m = re.match("sp4_v_([bt])_(\d+)$", netname) assert m @@ -1141,11 +1141,11 @@ def pos_follow_net(pos, direction, netname, is_ultra): m = re.match("sp4_v_[tb]_(\d+)$", netname) if m and direction in ("t", "T"): - if is_ultra and direction == "T" and pos in ("l", "r"): - return re.sub("sp4_v_", "span4_vert_", netname) n = sp4v_normalize(netname, "t") if n is not None: - if direction == "t": + if is_ultra and direction == "T" and pos in ("l", "r"): + return re.sub("sp4_v_", "span4_vert_", n) + elif direction == "t": n = re.sub("_t_", "_b_", n) n = sp4v_normalize(n) else: @@ -1153,11 +1153,11 @@ def pos_follow_net(pos, direction, netname, is_ultra): n = re.sub("sp4_v_", "span4_vert_", n) return n if m and direction in ("b", "B"): - if is_ultra and direction == "B" and pos in ("l", "r"): - return re.sub("sp4_v_", "span4_vert_", netname) n = sp4v_normalize(netname, "b") if n is not None: - if direction == "b": + if is_ultra and direction == "B" and pos in ("l", "r"): + return re.sub("sp4_v_", "span4_vert_", n) + elif direction == "b": n = re.sub("_b_", "_t_", n) n = sp4v_normalize(n) else: @@ -1230,8 +1230,10 @@ def pos_follow_net(pos, direction, netname, is_ultra): m = re.match("span4_horz_([rl])_(\d+)$", netname) if m: case, idx = direction + m.group(1), int(m.group(2)) - if direction == "L" or direction == "R": - return netname + if direction == "L": + return ultra_span4_horz_normalize(netname, "l") + elif direction == "R": + return ultra_span4_horz_normalize(netname, "r") if case == "ll": return "span4_horz_r_%d" % idx if case == "lr" and idx >= 4: @@ -1320,9 +1322,6 @@ def run_checks_neigh(): # Skip the corners. if x in (0, ic.max_x) and y in (0, ic.max_y): continue - # Skip the sides of a 5k device. - if self.is_ultra() and x in (0, ic.max_x): - continue add_segments((x, y), ic.tile_db(x, y)) if (x, y) in ic.logic_tiles: all_segments.add((x, y, "lutff_7/cout")) -- cgit v1.2.3 From 77eafa89b4b9d8852071cc68298f92465311470b Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 6 Dec 2017 17:48:15 +0000 Subject: HFOSC trimming info --- docs/ultraplus.html | 8 ++++++++ icebox/icebox.py | 13 ++++++++++++- 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/docs/ultraplus.html b/docs/ultraplus.html index 694b82d..dac648a 100644 --- a/docs/ultraplus.html +++ b/docs/ultraplus.html @@ -205,6 +205,14 @@ The CLKHF output of SB_HFOSC is conne

Configuration bit CLKHF_DIV[1] maps to DSP1 tile (0, 16) config bit CBIT_4, and CLKHF_DIV[0] maps to DSP1 tile (0, 16) config bit CBIT_3.

+

There is also an undocumented trimming function of the HFOSC, using the ports TRIM0 through TRIM9. This can only be accessed directly in iCECUBE if you modify the standard cell library. However + if you set the attribute VPP_2V5_TO_1P8V (which itself is not that well documented either) to 1 on the top level module, then the configuration bit + CBIT_5 of (0, 16) is set; and TRIM8 and TRIM4 are connected to + the same net as CLKHFPU.

+

TRIM[3:0] connect to (25, 28, lutff_[7:4]/in_0) and TRIM[9:4] + connect to (25, 29, lutff_[5:0]/in_3). CBIT_5 of (0, 16) must be set to enable trimming. The trim range +on the device used for testing was from 30.1 to 75.9 MHz. TRIM9 seemed to have no effect, the other inputs could broadly be considered to form a binary word, however it appeared neither linear +nor even monotonic.

SB_LFOSC

The CLKLFPU input connects through IPConnect tile (25, 29) input lutff_0/in_1; and the CLKLFEN input connects through input lutff_7/in_3 of the same tile.
diff --git a/icebox/icebox.py b/icebox/icebox.py index ed27d1b..331aa74 100644 --- a/icebox/icebox.py +++ b/icebox/icebox.py @@ -4695,8 +4695,19 @@ extra_cells_db = { "CLKHFEN": (0, 29, "lutff_7/in_3"), "CLKHF": (0, 29, "glb_netwk_4"), "CLKHF_FABRIC": (0, 28, "slf_op_7"), + "TRIM0": (25, 28, "lutff_4/in_0"), + "TRIM1": (25, 28, "lutff_5/in_0"), + "TRIM2": (25, 28, "lutff_6/in_0"), + "TRIM3": (25, 28, "lutff_7/in_0"), + "TRIM4": (25, 29, "lutff_0/in_3"), + "TRIM5": (25, 29, "lutff_1/in_3"), + "TRIM6": (25, 29, "lutff_2/in_3"), + "TRIM7": (25, 29, "lutff_3/in_3"), + "TRIM8": (25, 29, "lutff_4/in_3"), + "TRIM9": (25, 29, "lutff_5/in_3"), "CLKHF_DIV_1": (0, 16, "CBIT_4"), - "CLKHF_DIV_0": (0, 16, "CBIT_3") + "CLKHF_DIV_0": (0, 16, "CBIT_3"), + "TRIM_EN": (0, 16, "CBIT_5") }, ("LFOSC", (25, 31, 1)) : { "CLKLFPU": (25, 29, "lutff_0/in_1"), -- cgit v1.2.3 From 35bd638b4cad985a235d19374f7a37f64c6b47c8 Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 8 Jan 2018 17:38:05 +0000 Subject: Add SPI enable bits to docs --- docs/ultraplus.html | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/docs/ultraplus.html b/docs/ultraplus.html index dac648a..b5dda62 100644 --- a/docs/ultraplus.html +++ b/docs/ultraplus.html @@ -391,6 +391,10 @@ where multiple bits are used to enable an IP they are labeled as -- cgit v1.2.3 From 02a986b2f4b9d0cf5166a8a4915abe196116d259 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 11 Jan 2018 19:22:45 +0000 Subject: Add pinout for 5k UWG30 package --- icebox/icebox.py | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/icebox/icebox.py b/icebox/icebox.py index 331aa74..9816db7 100644 --- a/icebox/icebox.py +++ b/icebox/icebox.py @@ -4399,6 +4399,29 @@ pinloc_db = { ( "47", 6, 0, 0), ( "48", 7, 0, 0), ], + "5k-uwg30": [ + ( "A1", 19, 31, 1), + ( "A2", 19, 31, 0), + ( "A4", 12, 31, 0), + ( "A5", 4, 31, 0), + ( "B1", 19, 0, 0), + ( "B3", 12, 31, 1), + ( "B5", 5, 31, 0), + ( "C1", 24, 0, 1), + ( "C3", 12, 0, 0), + ( "C5", 6, 31, 0), + ( "D1", 24, 0, 0), + ( "D3", 13, 0, 0), + ( "D5", 6, 0, 0), + ( "E1", 23, 0, 1), + ( "E3", 13, 0, 1), + ( "E4", 9, 0, 1), + ( "E5", 5, 0, 0), + ( "F1", 23, 0, 0), + ( "F2", 19, 0, 1), + ( "F4", 12, 0, 1), + ( "F5", 6, 0, 1), + ] } # This database contains the locations of configuration bits of the DSP tiles -- cgit v1.2.3 From a59472812c808416d2a56bccc07a9540357e18d9 Mon Sep 17 00:00:00 2001 From: David Shah Date: Sat, 13 Jan 2018 15:55:32 +0000 Subject: Remove seperate 5k RAM DB and share with 8k instead This should ensure that the 5k RAM routing entries are now complete, fixing #115 --- icebox/icebox.py | 20 +- icebox/iceboxdb.py | 2838 ---------------------------------- icefuzz/Makefile | 5 +- icefuzz/cached_ramb_5k.txt | 3563 ------------------------------------------- icefuzz/cached_ramt_5k.txt | 3597 -------------------------------------------- icefuzz/database.py | 4 +- icefuzz/export.py | 2 +- 7 files changed, 13 insertions(+), 10016 deletions(-) delete mode 100644 icefuzz/cached_ramb_5k.txt delete mode 100644 icefuzz/cached_ramt_5k.txt diff --git a/icebox/icebox.py b/icebox/icebox.py index 9816db7..e19e489 100644 --- a/icebox/icebox.py +++ b/icebox/icebox.py @@ -318,8 +318,8 @@ class iceconfig: if (x, y) in self.ramt_tiles: return ramttile_db elif self.device == "5k": if (x, y) in self.logic_tiles: return logictile_5k_db - if (x, y) in self.ramb_tiles: return rambtile_5k_db - if (x, y) in self.ramt_tiles: return ramttile_5k_db + if (x, y) in self.ramb_tiles: return rambtile_8k_db + if (x, y) in self.ramt_tiles: return ramttile_8k_db if (x, y) in self.ipcon_tiles: return ipcon_5k_db if (x, y) in self.dsp_tiles[0]: return dsp0_5k_db if (x, y) in self.dsp_tiles[1]: return dsp1_5k_db @@ -725,7 +725,7 @@ class iceconfig: if self.device == "1k": add_seed_segments(idx, tile, rambtile_db) elif self.device == "5k": - add_seed_segments(idx, tile, rambtile_5k_db) + add_seed_segments(idx, tile, rambtile_8k_db) elif self.device == "8k": add_seed_segments(idx, tile, rambtile_8k_db) else: @@ -735,7 +735,7 @@ class iceconfig: if self.device == "1k": add_seed_segments(idx, tile, ramttile_db) elif self.device == "5k": - add_seed_segments(idx, tile, ramttile_5k_db) + add_seed_segments(idx, tile, ramttile_8k_db) elif self.device == "8k": add_seed_segments(idx, tile, ramttile_8k_db) else: @@ -4991,8 +4991,6 @@ logictile_8k_db = parse_db(iceboxdb.database_logic_txt, "8k") logictile_384_db = parse_db(iceboxdb.database_logic_txt, "384") rambtile_db = parse_db(iceboxdb.database_ramb_txt, "1k") ramttile_db = parse_db(iceboxdb.database_ramt_txt, "1k") -rambtile_5k_db = parse_db(iceboxdb.database_ramb_5k_txt, "5k") -ramttile_5k_db = parse_db(iceboxdb.database_ramt_5k_txt, "5k") rambtile_8k_db = parse_db(iceboxdb.database_ramb_8k_txt, "8k") ramttile_8k_db = parse_db(iceboxdb.database_ramt_8k_txt, "8k") @@ -5089,19 +5087,19 @@ iotile_b_5k_db.append([["B12[2]"], "IpConfig", "cbit2usealt_in_1"]) iotile_b_5k_db.append([["B12[3]"], "IpConfig", "SDA_input_delay"]) iotile_b_5k_db.append([["B15[3]"], "IpConfig", "SDA_output_delay"]) -for db in [iotile_l_db, iotile_r_db, iotile_t_db, iotile_b_db, iotile_t_5k_db, iotile_b_5k_db, logictile_db, logictile_5k_db, logictile_8k_db, logictile_384_db, rambtile_db, ramttile_db, rambtile_5k_db, ramttile_5k_db, rambtile_8k_db, ramttile_8k_db, dsp0_5k_db, dsp1_5k_db, dsp2_5k_db, dsp3_5k_db, ipcon_5k_db]: +for db in [iotile_l_db, iotile_r_db, iotile_t_db, iotile_b_db, iotile_t_5k_db, iotile_b_5k_db, logictile_db, logictile_5k_db, logictile_8k_db, logictile_384_db, rambtile_db, ramttile_db, rambtile_8k_db, ramttile_8k_db, dsp0_5k_db, dsp1_5k_db, dsp2_5k_db, dsp3_5k_db, ipcon_5k_db]: for entry in db: if entry[1] in ("buffer", "routing"): entry[2] = netname_normalize(entry[2], ramb=(db == rambtile_db), ramt=(db == ramttile_db), - ramb_8k=(db in (rambtile_8k_db, rambtile_5k_db)), - ramt_8k=(db in (ramttile_8k_db, ramttile_5k_db))) + ramb_8k=(db == rambtile_8k_db), + ramt_8k=(db == ramttile_8k_db)) entry[3] = netname_normalize(entry[3], ramb=(db == rambtile_db), ramt=(db == ramttile_db), - ramb_8k=(db in (rambtile_8k_db, rambtile_5k_db)), - ramt_8k=(db in (ramttile_8k_db, ramttile_5k_db))) + ramb_8k=(db == rambtile_8k_db), + ramt_8k=(db == ramttile_8k_db)) unique_entries = dict() while db: entry = db.pop() diff --git a/icebox/iceboxdb.py b/icebox/iceboxdb.py index 61c0757..b2cca34 100644 --- a/icebox/iceboxdb.py +++ b/icebox/iceboxdb.py @@ -6709,2844 +6709,6 @@ B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1 !B13[8],B13[9],!B13[10] routing sp4_v_t_47 sp4_v_b_10 B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6 """ -database_ramb_5k_txt = """ -B8[7] ColBufCtrl 8k_glb_netwk_1 -B11[7] ColBufCtrl 8k_glb_netwk_2 -B10[7] ColBufCtrl 8k_glb_netwk_3 -B13[7] ColBufCtrl 8k_glb_netwk_4 -B12[7] ColBufCtrl 8k_glb_netwk_5 -B15[7] ColBufCtrl 8k_glb_netwk_6 -B14[7] ColBufCtrl 8k_glb_netwk_7 -B0[0] NegClk -B1[7] RamConfig PowerUp -B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer bnl_op_0 lc_trk_g2_0 -B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer bnl_op_0 lc_trk_g3_0 -!B8[15],!B8[16],B8[17],B8[18],B9[18] buffer bnl_op_1 lc_trk_g2_1 -!B12[15],!B12[16],B12[17],B12[18],B13[18] buffer bnl_op_1 lc_trk_g3_1 -B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer bnl_op_2 lc_trk_g2_2 -B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer bnl_op_2 lc_trk_g3_2 -B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer bnl_op_3 lc_trk_g2_3 -B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer bnl_op_3 lc_trk_g3_3 -B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer bnl_op_4 lc_trk_g2_4 -B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer bnl_op_4 lc_trk_g3_4 -!B10[15],!B10[16],B10[17],B10[18],B11[18] buffer bnl_op_5 lc_trk_g2_5 -!B14[15],!B14[16],B14[17],B14[18],B15[18] buffer bnl_op_5 lc_trk_g3_5 -B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer bnl_op_6 lc_trk_g2_6 -B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer bnl_op_6 lc_trk_g3_6 -B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer bnl_op_7 lc_trk_g2_7 -B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer bnl_op_7 lc_trk_g3_7 -B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer bnr_op_0 lc_trk_g0_0 -B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer bnr_op_0 lc_trk_g1_0 -!B0[15],!B0[16],B0[17],B0[18],B1[18] buffer bnr_op_1 lc_trk_g0_1 -!B4[15],!B4[16],B4[17],B4[18],B5[18] buffer bnr_op_1 lc_trk_g1_1 -B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer bnr_op_2 lc_trk_g0_2 -B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer bnr_op_2 lc_trk_g1_2 -B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer bnr_op_3 lc_trk_g0_3 -B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer bnr_op_3 lc_trk_g1_3 -B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer bnr_op_4 lc_trk_g0_4 -B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer bnr_op_4 lc_trk_g1_4 -!B2[15],!B2[16],B2[17],B2[18],B3[18] buffer bnr_op_5 lc_trk_g0_5 -!B6[15],!B6[16],B6[17],B6[18],B7[18] buffer bnr_op_5 lc_trk_g1_5 -B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer bnr_op_6 lc_trk_g0_6 -B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer bnr_op_6 lc_trk_g1_6 -B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer bnr_op_7 lc_trk_g0_7 -B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7 -!B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer bot_op_0 lc_trk_g0_0 -!B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer bot_op_0 lc_trk_g1_0 -!B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer bot_op_2 lc_trk_g0_2 -!B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer bot_op_2 lc_trk_g1_2 -!B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer bot_op_4 lc_trk_g0_4 -!B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer bot_op_4 lc_trk_g1_4 -!B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer bot_op_6 lc_trk_g0_6 -!B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer bot_op_6 lc_trk_g1_6 -!B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer glb2local_0 lc_trk_g0_4 -!B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer glb2local_1 lc_trk_g0_5 -!B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6 -!B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer glb2local_3 lc_trk_g0_7 -!B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0 -!B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1 -!B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2 -!B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3 -!B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_1 wire_bram/ram/RCLK -B10[0],B10[1],!B11[0],!B11[1] buffer glb_netwk_2 glb2local_2 -B12[0],B12[1],!B13[0],!B13[1] buffer glb_netwk_2 glb2local_3 -B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_bram/ram/RCLK -!B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_2 wire_bram/ram/RE -B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0 -B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_3 glb2local_1 -B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_3 glb2local_2 -B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_3 glb2local_3 -B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_3 wire_bram/ram/RCLK -!B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_4 glb2local_0 -!B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_4 glb2local_1 -!B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_4 glb2local_2 -!B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_4 glb2local_3 -!B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 wire_bram/ram/RCLK -B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_bram/ram/RE -!B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0 -!B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_5 glb2local_1 -!B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2 -!B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3 -!B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_bram/ram/RCLK -B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_6 glb2local_0 -B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_6 glb2local_1 -B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2 -B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_6 glb2local_3 -B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_6 wire_bram/ram/RCLK -B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_bram/ram/RE -B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_7 glb2local_0 -B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_7 glb2local_2 -B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_7 glb2local_3 -B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/RCLK -!B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 input0_0 -!B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_0 input0_2 -!B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_0 input0_4 -!B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_0 input0_6 -!B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_0 input2_6 -!B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g0_0 wire_bram/ram/RCLK -!B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_10 -!B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_12 -!B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_14 -!B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_8 -!B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_1 input0_1 -!B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_1 input0_3 -!B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_1 input0_5 -!B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_1 input0_7 -!B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_1 input2_5 -!B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_1 input2_7 -!B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_11 -!B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_13 -!B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_15 -!B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_9 -!B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_2 input0_0 -!B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_2 input0_2 -!B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_2 input0_4 -!B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_2 input0_6 -!B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_2 input2_6 -!B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_10 -!B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_12 -!B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_14 -!B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_8 -!B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g0_2 wire_bram/ram/RCLKE -!B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_10 -!B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_12 -!B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_14 -!B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_8 -!B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_3 input0_1 -!B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_3 input0_3 -!B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_3 input0_5 -!B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_3 input0_7 -!B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_3 input2_5 -!B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_3 input2_7 -!B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_11 -!B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_13 -!B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_15 -!B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_9 -!B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_11 -!B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_13 -!B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_15 -!B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_9 -B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_4 input0_0 -B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_4 input0_2 -B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_4 input0_4 -B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_4 input0_6 -B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_4 input2_6 -B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_10 -B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_12 -B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_14 -B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_8 -!B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_bram/ram/RE -!B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_10 -!B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_12 -!B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_14 -!B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_8 -B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_5 input0_1 -B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_5 input0_3 -B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_5 input0_5 -B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_5 input0_7 -B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_5 input2_5 -B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_5 input2_7 -B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_11 -B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_13 -B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_15 -B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_9 -!B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_11 -!B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_13 -!B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_15 -!B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_9 -B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_6 input0_0 -B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_6 input0_2 -B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_6 input0_4 -B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_6 input0_6 -B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_6 input2_6 -B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_10 -B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_12 -B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_14 -B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_8 -!B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_10 -!B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_12 -!B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_14 -!B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_8 -B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_7 input0_1 -B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_7 input0_3 -B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_7 input0_5 -B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_7 input0_7 -B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_7 input2_5 -B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_7 input2_7 -B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_11 -B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_13 -B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_15 -B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_9 -!B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_11 -!B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_13 -!B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_15 -!B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_9 -!B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_0 input0_1 -!B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_0 input0_3 -!B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_0 input0_5 -!B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_0 input0_7 -!B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_0 input2_5 -!B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_0 input2_7 -!B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_11 -!B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_13 -!B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_15 -!B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_9 -B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_11 -B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_13 -B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_15 -B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_9 -!B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_1 input0_0 -!B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_1 input0_2 -!B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_1 input0_4 -!B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_1 input0_6 -!B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_1 input2_6 -!B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_10 -!B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_12 -!B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_14 -!B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_8 -!B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g1_1 wire_bram/ram/RCLK -B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_10 -B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_12 -B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_14 -B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_8 -!B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_2 input0_1 -!B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_2 input0_3 -!B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_2 input0_5 -!B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_2 input0_7 -!B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_2 input2_5 -!B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_2 input2_7 -!B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_11 -!B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_13 -!B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_15 -!B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_9 -B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_11 -B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_13 -B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_15 -B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_9 -!B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_3 input0_0 -!B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_3 input0_2 -!B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_3 input0_4 -!B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_3 input0_6 -!B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_3 input2_6 -!B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_10 -!B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_12 -!B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_14 -!B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_8 -!B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g1_3 wire_bram/ram/RCLKE -B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_10 -B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_12 -B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_14 -B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_8 -B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_4 input0_1 -B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_4 input0_3 -B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_4 input0_5 -B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_4 input0_7 -B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_4 input2_5 -B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_4 input2_7 -B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_11 -B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_13 -B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_15 -B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_9 -B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_11 -B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_13 -B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_15 -B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_9 -B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_5 input0_0 -B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_5 input0_2 -B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_5 input0_4 -B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_5 input0_6 -B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_5 input2_6 -B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_10 -B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_12 -B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_14 -B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_8 -!B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_bram/ram/RE -B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_10 -B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_12 -B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_14 -B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_8 -B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_6 input0_1 -B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_6 input0_3 -B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_6 input0_5 -B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_6 input0_7 -B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_6 input2_5 -B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_6 input2_7 -B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_11 -B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_13 -B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_15 -B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_9 -B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_11 -B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_13 -B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_15 -B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_9 -B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_7 input0_0 -B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_7 input0_2 -B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_7 input0_4 -B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_7 input0_6 -B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_7 input2_6 -B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_10 -B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_12 -B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_14 -B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_8 -B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_10 -B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_12 -B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_14 -B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_8 -!B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 input0_0 -!B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_0 input0_2 -!B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_0 input0_4 -!B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_0 input0_6 -!B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_0 input2_6 -!B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_10 -!B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_12 -!B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_14 -!B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_8 -B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/RCLK -!B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_10 -!B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_12 -!B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_14 -!B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_8 -!B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_1 input0_1 -!B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_1 input0_3 -!B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_1 input0_5 -!B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_1 input0_7 -!B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_1 input2_5 -!B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_1 input2_7 -!B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_11 -!B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_13 -!B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_15 -!B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_9 -!B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_11 -!B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_13 -!B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_15 -!B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_9 -!B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_2 input0_0 -!B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_2 input0_2 -!B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_2 input0_4 -!B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_2 input0_6 -!B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_2 input2_6 -!B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_10 -!B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_12 -!B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_14 -!B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_8 -B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_bram/ram/RCLKE -!B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_10 -!B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_12 -!B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_14 -!B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_8 -!B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_3 input0_1 -!B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_3 input0_3 -!B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_3 input0_5 -!B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_3 input0_7 -!B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_3 input2_5 -!B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_3 input2_7 -!B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_11 -!B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_13 -!B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_15 -!B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_9 -!B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_11 -!B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_13 -!B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_15 -!B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_9 -B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_4 input0_0 -B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_4 input0_2 -B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_4 input0_4 -B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_4 input0_6 -B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_4 input2_6 -B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_10 -B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_12 -B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_14 -B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_8 -B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_bram/ram/RE -!B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_10 -!B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_12 -!B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_14 -!B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_8 -B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_5 input0_1 -B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_5 input0_3 -B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_5 input0_5 -B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_5 input0_7 -B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_5 input2_5 -B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_5 input2_7 -B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_11 -B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_13 -B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_15 -B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_9 -!B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_11 -!B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_13 -!B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_15 -!B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_9 -B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_6 input0_0 -B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_6 input0_2 -B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_6 input0_4 -B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_6 input0_6 -B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_6 input2_6 -B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_10 -B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_12 -B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_14 -B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_8 -!B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_10 -!B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_12 -!B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_14 -!B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_8 -B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_7 input0_1 -B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_7 input0_3 -B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_7 input0_5 -B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_7 input0_7 -B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_7 input2_5 -B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_7 input2_7 -B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_11 -B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_13 -B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_15 -B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_9 -!B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_11 -!B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_13 -!B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_15 -!B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_9 -!B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_0 input0_1 -!B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_0 input0_3 -!B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_0 input0_5 -!B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_0 input0_7 -!B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_0 input2_5 -!B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_0 input2_7 -!B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_11 -!B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_13 -!B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_15 -!B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_9 -B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_11 -B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_13 -B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_15 -B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_9 -!B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_1 input0_0 -!B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_1 input0_2 -!B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_1 input0_4 -!B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_1 input0_6 -!B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_1 input2_6 -!B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_10 -!B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_12 -!B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_14 -!B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_8 -B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g3_1 wire_bram/ram/RCLK -B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_10 -B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_12 -B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_14 -B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_8 -!B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_2 input0_1 -!B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_2 input0_3 -!B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_2 input0_5 -!B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_2 input0_7 -!B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_2 input2_5 -!B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_2 input2_7 -!B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_11 -!B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_13 -!B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_15 -!B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_9 -B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_11 -B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_13 -B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_15 -B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_9 -!B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_3 input0_0 -!B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_3 input0_2 -!B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_3 input0_4 -!B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_3 input0_6 -!B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_3 input2_6 -!B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_10 -!B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_12 -!B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_14 -!B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_8 -B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g3_3 wire_bram/ram/RCLKE -B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_10 -B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_12 -B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_14 -B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_8 -B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_4 input0_1 -B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_4 input0_3 -B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_4 input0_5 -B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_4 input0_7 -B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_4 input2_5 -B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_4 input2_7 -B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_11 -B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_13 -B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_15 -B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_9 -B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_11 -B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_13 -B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_15 -B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_9 -B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_5 input0_0 -B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_5 input0_2 -B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_5 input0_4 -B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_5 input0_6 -B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_5 input2_6 -B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_10 -B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_12 -B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_14 -B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_8 -B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g3_5 wire_bram/ram/RE -B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_10 -B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_12 -B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_14 -B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_8 -B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_6 input0_1 -B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_6 input0_3 -B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_6 input0_5 -B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_6 input0_7 -B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_6 input2_5 -B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_6 input2_7 -B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_11 -B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_13 -B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_15 -B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_9 -B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_11 -B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_13 -B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_15 -B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_9 -B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_7 input0_0 -B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_7 input0_2 -B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_7 input0_4 -B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_7 input0_6 -B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_7 input2_6 -B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_10 -B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_12 -B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_14 -B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_8 -B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_10 -B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_12 -B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_14 -B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_8 -B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer lft_op_0 lc_trk_g0_0 -B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer lft_op_0 lc_trk_g1_0 -B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer lft_op_1 lc_trk_g0_1 -B4[15],!B4[16],B4[17],B4[18],!B5[18] buffer lft_op_1 lc_trk_g1_1 -B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer lft_op_2 lc_trk_g0_2 -B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer lft_op_2 lc_trk_g1_2 -B0[21],B0[22],!B0[23],B0[24],!B1[21] buffer lft_op_3 lc_trk_g0_3 -B4[21],B4[22],!B4[23],B4[24],!B5[21] buffer lft_op_3 lc_trk_g1_3 -B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer lft_op_4 lc_trk_g0_4 -B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer lft_op_4 lc_trk_g1_4 -B2[15],!B2[16],B2[17],B2[18],!B3[18] buffer lft_op_5 lc_trk_g0_5 -B6[15],!B6[16],B6[17],B6[18],!B7[18] buffer lft_op_5 lc_trk_g1_5 -B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer lft_op_6 lc_trk_g0_6 -B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer lft_op_6 lc_trk_g1_6 -B2[21],B2[22],!B2[23],B2[24],!B3[21] buffer lft_op_7 lc_trk_g0_7 -B6[21],B6[22],!B6[23],B6[24],!B7[21] buffer lft_op_7 lc_trk_g1_7 -B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer rgt_op_0 lc_trk_g2_0 -B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer rgt_op_0 lc_trk_g3_0 -B8[15],!B8[16],B8[17],B8[18],!B9[18] buffer rgt_op_1 lc_trk_g2_1 -B12[15],!B12[16],B12[17],B12[18],!B13[18] buffer rgt_op_1 lc_trk_g3_1 -B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer rgt_op_2 lc_trk_g2_2 -B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer rgt_op_2 lc_trk_g3_2 -B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer rgt_op_3 lc_trk_g2_3 -B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer rgt_op_3 lc_trk_g3_3 -B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer rgt_op_4 lc_trk_g2_4 -B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer rgt_op_4 lc_trk_g3_4 -B10[15],!B10[16],B10[17],B10[18],!B11[18] buffer rgt_op_5 lc_trk_g2_5 -B14[15],!B14[16],B14[17],B14[18],!B15[18] buffer rgt_op_5 lc_trk_g3_5 -B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer rgt_op_6 lc_trk_g2_6 -B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer rgt_op_6 lc_trk_g3_6 -B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer rgt_op_7 lc_trk_g2_7 -B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer rgt_op_7 lc_trk_g3_7 -B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_l_1 lc_trk_g0_2 -B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_l_1 lc_trk_g1_2 -B12[19] buffer sp12_h_l_1 sp4_h_r_13 -!B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_l_10 lc_trk_g0_5 -!B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_l_10 lc_trk_g1_5 -!B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp12_h_l_12 lc_trk_g0_7 -!B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp12_h_l_12 lc_trk_g1_7 -!B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp12_h_l_14 lc_trk_g0_1 -!B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_l_14 lc_trk_g1_1 -!B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_l_15 lc_trk_g0_0 -!B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_l_15 lc_trk_g1_0 -B8[2] buffer sp12_h_l_15 sp4_h_l_9 -!B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp12_h_l_16 lc_trk_g0_3 -!B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp12_h_l_16 lc_trk_g1_3 -!B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_l_17 lc_trk_g0_2 -!B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp12_h_l_17 lc_trk_g1_2 -B10[2] buffer sp12_h_l_17 sp4_h_r_21 -B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_l_2 lc_trk_g0_5 -B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_l_2 lc_trk_g1_5 -!B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_l_20 lc_trk_g0_7 -!B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_l_20 lc_trk_g1_7 -B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_l_3 lc_trk_g0_4 -B6[14],B7[14],B7[15],!B7[16],B7[17] buffer sp12_h_l_3 lc_trk_g1_4 -B15[19] buffer sp12_h_l_3 sp4_h_l_3 -B2[25],B3[22],!B3[23],B3[24],B3[25] buffer sp12_h_l_5 lc_trk_g0_6 -B6[25],B7[22],!B7[23],B7[24],B7[25] buffer sp12_h_l_5 lc_trk_g1_6 -B14[19] buffer sp12_h_l_5 sp4_h_r_15 -!B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_l_9 lc_trk_g0_2 -!B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_l_9 lc_trk_g1_2 -B3[1] buffer sp12_h_l_9 sp4_h_r_17 -B0[14],B1[14],B1[15],!B1[16],B1[17] buffer sp12_h_r_0 lc_trk_g0_0 -B4[14],B5[14],B5[15],!B5[16],B5[17] buffer sp12_h_r_0 lc_trk_g1_0 -B13[19] buffer sp12_h_r_0 sp4_h_l_1 -B0[15],!B0[16],B0[17],B0[18],B1[18] buffer sp12_h_r_1 lc_trk_g0_1 -B4[15],!B4[16],B4[17],B4[18],B5[18] buffer sp12_h_r_1 lc_trk_g1_1 -!B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp12_h_r_11 lc_trk_g0_3 -!B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp12_h_r_11 lc_trk_g1_3 -!B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_12 lc_trk_g0_4 -!B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_12 lc_trk_g1_4 -B4[2] buffer sp12_h_r_12 sp4_h_r_18 -!B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_r_14 lc_trk_g0_6 -!B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_r_14 lc_trk_g1_6 -B6[2] buffer sp12_h_r_14 sp4_h_l_6 -!B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_20 lc_trk_g0_4 -!B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_20 lc_trk_g1_4 -B12[2] buffer sp12_h_r_20 sp4_h_l_11 -!B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp12_h_r_21 lc_trk_g0_5 -!B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp12_h_r_21 lc_trk_g1_5 -!B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_r_22 lc_trk_g0_6 -!B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_r_22 lc_trk_g1_6 -B14[2] buffer sp12_h_r_22 sp4_h_r_23 -B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_r_3 lc_trk_g0_3 -B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_r_3 lc_trk_g1_3 -B2[21],B2[22],!B2[23],B2[24],B3[21] buffer sp12_h_r_7 lc_trk_g0_7 -B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_r_7 lc_trk_g1_7 -!B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_8 lc_trk_g0_0 -!B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_8 lc_trk_g1_0 -B0[2] buffer sp12_h_r_8 sp4_h_r_16 -!B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp12_h_r_9 lc_trk_g0_1 -!B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_r_9 lc_trk_g1_1 -B8[14],B9[14],B9[15],!B9[16],B9[17] buffer sp12_v_b_0 lc_trk_g2_0 -B12[14],B13[14],B13[15],!B13[16],B13[17] buffer sp12_v_b_0 lc_trk_g3_0 -B8[15],!B8[16],B8[17],B8[18],B9[18] buffer sp12_v_b_1 lc_trk_g2_1 -B12[15],!B12[16],B12[17],B12[18],B13[18] buffer sp12_v_b_1 lc_trk_g3_1 -B1[19] buffer sp12_v_b_1 sp4_v_b_12 -!B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_b_10 lc_trk_g2_2 -!B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp12_v_b_10 lc_trk_g3_2 -!B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp12_v_b_13 lc_trk_g2_5 -!B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp12_v_b_13 lc_trk_g3_5 -B7[19] buffer sp12_v_b_13 sp4_v_t_7 -!B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp12_v_b_14 lc_trk_g2_6 -!B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp12_v_b_14 lc_trk_g3_6 -!B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_16 lc_trk_g2_0 -!B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_b_16 lc_trk_g3_0 -!B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp12_v_b_18 lc_trk_g2_2 -!B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp12_v_b_18 lc_trk_g3_2 -!B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp12_v_b_19 lc_trk_g2_3 -!B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp12_v_b_19 lc_trk_g3_3 -B8[19] buffer sp12_v_b_19 sp4_v_t_8 -!B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_20 lc_trk_g2_4 -!B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_20 lc_trk_g3_4 -!B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_b_22 lc_trk_g2_6 -!B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_b_22 lc_trk_g3_6 -B8[21],B8[22],!B8[23],B8[24],B9[21] buffer sp12_v_b_3 lc_trk_g2_3 -B12[21],B12[22],!B12[23],B12[24],B13[21] buffer sp12_v_b_3 lc_trk_g3_3 -B0[19] buffer sp12_v_b_3 sp4_v_b_13 -B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_b_4 lc_trk_g2_4 -B14[14],B15[14],B15[15],!B15[16],B15[17] buffer sp12_v_b_4 lc_trk_g3_4 -B10[15],!B10[16],B10[17],B10[18],B11[18] buffer sp12_v_b_5 lc_trk_g2_5 -B14[15],!B14[16],B14[17],B14[18],B15[18] buffer sp12_v_b_5 lc_trk_g3_5 -B3[19] buffer sp12_v_b_5 sp4_v_b_14 -!B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp12_v_b_9 lc_trk_g2_1 -!B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp12_v_b_9 lc_trk_g3_1 -B5[19] buffer sp12_v_b_9 sp4_v_b_16 -B8[25],B9[22],!B9[23],B9[24],B9[25] buffer sp12_v_t_1 lc_trk_g2_2 -B12[25],B13[22],!B13[23],B13[24],B13[25] buffer sp12_v_t_1 lc_trk_g3_2 -!B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_t_11 lc_trk_g2_4 -!B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_t_11 lc_trk_g3_4 -!B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp12_v_t_12 lc_trk_g2_7 -!B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp12_v_t_12 lc_trk_g3_7 -B6[19] buffer sp12_v_t_12 sp4_v_t_6 -!B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp12_v_t_14 lc_trk_g2_1 -!B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp12_v_t_14 lc_trk_g3_1 -B9[19] buffer sp12_v_t_14 sp4_v_b_20 -!B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp12_v_t_18 lc_trk_g2_5 -!B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp12_v_t_18 lc_trk_g3_5 -B11[19] buffer sp12_v_t_18 sp4_v_t_11 -!B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp12_v_t_20 lc_trk_g2_7 -!B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp12_v_t_20 lc_trk_g3_7 -B10[19] buffer sp12_v_t_20 sp4_v_b_23 -B10[21],B10[22],!B10[23],B10[24],B11[21] buffer sp12_v_t_4 lc_trk_g2_7 -B14[21],B14[22],!B14[23],B14[24],B15[21] buffer sp12_v_t_4 lc_trk_g3_7 -B2[19] buffer sp12_v_t_4 sp4_v_t_2 -B10[25],B11[22],!B11[23],B11[24],B11[25] buffer sp12_v_t_5 lc_trk_g2_6 -B14[25],B15[22],!B15[23],B15[24],B15[25] buffer sp12_v_t_5 lc_trk_g3_6 -!B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_t_7 lc_trk_g2_0 -!B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_t_7 lc_trk_g3_0 -!B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp12_v_t_8 lc_trk_g2_3 -!B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_t_8 lc_trk_g3_3 -B4[19] buffer sp12_v_t_8 sp4_v_t_4 -B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_1 lc_trk_g0_4 -B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_1 lc_trk_g1_4 -B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_l_11 lc_trk_g0_6 -B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_l_11 lc_trk_g1_6 -!B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_l_14 lc_trk_g2_3 -!B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_l_14 lc_trk_g3_3 -!B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_l_15 lc_trk_g2_2 -!B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_l_15 lc_trk_g3_2 -!B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_l_19 lc_trk_g2_6 -!B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_l_19 lc_trk_g3_6 -B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_l_22 lc_trk_g2_3 -B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_l_22 lc_trk_g3_3 -B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_l_26 lc_trk_g2_7 -B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_l_26 lc_trk_g3_7 -B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_l_27 lc_trk_g2_6 -B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_l_27 lc_trk_g3_6 -B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_h_l_28 lc_trk_g2_1 -B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_h_l_28 lc_trk_g3_1 -B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_h_l_3 lc_trk_g0_6 -B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_h_l_3 lc_trk_g1_6 -B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_l_6 lc_trk_g0_3 -B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_l_6 lc_trk_g1_3 -B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_l_9 lc_trk_g0_4 -B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_l_9 lc_trk_g1_4 -!B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_0 lc_trk_g0_0 -!B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_0 lc_trk_g1_0 -B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp4_h_r_1 lc_trk_g0_1 -B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp4_h_r_1 lc_trk_g1_1 -B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_h_r_10 lc_trk_g0_2 -B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_h_r_10 lc_trk_g1_2 -B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_h_r_11 lc_trk_g0_3 -B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_h_r_11 lc_trk_g1_3 -B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_h_r_13 lc_trk_g0_5 -B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_h_r_13 lc_trk_g1_5 -B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_h_r_15 lc_trk_g0_7 -B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_r_15 lc_trk_g1_7 -B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_16 lc_trk_g0_0 -B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_16 lc_trk_g1_0 -B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_h_r_17 lc_trk_g0_1 -B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_h_r_17 lc_trk_g1_1 -B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_18 lc_trk_g0_2 -B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_18 lc_trk_g1_2 -!B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_2 lc_trk_g0_2 -!B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_2 lc_trk_g1_2 -B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_r_21 lc_trk_g0_5 -B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_r_21 lc_trk_g1_5 -B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_23 lc_trk_g0_7 -B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_23 lc_trk_g1_7 -!B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_24 lc_trk_g2_0 -!B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_24 lc_trk_g3_0 -B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp4_h_r_25 lc_trk_g2_1 -B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp4_h_r_25 lc_trk_g3_1 -!B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_28 lc_trk_g2_4 -!B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_28 lc_trk_g3_4 -B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_r_29 lc_trk_g2_5 -B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_r_29 lc_trk_g3_5 -!B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_3 lc_trk_g0_3 -!B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_3 lc_trk_g1_3 -!B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_31 lc_trk_g2_7 -!B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_31 lc_trk_g3_7 -B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_32 lc_trk_g2_0 -B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_32 lc_trk_g3_0 -B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_h_r_33 lc_trk_g2_1 -B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_h_r_33 lc_trk_g3_1 -B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_h_r_34 lc_trk_g2_2 -B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_h_r_34 lc_trk_g3_2 -B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_36 lc_trk_g2_4 -B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_36 lc_trk_g3_4 -B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_h_r_37 lc_trk_g2_5 -B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_h_r_37 lc_trk_g3_5 -!B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_4 lc_trk_g0_4 -!B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_4 lc_trk_g1_4 -B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_r_40 lc_trk_g2_0 -B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_r_40 lc_trk_g3_0 -B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_r_42 lc_trk_g2_2 -B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_r_42 lc_trk_g3_2 -B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_43 lc_trk_g2_3 -B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_43 lc_trk_g3_3 -B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_44 lc_trk_g2_4 -B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_44 lc_trk_g3_4 -B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_h_r_45 lc_trk_g2_5 -B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_h_r_45 lc_trk_g3_5 -B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_46 lc_trk_g2_6 -B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_46 lc_trk_g3_6 -B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_47 lc_trk_g2_7 -B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_47 lc_trk_g3_7 -B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp4_h_r_5 lc_trk_g0_5 -B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5 -!B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_6 lc_trk_g0_6 -!B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_6 lc_trk_g1_6 -!B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_7 lc_trk_g0_7 -!B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_7 lc_trk_g1_7 -B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_8 lc_trk_g0_0 -B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_8 lc_trk_g1_0 -B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_h_r_9 lc_trk_g0_1 -B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_h_r_9 lc_trk_g1_1 -!B4[14],!B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_0 lc_trk_g1_0 -!B4[15],!B4[16],B4[17],!B4[18],!B5[18] buffer sp4_r_v_b_1 lc_trk_g1_1 -!B8[25],B9[22],!B9[23],!B9[24],!B9[25] buffer sp4_r_v_b_10 lc_trk_g2_2 -!B8[21],B8[22],!B8[23],!B8[24],!B9[21] buffer sp4_r_v_b_11 lc_trk_g2_3 -!B10[14],!B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_12 lc_trk_g2_4 -!B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer sp4_r_v_b_13 lc_trk_g2_5 -!B10[25],B11[22],!B11[23],!B11[24],!B11[25] buffer sp4_r_v_b_14 lc_trk_g2_6 -!B10[21],B10[22],!B10[23],!B10[24],!B11[21] buffer sp4_r_v_b_15 lc_trk_g2_7 -!B12[14],!B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_16 lc_trk_g3_0 -!B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer sp4_r_v_b_17 lc_trk_g3_1 -!B12[25],B13[22],!B13[23],!B13[24],!B13[25] buffer sp4_r_v_b_18 lc_trk_g3_2 -!B12[21],B12[22],!B12[23],!B12[24],!B13[21] buffer sp4_r_v_b_19 lc_trk_g3_3 -!B4[25],B5[22],!B5[23],!B5[24],!B5[25] buffer sp4_r_v_b_2 lc_trk_g1_2 -!B14[14],!B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_20 lc_trk_g3_4 -!B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer sp4_r_v_b_21 lc_trk_g3_5 -!B14[25],B15[22],!B15[23],!B15[24],!B15[25] buffer sp4_r_v_b_22 lc_trk_g3_6 -!B14[21],B14[22],!B14[23],!B14[24],!B15[21] buffer sp4_r_v_b_23 lc_trk_g3_7 -!B0[14],!B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_24 lc_trk_g0_0 -!B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_24 lc_trk_g1_0 -!B0[15],!B0[16],B0[17],!B0[18],!B1[18] buffer sp4_r_v_b_25 lc_trk_g0_1 -!B4[15],!B4[16],B4[17],!B4[18],B5[18] buffer sp4_r_v_b_25 lc_trk_g1_1 -!B0[25],B1[22],!B1[23],!B1[24],!B1[25] buffer sp4_r_v_b_26 lc_trk_g0_2 -!B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer sp4_r_v_b_26 lc_trk_g1_2 -!B0[21],B0[22],!B0[23],!B0[24],!B1[21] buffer sp4_r_v_b_27 lc_trk_g0_3 -!B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer sp4_r_v_b_27 lc_trk_g1_3 -!B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer sp4_r_v_b_28 lc_trk_g0_4 -!B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_28 lc_trk_g1_4 -!B2[15],!B2[16],B2[17],!B2[18],B3[18] buffer sp4_r_v_b_29 lc_trk_g0_5 -!B6[15],!B6[16],B6[17],!B6[18],B7[18] buffer sp4_r_v_b_29 lc_trk_g1_5 -!B4[21],B4[22],!B4[23],!B4[24],!B5[21] buffer sp4_r_v_b_3 lc_trk_g1_3 -!B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer sp4_r_v_b_30 lc_trk_g0_6 -!B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer sp4_r_v_b_30 lc_trk_g1_6 -!B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer sp4_r_v_b_31 lc_trk_g0_7 -!B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer sp4_r_v_b_31 lc_trk_g1_7 -!B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer sp4_r_v_b_32 lc_trk_g0_3 -!B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_32 lc_trk_g2_0 -!B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer sp4_r_v_b_33 lc_trk_g0_2 -!B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer sp4_r_v_b_33 lc_trk_g2_1 -!B0[15],!B0[16],B0[17],!B0[18],B1[18] buffer sp4_r_v_b_34 lc_trk_g0_1 -!B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer sp4_r_v_b_34 lc_trk_g2_2 -!B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_35 lc_trk_g0_0 -!B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer sp4_r_v_b_35 lc_trk_g2_3 -!B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_36 lc_trk_g2_4 -!B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer sp4_r_v_b_37 lc_trk_g2_5 -!B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer sp4_r_v_b_38 lc_trk_g2_6 -!B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer sp4_r_v_b_39 lc_trk_g2_7 -!B6[14],!B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_4 lc_trk_g1_4 -!B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_40 lc_trk_g3_0 -!B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer sp4_r_v_b_41 lc_trk_g3_1 -!B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer sp4_r_v_b_42 lc_trk_g3_2 -!B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer sp4_r_v_b_43 lc_trk_g3_3 -!B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_44 lc_trk_g3_4 -!B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer sp4_r_v_b_45 lc_trk_g3_5 -!B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer sp4_r_v_b_46 lc_trk_g3_6 -!B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer sp4_r_v_b_47 lc_trk_g3_7 -!B6[15],!B6[16],B6[17],!B6[18],!B7[18] buffer sp4_r_v_b_5 lc_trk_g1_5 -!B6[25],B7[22],!B7[23],!B7[24],!B7[25] buffer sp4_r_v_b_6 lc_trk_g1_6 -!B6[21],B6[22],!B6[23],!B6[24],!B7[21] buffer sp4_r_v_b_7 lc_trk_g1_7 -!B8[14],!B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_8 lc_trk_g2_0 -!B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer sp4_r_v_b_9 lc_trk_g2_1 -B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_0 lc_trk_g0_0 -B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_0 lc_trk_g1_0 -!B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_v_b_1 lc_trk_g0_1 -!B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_v_b_1 lc_trk_g1_1 -B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp4_v_b_10 lc_trk_g0_2 -B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp4_v_b_10 lc_trk_g1_2 -B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp4_v_b_11 lc_trk_g0_3 -B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp4_v_b_11 lc_trk_g1_3 -B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_12 lc_trk_g0_4 -B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_12 lc_trk_g1_4 -!B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_v_b_13 lc_trk_g0_5 -!B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_v_b_13 lc_trk_g1_5 -B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp4_v_b_14 lc_trk_g0_6 -B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp4_v_b_14 lc_trk_g1_6 -!B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_v_b_16 lc_trk_g0_0 -!B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_v_b_16 lc_trk_g1_0 -B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp4_v_b_2 lc_trk_g0_2 -B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp4_v_b_2 lc_trk_g1_2 -!B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_v_b_20 lc_trk_g0_4 -!B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_v_b_20 lc_trk_g1_4 -!B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_v_b_23 lc_trk_g0_7 -!B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_v_b_23 lc_trk_g1_7 -!B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_v_b_25 lc_trk_g2_1 -!B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_v_b_25 lc_trk_g3_1 -B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp4_v_b_27 lc_trk_g2_3 -B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp4_v_b_27 lc_trk_g3_3 -B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_b_28 lc_trk_g2_4 -B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_b_28 lc_trk_g3_4 -!B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_v_b_29 lc_trk_g2_5 -!B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_v_b_29 lc_trk_g3_5 -B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp4_v_b_3 lc_trk_g0_3 -B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp4_v_b_3 lc_trk_g1_3 -B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp4_v_b_31 lc_trk_g2_7 -B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp4_v_b_31 lc_trk_g3_7 -B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_b_32 lc_trk_g2_0 -B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_b_32 lc_trk_g3_0 -B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp4_v_b_34 lc_trk_g2_2 -B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp4_v_b_34 lc_trk_g3_2 -B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp4_v_b_35 lc_trk_g2_3 -B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp4_v_b_35 lc_trk_g3_3 -B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_4 lc_trk_g0_4 -B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_4 lc_trk_g1_4 -!B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_v_b_40 lc_trk_g2_0 -!B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_v_b_40 lc_trk_g3_0 -B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp4_v_b_41 lc_trk_g2_1 -B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp4_v_b_41 lc_trk_g3_1 -!B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_v_b_43 lc_trk_g2_3 -!B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_b_43 lc_trk_g3_3 -!B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_b_44 lc_trk_g2_4 -!B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_b_44 lc_trk_g3_4 -B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp4_v_b_45 lc_trk_g2_5 -B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp4_v_b_45 lc_trk_g3_5 -!B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_v_b_46 lc_trk_g2_6 -!B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_v_b_46 lc_trk_g3_6 -!B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_v_b_5 lc_trk_g0_5 -!B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_v_b_5 lc_trk_g1_5 -B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp4_v_b_6 lc_trk_g0_6 -B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp4_v_b_6 lc_trk_g1_6 -B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp4_v_b_7 lc_trk_g0_7 -B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp4_v_b_7 lc_trk_g1_7 -B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_8 lc_trk_g0_0 -B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_8 lc_trk_g1_0 -!B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_v_b_9 lc_trk_g0_1 -!B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_v_b_9 lc_trk_g1_1 -!B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_v_t_11 lc_trk_g0_6 -!B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_v_t_11 lc_trk_g1_6 -B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_13 lc_trk_g2_0 -B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_13 lc_trk_g3_0 -B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp4_v_t_15 lc_trk_g2_2 -B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp4_v_t_15 lc_trk_g3_2 -B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp4_v_t_19 lc_trk_g2_6 -B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp4_v_t_19 lc_trk_g3_6 -B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp4_v_t_2 lc_trk_g0_7 -B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp4_v_t_2 lc_trk_g1_7 -!B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_v_t_20 lc_trk_g2_1 -!B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_v_t_20 lc_trk_g3_1 -!B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_v_t_24 lc_trk_g2_5 -!B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_v_t_24 lc_trk_g3_5 -B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_t_25 lc_trk_g2_4 -B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_t_25 lc_trk_g3_4 -B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp4_v_t_26 lc_trk_g2_7 -B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp4_v_t_26 lc_trk_g3_7 -B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp4_v_t_27 lc_trk_g2_6 -B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp4_v_t_27 lc_trk_g3_6 -!B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_v_t_31 lc_trk_g2_2 -!B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_v_t_31 lc_trk_g3_2 -!B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_v_t_34 lc_trk_g2_7 -!B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_v_t_34 lc_trk_g3_7 -B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp4_v_t_4 lc_trk_g0_1 -B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp4_v_t_4 lc_trk_g1_1 -!B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_v_t_6 lc_trk_g0_3 -!B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_v_t_6 lc_trk_g1_3 -!B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_v_t_7 lc_trk_g0_2 -!B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_v_t_7 lc_trk_g1_2 -B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp4_v_t_8 lc_trk_g0_5 -B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp4_v_t_8 lc_trk_g1_5 -!B8[14],B9[14],B9[15],!B9[16],B9[17] buffer tnl_op_0 lc_trk_g2_0 -!B12[14],B13[14],B13[15],!B13[16],B13[17] buffer tnl_op_0 lc_trk_g3_0 -B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer tnl_op_1 lc_trk_g2_1 -B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer tnl_op_1 lc_trk_g3_1 -!B8[25],B9[22],!B9[23],B9[24],B9[25] buffer tnl_op_2 lc_trk_g2_2 -!B12[25],B13[22],!B13[23],B13[24],B13[25] buffer tnl_op_2 lc_trk_g3_2 -!B8[21],B8[22],!B8[23],B8[24],B9[21] buffer tnl_op_3 lc_trk_g2_3 -!B12[21],B12[22],!B12[23],B12[24],B13[21] buffer tnl_op_3 lc_trk_g3_3 -!B10[14],B11[14],B11[15],!B11[16],B11[17] buffer tnl_op_4 lc_trk_g2_4 -!B14[14],B15[14],B15[15],!B15[16],B15[17] buffer tnl_op_4 lc_trk_g3_4 -B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer tnl_op_5 lc_trk_g2_5 -B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer tnl_op_5 lc_trk_g3_5 -!B10[25],B11[22],!B11[23],B11[24],B11[25] buffer tnl_op_6 lc_trk_g2_6 -!B14[25],B15[22],!B15[23],B15[24],B15[25] buffer tnl_op_6 lc_trk_g3_6 -!B10[21],B10[22],!B10[23],B10[24],B11[21] buffer tnl_op_7 lc_trk_g2_7 -!B14[21],B14[22],!B14[23],B14[24],B15[21] buffer tnl_op_7 lc_trk_g3_7 -!B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer tnr_op_0 lc_trk_g2_0 -!B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer tnr_op_0 lc_trk_g3_0 -B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer tnr_op_1 lc_trk_g2_1 -B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer tnr_op_1 lc_trk_g3_1 -!B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer tnr_op_2 lc_trk_g2_2 -!B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer tnr_op_2 lc_trk_g3_2 -!B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer tnr_op_3 lc_trk_g2_3 -!B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer tnr_op_3 lc_trk_g3_3 -!B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer tnr_op_4 lc_trk_g2_4 -!B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer tnr_op_4 lc_trk_g3_4 -B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer tnr_op_5 lc_trk_g2_5 -B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer tnr_op_5 lc_trk_g3_5 -!B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer tnr_op_6 lc_trk_g2_6 -!B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer tnr_op_6 lc_trk_g3_6 -!B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer tnr_op_7 lc_trk_g2_7 -!B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer tnr_op_7 lc_trk_g3_7 -B10[37] buffer wire_bram/ram/RDATA_10 sp12_h_l_1 -B11[38] buffer wire_bram/ram/RDATA_10 sp12_h_l_17 -B11[40] buffer wire_bram/ram/RDATA_10 sp12_v_b_10 -B11[37] buffer wire_bram/ram/RDATA_10 sp4_h_l_15 -B11[36] buffer wire_bram/ram/RDATA_10 sp4_h_r_10 -B10[36] buffer wire_bram/ram/RDATA_10 sp4_h_r_42 -B11[41] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_11 -B10[40] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_27 -B10[41] buffer wire_bram/ram/RDATA_10 sp4_r_v_b_43 -B11[39] buffer wire_bram/ram/RDATA_10 sp4_v_b_10 -B10[38] buffer wire_bram/ram/RDATA_10 sp4_v_t_15 -B10[39] buffer wire_bram/ram/RDATA_10 sp4_v_t_31 -B9[38] buffer wire_bram/ram/RDATA_11 sp12_h_l_15 -B8[37] buffer wire_bram/ram/RDATA_11 sp12_h_r_0 -B9[40] buffer wire_bram/ram/RDATA_11 sp12_v_t_7 -B9[37] buffer wire_bram/ram/RDATA_11 sp4_h_r_24 -B8[36] buffer wire_bram/ram/RDATA_11 sp4_h_r_40 -B9[36] buffer wire_bram/ram/RDATA_11 sp4_h_r_8 -B8[40] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_25 -B8[41] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_41 -B9[41] buffer wire_bram/ram/RDATA_11 sp4_r_v_b_9 -B8[39] buffer wire_bram/ram/RDATA_11 sp4_v_b_40 -B9[39] buffer wire_bram/ram/RDATA_11 sp4_v_b_8 -B8[38] buffer wire_bram/ram/RDATA_11 sp4_v_t_13 -B6[37] buffer wire_bram/ram/RDATA_12 sp12_h_r_14 -B7[40] buffer wire_bram/ram/RDATA_12 sp12_v_b_22 -B6[39] buffer wire_bram/ram/RDATA_12 sp12_v_t_5 -B7[37] buffer wire_bram/ram/RDATA_12 sp4_h_l_11 -B6[36] buffer wire_bram/ram/RDATA_12 sp4_h_l_27 -B7[36] buffer wire_bram/ram/RDATA_12 sp4_h_r_6 -B6[40] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_23 -B6[41] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_39 -B7[41] buffer wire_bram/ram/RDATA_12 sp4_r_v_b_7 -B7[38] buffer wire_bram/ram/RDATA_12 sp4_v_b_6 -B7[39] buffer wire_bram/ram/RDATA_12 sp4_v_t_11 -B6[38] buffer wire_bram/ram/RDATA_12 sp4_v_t_27 -B4[37] buffer wire_bram/ram/RDATA_13 sp12_h_r_12 -B5[40] buffer wire_bram/ram/RDATA_13 sp12_v_b_20 -B4[39] buffer wire_bram/ram/RDATA_13 sp12_v_b_4 -B5[37] buffer wire_bram/ram/RDATA_13 sp4_h_l_9 -B4[36] buffer wire_bram/ram/RDATA_13 sp4_h_r_36 -B5[36] buffer wire_bram/ram/RDATA_13 sp4_h_r_4 -B4[40] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_21 -B4[41] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_37 -B5[41] buffer wire_bram/ram/RDATA_13 sp4_r_v_b_5 -B5[39] buffer wire_bram/ram/RDATA_13 sp4_v_b_20 -B5[38] buffer wire_bram/ram/RDATA_13 sp4_v_b_4 -B4[38] buffer wire_bram/ram/RDATA_13 sp4_v_t_25 -B2[37] buffer wire_bram/ram/RDATA_14 sp12_h_l_9 -B3[40] buffer wire_bram/ram/RDATA_14 sp12_v_b_18 -B2[39] buffer wire_bram/ram/RDATA_14 sp12_v_t_1 -B3[37] buffer wire_bram/ram/RDATA_14 sp4_h_r_18 -B3[36] buffer wire_bram/ram/RDATA_14 sp4_h_r_2 -B2[36] buffer wire_bram/ram/RDATA_14 sp4_h_r_34 -B2[40] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_19 -B3[41] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_3 -B2[41] buffer wire_bram/ram/RDATA_14 sp4_r_v_b_35 -B3[38] buffer wire_bram/ram/RDATA_14 sp4_v_b_2 -B2[38] buffer wire_bram/ram/RDATA_14 sp4_v_b_34 -B3[39] buffer wire_bram/ram/RDATA_14 sp4_v_t_7 -B0[37] buffer wire_bram/ram/RDATA_15 sp12_h_r_8 -B0[39] buffer wire_bram/ram/RDATA_15 sp12_v_b_0 -B1[40] buffer wire_bram/ram/RDATA_15 sp12_v_b_16 -B1[36] buffer wire_bram/ram/RDATA_15 sp4_h_r_0 -B1[37] buffer wire_bram/ram/RDATA_15 sp4_h_r_16 -B0[36] buffer wire_bram/ram/RDATA_15 sp4_h_r_32 -B1[41] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_1 -B0[40] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_17 -B0[41] buffer wire_bram/ram/RDATA_15 sp4_r_v_b_33 -B1[38] buffer wire_bram/ram/RDATA_15 sp4_v_b_0 -B1[39] buffer wire_bram/ram/RDATA_15 sp4_v_b_16 -B0[38] buffer wire_bram/ram/RDATA_15 sp4_v_b_32 -B14[37] buffer wire_bram/ram/RDATA_8 sp12_h_l_5 -B15[38] buffer wire_bram/ram/RDATA_8 sp12_h_r_22 -B15[40] buffer wire_bram/ram/RDATA_8 sp12_v_b_14 -B15[37] buffer wire_bram/ram/RDATA_8 sp4_h_l_19 -B15[36] buffer wire_bram/ram/RDATA_8 sp4_h_l_3 -B14[36] buffer wire_bram/ram/RDATA_8 sp4_h_r_46 -B15[41] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_15 -B14[40] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_31 -B14[41] buffer wire_bram/ram/RDATA_8 sp4_r_v_b_47 -B15[39] buffer wire_bram/ram/RDATA_8 sp4_v_b_14 -B14[39] buffer wire_bram/ram/RDATA_8 sp4_v_b_46 -B14[38] buffer wire_bram/ram/RDATA_8 sp4_v_t_19 -B12[37] buffer wire_bram/ram/RDATA_9 sp12_h_l_3 -B13[38] buffer wire_bram/ram/RDATA_9 sp12_h_r_20 -B13[40] buffer wire_bram/ram/RDATA_9 sp12_v_t_11 -B13[36] buffer wire_bram/ram/RDATA_9 sp4_h_l_1 -B13[37] buffer wire_bram/ram/RDATA_9 sp4_h_r_28 -B12[36] buffer wire_bram/ram/RDATA_9 sp4_h_r_44 -B13[41] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_13 -B12[40] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_29 -B12[41] buffer wire_bram/ram/RDATA_9 sp4_r_v_b_45 -B13[39] buffer wire_bram/ram/RDATA_9 sp4_v_b_12 -B12[38] buffer wire_bram/ram/RDATA_9 sp4_v_b_28 -B12[39] buffer wire_bram/ram/RDATA_9 sp4_v_b_44 -!B12[3],B13[3] routing sp12_h_l_22 sp12_h_r_1 -!B8[3],B9[3] routing sp12_h_l_22 sp12_v_b_1 -!B14[3],B15[3] routing sp12_h_l_22 sp12_v_t_22 -!B4[3],B5[3] routing sp12_h_l_23 sp12_h_r_0 -!B0[3],B1[3] routing sp12_h_l_23 sp12_v_b_0 -!B6[3],B7[3] routing sp12_h_l_23 sp12_v_t_23 -B2[3],B3[3] routing sp12_h_r_0 sp12_h_l_23 -B0[3],B1[3] routing sp12_h_r_0 sp12_v_b_0 -B6[3],B7[3] routing sp12_h_r_0 sp12_v_t_23 -B10[3],B11[3] routing sp12_h_r_1 sp12_h_l_22 -B8[3],B9[3] routing sp12_h_r_1 sp12_v_b_1 -B14[3],B15[3] routing sp12_h_r_1 sp12_v_t_22 -!B2[3],B3[3] routing sp12_v_b_0 sp12_h_l_23 -B4[3],B5[3] routing sp12_v_b_0 sp12_h_r_0 -B6[3],!B7[3] routing sp12_v_b_0 sp12_v_t_23 -!B10[3],B11[3] routing sp12_v_b_1 sp12_h_l_22 -B12[3],B13[3] routing sp12_v_b_1 sp12_h_r_1 -B14[3],!B15[3] routing sp12_v_b_1 sp12_v_t_22 -B10[3],!B11[3] routing sp12_v_t_22 sp12_h_l_22 -B12[3],!B13[3] routing sp12_v_t_22 sp12_h_r_1 -B8[3],!B9[3] routing sp12_v_t_22 sp12_v_b_1 -B2[3],!B3[3] routing sp12_v_t_23 sp12_h_l_23 -B4[3],!B5[3] routing sp12_v_t_23 sp12_h_r_0 -B0[3],!B1[3] routing sp12_v_t_23 sp12_v_b_0 -B0[8],!B0[9],!B0[10] routing sp4_h_l_36 sp4_h_r_1 -!B4[8],B4[9],B4[10] routing sp4_h_l_36 sp4_h_r_4 -!B12[5],B13[4],B13[6] routing sp4_h_l_36 sp4_h_r_9 -B1[8],B1[9],!B1[10] routing sp4_h_l_36 sp4_v_b_1 -B9[8],B9[9],B9[10] routing sp4_h_l_36 sp4_v_b_7 -B3[8],!B3[9],!B3[10] routing sp4_h_l_36 sp4_v_t_36 -!B10[4],B10[6],!B11[5] routing sp4_h_l_36 sp4_v_t_43 -!B0[5],!B1[4],B1[6] routing sp4_h_l_37 sp4_h_r_0 -B4[5],B5[4],!B5[6] routing sp4_h_l_37 sp4_h_r_3 -!B8[12],B9[11],B9[13] routing sp4_h_l_37 sp4_h_r_8 -B0[4],!B0[6],B1[5] routing sp4_h_l_37 sp4_v_b_0 -B8[4],B8[6],B9[5] routing sp4_h_l_37 sp4_v_b_6 -!B2[4],!B2[6],B3[5] routing sp4_h_l_37 sp4_v_t_37 -B6[11],!B6[13],!B7[12] routing sp4_h_l_37 sp4_v_t_40 -!B12[12],B13[11],B13[13] routing sp4_h_l_38 sp4_h_r_11 -!B4[5],!B5[4],B5[6] routing sp4_h_l_38 sp4_h_r_3 -B8[5],B9[4],!B9[6] routing sp4_h_l_38 sp4_h_r_6 -B4[4],!B4[6],B5[5] routing sp4_h_l_38 sp4_v_b_3 -B12[4],B12[6],B13[5] routing sp4_h_l_38 sp4_v_b_9 -!B6[4],!B6[6],B7[5] routing sp4_h_l_38 sp4_v_t_38 -B10[11],!B10[13],!B11[12] routing sp4_h_l_38 sp4_v_t_45 -B12[8],!B12[9],B12[10] routing sp4_h_l_39 sp4_h_r_10 -!B0[12],B1[11],!B1[13] routing sp4_h_l_39 sp4_h_r_2 -B4[12],!B5[11],B5[13] routing sp4_h_l_39 sp4_h_r_5 -!B0[11],B0[13],B1[12] routing sp4_h_l_39 sp4_v_b_2 -B8[11],B8[13],B9[12] routing sp4_h_l_39 sp4_v_b_8 -!B2[11],!B2[13],B3[12] routing sp4_h_l_39 sp4_v_t_39 -!B11[8],!B11[9],B11[10] routing sp4_h_l_39 sp4_v_t_42 -B0[8],!B0[9],B0[10] routing sp4_h_l_40 sp4_h_r_1 -!B4[12],B5[11],!B5[13] routing sp4_h_l_40 sp4_h_r_5 -B8[12],!B9[11],B9[13] routing sp4_h_l_40 sp4_h_r_8 -B12[11],B12[13],B13[12] routing sp4_h_l_40 sp4_v_b_11 -!B4[11],B4[13],B5[12] routing sp4_h_l_40 sp4_v_b_5 -!B6[11],!B6[13],B7[12] routing sp4_h_l_40 sp4_v_t_40 -!B15[8],!B15[9],B15[10] routing sp4_h_l_40 sp4_v_t_47 -!B0[5],B1[4],B1[6] routing sp4_h_l_41 sp4_h_r_0 -B4[8],!B4[9],!B4[10] routing sp4_h_l_41 sp4_h_r_4 -!B8[8],B8[9],B8[10] routing sp4_h_l_41 sp4_h_r_7 -B13[8],B13[9],B13[10] routing sp4_h_l_41 sp4_v_b_10 -B5[8],B5[9],!B5[10] routing sp4_h_l_41 sp4_v_b_4 -B7[8],!B7[9],!B7[10] routing sp4_h_l_41 sp4_v_t_41 -!B14[4],B14[6],!B15[5] routing sp4_h_l_41 sp4_v_t_44 -!B12[8],B12[9],B12[10] routing sp4_h_l_42 sp4_h_r_10 -!B4[5],B5[4],B5[6] routing sp4_h_l_42 sp4_h_r_3 -B8[8],!B8[9],!B8[10] routing sp4_h_l_42 sp4_h_r_7 -B1[8],B1[9],B1[10] routing sp4_h_l_42 sp4_v_b_1 -B9[8],B9[9],!B9[10] routing sp4_h_l_42 sp4_v_b_7 -!B2[4],B2[6],!B3[5] routing sp4_h_l_42 sp4_v_t_37 -B11[8],!B11[9],!B11[10] routing sp4_h_l_42 sp4_v_t_42 -!B0[12],B1[11],B1[13] routing sp4_h_l_43 sp4_h_r_2 -!B8[5],!B9[4],B9[6] routing sp4_h_l_43 sp4_h_r_6 -B12[5],B13[4],!B13[6] routing sp4_h_l_43 sp4_h_r_9 -B0[4],B0[6],B1[5] routing sp4_h_l_43 sp4_v_b_0 -B8[4],!B8[6],B9[5] routing sp4_h_l_43 sp4_v_b_6 -!B10[4],!B10[6],B11[5] routing sp4_h_l_43 sp4_v_t_43 -B14[11],!B14[13],!B15[12] routing sp4_h_l_43 sp4_v_t_46 -B0[5],B1[4],!B1[6] routing sp4_h_l_44 sp4_h_r_0 -!B4[12],B5[11],B5[13] routing sp4_h_l_44 sp4_h_r_5 -!B12[5],!B13[4],B13[6] routing sp4_h_l_44 sp4_h_r_9 -B4[4],B4[6],B5[5] routing sp4_h_l_44 sp4_v_b_3 -B12[4],!B12[6],B13[5] routing sp4_h_l_44 sp4_v_b_9 -B2[11],!B2[13],!B3[12] routing sp4_h_l_44 sp4_v_t_39 -!B14[4],!B14[6],B15[5] routing sp4_h_l_44 sp4_v_t_44 -B12[12],!B13[11],B13[13] routing sp4_h_l_45 sp4_h_r_11 -B4[8],!B4[9],B4[10] routing sp4_h_l_45 sp4_h_r_4 -!B8[12],B9[11],!B9[13] routing sp4_h_l_45 sp4_h_r_8 -B0[11],B0[13],B1[12] routing sp4_h_l_45 sp4_v_b_2 -!B8[11],B8[13],B9[12] routing sp4_h_l_45 sp4_v_b_8 -!B3[8],!B3[9],B3[10] routing sp4_h_l_45 sp4_v_t_36 -!B10[11],!B10[13],B11[12] routing sp4_h_l_45 sp4_v_t_45 -!B12[12],B13[11],!B13[13] routing sp4_h_l_46 sp4_h_r_11 -B0[12],!B1[11],B1[13] routing sp4_h_l_46 sp4_h_r_2 -B8[8],!B8[9],B8[10] routing sp4_h_l_46 sp4_h_r_7 -!B12[11],B12[13],B13[12] routing sp4_h_l_46 sp4_v_b_11 -B4[11],B4[13],B5[12] routing sp4_h_l_46 sp4_v_b_5 -!B7[8],!B7[9],B7[10] routing sp4_h_l_46 sp4_v_t_41 -!B14[11],!B14[13],B15[12] routing sp4_h_l_46 sp4_v_t_46 -!B0[8],B0[9],B0[10] routing sp4_h_l_47 sp4_h_r_1 -B12[8],!B12[9],!B12[10] routing sp4_h_l_47 sp4_h_r_10 -!B8[5],B9[4],B9[6] routing sp4_h_l_47 sp4_h_r_6 -B13[8],B13[9],!B13[10] routing sp4_h_l_47 sp4_v_b_10 -B5[8],B5[9],B5[10] routing sp4_h_l_47 sp4_v_b_4 -!B6[4],B6[6],!B7[5] routing sp4_h_l_47 sp4_v_t_38 -B15[8],!B15[9],!B15[10] routing sp4_h_l_47 sp4_v_t_47 -!B2[5],!B3[4],B3[6] routing sp4_h_r_0 sp4_h_l_37 -B6[5],B7[4],!B7[6] routing sp4_h_r_0 sp4_h_l_38 -!B10[12],B11[11],B11[13] routing sp4_h_r_0 sp4_h_l_45 -!B0[4],!B0[6],B1[5] routing sp4_h_r_0 sp4_v_b_0 -B4[11],!B4[13],!B5[12] routing sp4_h_r_0 sp4_v_b_5 -B2[4],!B2[6],B3[5] routing sp4_h_r_0 sp4_v_t_37 -B10[4],B10[6],B11[5] routing sp4_h_r_0 sp4_v_t_43 -B2[8],!B2[9],!B2[10] routing sp4_h_r_1 sp4_h_l_36 -!B6[8],B6[9],B6[10] routing sp4_h_r_1 sp4_h_l_41 -!B14[5],B15[4],B15[6] routing sp4_h_r_1 sp4_h_l_44 -B1[8],!B1[9],!B1[10] routing sp4_h_r_1 sp4_v_b_1 -!B8[4],B8[6],!B9[5] routing sp4_h_r_1 sp4_v_b_6 -B3[8],B3[9],!B3[10] routing sp4_h_r_1 sp4_v_t_36 -B11[8],B11[9],B11[10] routing sp4_h_r_1 sp4_v_t_42 -!B2[8],B2[9],B2[10] routing sp4_h_r_10 sp4_h_l_36 -!B10[5],B11[4],B11[6] routing sp4_h_r_10 sp4_h_l_43 -B14[8],!B14[9],!B14[10] routing sp4_h_r_10 sp4_h_l_47 -B13[8],!B13[9],!B13[10] routing sp4_h_r_10 sp4_v_b_10 -!B4[4],B4[6],!B5[5] routing sp4_h_r_10 sp4_v_b_3 -B7[8],B7[9],B7[10] routing sp4_h_r_10 sp4_v_t_41 -B15[8],B15[9],!B15[10] routing sp4_h_r_10 sp4_v_t_47 -B2[12],!B3[11],B3[13] routing sp4_h_r_11 sp4_h_l_39 -B10[8],!B10[9],B10[10] routing sp4_h_r_11 sp4_h_l_42 -!B14[12],B15[11],!B15[13] routing sp4_h_r_11 sp4_h_l_46 -!B12[11],!B12[13],B13[12] routing sp4_h_r_11 sp4_v_b_11 -!B5[8],!B5[9],B5[10] routing sp4_h_r_11 sp4_v_b_4 -B6[11],B6[13],B7[12] routing sp4_h_r_11 sp4_v_t_40 -!B14[11],B14[13],B15[12] routing sp4_h_r_11 sp4_v_t_46 -!B2[12],B3[11],!B3[13] routing sp4_h_r_2 sp4_h_l_39 -B6[12],!B7[11],B7[13] routing sp4_h_r_2 sp4_h_l_40 -B14[8],!B14[9],B14[10] routing sp4_h_r_2 sp4_h_l_47 -!B0[11],!B0[13],B1[12] routing sp4_h_r_2 sp4_v_b_2 -!B9[8],!B9[9],B9[10] routing sp4_h_r_2 sp4_v_b_7 -!B2[11],B2[13],B3[12] routing sp4_h_r_2 sp4_v_t_39 -B10[11],B10[13],B11[12] routing sp4_h_r_2 sp4_v_t_45 -!B6[5],!B7[4],B7[6] routing sp4_h_r_3 sp4_h_l_38 -B10[5],B11[4],!B11[6] routing sp4_h_r_3 sp4_h_l_43 -!B14[12],B15[11],B15[13] routing sp4_h_r_3 sp4_h_l_46 -!B4[4],!B4[6],B5[5] routing sp4_h_r_3 sp4_v_b_3 -B8[11],!B8[13],!B9[12] routing sp4_h_r_3 sp4_v_b_8 -B6[4],!B6[6],B7[5] routing sp4_h_r_3 sp4_v_t_38 -B14[4],B14[6],B15[5] routing sp4_h_r_3 sp4_v_t_44 -!B2[5],B3[4],B3[6] routing sp4_h_r_4 sp4_h_l_37 -B6[8],!B6[9],!B6[10] routing sp4_h_r_4 sp4_h_l_41 -!B10[8],B10[9],B10[10] routing sp4_h_r_4 sp4_h_l_42 -B5[8],!B5[9],!B5[10] routing sp4_h_r_4 sp4_v_b_4 -!B12[4],B12[6],!B13[5] routing sp4_h_r_4 sp4_v_b_9 -B7[8],B7[9],!B7[10] routing sp4_h_r_4 sp4_v_t_41 -B15[8],B15[9],B15[10] routing sp4_h_r_4 sp4_v_t_47 -B2[8],!B2[9],B2[10] routing sp4_h_r_5 sp4_h_l_36 -!B6[12],B7[11],!B7[13] routing sp4_h_r_5 sp4_h_l_40 -B10[12],!B11[11],B11[13] routing sp4_h_r_5 sp4_h_l_45 -!B13[8],!B13[9],B13[10] routing sp4_h_r_5 sp4_v_b_10 -!B4[11],!B4[13],B5[12] routing sp4_h_r_5 sp4_v_b_5 -!B6[11],B6[13],B7[12] routing sp4_h_r_5 sp4_v_t_40 -B14[11],B14[13],B15[12] routing sp4_h_r_5 sp4_v_t_46 -!B2[12],B3[11],B3[13] routing sp4_h_r_6 sp4_h_l_39 -!B10[5],!B11[4],B11[6] routing sp4_h_r_6 sp4_h_l_43 -B14[5],B15[4],!B15[6] routing sp4_h_r_6 sp4_h_l_44 -B12[11],!B12[13],!B13[12] routing sp4_h_r_6 sp4_v_b_11 -!B8[4],!B8[6],B9[5] routing sp4_h_r_6 sp4_v_b_6 -B2[4],B2[6],B3[5] routing sp4_h_r_6 sp4_v_t_37 -B10[4],!B10[6],B11[5] routing sp4_h_r_6 sp4_v_t_43 -!B6[5],B7[4],B7[6] routing sp4_h_r_7 sp4_h_l_38 -B10[8],!B10[9],!B10[10] routing sp4_h_r_7 sp4_h_l_42 -!B14[8],B14[9],B14[10] routing sp4_h_r_7 sp4_h_l_47 -!B0[4],B0[6],!B1[5] routing sp4_h_r_7 sp4_v_b_0 -B9[8],!B9[9],!B9[10] routing sp4_h_r_7 sp4_v_b_7 -B3[8],B3[9],B3[10] routing sp4_h_r_7 sp4_v_t_36 -B11[8],B11[9],!B11[10] routing sp4_h_r_7 sp4_v_t_42 -B6[8],!B6[9],B6[10] routing sp4_h_r_8 sp4_h_l_41 -!B10[12],B11[11],!B11[13] routing sp4_h_r_8 sp4_h_l_45 -B14[12],!B15[11],B15[13] routing sp4_h_r_8 sp4_h_l_46 -!B1[8],!B1[9],B1[10] routing sp4_h_r_8 sp4_v_b_1 -!B8[11],!B8[13],B9[12] routing sp4_h_r_8 sp4_v_b_8 -B2[11],B2[13],B3[12] routing sp4_h_r_8 sp4_v_t_39 -!B10[11],B10[13],B11[12] routing sp4_h_r_8 sp4_v_t_45 -B2[5],B3[4],!B3[6] routing sp4_h_r_9 sp4_h_l_37 -!B6[12],B7[11],B7[13] routing sp4_h_r_9 sp4_h_l_40 -!B14[5],!B15[4],B15[6] routing sp4_h_r_9 sp4_h_l_44 -B0[11],!B0[13],!B1[12] routing sp4_h_r_9 sp4_v_b_2 -!B12[4],!B12[6],B13[5] routing sp4_h_r_9 sp4_v_b_9 -B6[4],B6[6],B7[5] routing sp4_h_r_9 sp4_v_t_38 -B14[4],!B14[6],B15[5] routing sp4_h_r_9 sp4_v_t_44 -B2[5],!B3[4],!B3[6] routing sp4_v_b_0 sp4_h_l_37 -!B6[12],!B7[11],B7[13] routing sp4_v_b_0 sp4_h_l_40 -B0[5],!B1[4],B1[6] routing sp4_v_b_0 sp4_h_r_0 -B8[5],B9[4],B9[6] routing sp4_v_b_0 sp4_h_r_6 -B2[4],!B2[6],!B3[5] routing sp4_v_b_0 sp4_v_t_37 -!B6[4],B6[6],B7[5] routing sp4_v_b_0 sp4_v_t_38 -B10[11],B10[13],!B11[12] routing sp4_v_b_0 sp4_v_t_45 -!B2[8],B2[9],!B2[10] routing sp4_v_b_1 sp4_h_l_36 -!B10[5],B11[4],!B11[6] routing sp4_v_b_1 sp4_h_l_43 -B0[8],B0[9],!B0[10] routing sp4_v_b_1 sp4_h_r_1 -B8[8],B8[9],B8[10] routing sp4_v_b_1 sp4_h_r_7 -!B3[8],B3[9],!B3[10] routing sp4_v_b_1 sp4_v_t_36 -B7[8],!B7[9],B7[10] routing sp4_v_b_1 sp4_v_t_41 -B14[4],B14[6],!B15[5] routing sp4_v_b_1 sp4_v_t_44 -!B6[5],B7[4],!B7[6] routing sp4_v_b_10 sp4_h_l_38 -!B14[8],B14[9],!B14[10] routing sp4_v_b_10 sp4_h_l_47 -B12[8],B12[9],!B12[10] routing sp4_v_b_10 sp4_h_r_10 -B4[8],B4[9],B4[10] routing sp4_v_b_10 sp4_h_r_4 -B3[8],!B3[9],B3[10] routing sp4_v_b_10 sp4_v_t_36 -B10[4],B10[6],!B11[5] routing sp4_v_b_10 sp4_v_t_43 -!B15[8],B15[9],!B15[10] routing sp4_v_b_10 sp4_v_t_47 -!B6[8],!B6[9],B6[10] routing sp4_v_b_11 sp4_h_l_41 -B14[12],!B15[11],!B15[13] routing sp4_v_b_11 sp4_h_l_46 -B12[12],B13[11],!B13[13] routing sp4_v_b_11 sp4_h_r_11 -B4[12],B5[11],B5[13] routing sp4_v_b_11 sp4_h_r_5 -B2[11],!B2[13],B3[12] routing sp4_v_b_11 sp4_v_t_39 -!B11[8],B11[9],B11[10] routing sp4_v_b_11 sp4_v_t_42 -!B14[11],B14[13],!B15[12] routing sp4_v_b_11 sp4_v_t_46 -B2[12],!B3[11],!B3[13] routing sp4_v_b_2 sp4_h_l_39 -!B10[8],!B10[9],B10[10] routing sp4_v_b_2 sp4_h_l_42 -B0[12],B1[11],!B1[13] routing sp4_v_b_2 sp4_h_r_2 -B8[12],B9[11],B9[13] routing sp4_v_b_2 sp4_h_r_8 -!B2[11],B2[13],!B3[12] routing sp4_v_b_2 sp4_v_t_39 -B6[11],!B6[13],B7[12] routing sp4_v_b_2 sp4_v_t_40 -!B15[8],B15[9],B15[10] routing sp4_v_b_2 sp4_v_t_47 -B6[5],!B7[4],!B7[6] routing sp4_v_b_3 sp4_h_l_38 -!B10[12],!B11[11],B11[13] routing sp4_v_b_3 sp4_h_l_45 -B4[5],!B5[4],B5[6] routing sp4_v_b_3 sp4_h_r_3 -B12[5],B13[4],B13[6] routing sp4_v_b_3 sp4_h_r_9 -B6[4],!B6[6],!B7[5] routing sp4_v_b_3 sp4_v_t_38 -!B10[4],B10[6],B11[5] routing sp4_v_b_3 sp4_v_t_43 -B14[11],B14[13],!B15[12] routing sp4_v_b_3 sp4_v_t_46 -!B6[8],B6[9],!B6[10] routing sp4_v_b_4 sp4_h_l_41 -!B14[5],B15[4],!B15[6] routing sp4_v_b_4 sp4_h_l_44 -B12[8],B12[9],B12[10] routing sp4_v_b_4 sp4_h_r_10 -B4[8],B4[9],!B4[10] routing sp4_v_b_4 sp4_h_r_4 -B2[4],B2[6],!B3[5] routing sp4_v_b_4 sp4_v_t_37 -!B7[8],B7[9],!B7[10] routing sp4_v_b_4 sp4_v_t_41 -B11[8],!B11[9],B11[10] routing sp4_v_b_4 sp4_v_t_42 -B6[12],!B7[11],!B7[13] routing sp4_v_b_5 sp4_h_l_40 -!B14[8],!B14[9],B14[10] routing sp4_v_b_5 sp4_h_l_47 -B12[12],B13[11],B13[13] routing sp4_v_b_5 sp4_h_r_11 -B4[12],B5[11],!B5[13] routing sp4_v_b_5 sp4_h_r_5 -!B3[8],B3[9],B3[10] routing sp4_v_b_5 sp4_v_t_36 -!B6[11],B6[13],!B7[12] routing sp4_v_b_5 sp4_v_t_40 -B10[11],!B10[13],B11[12] routing sp4_v_b_5 sp4_v_t_45 -B10[5],!B11[4],!B11[6] routing sp4_v_b_6 sp4_h_l_43 -!B14[12],!B15[11],B15[13] routing sp4_v_b_6 sp4_h_l_46 -B0[5],B1[4],B1[6] routing sp4_v_b_6 sp4_h_r_0 -B8[5],!B9[4],B9[6] routing sp4_v_b_6 sp4_h_r_6 -B2[11],B2[13],!B3[12] routing sp4_v_b_6 sp4_v_t_39 -B10[4],!B10[6],!B11[5] routing sp4_v_b_6 sp4_v_t_43 -!B14[4],B14[6],B15[5] routing sp4_v_b_6 sp4_v_t_44 -!B2[5],B3[4],!B3[6] routing sp4_v_b_7 sp4_h_l_37 -!B10[8],B10[9],!B10[10] routing sp4_v_b_7 sp4_h_l_42 -B0[8],B0[9],B0[10] routing sp4_v_b_7 sp4_h_r_1 -B8[8],B8[9],!B8[10] routing sp4_v_b_7 sp4_h_r_7 -B6[4],B6[6],!B7[5] routing sp4_v_b_7 sp4_v_t_38 -!B11[8],B11[9],!B11[10] routing sp4_v_b_7 sp4_v_t_42 -B15[8],!B15[9],B15[10] routing sp4_v_b_7 sp4_v_t_47 -!B2[8],!B2[9],B2[10] routing sp4_v_b_8 sp4_h_l_36 -B10[12],!B11[11],!B11[13] routing sp4_v_b_8 sp4_h_l_45 -B0[12],B1[11],B1[13] routing sp4_v_b_8 sp4_h_r_2 -B8[12],B9[11],!B9[13] routing sp4_v_b_8 sp4_h_r_8 -!B7[8],B7[9],B7[10] routing sp4_v_b_8 sp4_v_t_41 -!B10[11],B10[13],!B11[12] routing sp4_v_b_8 sp4_v_t_45 -B14[11],!B14[13],B15[12] routing sp4_v_b_8 sp4_v_t_46 -!B2[12],!B3[11],B3[13] routing sp4_v_b_9 sp4_h_l_39 -B14[5],!B15[4],!B15[6] routing sp4_v_b_9 sp4_h_l_44 -B4[5],B5[4],B5[6] routing sp4_v_b_9 sp4_h_r_3 -B12[5],!B13[4],B13[6] routing sp4_v_b_9 sp4_h_r_9 -!B2[4],B2[6],B3[5] routing sp4_v_b_9 sp4_v_t_37 -B6[11],B6[13],!B7[12] routing sp4_v_b_9 sp4_v_t_40 -B14[4],!B14[6],!B15[5] routing sp4_v_b_9 sp4_v_t_44 -B2[8],B2[9],!B2[10] routing sp4_v_t_36 sp4_h_l_36 -B10[8],B10[9],B10[10] routing sp4_v_t_36 sp4_h_l_42 -!B0[8],B0[9],!B0[10] routing sp4_v_t_36 sp4_h_r_1 -!B8[5],B9[4],!B9[6] routing sp4_v_t_36 sp4_h_r_6 -!B1[8],B1[9],!B1[10] routing sp4_v_t_36 sp4_v_b_1 -B5[8],!B5[9],B5[10] routing sp4_v_t_36 sp4_v_b_4 -B12[4],B12[6],!B13[5] routing sp4_v_t_36 sp4_v_b_9 -B2[5],!B3[4],B3[6] routing sp4_v_t_37 sp4_h_l_37 -B10[5],B11[4],B11[6] routing sp4_v_t_37 sp4_h_l_43 -B0[5],!B1[4],!B1[6] routing sp4_v_t_37 sp4_h_r_0 -!B4[12],!B5[11],B5[13] routing sp4_v_t_37 sp4_h_r_5 -B0[4],!B0[6],!B1[5] routing sp4_v_t_37 sp4_v_b_0 -!B4[4],B4[6],B5[5] routing sp4_v_t_37 sp4_v_b_3 -B8[11],B8[13],!B9[12] routing sp4_v_t_37 sp4_v_b_8 -B6[5],!B7[4],B7[6] routing sp4_v_t_38 sp4_h_l_38 -B14[5],B15[4],B15[6] routing sp4_v_t_38 sp4_h_l_44 -B4[5],!B5[4],!B5[6] routing sp4_v_t_38 sp4_h_r_3 -!B8[12],!B9[11],B9[13] routing sp4_v_t_38 sp4_h_r_8 -B12[11],B12[13],!B13[12] routing sp4_v_t_38 sp4_v_b_11 -B4[4],!B4[6],!B5[5] routing sp4_v_t_38 sp4_v_b_3 -!B8[4],B8[6],B9[5] routing sp4_v_t_38 sp4_v_b_6 -B2[12],B3[11],!B3[13] routing sp4_v_t_39 sp4_h_l_39 -B10[12],B11[11],B11[13] routing sp4_v_t_39 sp4_h_l_45 -B0[12],!B1[11],!B1[13] routing sp4_v_t_39 sp4_h_r_2 -!B8[8],!B8[9],B8[10] routing sp4_v_t_39 sp4_h_r_7 -!B13[8],B13[9],B13[10] routing sp4_v_t_39 sp4_v_b_10 -!B0[11],B0[13],!B1[12] routing sp4_v_t_39 sp4_v_b_2 -B4[11],!B4[13],B5[12] routing sp4_v_t_39 sp4_v_b_5 -B6[12],B7[11],!B7[13] routing sp4_v_t_40 sp4_h_l_40 -B14[12],B15[11],B15[13] routing sp4_v_t_40 sp4_h_l_46 -!B12[8],!B12[9],B12[10] routing sp4_v_t_40 sp4_h_r_10 -B4[12],!B5[11],!B5[13] routing sp4_v_t_40 sp4_h_r_5 -!B1[8],B1[9],B1[10] routing sp4_v_t_40 sp4_v_b_1 -!B4[11],B4[13],!B5[12] routing sp4_v_t_40 sp4_v_b_5 -B8[11],!B8[13],B9[12] routing sp4_v_t_40 sp4_v_b_8 -B6[8],B6[9],!B6[10] routing sp4_v_t_41 sp4_h_l_41 -B14[8],B14[9],B14[10] routing sp4_v_t_41 sp4_h_l_47 -!B4[8],B4[9],!B4[10] routing sp4_v_t_41 sp4_h_r_4 -!B12[5],B13[4],!B13[6] routing sp4_v_t_41 sp4_h_r_9 -B0[4],B0[6],!B1[5] routing sp4_v_t_41 sp4_v_b_0 -!B5[8],B5[9],!B5[10] routing sp4_v_t_41 sp4_v_b_4 -B9[8],!B9[9],B9[10] routing sp4_v_t_41 sp4_v_b_7 -B2[8],B2[9],B2[10] routing sp4_v_t_42 sp4_h_l_36 -B10[8],B10[9],!B10[10] routing sp4_v_t_42 sp4_h_l_42 -!B0[5],B1[4],!B1[6] routing sp4_v_t_42 sp4_h_r_0 -!B8[8],B8[9],!B8[10] routing sp4_v_t_42 sp4_h_r_7 -B13[8],!B13[9],B13[10] routing sp4_v_t_42 sp4_v_b_10 -B4[4],B4[6],!B5[5] routing sp4_v_t_42 sp4_v_b_3 -!B9[8],B9[9],!B9[10] routing sp4_v_t_42 sp4_v_b_7 -B2[5],B3[4],B3[6] routing sp4_v_t_43 sp4_h_l_37 -B10[5],!B11[4],B11[6] routing sp4_v_t_43 sp4_h_l_43 -!B12[12],!B13[11],B13[13] routing sp4_v_t_43 sp4_h_r_11 -B8[5],!B9[4],!B9[6] routing sp4_v_t_43 sp4_h_r_6 -B0[11],B0[13],!B1[12] routing sp4_v_t_43 sp4_v_b_2 -B8[4],!B8[6],!B9[5] routing sp4_v_t_43 sp4_v_b_6 -!B12[4],B12[6],B13[5] routing sp4_v_t_43 sp4_v_b_9 -B6[5],B7[4],B7[6] routing sp4_v_t_44 sp4_h_l_38 -B14[5],!B15[4],B15[6] routing sp4_v_t_44 sp4_h_l_44 -!B0[12],!B1[11],B1[13] routing sp4_v_t_44 sp4_h_r_2 -B12[5],!B13[4],!B13[6] routing sp4_v_t_44 sp4_h_r_9 -!B0[4],B0[6],B1[5] routing sp4_v_t_44 sp4_v_b_0 -B4[11],B4[13],!B5[12] routing sp4_v_t_44 sp4_v_b_5 -B12[4],!B12[6],!B13[5] routing sp4_v_t_44 sp4_v_b_9 -B2[12],B3[11],B3[13] routing sp4_v_t_45 sp4_h_l_39 -B10[12],B11[11],!B11[13] routing sp4_v_t_45 sp4_h_l_45 -!B0[8],!B0[9],B0[10] routing sp4_v_t_45 sp4_h_r_1 -B8[12],!B9[11],!B9[13] routing sp4_v_t_45 sp4_h_r_8 -B12[11],!B12[13],B13[12] routing sp4_v_t_45 sp4_v_b_11 -!B5[8],B5[9],B5[10] routing sp4_v_t_45 sp4_v_b_4 -!B8[11],B8[13],!B9[12] routing sp4_v_t_45 sp4_v_b_8 -B6[12],B7[11],B7[13] routing sp4_v_t_46 sp4_h_l_40 -B14[12],B15[11],!B15[13] routing sp4_v_t_46 sp4_h_l_46 -B12[12],!B13[11],!B13[13] routing sp4_v_t_46 sp4_h_r_11 -!B4[8],!B4[9],B4[10] routing sp4_v_t_46 sp4_h_r_4 -!B12[11],B12[13],!B13[12] routing sp4_v_t_46 sp4_v_b_11 -B0[11],!B0[13],B1[12] routing sp4_v_t_46 sp4_v_b_2 -!B9[8],B9[9],B9[10] routing sp4_v_t_46 sp4_v_b_7 -B6[8],B6[9],B6[10] routing sp4_v_t_47 sp4_h_l_41 -B14[8],B14[9],!B14[10] routing sp4_v_t_47 sp4_h_l_47 -!B12[8],B12[9],!B12[10] routing sp4_v_t_47 sp4_h_r_10 -!B4[5],B5[4],!B5[6] routing sp4_v_t_47 sp4_h_r_3 -B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1 -!B13[8],B13[9],!B13[10] routing sp4_v_t_47 sp4_v_b_10 -B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6 -""" -database_ramt_5k_txt = """ -B9[7] ColBufCtrl 8k_glb_netwk_0 -B8[7] ColBufCtrl 8k_glb_netwk_1 -B11[7] ColBufCtrl 8k_glb_netwk_2 -B10[7] ColBufCtrl 8k_glb_netwk_3 -B13[7] ColBufCtrl 8k_glb_netwk_4 -B12[7] ColBufCtrl 8k_glb_netwk_5 -B15[7] ColBufCtrl 8k_glb_netwk_6 -B14[7] ColBufCtrl 8k_glb_netwk_7 -B0[0] NegClk -B5[7] RamCascade CBIT_4 -B4[7] RamCascade CBIT_5 -B7[7] RamCascade CBIT_6 -B6[7] RamCascade CBIT_7 -B1[7] RamConfig CBIT_0 -B0[7] RamConfig CBIT_1 -B3[7] RamConfig CBIT_2 -B2[7] RamConfig CBIT_3 -B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer bnl_op_0 lc_trk_g2_0 -B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer bnl_op_0 lc_trk_g3_0 -!B8[15],!B8[16],B8[17],B8[18],B9[18] buffer bnl_op_1 lc_trk_g2_1 -!B12[15],!B12[16],B12[17],B12[18],B13[18] buffer bnl_op_1 lc_trk_g3_1 -B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer bnl_op_2 lc_trk_g2_2 -B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer bnl_op_2 lc_trk_g3_2 -B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer bnl_op_3 lc_trk_g2_3 -B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer bnl_op_3 lc_trk_g3_3 -B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer bnl_op_4 lc_trk_g2_4 -B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer bnl_op_4 lc_trk_g3_4 -!B10[15],!B10[16],B10[17],B10[18],B11[18] buffer bnl_op_5 lc_trk_g2_5 -!B14[15],!B14[16],B14[17],B14[18],B15[18] buffer bnl_op_5 lc_trk_g3_5 -B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer bnl_op_6 lc_trk_g2_6 -B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer bnl_op_6 lc_trk_g3_6 -B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer bnl_op_7 lc_trk_g2_7 -B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer bnl_op_7 lc_trk_g3_7 -B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer bnr_op_0 lc_trk_g0_0 -B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer bnr_op_0 lc_trk_g1_0 -!B0[15],!B0[16],B0[17],B0[18],B1[18] buffer bnr_op_1 lc_trk_g0_1 -!B4[15],!B4[16],B4[17],B4[18],B5[18] buffer bnr_op_1 lc_trk_g1_1 -B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer bnr_op_2 lc_trk_g0_2 -B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer bnr_op_2 lc_trk_g1_2 -B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer bnr_op_3 lc_trk_g0_3 -B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer bnr_op_3 lc_trk_g1_3 -B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer bnr_op_4 lc_trk_g0_4 -B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer bnr_op_4 lc_trk_g1_4 -!B2[15],!B2[16],B2[17],B2[18],B3[18] buffer bnr_op_5 lc_trk_g0_5 -!B6[15],!B6[16],B6[17],B6[18],B7[18] buffer bnr_op_5 lc_trk_g1_5 -B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer bnr_op_6 lc_trk_g0_6 -B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer bnr_op_6 lc_trk_g1_6 -B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer bnr_op_7 lc_trk_g0_7 -B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer bnr_op_7 lc_trk_g1_7 -!B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer glb2local_0 lc_trk_g0_4 -!B2[15],!B2[16],B2[17],!B2[18],!B3[18] buffer glb2local_1 lc_trk_g0_5 -!B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer glb2local_2 lc_trk_g0_6 -!B2[21],B2[22],!B2[23],!B2[24],!B3[21] buffer glb2local_3 lc_trk_g0_7 -!B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_1 glb2local_0 -!B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_1 glb2local_1 -!B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_1 glb2local_2 -!B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_1 glb2local_3 -!B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_1 wire_bram/ram/WCLK -B2[0],!B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_2 wire_bram/ram/WCLK -!B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_2 wire_bram/ram/WE -B6[0],B6[1],B7[0],!B7[1] buffer glb_netwk_3 glb2local_0 -B8[0],B8[1],B9[0],!B9[1] buffer glb_netwk_3 glb2local_1 -B10[0],B10[1],B11[0],!B11[1] buffer glb_netwk_3 glb2local_2 -B12[0],B12[1],B13[0],!B13[1] buffer glb_netwk_3 glb2local_3 -B2[0],!B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_3 wire_bram/ram/WCLK -!B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_4 glb2local_0 -!B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_4 glb2local_1 -!B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_4 glb2local_2 -!B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_4 glb2local_3 -!B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_4 wire_bram/ram/WCLK -B14[0],B14[1],!B15[0],!B15[1] buffer glb_netwk_4 wire_bram/ram/WE -!B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_5 glb2local_0 -!B8[0],B8[1],B9[0],B9[1] buffer glb_netwk_5 glb2local_1 -!B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_5 glb2local_2 -!B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_5 glb2local_3 -!B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_5 wire_bram/ram/WCLK -B6[0],B6[1],!B7[0],B7[1] buffer glb_netwk_6 glb2local_0 -B8[0],B8[1],!B9[0],B9[1] buffer glb_netwk_6 glb2local_1 -B10[0],B10[1],!B11[0],B11[1] buffer glb_netwk_6 glb2local_2 -B12[0],B12[1],!B13[0],B13[1] buffer glb_netwk_6 glb2local_3 -B2[0],B2[1],B2[2],!B3[0],!B3[2] buffer glb_netwk_6 wire_bram/ram/WCLK -B14[0],B14[1],B15[0],!B15[1] buffer glb_netwk_6 wire_bram/ram/WE -B6[0],B6[1],B7[0],B7[1] buffer glb_netwk_7 glb2local_0 -B10[0],B10[1],B11[0],B11[1] buffer glb_netwk_7 glb2local_2 -B12[0],B12[1],B13[0],B13[1] buffer glb_netwk_7 glb2local_3 -B2[0],B2[1],B2[2],B3[0],!B3[2] buffer glb_netwk_7 wire_bram/ram/WCLK -!B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_0 input0_0 -!B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_0 input0_2 -!B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_0 input0_4 -!B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_0 input0_6 -!B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_0 input2_6 -!B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g0_0 wire_bram/ram/WCLK -!B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_0 -!B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_2 -!B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_4 -!B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g0_0 wire_bram/ram/WDATA_6 -!B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_1 input0_1 -!B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_1 input0_3 -!B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_1 input0_5 -!B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_1 input0_7 -!B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_1 input2_5 -!B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_1 input2_7 -!B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_1 -!B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_3 -!B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_5 -!B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g0_1 wire_bram/ram/WDATA_7 -!B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_2 input0_0 -!B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_2 input0_2 -!B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_2 input0_4 -!B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_2 input0_6 -!B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_2 input2_6 -!B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_0 -!B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_2 -!B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_4 -!B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_2 wire_bram/ram/MASK_6 -!B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g0_2 wire_bram/ram/WCLKE -!B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_0 -!B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_2 -!B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_4 -!B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g0_2 wire_bram/ram/WDATA_6 -!B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_3 input0_1 -!B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_3 input0_3 -!B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_3 input0_5 -!B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_3 input0_7 -!B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_3 input2_5 -!B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_3 input2_7 -!B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_1 -!B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_3 -!B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_5 -!B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_3 wire_bram/ram/MASK_7 -!B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_1 -!B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_3 -!B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_5 -!B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g0_3 wire_bram/ram/WDATA_7 -B0[26],!B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_4 input0_0 -B4[26],!B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_4 input0_2 -B8[26],!B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_4 input0_4 -B12[26],!B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_4 input0_6 -B12[35],B13[32],!B13[33],!B13[34],!B13[35] buffer lc_trk_g0_4 input2_6 -B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_0 -B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_2 -B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_4 -B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer lc_trk_g0_4 wire_bram/ram/MASK_6 -!B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_0 -!B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_2 -!B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_4 -!B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g0_4 wire_bram/ram/WDATA_6 -!B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g0_4 wire_bram/ram/WE -B2[26],!B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_5 input0_1 -B6[26],!B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_5 input0_3 -B10[26],!B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_5 input0_5 -B14[26],!B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_5 input0_7 -B10[35],B11[32],!B11[33],!B11[34],!B11[35] buffer lc_trk_g0_5 input2_5 -B14[35],B15[32],!B15[33],!B15[34],!B15[35] buffer lc_trk_g0_5 input2_7 -B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_1 -B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_3 -B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_5 -B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer lc_trk_g0_5 wire_bram/ram/MASK_7 -!B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_1 -!B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_3 -!B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_5 -!B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g0_5 wire_bram/ram/WDATA_7 -B0[26],B1[26],!B1[27],!B1[28],B1[29] buffer lc_trk_g0_6 input0_0 -B4[26],B5[26],!B5[27],!B5[28],B5[29] buffer lc_trk_g0_6 input0_2 -B8[26],B9[26],!B9[27],!B9[28],B9[29] buffer lc_trk_g0_6 input0_4 -B12[26],B13[26],!B13[27],!B13[28],B13[29] buffer lc_trk_g0_6 input0_6 -B12[35],B13[32],!B13[33],!B13[34],B13[35] buffer lc_trk_g0_6 input2_6 -B14[31],B14[32],!B14[33],!B14[34],B15[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_0 -B10[31],B10[32],!B10[33],!B10[34],B11[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_2 -B6[31],B6[32],!B6[33],!B6[34],B7[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_4 -B2[31],B2[32],!B2[33],!B2[34],B3[31] buffer lc_trk_g0_6 wire_bram/ram/MASK_6 -!B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_0 -!B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_2 -!B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_4 -!B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g0_6 wire_bram/ram/WDATA_6 -B2[26],B3[26],!B3[27],!B3[28],B3[29] buffer lc_trk_g0_7 input0_1 -B6[26],B7[26],!B7[27],!B7[28],B7[29] buffer lc_trk_g0_7 input0_3 -B10[26],B11[26],!B11[27],!B11[28],B11[29] buffer lc_trk_g0_7 input0_5 -B14[26],B15[26],!B15[27],!B15[28],B15[29] buffer lc_trk_g0_7 input0_7 -B10[35],B11[32],!B11[33],!B11[34],B11[35] buffer lc_trk_g0_7 input2_5 -B14[35],B15[32],!B15[33],!B15[34],B15[35] buffer lc_trk_g0_7 input2_7 -B12[31],B12[32],!B12[33],!B12[34],B13[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_1 -B8[31],B8[32],!B8[33],!B8[34],B9[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_3 -B4[31],B4[32],!B4[33],!B4[34],B5[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_5 -B0[31],B0[32],!B0[33],!B0[34],B1[31] buffer lc_trk_g0_7 wire_bram/ram/MASK_7 -!B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_1 -!B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_3 -!B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_5 -!B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g0_7 wire_bram/ram/WDATA_7 -!B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_0 input0_1 -!B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_0 input0_3 -!B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_0 input0_5 -!B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_0 input0_7 -!B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_0 input2_5 -!B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_0 input2_7 -!B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_1 -!B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_3 -!B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_5 -!B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_0 wire_bram/ram/MASK_7 -B12[27],!B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_1 -B8[27],!B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_3 -B4[27],!B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_5 -B0[27],!B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g1_0 wire_bram/ram/WDATA_7 -!B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_1 input0_0 -!B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_1 input0_2 -!B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_1 input0_4 -!B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_1 input0_6 -!B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_1 input2_6 -!B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_0 -!B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_2 -!B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_4 -!B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_1 wire_bram/ram/MASK_6 -!B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g1_1 wire_bram/ram/WCLK -B14[27],!B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_0 -B10[27],!B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_2 -B6[27],!B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_4 -B2[27],!B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g1_1 wire_bram/ram/WDATA_6 -!B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_2 input0_1 -!B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_2 input0_3 -!B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_2 input0_5 -!B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_2 input0_7 -!B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_2 input2_5 -!B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_2 input2_7 -!B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_1 -!B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_3 -!B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_5 -!B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_2 wire_bram/ram/MASK_7 -B12[27],!B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_1 -B8[27],!B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_3 -B4[27],!B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_5 -B0[27],!B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g1_2 wire_bram/ram/WDATA_7 -!B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_3 input0_0 -!B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_3 input0_2 -!B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_3 input0_4 -!B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_3 input0_6 -!B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_3 input2_6 -!B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_0 -!B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_2 -!B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_4 -!B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_3 wire_bram/ram/MASK_6 -!B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g1_3 wire_bram/ram/WCLKE -B14[27],!B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_0 -B10[27],!B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_2 -B6[27],!B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_4 -B2[27],!B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g1_3 wire_bram/ram/WDATA_6 -B2[26],!B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_4 input0_1 -B6[26],!B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_4 input0_3 -B10[26],!B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_4 input0_5 -B14[26],!B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_4 input0_7 -B10[35],B11[32],!B11[33],B11[34],!B11[35] buffer lc_trk_g1_4 input2_5 -B14[35],B15[32],!B15[33],B15[34],!B15[35] buffer lc_trk_g1_4 input2_7 -B12[31],B12[32],!B12[33],B12[34],!B13[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_1 -B8[31],B8[32],!B8[33],B8[34],!B9[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_3 -B4[31],B4[32],!B4[33],B4[34],!B5[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_5 -B0[31],B0[32],!B0[33],B0[34],!B1[31] buffer lc_trk_g1_4 wire_bram/ram/MASK_7 -B12[27],!B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_1 -B8[27],!B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_3 -B4[27],!B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_5 -B0[27],!B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g1_4 wire_bram/ram/WDATA_7 -B0[26],!B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_5 input0_0 -B4[26],!B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_5 input0_2 -B8[26],!B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_5 input0_4 -B12[26],!B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_5 input0_6 -B12[35],B13[32],!B13[33],B13[34],!B13[35] buffer lc_trk_g1_5 input2_6 -B14[31],B14[32],!B14[33],B14[34],!B15[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_0 -B10[31],B10[32],!B10[33],B10[34],!B11[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_2 -B6[31],B6[32],!B6[33],B6[34],!B7[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_4 -B2[31],B2[32],!B2[33],B2[34],!B3[31] buffer lc_trk_g1_5 wire_bram/ram/MASK_6 -B14[27],!B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_0 -B10[27],!B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_2 -B6[27],!B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_4 -B2[27],!B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g1_5 wire_bram/ram/WDATA_6 -!B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g1_5 wire_bram/ram/WE -B2[26],B3[26],B3[27],!B3[28],B3[29] buffer lc_trk_g1_6 input0_1 -B6[26],B7[26],B7[27],!B7[28],B7[29] buffer lc_trk_g1_6 input0_3 -B10[26],B11[26],B11[27],!B11[28],B11[29] buffer lc_trk_g1_6 input0_5 -B14[26],B15[26],B15[27],!B15[28],B15[29] buffer lc_trk_g1_6 input0_7 -B10[35],B11[32],!B11[33],B11[34],B11[35] buffer lc_trk_g1_6 input2_5 -B14[35],B15[32],!B15[33],B15[34],B15[35] buffer lc_trk_g1_6 input2_7 -B12[31],B12[32],!B12[33],B12[34],B13[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_1 -B8[31],B8[32],!B8[33],B8[34],B9[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_3 -B4[31],B4[32],!B4[33],B4[34],B5[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_5 -B0[31],B0[32],!B0[33],B0[34],B1[31] buffer lc_trk_g1_6 wire_bram/ram/MASK_7 -B12[27],!B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_1 -B8[27],!B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_3 -B4[27],!B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_5 -B0[27],!B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g1_6 wire_bram/ram/WDATA_7 -B0[26],B1[26],B1[27],!B1[28],B1[29] buffer lc_trk_g1_7 input0_0 -B4[26],B5[26],B5[27],!B5[28],B5[29] buffer lc_trk_g1_7 input0_2 -B8[26],B9[26],B9[27],!B9[28],B9[29] buffer lc_trk_g1_7 input0_4 -B12[26],B13[26],B13[27],!B13[28],B13[29] buffer lc_trk_g1_7 input0_6 -B12[35],B13[32],!B13[33],B13[34],B13[35] buffer lc_trk_g1_7 input2_6 -B14[31],B14[32],!B14[33],B14[34],B15[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_0 -B10[31],B10[32],!B10[33],B10[34],B11[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_2 -B6[31],B6[32],!B6[33],B6[34],B7[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_4 -B2[31],B2[32],!B2[33],B2[34],B3[31] buffer lc_trk_g1_7 wire_bram/ram/MASK_6 -B14[27],!B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_0 -B10[27],!B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_2 -B6[27],!B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_4 -B2[27],!B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g1_7 wire_bram/ram/WDATA_6 -!B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_0 input0_0 -!B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_0 input0_2 -!B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_0 input0_4 -!B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_0 input0_6 -!B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_0 input2_6 -!B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_0 -!B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_2 -!B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_4 -!B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_0 wire_bram/ram/MASK_6 -B2[0],!B2[1],B2[2],!B3[0],B3[2] buffer lc_trk_g2_0 wire_bram/ram/WCLK -!B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_0 -!B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_2 -!B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_4 -!B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g2_0 wire_bram/ram/WDATA_6 -!B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_1 input0_1 -!B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_1 input0_3 -!B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_1 input0_5 -!B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_1 input0_7 -!B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_1 input2_5 -!B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_1 input2_7 -!B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_1 -!B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_3 -!B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_5 -!B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_1 wire_bram/ram/MASK_7 -!B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_1 -!B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_3 -!B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_5 -!B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g2_1 wire_bram/ram/WDATA_7 -!B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_2 input0_0 -!B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_2 input0_2 -!B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_2 input0_4 -!B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_2 input0_6 -!B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_2 input2_6 -!B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_0 -!B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_2 -!B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_4 -!B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_2 wire_bram/ram/MASK_6 -B4[0],B4[1],!B5[0],B5[1] buffer lc_trk_g2_2 wire_bram/ram/WCLKE -!B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_0 -!B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_2 -!B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_4 -!B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g2_2 wire_bram/ram/WDATA_6 -!B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_3 input0_1 -!B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_3 input0_3 -!B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_3 input0_5 -!B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_3 input0_7 -!B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_3 input2_5 -!B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_3 input2_7 -!B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_1 -!B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_3 -!B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_5 -!B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_3 wire_bram/ram/MASK_7 -!B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_1 -!B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_3 -!B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_5 -!B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g2_3 wire_bram/ram/WDATA_7 -B0[26],!B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_4 input0_0 -B4[26],!B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_4 input0_2 -B8[26],!B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_4 input0_4 -B12[26],!B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_4 input0_6 -B12[35],B13[32],B13[33],!B13[34],!B13[35] buffer lc_trk_g2_4 input2_6 -B14[31],B14[32],B14[33],!B14[34],!B15[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_0 -B10[31],B10[32],B10[33],!B10[34],!B11[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_2 -B6[31],B6[32],B6[33],!B6[34],!B7[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_4 -B2[31],B2[32],B2[33],!B2[34],!B3[31] buffer lc_trk_g2_4 wire_bram/ram/MASK_6 -!B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_0 -!B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_2 -!B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_4 -!B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g2_4 wire_bram/ram/WDATA_6 -B14[0],B14[1],!B15[0],B15[1] buffer lc_trk_g2_4 wire_bram/ram/WE -B2[26],!B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_5 input0_1 -B6[26],!B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_5 input0_3 -B10[26],!B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_5 input0_5 -B14[26],!B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_5 input0_7 -B10[35],B11[32],B11[33],!B11[34],!B11[35] buffer lc_trk_g2_5 input2_5 -B14[35],B15[32],B15[33],!B15[34],!B15[35] buffer lc_trk_g2_5 input2_7 -B12[31],B12[32],B12[33],!B12[34],!B13[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_1 -B8[31],B8[32],B8[33],!B8[34],!B9[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_3 -B4[31],B4[32],B4[33],!B4[34],!B5[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_5 -B0[31],B0[32],B0[33],!B0[34],!B1[31] buffer lc_trk_g2_5 wire_bram/ram/MASK_7 -!B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_1 -!B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_3 -!B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_5 -!B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g2_5 wire_bram/ram/WDATA_7 -B0[26],B1[26],!B1[27],B1[28],B1[29] buffer lc_trk_g2_6 input0_0 -B4[26],B5[26],!B5[27],B5[28],B5[29] buffer lc_trk_g2_6 input0_2 -B8[26],B9[26],!B9[27],B9[28],B9[29] buffer lc_trk_g2_6 input0_4 -B12[26],B13[26],!B13[27],B13[28],B13[29] buffer lc_trk_g2_6 input0_6 -B12[35],B13[32],B13[33],!B13[34],B13[35] buffer lc_trk_g2_6 input2_6 -B14[31],B14[32],B14[33],!B14[34],B15[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_0 -B10[31],B10[32],B10[33],!B10[34],B11[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_2 -B6[31],B6[32],B6[33],!B6[34],B7[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_4 -B2[31],B2[32],B2[33],!B2[34],B3[31] buffer lc_trk_g2_6 wire_bram/ram/MASK_6 -!B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_0 -!B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_2 -!B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_4 -!B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g2_6 wire_bram/ram/WDATA_6 -B2[26],B3[26],!B3[27],B3[28],B3[29] buffer lc_trk_g2_7 input0_1 -B6[26],B7[26],!B7[27],B7[28],B7[29] buffer lc_trk_g2_7 input0_3 -B10[26],B11[26],!B11[27],B11[28],B11[29] buffer lc_trk_g2_7 input0_5 -B14[26],B15[26],!B15[27],B15[28],B15[29] buffer lc_trk_g2_7 input0_7 -B10[35],B11[32],B11[33],!B11[34],B11[35] buffer lc_trk_g2_7 input2_5 -B14[35],B15[32],B15[33],!B15[34],B15[35] buffer lc_trk_g2_7 input2_7 -B12[31],B12[32],B12[33],!B12[34],B13[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_1 -B8[31],B8[32],B8[33],!B8[34],B9[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_3 -B4[31],B4[32],B4[33],!B4[34],B5[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_5 -B0[31],B0[32],B0[33],!B0[34],B1[31] buffer lc_trk_g2_7 wire_bram/ram/MASK_7 -!B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_1 -!B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_3 -!B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_5 -!B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g2_7 wire_bram/ram/WDATA_7 -!B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_0 input0_1 -!B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_0 input0_3 -!B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_0 input0_5 -!B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_0 input0_7 -!B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_0 input2_5 -!B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_0 input2_7 -!B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_1 -!B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_3 -!B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_5 -!B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_0 wire_bram/ram/MASK_7 -B12[27],B12[28],B12[29],!B12[30],!B13[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_1 -B8[27],B8[28],B8[29],!B8[30],!B9[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_3 -B4[27],B4[28],B4[29],!B4[30],!B5[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_5 -B0[27],B0[28],B0[29],!B0[30],!B1[30] buffer lc_trk_g3_0 wire_bram/ram/WDATA_7 -!B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_1 input0_0 -!B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_1 input0_2 -!B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_1 input0_4 -!B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_1 input0_6 -!B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_1 input2_6 -!B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_0 -!B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_2 -!B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_4 -!B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_1 wire_bram/ram/MASK_6 -B2[0],!B2[1],B2[2],B3[0],B3[2] buffer lc_trk_g3_1 wire_bram/ram/WCLK -B14[27],B14[28],B14[29],!B14[30],!B15[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_0 -B10[27],B10[28],B10[29],!B10[30],!B11[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_2 -B6[27],B6[28],B6[29],!B6[30],!B7[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_4 -B2[27],B2[28],B2[29],!B2[30],!B3[30] buffer lc_trk_g3_1 wire_bram/ram/WDATA_6 -!B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_2 input0_1 -!B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_2 input0_3 -!B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_2 input0_5 -!B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_2 input0_7 -!B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_2 input2_5 -!B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_2 input2_7 -!B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_1 -!B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_3 -!B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_5 -!B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_2 wire_bram/ram/MASK_7 -B12[27],B12[28],B12[29],!B12[30],B13[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_1 -B8[27],B8[28],B8[29],!B8[30],B9[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_3 -B4[27],B4[28],B4[29],!B4[30],B5[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_5 -B0[27],B0[28],B0[29],!B0[30],B1[30] buffer lc_trk_g3_2 wire_bram/ram/WDATA_7 -!B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_3 input0_0 -!B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_3 input0_2 -!B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_3 input0_4 -!B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_3 input0_6 -!B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_3 input2_6 -!B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_0 -!B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_2 -!B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_4 -!B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_3 wire_bram/ram/MASK_6 -B4[0],B4[1],B5[0],B5[1] buffer lc_trk_g3_3 wire_bram/ram/WCLKE -B14[27],B14[28],B14[29],!B14[30],B15[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_0 -B10[27],B10[28],B10[29],!B10[30],B11[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_2 -B6[27],B6[28],B6[29],!B6[30],B7[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_4 -B2[27],B2[28],B2[29],!B2[30],B3[30] buffer lc_trk_g3_3 wire_bram/ram/WDATA_6 -B2[26],!B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_4 input0_1 -B6[26],!B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_4 input0_3 -B10[26],!B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_4 input0_5 -B14[26],!B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_4 input0_7 -B10[35],B11[32],B11[33],B11[34],!B11[35] buffer lc_trk_g3_4 input2_5 -B14[35],B15[32],B15[33],B15[34],!B15[35] buffer lc_trk_g3_4 input2_7 -B12[31],B12[32],B12[33],B12[34],!B13[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_1 -B8[31],B8[32],B8[33],B8[34],!B9[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_3 -B4[31],B4[32],B4[33],B4[34],!B5[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_5 -B0[31],B0[32],B0[33],B0[34],!B1[31] buffer lc_trk_g3_4 wire_bram/ram/MASK_7 -B12[27],B12[28],B12[29],B12[30],!B13[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_1 -B8[27],B8[28],B8[29],B8[30],!B9[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_3 -B4[27],B4[28],B4[29],B4[30],!B5[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_5 -B0[27],B0[28],B0[29],B0[30],!B1[30] buffer lc_trk_g3_4 wire_bram/ram/WDATA_7 -B0[26],!B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_5 input0_0 -B4[26],!B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_5 input0_2 -B8[26],!B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_5 input0_4 -B12[26],!B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_5 input0_6 -B12[35],B13[32],B13[33],B13[34],!B13[35] buffer lc_trk_g3_5 input2_6 -B14[31],B14[32],B14[33],B14[34],!B15[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_0 -B10[31],B10[32],B10[33],B10[34],!B11[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_2 -B6[31],B6[32],B6[33],B6[34],!B7[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_4 -B2[31],B2[32],B2[33],B2[34],!B3[31] buffer lc_trk_g3_5 wire_bram/ram/MASK_6 -B14[27],B14[28],B14[29],B14[30],!B15[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_0 -B10[27],B10[28],B10[29],B10[30],!B11[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_2 -B6[27],B6[28],B6[29],B6[30],!B7[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_4 -B2[27],B2[28],B2[29],B2[30],!B3[30] buffer lc_trk_g3_5 wire_bram/ram/WDATA_6 -B14[0],B14[1],B15[0],B15[1] buffer lc_trk_g3_5 wire_bram/ram/WE -B2[26],B3[26],B3[27],B3[28],B3[29] buffer lc_trk_g3_6 input0_1 -B6[26],B7[26],B7[27],B7[28],B7[29] buffer lc_trk_g3_6 input0_3 -B10[26],B11[26],B11[27],B11[28],B11[29] buffer lc_trk_g3_6 input0_5 -B14[26],B15[26],B15[27],B15[28],B15[29] buffer lc_trk_g3_6 input0_7 -B10[35],B11[32],B11[33],B11[34],B11[35] buffer lc_trk_g3_6 input2_5 -B14[35],B15[32],B15[33],B15[34],B15[35] buffer lc_trk_g3_6 input2_7 -B12[31],B12[32],B12[33],B12[34],B13[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_1 -B8[31],B8[32],B8[33],B8[34],B9[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_3 -B4[31],B4[32],B4[33],B4[34],B5[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_5 -B0[31],B0[32],B0[33],B0[34],B1[31] buffer lc_trk_g3_6 wire_bram/ram/MASK_7 -B12[27],B12[28],B12[29],B12[30],B13[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_1 -B8[27],B8[28],B8[29],B8[30],B9[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_3 -B4[27],B4[28],B4[29],B4[30],B5[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_5 -B0[27],B0[28],B0[29],B0[30],B1[30] buffer lc_trk_g3_6 wire_bram/ram/WDATA_7 -B0[26],B1[26],B1[27],B1[28],B1[29] buffer lc_trk_g3_7 input0_0 -B4[26],B5[26],B5[27],B5[28],B5[29] buffer lc_trk_g3_7 input0_2 -B8[26],B9[26],B9[27],B9[28],B9[29] buffer lc_trk_g3_7 input0_4 -B12[26],B13[26],B13[27],B13[28],B13[29] buffer lc_trk_g3_7 input0_6 -B12[35],B13[32],B13[33],B13[34],B13[35] buffer lc_trk_g3_7 input2_6 -B14[31],B14[32],B14[33],B14[34],B15[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_0 -B10[31],B10[32],B10[33],B10[34],B11[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_2 -B6[31],B6[32],B6[33],B6[34],B7[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_4 -B2[31],B2[32],B2[33],B2[34],B3[31] buffer lc_trk_g3_7 wire_bram/ram/MASK_6 -B14[27],B14[28],B14[29],B14[30],B15[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_0 -B10[27],B10[28],B10[29],B10[30],B11[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_2 -B6[27],B6[28],B6[29],B6[30],B7[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_4 -B2[27],B2[28],B2[29],B2[30],B3[30] buffer lc_trk_g3_7 wire_bram/ram/WDATA_6 -B0[14],!B1[14],B1[15],!B1[16],B1[17] buffer lft_op_0 lc_trk_g0_0 -B4[14],!B5[14],B5[15],!B5[16],B5[17] buffer lft_op_0 lc_trk_g1_0 -B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer lft_op_1 lc_trk_g0_1 -B4[15],!B4[16],B4[17],B4[18],!B5[18] buffer lft_op_1 lc_trk_g1_1 -B0[25],B1[22],!B1[23],B1[24],!B1[25] buffer lft_op_2 lc_trk_g0_2 -B4[25],B5[22],!B5[23],B5[24],!B5[25] buffer lft_op_2 lc_trk_g1_2 -B0[21],B0[22],!B0[23],B0[24],!B1[21] buffer lft_op_3 lc_trk_g0_3 -B4[21],B4[22],!B4[23],B4[24],!B5[21] buffer lft_op_3 lc_trk_g1_3 -B2[14],!B3[14],B3[15],!B3[16],B3[17] buffer lft_op_4 lc_trk_g0_4 -B6[14],!B7[14],B7[15],!B7[16],B7[17] buffer lft_op_4 lc_trk_g1_4 -B2[15],!B2[16],B2[17],B2[18],!B3[18] buffer lft_op_5 lc_trk_g0_5 -B6[15],!B6[16],B6[17],B6[18],!B7[18] buffer lft_op_5 lc_trk_g1_5 -B2[25],B3[22],!B3[23],B3[24],!B3[25] buffer lft_op_6 lc_trk_g0_6 -B6[25],B7[22],!B7[23],B7[24],!B7[25] buffer lft_op_6 lc_trk_g1_6 -B2[21],B2[22],!B2[23],B2[24],!B3[21] buffer lft_op_7 lc_trk_g0_7 -B6[21],B6[22],!B6[23],B6[24],!B7[21] buffer lft_op_7 lc_trk_g1_7 -B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer rgt_op_0 lc_trk_g2_0 -B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer rgt_op_0 lc_trk_g3_0 -B8[15],!B8[16],B8[17],B8[18],!B9[18] buffer rgt_op_1 lc_trk_g2_1 -B12[15],!B12[16],B12[17],B12[18],!B13[18] buffer rgt_op_1 lc_trk_g3_1 -B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer rgt_op_2 lc_trk_g2_2 -B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer rgt_op_2 lc_trk_g3_2 -B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer rgt_op_3 lc_trk_g2_3 -B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer rgt_op_3 lc_trk_g3_3 -B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer rgt_op_4 lc_trk_g2_4 -B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer rgt_op_4 lc_trk_g3_4 -B10[15],!B10[16],B10[17],B10[18],!B11[18] buffer rgt_op_5 lc_trk_g2_5 -B14[15],!B14[16],B14[17],B14[18],!B15[18] buffer rgt_op_5 lc_trk_g3_5 -B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer rgt_op_6 lc_trk_g2_6 -B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer rgt_op_6 lc_trk_g3_6 -B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer rgt_op_7 lc_trk_g2_7 -B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer rgt_op_7 lc_trk_g3_7 -B0[21],B0[22],!B0[23],B0[24],B1[21] buffer sp12_h_l_0 lc_trk_g0_3 -B4[21],B4[22],!B4[23],B4[24],B5[21] buffer sp12_h_l_0 lc_trk_g1_3 -!B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp12_h_l_12 lc_trk_g0_7 -!B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp12_h_l_12 lc_trk_g1_7 -!B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp12_h_l_13 lc_trk_g0_6 -!B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp12_h_l_13 lc_trk_g1_6 -B6[2] buffer sp12_h_l_13 sp4_h_r_19 -!B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp12_h_l_16 lc_trk_g0_3 -!B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp12_h_l_16 lc_trk_g1_3 -!B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp12_h_l_18 lc_trk_g0_5 -!B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp12_h_l_18 lc_trk_g1_5 -!B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp12_h_l_21 lc_trk_g0_6 -!B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp12_h_l_21 lc_trk_g1_6 -B14[2] buffer sp12_h_l_21 sp4_h_l_10 -B2[14],B3[14],B3[15],!B3[16],B3[17] buffer sp12_h_l_3 lc_trk_g0_4 -B6[14],B7[14],B7[15],!B7[16],B7[17] buffer sp12_h_l_3 lc_trk_g1_4 -B15[19] buffer sp12_h_l_3 sp4_h_l_3 -B2[21],B2[22],!B2[23],B2[24],B3[21] buffer sp12_h_l_4 lc_trk_g0_7 -B6[21],B6[22],!B6[23],B6[24],B7[21] buffer sp12_h_l_4 lc_trk_g1_7 -B2[25],B3[22],!B3[23],B3[24],B3[25] buffer sp12_h_l_5 lc_trk_g0_6 -B6[25],B7[22],!B7[23],B7[24],B7[25] buffer sp12_h_l_5 lc_trk_g1_6 -B14[19] buffer sp12_h_l_5 sp4_h_l_2 -!B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp12_h_l_6 lc_trk_g0_1 -!B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp12_h_l_6 lc_trk_g1_1 -B0[14],B1[14],B1[15],!B1[16],B1[17] buffer sp12_h_r_0 lc_trk_g0_0 -B4[14],B5[14],B5[15],!B5[16],B5[17] buffer sp12_h_r_0 lc_trk_g1_0 -B13[19] buffer sp12_h_r_0 sp4_h_r_12 -B0[15],!B0[16],B0[17],B0[18],B1[18] buffer sp12_h_r_1 lc_trk_g0_1 -B4[15],!B4[16],B4[17],B4[18],B5[18] buffer sp12_h_r_1 lc_trk_g1_1 -!B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp12_h_r_10 lc_trk_g0_2 -!B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp12_h_r_10 lc_trk_g1_2 -B3[1] buffer sp12_h_r_10 sp4_h_r_17 -!B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp12_h_r_11 lc_trk_g0_3 -!B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp12_h_r_11 lc_trk_g1_3 -!B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_12 lc_trk_g0_4 -!B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_12 lc_trk_g1_4 -B4[2] buffer sp12_h_r_12 sp4_h_l_7 -!B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp12_h_r_13 lc_trk_g0_5 -!B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp12_h_r_13 lc_trk_g1_5 -!B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_16 lc_trk_g0_0 -!B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_16 lc_trk_g1_0 -B8[2] buffer sp12_h_r_16 sp4_h_r_20 -!B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp12_h_r_17 lc_trk_g0_1 -!B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp12_h_r_17 lc_trk_g1_1 -!B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp12_h_r_18 lc_trk_g0_2 -!B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp12_h_r_18 lc_trk_g1_2 -B10[2] buffer sp12_h_r_18 sp4_h_l_8 -B0[25],B1[22],!B1[23],B1[24],B1[25] buffer sp12_h_r_2 lc_trk_g0_2 -B4[25],B5[22],!B5[23],B5[24],B5[25] buffer sp12_h_r_2 lc_trk_g1_2 -B12[19] buffer sp12_h_r_2 sp4_h_r_13 -!B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp12_h_r_20 lc_trk_g0_4 -!B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp12_h_r_20 lc_trk_g1_4 -B12[2] buffer sp12_h_r_20 sp4_h_r_22 -!B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp12_h_r_23 lc_trk_g0_7 -!B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp12_h_r_23 lc_trk_g1_7 -B2[15],!B2[16],B2[17],B2[18],B3[18] buffer sp12_h_r_5 lc_trk_g0_5 -B6[15],!B6[16],B6[17],B6[18],B7[18] buffer sp12_h_r_5 lc_trk_g1_5 -!B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp12_h_r_8 lc_trk_g0_0 -!B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp12_h_r_8 lc_trk_g1_0 -B0[2] buffer sp12_h_r_8 sp4_h_l_5 -B8[14],B9[14],B9[15],!B9[16],B9[17] buffer sp12_v_b_0 lc_trk_g2_0 -B12[14],B13[14],B13[15],!B13[16],B13[17] buffer sp12_v_b_0 lc_trk_g3_0 -B8[15],!B8[16],B8[17],B8[18],B9[18] buffer sp12_v_b_1 lc_trk_g2_1 -B12[15],!B12[16],B12[17],B12[18],B13[18] buffer sp12_v_b_1 lc_trk_g3_1 -B1[19] buffer sp12_v_b_1 sp4_v_t_1 -!B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp12_v_b_11 lc_trk_g2_3 -!B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp12_v_b_11 lc_trk_g3_3 -B4[19] buffer sp12_v_b_11 sp4_v_b_17 -!B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_b_12 lc_trk_g2_4 -!B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_b_12 lc_trk_g3_4 -!B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp12_v_b_14 lc_trk_g2_6 -!B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp12_v_b_14 lc_trk_g3_6 -!B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_b_16 lc_trk_g2_0 -!B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_b_16 lc_trk_g3_0 -!B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp12_v_b_17 lc_trk_g2_1 -!B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp12_v_b_17 lc_trk_g3_1 -B9[19] buffer sp12_v_b_17 sp4_v_b_20 -B8[25],B9[22],!B9[23],B9[24],B9[25] buffer sp12_v_b_2 lc_trk_g2_2 -B12[25],B13[22],!B13[23],B13[24],B13[25] buffer sp12_v_b_2 lc_trk_g3_2 -!B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp12_v_b_21 lc_trk_g2_5 -!B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp12_v_b_21 lc_trk_g3_5 -B11[19] buffer sp12_v_b_21 sp4_v_b_22 -!B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp12_v_b_23 lc_trk_g2_7 -!B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp12_v_b_23 lc_trk_g3_7 -B10[19] buffer sp12_v_b_23 sp4_v_t_10 -B10[15],!B10[16],B10[17],B10[18],B11[18] buffer sp12_v_b_5 lc_trk_g2_5 -B14[15],!B14[16],B14[17],B14[18],B15[18] buffer sp12_v_b_5 lc_trk_g3_5 -B3[19] buffer sp12_v_b_5 sp4_v_b_14 -B10[25],B11[22],!B11[23],B11[24],B11[25] buffer sp12_v_b_6 lc_trk_g2_6 -B14[25],B15[22],!B15[23],B15[24],B15[25] buffer sp12_v_b_6 lc_trk_g3_6 -B10[21],B10[22],!B10[23],B10[24],B11[21] buffer sp12_v_b_7 lc_trk_g2_7 -B14[21],B14[22],!B14[23],B14[24],B15[21] buffer sp12_v_b_7 lc_trk_g3_7 -B2[19] buffer sp12_v_b_7 sp4_v_t_2 -!B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp12_v_b_9 lc_trk_g2_1 -!B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp12_v_b_9 lc_trk_g3_1 -B5[19] buffer sp12_v_b_9 sp4_v_b_16 -B8[21],B8[22],!B8[23],B8[24],B9[21] buffer sp12_v_t_0 lc_trk_g2_3 -B12[21],B12[22],!B12[23],B12[24],B13[21] buffer sp12_v_t_0 lc_trk_g3_3 -B0[19] buffer sp12_v_t_0 sp4_v_b_13 -!B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp12_v_t_10 lc_trk_g2_5 -!B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp12_v_t_10 lc_trk_g3_5 -B7[19] buffer sp12_v_t_10 sp4_v_t_7 -!B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp12_v_t_12 lc_trk_g2_7 -!B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp12_v_t_12 lc_trk_g3_7 -B6[19] buffer sp12_v_t_12 sp4_v_b_19 -!B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp12_v_t_16 lc_trk_g2_3 -!B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp12_v_t_16 lc_trk_g3_3 -B8[19] buffer sp12_v_t_16 sp4_v_t_8 -!B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp12_v_t_17 lc_trk_g2_2 -!B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp12_v_t_17 lc_trk_g3_2 -!B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp12_v_t_19 lc_trk_g2_4 -!B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp12_v_t_19 lc_trk_g3_4 -!B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp12_v_t_21 lc_trk_g2_6 -!B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp12_v_t_21 lc_trk_g3_6 -B10[14],B11[14],B11[15],!B11[16],B11[17] buffer sp12_v_t_3 lc_trk_g2_4 -B14[14],B15[14],B15[15],!B15[16],B15[17] buffer sp12_v_t_3 lc_trk_g3_4 -!B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp12_v_t_7 lc_trk_g2_0 -!B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp12_v_t_7 lc_trk_g3_0 -!B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp12_v_t_9 lc_trk_g2_2 -!B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp12_v_t_9 lc_trk_g3_2 -B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_l_10 lc_trk_g0_7 -B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_l_10 lc_trk_g1_7 -!B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_13 lc_trk_g2_0 -!B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_13 lc_trk_g3_0 -!B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_l_15 lc_trk_g2_2 -!B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_l_15 lc_trk_g3_2 -B10[15],B10[16],B10[17],!B10[18],B11[18] buffer sp4_h_l_16 lc_trk_g2_5 -B14[15],B14[16],B14[17],!B14[18],B15[18] buffer sp4_h_l_16 lc_trk_g3_5 -!B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_l_17 lc_trk_g2_4 -!B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_l_17 lc_trk_g3_4 -!B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_l_18 lc_trk_g2_7 -!B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_l_18 lc_trk_g3_7 -B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_h_l_2 lc_trk_g0_7 -B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_h_l_2 lc_trk_g1_7 -B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_h_l_20 lc_trk_g2_1 -B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_h_l_20 lc_trk_g3_1 -B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_21 lc_trk_g2_0 -B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_21 lc_trk_g3_0 -B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_h_l_26 lc_trk_g2_7 -B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_h_l_26 lc_trk_g3_7 -B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_h_l_27 lc_trk_g2_6 -B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_h_l_27 lc_trk_g3_6 -B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_h_l_28 lc_trk_g2_1 -B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_h_l_28 lc_trk_g3_1 -B8[14],B9[14],B9[15],B9[16],B9[17] buffer sp4_h_l_29 lc_trk_g2_0 -B12[14],B13[14],B13[15],B13[16],B13[17] buffer sp4_h_l_29 lc_trk_g3_0 -B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_h_l_3 lc_trk_g0_6 -B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_h_l_3 lc_trk_g1_6 -B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_l_30 lc_trk_g2_3 -B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_l_30 lc_trk_g3_3 -B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_l_5 lc_trk_g0_0 -B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_l_5 lc_trk_g1_0 -B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_l_7 lc_trk_g0_2 -B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_l_7 lc_trk_g1_2 -B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_h_l_8 lc_trk_g0_5 -B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_h_l_8 lc_trk_g1_5 -!B0[14],B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_0 lc_trk_g0_0 -!B4[14],B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_0 lc_trk_g1_0 -B0[15],B0[16],B0[17],!B0[18],B1[18] buffer sp4_h_r_1 lc_trk_g0_1 -B4[15],B4[16],B4[17],!B4[18],B5[18] buffer sp4_h_r_1 lc_trk_g1_1 -B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_h_r_10 lc_trk_g0_2 -B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_h_r_10 lc_trk_g1_2 -B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_h_r_11 lc_trk_g0_3 -B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_h_r_11 lc_trk_g1_3 -B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_12 lc_trk_g0_4 -B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_12 lc_trk_g1_4 -B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_h_r_13 lc_trk_g0_5 -B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_h_r_13 lc_trk_g1_5 -B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_h_r_17 lc_trk_g0_1 -B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_h_r_17 lc_trk_g1_1 -B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_19 lc_trk_g0_3 -B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_19 lc_trk_g1_3 -!B0[25],B1[22],B1[23],B1[24],B1[25] buffer sp4_h_r_2 lc_trk_g0_2 -!B4[25],B5[22],B5[23],B5[24],B5[25] buffer sp4_h_r_2 lc_trk_g1_2 -B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_20 lc_trk_g0_4 -B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_20 lc_trk_g1_4 -B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_22 lc_trk_g0_6 -B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_22 lc_trk_g1_6 -B8[15],B8[16],B8[17],!B8[18],B9[18] buffer sp4_h_r_25 lc_trk_g2_1 -B12[15],B12[16],B12[17],!B12[18],B13[18] buffer sp4_h_r_25 lc_trk_g3_1 -!B8[21],B8[22],B8[23],B8[24],B9[21] buffer sp4_h_r_27 lc_trk_g2_3 -!B12[21],B12[22],B12[23],B12[24],B13[21] buffer sp4_h_r_27 lc_trk_g3_3 -!B0[21],B0[22],B0[23],B0[24],B1[21] buffer sp4_h_r_3 lc_trk_g0_3 -!B4[21],B4[22],B4[23],B4[24],B5[21] buffer sp4_h_r_3 lc_trk_g1_3 -!B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_30 lc_trk_g2_6 -!B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_30 lc_trk_g3_6 -B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_h_r_34 lc_trk_g2_2 -B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_h_r_34 lc_trk_g3_2 -B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_h_r_35 lc_trk_g2_3 -B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_h_r_35 lc_trk_g3_3 -B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_36 lc_trk_g2_4 -B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_36 lc_trk_g3_4 -B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_h_r_37 lc_trk_g2_5 -B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_h_r_37 lc_trk_g3_5 -!B2[14],B3[14],B3[15],B3[16],B3[17] buffer sp4_h_r_4 lc_trk_g0_4 -!B6[14],B7[14],B7[15],B7[16],B7[17] buffer sp4_h_r_4 lc_trk_g1_4 -B8[25],B9[22],B9[23],B9[24],B9[25] buffer sp4_h_r_42 lc_trk_g2_2 -B12[25],B13[22],B13[23],B13[24],B13[25] buffer sp4_h_r_42 lc_trk_g3_2 -B10[14],B11[14],B11[15],B11[16],B11[17] buffer sp4_h_r_44 lc_trk_g2_4 -B14[14],B15[14],B15[15],B15[16],B15[17] buffer sp4_h_r_44 lc_trk_g3_4 -B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_h_r_45 lc_trk_g2_5 -B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_h_r_45 lc_trk_g3_5 -B10[25],B11[22],B11[23],B11[24],B11[25] buffer sp4_h_r_46 lc_trk_g2_6 -B14[25],B15[22],B15[23],B15[24],B15[25] buffer sp4_h_r_46 lc_trk_g3_6 -B10[21],B10[22],B10[23],B10[24],B11[21] buffer sp4_h_r_47 lc_trk_g2_7 -B14[21],B14[22],B14[23],B14[24],B15[21] buffer sp4_h_r_47 lc_trk_g3_7 -B2[15],B2[16],B2[17],!B2[18],B3[18] buffer sp4_h_r_5 lc_trk_g0_5 -B6[15],B6[16],B6[17],!B6[18],B7[18] buffer sp4_h_r_5 lc_trk_g1_5 -!B2[25],B3[22],B3[23],B3[24],B3[25] buffer sp4_h_r_6 lc_trk_g0_6 -!B6[25],B7[22],B7[23],B7[24],B7[25] buffer sp4_h_r_6 lc_trk_g1_6 -!B2[21],B2[22],B2[23],B2[24],B3[21] buffer sp4_h_r_7 lc_trk_g0_7 -!B6[21],B6[22],B6[23],B6[24],B7[21] buffer sp4_h_r_7 lc_trk_g1_7 -B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_h_r_8 lc_trk_g0_0 -B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_h_r_8 lc_trk_g1_0 -B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_h_r_9 lc_trk_g0_1 -B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_h_r_9 lc_trk_g1_1 -!B4[14],!B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_0 lc_trk_g1_0 -!B4[15],!B4[16],B4[17],!B4[18],!B5[18] buffer sp4_r_v_b_1 lc_trk_g1_1 -!B8[25],B9[22],!B9[23],!B9[24],!B9[25] buffer sp4_r_v_b_10 lc_trk_g2_2 -!B8[21],B8[22],!B8[23],!B8[24],!B9[21] buffer sp4_r_v_b_11 lc_trk_g2_3 -!B10[14],!B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_12 lc_trk_g2_4 -!B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer sp4_r_v_b_13 lc_trk_g2_5 -!B10[25],B11[22],!B11[23],!B11[24],!B11[25] buffer sp4_r_v_b_14 lc_trk_g2_6 -!B10[21],B10[22],!B10[23],!B10[24],!B11[21] buffer sp4_r_v_b_15 lc_trk_g2_7 -!B12[14],!B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_16 lc_trk_g3_0 -!B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer sp4_r_v_b_17 lc_trk_g3_1 -!B12[25],B13[22],!B13[23],!B13[24],!B13[25] buffer sp4_r_v_b_18 lc_trk_g3_2 -!B12[21],B12[22],!B12[23],!B12[24],!B13[21] buffer sp4_r_v_b_19 lc_trk_g3_3 -!B4[25],B5[22],!B5[23],!B5[24],!B5[25] buffer sp4_r_v_b_2 lc_trk_g1_2 -!B14[14],!B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_20 lc_trk_g3_4 -!B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer sp4_r_v_b_21 lc_trk_g3_5 -!B14[25],B15[22],!B15[23],!B15[24],!B15[25] buffer sp4_r_v_b_22 lc_trk_g3_6 -!B14[21],B14[22],!B14[23],!B14[24],!B15[21] buffer sp4_r_v_b_23 lc_trk_g3_7 -!B0[14],!B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_24 lc_trk_g0_0 -!B4[14],B5[14],!B5[15],!B5[16],B5[17] buffer sp4_r_v_b_24 lc_trk_g1_0 -!B0[15],!B0[16],B0[17],!B0[18],!B1[18] buffer sp4_r_v_b_25 lc_trk_g0_1 -!B4[15],!B4[16],B4[17],!B4[18],B5[18] buffer sp4_r_v_b_25 lc_trk_g1_1 -!B0[25],B1[22],!B1[23],!B1[24],!B1[25] buffer sp4_r_v_b_26 lc_trk_g0_2 -!B4[25],B5[22],!B5[23],!B5[24],B5[25] buffer sp4_r_v_b_26 lc_trk_g1_2 -!B0[21],B0[22],!B0[23],!B0[24],!B1[21] buffer sp4_r_v_b_27 lc_trk_g0_3 -!B4[21],B4[22],!B4[23],!B4[24],B5[21] buffer sp4_r_v_b_27 lc_trk_g1_3 -!B2[14],B3[14],!B3[15],!B3[16],B3[17] buffer sp4_r_v_b_28 lc_trk_g0_4 -!B6[14],B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_28 lc_trk_g1_4 -!B2[15],!B2[16],B2[17],!B2[18],B3[18] buffer sp4_r_v_b_29 lc_trk_g0_5 -!B6[15],!B6[16],B6[17],!B6[18],B7[18] buffer sp4_r_v_b_29 lc_trk_g1_5 -!B4[21],B4[22],!B4[23],!B4[24],!B5[21] buffer sp4_r_v_b_3 lc_trk_g1_3 -!B2[25],B3[22],!B3[23],!B3[24],B3[25] buffer sp4_r_v_b_30 lc_trk_g0_6 -!B6[25],B7[22],!B7[23],!B7[24],B7[25] buffer sp4_r_v_b_30 lc_trk_g1_6 -!B2[21],B2[22],!B2[23],!B2[24],B3[21] buffer sp4_r_v_b_31 lc_trk_g0_7 -!B6[21],B6[22],!B6[23],!B6[24],B7[21] buffer sp4_r_v_b_31 lc_trk_g1_7 -!B0[21],B0[22],!B0[23],!B0[24],B1[21] buffer sp4_r_v_b_32 lc_trk_g0_3 -!B8[14],B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_32 lc_trk_g2_0 -!B0[25],B1[22],!B1[23],!B1[24],B1[25] buffer sp4_r_v_b_33 lc_trk_g0_2 -!B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer sp4_r_v_b_33 lc_trk_g2_1 -!B0[15],!B0[16],B0[17],!B0[18],B1[18] buffer sp4_r_v_b_34 lc_trk_g0_1 -!B8[25],B9[22],!B9[23],!B9[24],B9[25] buffer sp4_r_v_b_34 lc_trk_g2_2 -!B0[14],B1[14],!B1[15],!B1[16],B1[17] buffer sp4_r_v_b_35 lc_trk_g0_0 -!B8[21],B8[22],!B8[23],!B8[24],B9[21] buffer sp4_r_v_b_35 lc_trk_g2_3 -!B10[14],B11[14],!B11[15],!B11[16],B11[17] buffer sp4_r_v_b_36 lc_trk_g2_4 -!B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer sp4_r_v_b_37 lc_trk_g2_5 -!B10[25],B11[22],!B11[23],!B11[24],B11[25] buffer sp4_r_v_b_38 lc_trk_g2_6 -!B10[21],B10[22],!B10[23],!B10[24],B11[21] buffer sp4_r_v_b_39 lc_trk_g2_7 -!B6[14],!B7[14],!B7[15],!B7[16],B7[17] buffer sp4_r_v_b_4 lc_trk_g1_4 -!B12[14],B13[14],!B13[15],!B13[16],B13[17] buffer sp4_r_v_b_40 lc_trk_g3_0 -!B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer sp4_r_v_b_41 lc_trk_g3_1 -!B12[25],B13[22],!B13[23],!B13[24],B13[25] buffer sp4_r_v_b_42 lc_trk_g3_2 -!B12[21],B12[22],!B12[23],!B12[24],B13[21] buffer sp4_r_v_b_43 lc_trk_g3_3 -!B14[14],B15[14],!B15[15],!B15[16],B15[17] buffer sp4_r_v_b_44 lc_trk_g3_4 -!B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer sp4_r_v_b_45 lc_trk_g3_5 -!B14[25],B15[22],!B15[23],!B15[24],B15[25] buffer sp4_r_v_b_46 lc_trk_g3_6 -!B14[21],B14[22],!B14[23],!B14[24],B15[21] buffer sp4_r_v_b_47 lc_trk_g3_7 -!B6[15],!B6[16],B6[17],!B6[18],!B7[18] buffer sp4_r_v_b_5 lc_trk_g1_5 -!B6[25],B7[22],!B7[23],!B7[24],!B7[25] buffer sp4_r_v_b_6 lc_trk_g1_6 -!B6[21],B6[22],!B6[23],!B6[24],!B7[21] buffer sp4_r_v_b_7 lc_trk_g1_7 -!B8[14],!B9[14],!B9[15],!B9[16],B9[17] buffer sp4_r_v_b_8 lc_trk_g2_0 -!B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer sp4_r_v_b_9 lc_trk_g2_1 -B0[14],!B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_0 lc_trk_g0_0 -B4[14],!B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_0 lc_trk_g1_0 -!B0[15],B0[16],B0[17],B0[18],!B1[18] buffer sp4_v_b_1 lc_trk_g0_1 -!B4[15],B4[16],B4[17],B4[18],!B5[18] buffer sp4_v_b_1 lc_trk_g1_1 -B0[25],B1[22],B1[23],!B1[24],B1[25] buffer sp4_v_b_10 lc_trk_g0_2 -B4[25],B5[22],B5[23],!B5[24],B5[25] buffer sp4_v_b_10 lc_trk_g1_2 -B0[21],B0[22],B0[23],!B0[24],B1[21] buffer sp4_v_b_11 lc_trk_g0_3 -B4[21],B4[22],B4[23],!B4[24],B5[21] buffer sp4_v_b_11 lc_trk_g1_3 -!B2[15],B2[16],B2[17],B2[18],B3[18] buffer sp4_v_b_13 lc_trk_g0_5 -!B6[15],B6[16],B6[17],B6[18],B7[18] buffer sp4_v_b_13 lc_trk_g1_5 -B2[25],B3[22],B3[23],!B3[24],B3[25] buffer sp4_v_b_14 lc_trk_g0_6 -B6[25],B7[22],B7[23],!B7[24],B7[25] buffer sp4_v_b_14 lc_trk_g1_6 -!B0[14],!B1[14],B1[15],B1[16],B1[17] buffer sp4_v_b_16 lc_trk_g0_0 -!B4[14],!B5[14],B5[15],B5[16],B5[17] buffer sp4_v_b_16 lc_trk_g1_0 -B0[15],B0[16],B0[17],!B0[18],!B1[18] buffer sp4_v_b_17 lc_trk_g0_1 -B4[15],B4[16],B4[17],!B4[18],!B5[18] buffer sp4_v_b_17 lc_trk_g1_1 -!B0[21],B0[22],B0[23],B0[24],!B1[21] buffer sp4_v_b_19 lc_trk_g0_3 -!B4[21],B4[22],B4[23],B4[24],!B5[21] buffer sp4_v_b_19 lc_trk_g1_3 -B0[25],B1[22],B1[23],!B1[24],!B1[25] buffer sp4_v_b_2 lc_trk_g0_2 -B4[25],B5[22],B5[23],!B5[24],!B5[25] buffer sp4_v_b_2 lc_trk_g1_2 -!B2[14],!B3[14],B3[15],B3[16],B3[17] buffer sp4_v_b_20 lc_trk_g0_4 -!B6[14],!B7[14],B7[15],B7[16],B7[17] buffer sp4_v_b_20 lc_trk_g1_4 -!B2[25],B3[22],B3[23],B3[24],!B3[25] buffer sp4_v_b_22 lc_trk_g0_6 -!B6[25],B7[22],B7[23],B7[24],!B7[25] buffer sp4_v_b_22 lc_trk_g1_6 -!B8[15],B8[16],B8[17],B8[18],!B9[18] buffer sp4_v_b_25 lc_trk_g2_1 -!B12[15],B12[16],B12[17],B12[18],!B13[18] buffer sp4_v_b_25 lc_trk_g3_1 -B8[25],B9[22],B9[23],!B9[24],!B9[25] buffer sp4_v_b_26 lc_trk_g2_2 -B12[25],B13[22],B13[23],!B13[24],!B13[25] buffer sp4_v_b_26 lc_trk_g3_2 -B10[14],!B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_b_28 lc_trk_g2_4 -B14[14],!B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_b_28 lc_trk_g3_4 -!B10[15],B10[16],B10[17],B10[18],!B11[18] buffer sp4_v_b_29 lc_trk_g2_5 -!B14[15],B14[16],B14[17],B14[18],!B15[18] buffer sp4_v_b_29 lc_trk_g3_5 -B0[21],B0[22],B0[23],!B0[24],!B1[21] buffer sp4_v_b_3 lc_trk_g0_3 -B4[21],B4[22],B4[23],!B4[24],!B5[21] buffer sp4_v_b_3 lc_trk_g1_3 -B10[25],B11[22],B11[23],!B11[24],!B11[25] buffer sp4_v_b_30 lc_trk_g2_6 -B14[25],B15[22],B15[23],!B15[24],!B15[25] buffer sp4_v_b_30 lc_trk_g3_6 -!B8[15],B8[16],B8[17],B8[18],B9[18] buffer sp4_v_b_33 lc_trk_g2_1 -!B12[15],B12[16],B12[17],B12[18],B13[18] buffer sp4_v_b_33 lc_trk_g3_1 -!B10[15],B10[16],B10[17],B10[18],B11[18] buffer sp4_v_b_37 lc_trk_g2_5 -!B14[15],B14[16],B14[17],B14[18],B15[18] buffer sp4_v_b_37 lc_trk_g3_5 -B10[25],B11[22],B11[23],!B11[24],B11[25] buffer sp4_v_b_38 lc_trk_g2_6 -B14[25],B15[22],B15[23],!B15[24],B15[25] buffer sp4_v_b_38 lc_trk_g3_6 -B2[14],!B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_b_4 lc_trk_g0_4 -B6[14],!B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_b_4 lc_trk_g1_4 -!B8[14],!B9[14],B9[15],B9[16],B9[17] buffer sp4_v_b_40 lc_trk_g2_0 -!B12[14],!B13[14],B13[15],B13[16],B13[17] buffer sp4_v_b_40 lc_trk_g3_0 -B8[15],B8[16],B8[17],!B8[18],!B9[18] buffer sp4_v_b_41 lc_trk_g2_1 -B12[15],B12[16],B12[17],!B12[18],!B13[18] buffer sp4_v_b_41 lc_trk_g3_1 -B10[15],B10[16],B10[17],!B10[18],!B11[18] buffer sp4_v_b_45 lc_trk_g2_5 -B14[15],B14[16],B14[17],!B14[18],!B15[18] buffer sp4_v_b_45 lc_trk_g3_5 -!B10[25],B11[22],B11[23],B11[24],!B11[25] buffer sp4_v_b_46 lc_trk_g2_6 -!B14[25],B15[22],B15[23],B15[24],!B15[25] buffer sp4_v_b_46 lc_trk_g3_6 -!B10[21],B10[22],B10[23],B10[24],!B11[21] buffer sp4_v_b_47 lc_trk_g2_7 -!B14[21],B14[22],B14[23],B14[24],!B15[21] buffer sp4_v_b_47 lc_trk_g3_7 -!B2[15],B2[16],B2[17],B2[18],!B3[18] buffer sp4_v_b_5 lc_trk_g0_5 -!B6[15],B6[16],B6[17],B6[18],!B7[18] buffer sp4_v_b_5 lc_trk_g1_5 -B2[25],B3[22],B3[23],!B3[24],!B3[25] buffer sp4_v_b_6 lc_trk_g0_6 -B6[25],B7[22],B7[23],!B7[24],!B7[25] buffer sp4_v_b_6 lc_trk_g1_6 -B2[21],B2[22],B2[23],!B2[24],!B3[21] buffer sp4_v_b_7 lc_trk_g0_7 -B6[21],B6[22],B6[23],!B6[24],!B7[21] buffer sp4_v_b_7 lc_trk_g1_7 -B0[14],B1[14],!B1[15],B1[16],B1[17] buffer sp4_v_b_8 lc_trk_g0_0 -B4[14],B5[14],!B5[15],B5[16],B5[17] buffer sp4_v_b_8 lc_trk_g1_0 -!B0[15],B0[16],B0[17],B0[18],B1[18] buffer sp4_v_b_9 lc_trk_g0_1 -!B4[15],B4[16],B4[17],B4[18],B5[18] buffer sp4_v_b_9 lc_trk_g1_1 -B2[14],B3[14],!B3[15],B3[16],B3[17] buffer sp4_v_t_1 lc_trk_g0_4 -B6[14],B7[14],!B7[15],B7[16],B7[17] buffer sp4_v_t_1 lc_trk_g1_4 -!B2[21],B2[22],B2[23],B2[24],!B3[21] buffer sp4_v_t_10 lc_trk_g0_7 -!B6[21],B6[22],B6[23],B6[24],!B7[21] buffer sp4_v_t_10 lc_trk_g1_7 -B8[14],!B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_13 lc_trk_g2_0 -B12[14],!B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_13 lc_trk_g3_0 -B8[21],B8[22],B8[23],!B8[24],!B9[21] buffer sp4_v_t_14 lc_trk_g2_3 -B12[21],B12[22],B12[23],!B12[24],!B13[21] buffer sp4_v_t_14 lc_trk_g3_3 -B10[21],B10[22],B10[23],!B10[24],!B11[21] buffer sp4_v_t_18 lc_trk_g2_7 -B14[21],B14[22],B14[23],!B14[24],!B15[21] buffer sp4_v_t_18 lc_trk_g3_7 -B2[21],B2[22],B2[23],!B2[24],B3[21] buffer sp4_v_t_2 lc_trk_g0_7 -B6[21],B6[22],B6[23],!B6[24],B7[21] buffer sp4_v_t_2 lc_trk_g1_7 -B8[14],B9[14],!B9[15],B9[16],B9[17] buffer sp4_v_t_21 lc_trk_g2_0 -B12[14],B13[14],!B13[15],B13[16],B13[17] buffer sp4_v_t_21 lc_trk_g3_0 -B8[21],B8[22],B8[23],!B8[24],B9[21] buffer sp4_v_t_22 lc_trk_g2_3 -B12[21],B12[22],B12[23],!B12[24],B13[21] buffer sp4_v_t_22 lc_trk_g3_3 -B8[25],B9[22],B9[23],!B9[24],B9[25] buffer sp4_v_t_23 lc_trk_g2_2 -B12[25],B13[22],B13[23],!B13[24],B13[25] buffer sp4_v_t_23 lc_trk_g3_2 -B10[14],B11[14],!B11[15],B11[16],B11[17] buffer sp4_v_t_25 lc_trk_g2_4 -B14[14],B15[14],!B15[15],B15[16],B15[17] buffer sp4_v_t_25 lc_trk_g3_4 -B10[21],B10[22],B10[23],!B10[24],B11[21] buffer sp4_v_t_26 lc_trk_g2_7 -B14[21],B14[22],B14[23],!B14[24],B15[21] buffer sp4_v_t_26 lc_trk_g3_7 -!B8[21],B8[22],B8[23],B8[24],!B9[21] buffer sp4_v_t_30 lc_trk_g2_3 -!B12[21],B12[22],B12[23],B12[24],!B13[21] buffer sp4_v_t_30 lc_trk_g3_3 -!B8[25],B9[22],B9[23],B9[24],!B9[25] buffer sp4_v_t_31 lc_trk_g2_2 -!B12[25],B13[22],B13[23],B13[24],!B13[25] buffer sp4_v_t_31 lc_trk_g3_2 -!B10[14],!B11[14],B11[15],B11[16],B11[17] buffer sp4_v_t_33 lc_trk_g2_4 -!B14[14],!B15[14],B15[15],B15[16],B15[17] buffer sp4_v_t_33 lc_trk_g3_4 -!B0[25],B1[22],B1[23],B1[24],!B1[25] buffer sp4_v_t_7 lc_trk_g0_2 -!B4[25],B5[22],B5[23],B5[24],!B5[25] buffer sp4_v_t_7 lc_trk_g1_2 -B2[15],B2[16],B2[17],!B2[18],!B3[18] buffer sp4_v_t_8 lc_trk_g0_5 -B6[15],B6[16],B6[17],!B6[18],!B7[18] buffer sp4_v_t_8 lc_trk_g1_5 -!B8[14],B9[14],B9[15],!B9[16],B9[17] buffer tnl_op_0 lc_trk_g2_0 -!B12[14],B13[14],B13[15],!B13[16],B13[17] buffer tnl_op_0 lc_trk_g3_0 -B8[15],!B8[16],B8[17],!B8[18],B9[18] buffer tnl_op_1 lc_trk_g2_1 -B12[15],!B12[16],B12[17],!B12[18],B13[18] buffer tnl_op_1 lc_trk_g3_1 -!B8[25],B9[22],!B9[23],B9[24],B9[25] buffer tnl_op_2 lc_trk_g2_2 -!B12[25],B13[22],!B13[23],B13[24],B13[25] buffer tnl_op_2 lc_trk_g3_2 -!B8[21],B8[22],!B8[23],B8[24],B9[21] buffer tnl_op_3 lc_trk_g2_3 -!B12[21],B12[22],!B12[23],B12[24],B13[21] buffer tnl_op_3 lc_trk_g3_3 -!B10[14],B11[14],B11[15],!B11[16],B11[17] buffer tnl_op_4 lc_trk_g2_4 -!B14[14],B15[14],B15[15],!B15[16],B15[17] buffer tnl_op_4 lc_trk_g3_4 -B10[15],!B10[16],B10[17],!B10[18],B11[18] buffer tnl_op_5 lc_trk_g2_5 -B14[15],!B14[16],B14[17],!B14[18],B15[18] buffer tnl_op_5 lc_trk_g3_5 -!B10[25],B11[22],!B11[23],B11[24],B11[25] buffer tnl_op_6 lc_trk_g2_6 -!B14[25],B15[22],!B15[23],B15[24],B15[25] buffer tnl_op_6 lc_trk_g3_6 -!B10[21],B10[22],!B10[23],B10[24],B11[21] buffer tnl_op_7 lc_trk_g2_7 -!B14[21],B14[22],!B14[23],B14[24],B15[21] buffer tnl_op_7 lc_trk_g3_7 -!B8[14],!B9[14],B9[15],!B9[16],B9[17] buffer tnr_op_0 lc_trk_g2_0 -!B12[14],!B13[14],B13[15],!B13[16],B13[17] buffer tnr_op_0 lc_trk_g3_0 -B8[15],!B8[16],B8[17],!B8[18],!B9[18] buffer tnr_op_1 lc_trk_g2_1 -B12[15],!B12[16],B12[17],!B12[18],!B13[18] buffer tnr_op_1 lc_trk_g3_1 -!B8[25],B9[22],!B9[23],B9[24],!B9[25] buffer tnr_op_2 lc_trk_g2_2 -!B12[25],B13[22],!B13[23],B13[24],!B13[25] buffer tnr_op_2 lc_trk_g3_2 -!B8[21],B8[22],!B8[23],B8[24],!B9[21] buffer tnr_op_3 lc_trk_g2_3 -!B12[21],B12[22],!B12[23],B12[24],!B13[21] buffer tnr_op_3 lc_trk_g3_3 -!B10[14],!B11[14],B11[15],!B11[16],B11[17] buffer tnr_op_4 lc_trk_g2_4 -!B14[14],!B15[14],B15[15],!B15[16],B15[17] buffer tnr_op_4 lc_trk_g3_4 -B10[15],!B10[16],B10[17],!B10[18],!B11[18] buffer tnr_op_5 lc_trk_g2_5 -B14[15],!B14[16],B14[17],!B14[18],!B15[18] buffer tnr_op_5 lc_trk_g3_5 -!B10[25],B11[22],!B11[23],B11[24],!B11[25] buffer tnr_op_6 lc_trk_g2_6 -!B14[25],B15[22],!B15[23],B15[24],!B15[25] buffer tnr_op_6 lc_trk_g3_6 -!B10[21],B10[22],!B10[23],B10[24],!B11[21] buffer tnr_op_7 lc_trk_g2_7 -!B14[21],B14[22],!B14[23],B14[24],!B15[21] buffer tnr_op_7 lc_trk_g3_7 -!B0[25],B1[22],!B1[23],B1[24],B1[25] buffer top_op_2 lc_trk_g0_2 -!B4[25],B5[22],!B5[23],B5[24],B5[25] buffer top_op_2 lc_trk_g1_2 -!B2[25],B3[22],!B3[23],B3[24],B3[25] buffer top_op_6 lc_trk_g0_6 -!B6[25],B7[22],!B7[23],B7[24],B7[25] buffer top_op_6 lc_trk_g1_6 -B15[38] buffer wire_bram/ram/RDATA_0 sp12_h_l_21 -B14[37] buffer wire_bram/ram/RDATA_0 sp12_h_l_5 -B15[40] buffer wire_bram/ram/RDATA_0 sp12_v_b_14 -B15[36] buffer wire_bram/ram/RDATA_0 sp4_h_l_3 -B15[37] buffer wire_bram/ram/RDATA_0 sp4_h_r_30 -B14[36] buffer wire_bram/ram/RDATA_0 sp4_h_r_46 -B15[41] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_15 -B14[40] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_31 -B14[41] buffer wire_bram/ram/RDATA_0 sp4_r_v_b_47 -B15[39] buffer wire_bram/ram/RDATA_0 sp4_v_b_14 -B14[38] buffer wire_bram/ram/RDATA_0 sp4_v_b_30 -B14[39] buffer wire_bram/ram/RDATA_0 sp4_v_b_46 -B12[37] buffer wire_bram/ram/RDATA_1 sp12_h_l_3 -B13[38] buffer wire_bram/ram/RDATA_1 sp12_h_r_20 -B13[40] buffer wire_bram/ram/RDATA_1 sp12_v_b_12 -B13[37] buffer wire_bram/ram/RDATA_1 sp4_h_l_17 -B13[36] buffer wire_bram/ram/RDATA_1 sp4_h_r_12 -B12[36] buffer wire_bram/ram/RDATA_1 sp4_h_r_44 -B13[41] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_13 -B12[40] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_29 -B12[41] buffer wire_bram/ram/RDATA_1 sp4_r_v_b_45 -B12[38] buffer wire_bram/ram/RDATA_1 sp4_v_b_28 -B13[39] buffer wire_bram/ram/RDATA_1 sp4_v_t_1 -B12[39] buffer wire_bram/ram/RDATA_1 sp4_v_t_33 -B11[38] buffer wire_bram/ram/RDATA_2 sp12_h_r_18 -B10[37] buffer wire_bram/ram/RDATA_2 sp12_h_r_2 -B11[40] buffer wire_bram/ram/RDATA_2 sp12_v_t_9 -B11[37] buffer wire_bram/ram/RDATA_2 sp4_h_l_15 -B11[36] buffer wire_bram/ram/RDATA_2 sp4_h_r_10 -B10[36] buffer wire_bram/ram/RDATA_2 sp4_h_r_42 -B11[41] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_11 -B10[40] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_27 -B10[41] buffer wire_bram/ram/RDATA_2 sp4_r_v_b_43 -B11[39] buffer wire_bram/ram/RDATA_2 sp4_v_b_10 -B10[38] buffer wire_bram/ram/RDATA_2 sp4_v_b_26 -B10[39] buffer wire_bram/ram/RDATA_2 sp4_v_t_31 -B8[37] buffer wire_bram/ram/RDATA_3 sp12_h_r_0 -B9[38] buffer wire_bram/ram/RDATA_3 sp12_h_r_16 -B9[40] buffer wire_bram/ram/RDATA_3 sp12_v_t_7 -B9[37] buffer wire_bram/ram/RDATA_3 sp4_h_l_13 -B8[36] buffer wire_bram/ram/RDATA_3 sp4_h_l_29 -B9[36] buffer wire_bram/ram/RDATA_3 sp4_h_r_8 -B8[40] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_25 -B8[41] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_41 -B9[41] buffer wire_bram/ram/RDATA_3 sp4_r_v_b_9 -B8[39] buffer wire_bram/ram/RDATA_3 sp4_v_b_40 -B9[39] buffer wire_bram/ram/RDATA_3 sp4_v_b_8 -B8[38] buffer wire_bram/ram/RDATA_3 sp4_v_t_13 -B6[37] buffer wire_bram/ram/RDATA_4 sp12_h_l_13 -B6[39] buffer wire_bram/ram/RDATA_4 sp12_v_b_6 -B7[40] buffer wire_bram/ram/RDATA_4 sp12_v_t_21 -B6[36] buffer wire_bram/ram/RDATA_4 sp4_h_l_27 -B7[37] buffer wire_bram/ram/RDATA_4 sp4_h_r_22 -B7[36] buffer wire_bram/ram/RDATA_4 sp4_h_r_6 -B6[40] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_23 -B6[41] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_39 -B7[41] buffer wire_bram/ram/RDATA_4 sp4_r_v_b_7 -B7[39] buffer wire_bram/ram/RDATA_4 sp4_v_b_22 -B6[38] buffer wire_bram/ram/RDATA_4 sp4_v_b_38 -B7[38] buffer wire_bram/ram/RDATA_4 sp4_v_b_6 -B4[37] buffer wire_bram/ram/RDATA_5 sp12_h_r_12 -B5[40] buffer wire_bram/ram/RDATA_5 sp12_v_t_19 -B4[39] buffer wire_bram/ram/RDATA_5 sp12_v_t_3 -B5[37] buffer wire_bram/ram/RDATA_5 sp4_h_r_20 -B4[36] buffer wire_bram/ram/RDATA_5 sp4_h_r_36 -B5[36] buffer wire_bram/ram/RDATA_5 sp4_h_r_4 -B4[40] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_21 -B4[41] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_37 -B5[41] buffer wire_bram/ram/RDATA_5 sp4_r_v_b_5 -B5[39] buffer wire_bram/ram/RDATA_5 sp4_v_b_20 -B5[38] buffer wire_bram/ram/RDATA_5 sp4_v_b_4 -B4[38] buffer wire_bram/ram/RDATA_5 sp4_v_t_25 -B2[37] buffer wire_bram/ram/RDATA_6 sp12_h_r_10 -B2[39] buffer wire_bram/ram/RDATA_6 sp12_v_b_2 -B3[40] buffer wire_bram/ram/RDATA_6 sp12_v_t_17 -B3[37] buffer wire_bram/ram/RDATA_6 sp4_h_l_7 -B3[36] buffer wire_bram/ram/RDATA_6 sp4_h_r_2 -B2[36] buffer wire_bram/ram/RDATA_6 sp4_h_r_34 -B2[40] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_19 -B3[41] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_3 -B2[41] buffer wire_bram/ram/RDATA_6 sp4_r_v_b_35 -B3[38] buffer wire_bram/ram/RDATA_6 sp4_v_b_2 -B2[38] buffer wire_bram/ram/RDATA_6 sp4_v_t_23 -B3[39] buffer wire_bram/ram/RDATA_6 sp4_v_t_7 -B0[37] buffer wire_bram/ram/RDATA_7 sp12_h_r_8 -B0[39] buffer wire_bram/ram/RDATA_7 sp12_v_b_0 -B1[40] buffer wire_bram/ram/RDATA_7 sp12_v_b_16 -B0[36] buffer wire_bram/ram/RDATA_7 sp4_h_l_21 -B1[37] buffer wire_bram/ram/RDATA_7 sp4_h_l_5 -B1[36] buffer wire_bram/ram/RDATA_7 sp4_h_r_0 -B1[41] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_1 -B0[40] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_17 -B0[41] buffer wire_bram/ram/RDATA_7 sp4_r_v_b_33 -B1[38] buffer wire_bram/ram/RDATA_7 sp4_v_b_0 -B1[39] buffer wire_bram/ram/RDATA_7 sp4_v_b_16 -B0[38] buffer wire_bram/ram/RDATA_7 sp4_v_t_21 -!B12[3],B13[3] routing sp12_h_l_22 sp12_h_r_1 -!B8[3],B9[3] routing sp12_h_l_22 sp12_v_b_1 -!B14[3],B15[3] routing sp12_h_l_22 sp12_v_t_22 -!B4[3],B5[3] routing sp12_h_l_23 sp12_h_r_0 -!B0[3],B1[3] routing sp12_h_l_23 sp12_v_b_0 -!B6[3],B7[3] routing sp12_h_l_23 sp12_v_t_23 -B2[3],B3[3] routing sp12_h_r_0 sp12_h_l_23 -B0[3],B1[3] routing sp12_h_r_0 sp12_v_b_0 -B6[3],B7[3] routing sp12_h_r_0 sp12_v_t_23 -B10[3],B11[3] routing sp12_h_r_1 sp12_h_l_22 -B8[3],B9[3] routing sp12_h_r_1 sp12_v_b_1 -B14[3],B15[3] routing sp12_h_r_1 sp12_v_t_22 -!B2[3],B3[3] routing sp12_v_b_0 sp12_h_l_23 -B4[3],B5[3] routing sp12_v_b_0 sp12_h_r_0 -B6[3],!B7[3] routing sp12_v_b_0 sp12_v_t_23 -!B10[3],B11[3] routing sp12_v_b_1 sp12_h_l_22 -B12[3],B13[3] routing sp12_v_b_1 sp12_h_r_1 -B14[3],!B15[3] routing sp12_v_b_1 sp12_v_t_22 -B10[3],!B11[3] routing sp12_v_t_22 sp12_h_l_22 -B12[3],!B13[3] routing sp12_v_t_22 sp12_h_r_1 -B8[3],!B9[3] routing sp12_v_t_22 sp12_v_b_1 -B2[3],!B3[3] routing sp12_v_t_23 sp12_h_l_23 -B4[3],!B5[3] routing sp12_v_t_23 sp12_h_r_0 -B0[3],!B1[3] routing sp12_v_t_23 sp12_v_b_0 -B0[8],!B0[9],!B0[10] routing sp4_h_l_36 sp4_h_r_1 -!B4[8],B4[9],B4[10] routing sp4_h_l_36 sp4_h_r_4 -!B12[5],B13[4],B13[6] routing sp4_h_l_36 sp4_h_r_9 -B1[8],B1[9],!B1[10] routing sp4_h_l_36 sp4_v_b_1 -B9[8],B9[9],B9[10] routing sp4_h_l_36 sp4_v_b_7 -B3[8],!B3[9],!B3[10] routing sp4_h_l_36 sp4_v_t_36 -!B10[4],B10[6],!B11[5] routing sp4_h_l_36 sp4_v_t_43 -!B0[5],!B1[4],B1[6] routing sp4_h_l_37 sp4_h_r_0 -B4[5],B5[4],!B5[6] routing sp4_h_l_37 sp4_h_r_3 -!B8[12],B9[11],B9[13] routing sp4_h_l_37 sp4_h_r_8 -B0[4],!B0[6],B1[5] routing sp4_h_l_37 sp4_v_b_0 -B8[4],B8[6],B9[5] routing sp4_h_l_37 sp4_v_b_6 -!B2[4],!B2[6],B3[5] routing sp4_h_l_37 sp4_v_t_37 -B6[11],!B6[13],!B7[12] routing sp4_h_l_37 sp4_v_t_40 -!B12[12],B13[11],B13[13] routing sp4_h_l_38 sp4_h_r_11 -!B4[5],!B5[4],B5[6] routing sp4_h_l_38 sp4_h_r_3 -B8[5],B9[4],!B9[6] routing sp4_h_l_38 sp4_h_r_6 -B4[4],!B4[6],B5[5] routing sp4_h_l_38 sp4_v_b_3 -B12[4],B12[6],B13[5] routing sp4_h_l_38 sp4_v_b_9 -!B6[4],!B6[6],B7[5] routing sp4_h_l_38 sp4_v_t_38 -B10[11],!B10[13],!B11[12] routing sp4_h_l_38 sp4_v_t_45 -B12[8],!B12[9],B12[10] routing sp4_h_l_39 sp4_h_r_10 -!B0[12],B1[11],!B1[13] routing sp4_h_l_39 sp4_h_r_2 -B4[12],!B5[11],B5[13] routing sp4_h_l_39 sp4_h_r_5 -!B0[11],B0[13],B1[12] routing sp4_h_l_39 sp4_v_b_2 -B8[11],B8[13],B9[12] routing sp4_h_l_39 sp4_v_b_8 -!B2[11],!B2[13],B3[12] routing sp4_h_l_39 sp4_v_t_39 -!B11[8],!B11[9],B11[10] routing sp4_h_l_39 sp4_v_t_42 -B0[8],!B0[9],B0[10] routing sp4_h_l_40 sp4_h_r_1 -!B4[12],B5[11],!B5[13] routing sp4_h_l_40 sp4_h_r_5 -B8[12],!B9[11],B9[13] routing sp4_h_l_40 sp4_h_r_8 -B12[11],B12[13],B13[12] routing sp4_h_l_40 sp4_v_b_11 -!B4[11],B4[13],B5[12] routing sp4_h_l_40 sp4_v_b_5 -!B6[11],!B6[13],B7[12] routing sp4_h_l_40 sp4_v_t_40 -!B15[8],!B15[9],B15[10] routing sp4_h_l_40 sp4_v_t_47 -!B0[5],B1[4],B1[6] routing sp4_h_l_41 sp4_h_r_0 -B4[8],!B4[9],!B4[10] routing sp4_h_l_41 sp4_h_r_4 -!B8[8],B8[9],B8[10] routing sp4_h_l_41 sp4_h_r_7 -B13[8],B13[9],B13[10] routing sp4_h_l_41 sp4_v_b_10 -B5[8],B5[9],!B5[10] routing sp4_h_l_41 sp4_v_b_4 -B7[8],!B7[9],!B7[10] routing sp4_h_l_41 sp4_v_t_41 -!B14[4],B14[6],!B15[5] routing sp4_h_l_41 sp4_v_t_44 -!B12[8],B12[9],B12[10] routing sp4_h_l_42 sp4_h_r_10 -!B4[5],B5[4],B5[6] routing sp4_h_l_42 sp4_h_r_3 -B8[8],!B8[9],!B8[10] routing sp4_h_l_42 sp4_h_r_7 -B1[8],B1[9],B1[10] routing sp4_h_l_42 sp4_v_b_1 -B9[8],B9[9],!B9[10] routing sp4_h_l_42 sp4_v_b_7 -!B2[4],B2[6],!B3[5] routing sp4_h_l_42 sp4_v_t_37 -B11[8],!B11[9],!B11[10] routing sp4_h_l_42 sp4_v_t_42 -!B0[12],B1[11],B1[13] routing sp4_h_l_43 sp4_h_r_2 -!B8[5],!B9[4],B9[6] routing sp4_h_l_43 sp4_h_r_6 -B12[5],B13[4],!B13[6] routing sp4_h_l_43 sp4_h_r_9 -B0[4],B0[6],B1[5] routing sp4_h_l_43 sp4_v_b_0 -B8[4],!B8[6],B9[5] routing sp4_h_l_43 sp4_v_b_6 -!B10[4],!B10[6],B11[5] routing sp4_h_l_43 sp4_v_t_43 -B14[11],!B14[13],!B15[12] routing sp4_h_l_43 sp4_v_t_46 -B0[5],B1[4],!B1[6] routing sp4_h_l_44 sp4_h_r_0 -!B4[12],B5[11],B5[13] routing sp4_h_l_44 sp4_h_r_5 -!B12[5],!B13[4],B13[6] routing sp4_h_l_44 sp4_h_r_9 -B4[4],B4[6],B5[5] routing sp4_h_l_44 sp4_v_b_3 -B12[4],!B12[6],B13[5] routing sp4_h_l_44 sp4_v_b_9 -B2[11],!B2[13],!B3[12] routing sp4_h_l_44 sp4_v_t_39 -!B14[4],!B14[6],B15[5] routing sp4_h_l_44 sp4_v_t_44 -B12[12],!B13[11],B13[13] routing sp4_h_l_45 sp4_h_r_11 -B4[8],!B4[9],B4[10] routing sp4_h_l_45 sp4_h_r_4 -!B8[12],B9[11],!B9[13] routing sp4_h_l_45 sp4_h_r_8 -B0[11],B0[13],B1[12] routing sp4_h_l_45 sp4_v_b_2 -!B8[11],B8[13],B9[12] routing sp4_h_l_45 sp4_v_b_8 -!B3[8],!B3[9],B3[10] routing sp4_h_l_45 sp4_v_t_36 -!B10[11],!B10[13],B11[12] routing sp4_h_l_45 sp4_v_t_45 -!B12[12],B13[11],!B13[13] routing sp4_h_l_46 sp4_h_r_11 -B0[12],!B1[11],B1[13] routing sp4_h_l_46 sp4_h_r_2 -B8[8],!B8[9],B8[10] routing sp4_h_l_46 sp4_h_r_7 -!B12[11],B12[13],B13[12] routing sp4_h_l_46 sp4_v_b_11 -B4[11],B4[13],B5[12] routing sp4_h_l_46 sp4_v_b_5 -!B7[8],!B7[9],B7[10] routing sp4_h_l_46 sp4_v_t_41 -!B14[11],!B14[13],B15[12] routing sp4_h_l_46 sp4_v_t_46 -!B0[8],B0[9],B0[10] routing sp4_h_l_47 sp4_h_r_1 -B12[8],!B12[9],!B12[10] routing sp4_h_l_47 sp4_h_r_10 -!B8[5],B9[4],B9[6] routing sp4_h_l_47 sp4_h_r_6 -B13[8],B13[9],!B13[10] routing sp4_h_l_47 sp4_v_b_10 -B5[8],B5[9],B5[10] routing sp4_h_l_47 sp4_v_b_4 -!B6[4],B6[6],!B7[5] routing sp4_h_l_47 sp4_v_t_38 -B15[8],!B15[9],!B15[10] routing sp4_h_l_47 sp4_v_t_47 -!B2[5],!B3[4],B3[6] routing sp4_h_r_0 sp4_h_l_37 -B6[5],B7[4],!B7[6] routing sp4_h_r_0 sp4_h_l_38 -!B10[12],B11[11],B11[13] routing sp4_h_r_0 sp4_h_l_45 -!B0[4],!B0[6],B1[5] routing sp4_h_r_0 sp4_v_b_0 -B4[11],!B4[13],!B5[12] routing sp4_h_r_0 sp4_v_b_5 -B2[4],!B2[6],B3[5] routing sp4_h_r_0 sp4_v_t_37 -B10[4],B10[6],B11[5] routing sp4_h_r_0 sp4_v_t_43 -B2[8],!B2[9],!B2[10] routing sp4_h_r_1 sp4_h_l_36 -!B6[8],B6[9],B6[10] routing sp4_h_r_1 sp4_h_l_41 -!B14[5],B15[4],B15[6] routing sp4_h_r_1 sp4_h_l_44 -B1[8],!B1[9],!B1[10] routing sp4_h_r_1 sp4_v_b_1 -!B8[4],B8[6],!B9[5] routing sp4_h_r_1 sp4_v_b_6 -B3[8],B3[9],!B3[10] routing sp4_h_r_1 sp4_v_t_36 -B11[8],B11[9],B11[10] routing sp4_h_r_1 sp4_v_t_42 -!B2[8],B2[9],B2[10] routing sp4_h_r_10 sp4_h_l_36 -!B10[5],B11[4],B11[6] routing sp4_h_r_10 sp4_h_l_43 -B14[8],!B14[9],!B14[10] routing sp4_h_r_10 sp4_h_l_47 -B13[8],!B13[9],!B13[10] routing sp4_h_r_10 sp4_v_b_10 -!B4[4],B4[6],!B5[5] routing sp4_h_r_10 sp4_v_b_3 -B7[8],B7[9],B7[10] routing sp4_h_r_10 sp4_v_t_41 -B15[8],B15[9],!B15[10] routing sp4_h_r_10 sp4_v_t_47 -B2[12],!B3[11],B3[13] routing sp4_h_r_11 sp4_h_l_39 -B10[8],!B10[9],B10[10] routing sp4_h_r_11 sp4_h_l_42 -!B14[12],B15[11],!B15[13] routing sp4_h_r_11 sp4_h_l_46 -!B12[11],!B12[13],B13[12] routing sp4_h_r_11 sp4_v_b_11 -!B5[8],!B5[9],B5[10] routing sp4_h_r_11 sp4_v_b_4 -B6[11],B6[13],B7[12] routing sp4_h_r_11 sp4_v_t_40 -!B14[11],B14[13],B15[12] routing sp4_h_r_11 sp4_v_t_46 -!B2[12],B3[11],!B3[13] routing sp4_h_r_2 sp4_h_l_39 -B6[12],!B7[11],B7[13] routing sp4_h_r_2 sp4_h_l_40 -B14[8],!B14[9],B14[10] routing sp4_h_r_2 sp4_h_l_47 -!B0[11],!B0[13],B1[12] routing sp4_h_r_2 sp4_v_b_2 -!B9[8],!B9[9],B9[10] routing sp4_h_r_2 sp4_v_b_7 -!B2[11],B2[13],B3[12] routing sp4_h_r_2 sp4_v_t_39 -B10[11],B10[13],B11[12] routing sp4_h_r_2 sp4_v_t_45 -!B6[5],!B7[4],B7[6] routing sp4_h_r_3 sp4_h_l_38 -B10[5],B11[4],!B11[6] routing sp4_h_r_3 sp4_h_l_43 -!B14[12],B15[11],B15[13] routing sp4_h_r_3 sp4_h_l_46 -!B4[4],!B4[6],B5[5] routing sp4_h_r_3 sp4_v_b_3 -B8[11],!B8[13],!B9[12] routing sp4_h_r_3 sp4_v_b_8 -B6[4],!B6[6],B7[5] routing sp4_h_r_3 sp4_v_t_38 -B14[4],B14[6],B15[5] routing sp4_h_r_3 sp4_v_t_44 -!B2[5],B3[4],B3[6] routing sp4_h_r_4 sp4_h_l_37 -B6[8],!B6[9],!B6[10] routing sp4_h_r_4 sp4_h_l_41 -!B10[8],B10[9],B10[10] routing sp4_h_r_4 sp4_h_l_42 -B5[8],!B5[9],!B5[10] routing sp4_h_r_4 sp4_v_b_4 -!B12[4],B12[6],!B13[5] routing sp4_h_r_4 sp4_v_b_9 -B7[8],B7[9],!B7[10] routing sp4_h_r_4 sp4_v_t_41 -B15[8],B15[9],B15[10] routing sp4_h_r_4 sp4_v_t_47 -B2[8],!B2[9],B2[10] routing sp4_h_r_5 sp4_h_l_36 -!B6[12],B7[11],!B7[13] routing sp4_h_r_5 sp4_h_l_40 -B10[12],!B11[11],B11[13] routing sp4_h_r_5 sp4_h_l_45 -!B13[8],!B13[9],B13[10] routing sp4_h_r_5 sp4_v_b_10 -!B4[11],!B4[13],B5[12] routing sp4_h_r_5 sp4_v_b_5 -!B6[11],B6[13],B7[12] routing sp4_h_r_5 sp4_v_t_40 -B14[11],B14[13],B15[12] routing sp4_h_r_5 sp4_v_t_46 -!B2[12],B3[11],B3[13] routing sp4_h_r_6 sp4_h_l_39 -!B10[5],!B11[4],B11[6] routing sp4_h_r_6 sp4_h_l_43 -B14[5],B15[4],!B15[6] routing sp4_h_r_6 sp4_h_l_44 -B12[11],!B12[13],!B13[12] routing sp4_h_r_6 sp4_v_b_11 -!B8[4],!B8[6],B9[5] routing sp4_h_r_6 sp4_v_b_6 -B2[4],B2[6],B3[5] routing sp4_h_r_6 sp4_v_t_37 -B10[4],!B10[6],B11[5] routing sp4_h_r_6 sp4_v_t_43 -!B6[5],B7[4],B7[6] routing sp4_h_r_7 sp4_h_l_38 -B10[8],!B10[9],!B10[10] routing sp4_h_r_7 sp4_h_l_42 -!B14[8],B14[9],B14[10] routing sp4_h_r_7 sp4_h_l_47 -!B0[4],B0[6],!B1[5] routing sp4_h_r_7 sp4_v_b_0 -B9[8],!B9[9],!B9[10] routing sp4_h_r_7 sp4_v_b_7 -B3[8],B3[9],B3[10] routing sp4_h_r_7 sp4_v_t_36 -B11[8],B11[9],!B11[10] routing sp4_h_r_7 sp4_v_t_42 -B6[8],!B6[9],B6[10] routing sp4_h_r_8 sp4_h_l_41 -!B10[12],B11[11],!B11[13] routing sp4_h_r_8 sp4_h_l_45 -B14[12],!B15[11],B15[13] routing sp4_h_r_8 sp4_h_l_46 -!B1[8],!B1[9],B1[10] routing sp4_h_r_8 sp4_v_b_1 -!B8[11],!B8[13],B9[12] routing sp4_h_r_8 sp4_v_b_8 -B2[11],B2[13],B3[12] routing sp4_h_r_8 sp4_v_t_39 -!B10[11],B10[13],B11[12] routing sp4_h_r_8 sp4_v_t_45 -B2[5],B3[4],!B3[6] routing sp4_h_r_9 sp4_h_l_37 -!B6[12],B7[11],B7[13] routing sp4_h_r_9 sp4_h_l_40 -!B14[5],!B15[4],B15[6] routing sp4_h_r_9 sp4_h_l_44 -B0[11],!B0[13],!B1[12] routing sp4_h_r_9 sp4_v_b_2 -!B12[4],!B12[6],B13[5] routing sp4_h_r_9 sp4_v_b_9 -B6[4],B6[6],B7[5] routing sp4_h_r_9 sp4_v_t_38 -B14[4],!B14[6],B15[5] routing sp4_h_r_9 sp4_v_t_44 -B2[5],!B3[4],!B3[6] routing sp4_v_b_0 sp4_h_l_37 -!B6[12],!B7[11],B7[13] routing sp4_v_b_0 sp4_h_l_40 -B0[5],!B1[4],B1[6] routing sp4_v_b_0 sp4_h_r_0 -B8[5],B9[4],B9[6] routing sp4_v_b_0 sp4_h_r_6 -B2[4],!B2[6],!B3[5] routing sp4_v_b_0 sp4_v_t_37 -!B6[4],B6[6],B7[5] routing sp4_v_b_0 sp4_v_t_38 -B10[11],B10[13],!B11[12] routing sp4_v_b_0 sp4_v_t_45 -!B2[8],B2[9],!B2[10] routing sp4_v_b_1 sp4_h_l_36 -!B10[5],B11[4],!B11[6] routing sp4_v_b_1 sp4_h_l_43 -B0[8],B0[9],!B0[10] routing sp4_v_b_1 sp4_h_r_1 -B8[8],B8[9],B8[10] routing sp4_v_b_1 sp4_h_r_7 -!B3[8],B3[9],!B3[10] routing sp4_v_b_1 sp4_v_t_36 -B7[8],!B7[9],B7[10] routing sp4_v_b_1 sp4_v_t_41 -B14[4],B14[6],!B15[5] routing sp4_v_b_1 sp4_v_t_44 -!B6[5],B7[4],!B7[6] routing sp4_v_b_10 sp4_h_l_38 -!B14[8],B14[9],!B14[10] routing sp4_v_b_10 sp4_h_l_47 -B12[8],B12[9],!B12[10] routing sp4_v_b_10 sp4_h_r_10 -B4[8],B4[9],B4[10] routing sp4_v_b_10 sp4_h_r_4 -B3[8],!B3[9],B3[10] routing sp4_v_b_10 sp4_v_t_36 -B10[4],B10[6],!B11[5] routing sp4_v_b_10 sp4_v_t_43 -!B15[8],B15[9],!B15[10] routing sp4_v_b_10 sp4_v_t_47 -!B6[8],!B6[9],B6[10] routing sp4_v_b_11 sp4_h_l_41 -B14[12],!B15[11],!B15[13] routing sp4_v_b_11 sp4_h_l_46 -B12[12],B13[11],!B13[13] routing sp4_v_b_11 sp4_h_r_11 -B4[12],B5[11],B5[13] routing sp4_v_b_11 sp4_h_r_5 -B2[11],!B2[13],B3[12] routing sp4_v_b_11 sp4_v_t_39 -!B11[8],B11[9],B11[10] routing sp4_v_b_11 sp4_v_t_42 -!B14[11],B14[13],!B15[12] routing sp4_v_b_11 sp4_v_t_46 -B2[12],!B3[11],!B3[13] routing sp4_v_b_2 sp4_h_l_39 -!B10[8],!B10[9],B10[10] routing sp4_v_b_2 sp4_h_l_42 -B0[12],B1[11],!B1[13] routing sp4_v_b_2 sp4_h_r_2 -B8[12],B9[11],B9[13] routing sp4_v_b_2 sp4_h_r_8 -!B2[11],B2[13],!B3[12] routing sp4_v_b_2 sp4_v_t_39 -B6[11],!B6[13],B7[12] routing sp4_v_b_2 sp4_v_t_40 -!B15[8],B15[9],B15[10] routing sp4_v_b_2 sp4_v_t_47 -B6[5],!B7[4],!B7[6] routing sp4_v_b_3 sp4_h_l_38 -!B10[12],!B11[11],B11[13] routing sp4_v_b_3 sp4_h_l_45 -B4[5],!B5[4],B5[6] routing sp4_v_b_3 sp4_h_r_3 -B12[5],B13[4],B13[6] routing sp4_v_b_3 sp4_h_r_9 -B6[4],!B6[6],!B7[5] routing sp4_v_b_3 sp4_v_t_38 -!B10[4],B10[6],B11[5] routing sp4_v_b_3 sp4_v_t_43 -B14[11],B14[13],!B15[12] routing sp4_v_b_3 sp4_v_t_46 -!B6[8],B6[9],!B6[10] routing sp4_v_b_4 sp4_h_l_41 -!B14[5],B15[4],!B15[6] routing sp4_v_b_4 sp4_h_l_44 -B12[8],B12[9],B12[10] routing sp4_v_b_4 sp4_h_r_10 -B4[8],B4[9],!B4[10] routing sp4_v_b_4 sp4_h_r_4 -B2[4],B2[6],!B3[5] routing sp4_v_b_4 sp4_v_t_37 -!B7[8],B7[9],!B7[10] routing sp4_v_b_4 sp4_v_t_41 -B11[8],!B11[9],B11[10] routing sp4_v_b_4 sp4_v_t_42 -B6[12],!B7[11],!B7[13] routing sp4_v_b_5 sp4_h_l_40 -!B14[8],!B14[9],B14[10] routing sp4_v_b_5 sp4_h_l_47 -B12[12],B13[11],B13[13] routing sp4_v_b_5 sp4_h_r_11 -B4[12],B5[11],!B5[13] routing sp4_v_b_5 sp4_h_r_5 -!B3[8],B3[9],B3[10] routing sp4_v_b_5 sp4_v_t_36 -!B6[11],B6[13],!B7[12] routing sp4_v_b_5 sp4_v_t_40 -B10[11],!B10[13],B11[12] routing sp4_v_b_5 sp4_v_t_45 -B10[5],!B11[4],!B11[6] routing sp4_v_b_6 sp4_h_l_43 -!B14[12],!B15[11],B15[13] routing sp4_v_b_6 sp4_h_l_46 -B0[5],B1[4],B1[6] routing sp4_v_b_6 sp4_h_r_0 -B8[5],!B9[4],B9[6] routing sp4_v_b_6 sp4_h_r_6 -B2[11],B2[13],!B3[12] routing sp4_v_b_6 sp4_v_t_39 -B10[4],!B10[6],!B11[5] routing sp4_v_b_6 sp4_v_t_43 -!B14[4],B14[6],B15[5] routing sp4_v_b_6 sp4_v_t_44 -!B2[5],B3[4],!B3[6] routing sp4_v_b_7 sp4_h_l_37 -!B10[8],B10[9],!B10[10] routing sp4_v_b_7 sp4_h_l_42 -B0[8],B0[9],B0[10] routing sp4_v_b_7 sp4_h_r_1 -B8[8],B8[9],!B8[10] routing sp4_v_b_7 sp4_h_r_7 -B6[4],B6[6],!B7[5] routing sp4_v_b_7 sp4_v_t_38 -!B11[8],B11[9],!B11[10] routing sp4_v_b_7 sp4_v_t_42 -B15[8],!B15[9],B15[10] routing sp4_v_b_7 sp4_v_t_47 -!B2[8],!B2[9],B2[10] routing sp4_v_b_8 sp4_h_l_36 -B10[12],!B11[11],!B11[13] routing sp4_v_b_8 sp4_h_l_45 -B0[12],B1[11],B1[13] routing sp4_v_b_8 sp4_h_r_2 -B8[12],B9[11],!B9[13] routing sp4_v_b_8 sp4_h_r_8 -!B7[8],B7[9],B7[10] routing sp4_v_b_8 sp4_v_t_41 -!B10[11],B10[13],!B11[12] routing sp4_v_b_8 sp4_v_t_45 -B14[11],!B14[13],B15[12] routing sp4_v_b_8 sp4_v_t_46 -!B2[12],!B3[11],B3[13] routing sp4_v_b_9 sp4_h_l_39 -B14[5],!B15[4],!B15[6] routing sp4_v_b_9 sp4_h_l_44 -B4[5],B5[4],B5[6] routing sp4_v_b_9 sp4_h_r_3 -B12[5],!B13[4],B13[6] routing sp4_v_b_9 sp4_h_r_9 -!B2[4],B2[6],B3[5] routing sp4_v_b_9 sp4_v_t_37 -B6[11],B6[13],!B7[12] routing sp4_v_b_9 sp4_v_t_40 -B14[4],!B14[6],!B15[5] routing sp4_v_b_9 sp4_v_t_44 -B2[8],B2[9],!B2[10] routing sp4_v_t_36 sp4_h_l_36 -B10[8],B10[9],B10[10] routing sp4_v_t_36 sp4_h_l_42 -!B0[8],B0[9],!B0[10] routing sp4_v_t_36 sp4_h_r_1 -!B8[5],B9[4],!B9[6] routing sp4_v_t_36 sp4_h_r_6 -!B1[8],B1[9],!B1[10] routing sp4_v_t_36 sp4_v_b_1 -B5[8],!B5[9],B5[10] routing sp4_v_t_36 sp4_v_b_4 -B12[4],B12[6],!B13[5] routing sp4_v_t_36 sp4_v_b_9 -B2[5],!B3[4],B3[6] routing sp4_v_t_37 sp4_h_l_37 -B10[5],B11[4],B11[6] routing sp4_v_t_37 sp4_h_l_43 -B0[5],!B1[4],!B1[6] routing sp4_v_t_37 sp4_h_r_0 -!B4[12],!B5[11],B5[13] routing sp4_v_t_37 sp4_h_r_5 -B0[4],!B0[6],!B1[5] routing sp4_v_t_37 sp4_v_b_0 -!B4[4],B4[6],B5[5] routing sp4_v_t_37 sp4_v_b_3 -B8[11],B8[13],!B9[12] routing sp4_v_t_37 sp4_v_b_8 -B6[5],!B7[4],B7[6] routing sp4_v_t_38 sp4_h_l_38 -B14[5],B15[4],B15[6] routing sp4_v_t_38 sp4_h_l_44 -B4[5],!B5[4],!B5[6] routing sp4_v_t_38 sp4_h_r_3 -!B8[12],!B9[11],B9[13] routing sp4_v_t_38 sp4_h_r_8 -B12[11],B12[13],!B13[12] routing sp4_v_t_38 sp4_v_b_11 -B4[4],!B4[6],!B5[5] routing sp4_v_t_38 sp4_v_b_3 -!B8[4],B8[6],B9[5] routing sp4_v_t_38 sp4_v_b_6 -B2[12],B3[11],!B3[13] routing sp4_v_t_39 sp4_h_l_39 -B10[12],B11[11],B11[13] routing sp4_v_t_39 sp4_h_l_45 -B0[12],!B1[11],!B1[13] routing sp4_v_t_39 sp4_h_r_2 -!B8[8],!B8[9],B8[10] routing sp4_v_t_39 sp4_h_r_7 -!B13[8],B13[9],B13[10] routing sp4_v_t_39 sp4_v_b_10 -!B0[11],B0[13],!B1[12] routing sp4_v_t_39 sp4_v_b_2 -B4[11],!B4[13],B5[12] routing sp4_v_t_39 sp4_v_b_5 -B6[12],B7[11],!B7[13] routing sp4_v_t_40 sp4_h_l_40 -B14[12],B15[11],B15[13] routing sp4_v_t_40 sp4_h_l_46 -!B12[8],!B12[9],B12[10] routing sp4_v_t_40 sp4_h_r_10 -B4[12],!B5[11],!B5[13] routing sp4_v_t_40 sp4_h_r_5 -!B1[8],B1[9],B1[10] routing sp4_v_t_40 sp4_v_b_1 -!B4[11],B4[13],!B5[12] routing sp4_v_t_40 sp4_v_b_5 -B8[11],!B8[13],B9[12] routing sp4_v_t_40 sp4_v_b_8 -B6[8],B6[9],!B6[10] routing sp4_v_t_41 sp4_h_l_41 -B14[8],B14[9],B14[10] routing sp4_v_t_41 sp4_h_l_47 -!B4[8],B4[9],!B4[10] routing sp4_v_t_41 sp4_h_r_4 -!B12[5],B13[4],!B13[6] routing sp4_v_t_41 sp4_h_r_9 -B0[4],B0[6],!B1[5] routing sp4_v_t_41 sp4_v_b_0 -!B5[8],B5[9],!B5[10] routing sp4_v_t_41 sp4_v_b_4 -B9[8],!B9[9],B9[10] routing sp4_v_t_41 sp4_v_b_7 -B2[8],B2[9],B2[10] routing sp4_v_t_42 sp4_h_l_36 -B10[8],B10[9],!B10[10] routing sp4_v_t_42 sp4_h_l_42 -!B0[5],B1[4],!B1[6] routing sp4_v_t_42 sp4_h_r_0 -!B8[8],B8[9],!B8[10] routing sp4_v_t_42 sp4_h_r_7 -B13[8],!B13[9],B13[10] routing sp4_v_t_42 sp4_v_b_10 -B4[4],B4[6],!B5[5] routing sp4_v_t_42 sp4_v_b_3 -!B9[8],B9[9],!B9[10] routing sp4_v_t_42 sp4_v_b_7 -B2[5],B3[4],B3[6] routing sp4_v_t_43 sp4_h_l_37 -B10[5],!B11[4],B11[6] routing sp4_v_t_43 sp4_h_l_43 -!B12[12],!B13[11],B13[13] routing sp4_v_t_43 sp4_h_r_11 -B8[5],!B9[4],!B9[6] routing sp4_v_t_43 sp4_h_r_6 -B0[11],B0[13],!B1[12] routing sp4_v_t_43 sp4_v_b_2 -B8[4],!B8[6],!B9[5] routing sp4_v_t_43 sp4_v_b_6 -!B12[4],B12[6],B13[5] routing sp4_v_t_43 sp4_v_b_9 -B6[5],B7[4],B7[6] routing sp4_v_t_44 sp4_h_l_38 -B14[5],!B15[4],B15[6] routing sp4_v_t_44 sp4_h_l_44 -!B0[12],!B1[11],B1[13] routing sp4_v_t_44 sp4_h_r_2 -B12[5],!B13[4],!B13[6] routing sp4_v_t_44 sp4_h_r_9 -!B0[4],B0[6],B1[5] routing sp4_v_t_44 sp4_v_b_0 -B4[11],B4[13],!B5[12] routing sp4_v_t_44 sp4_v_b_5 -B12[4],!B12[6],!B13[5] routing sp4_v_t_44 sp4_v_b_9 -B2[12],B3[11],B3[13] routing sp4_v_t_45 sp4_h_l_39 -B10[12],B11[11],!B11[13] routing sp4_v_t_45 sp4_h_l_45 -!B0[8],!B0[9],B0[10] routing sp4_v_t_45 sp4_h_r_1 -B8[12],!B9[11],!B9[13] routing sp4_v_t_45 sp4_h_r_8 -B12[11],!B12[13],B13[12] routing sp4_v_t_45 sp4_v_b_11 -!B5[8],B5[9],B5[10] routing sp4_v_t_45 sp4_v_b_4 -!B8[11],B8[13],!B9[12] routing sp4_v_t_45 sp4_v_b_8 -B6[12],B7[11],B7[13] routing sp4_v_t_46 sp4_h_l_40 -B14[12],B15[11],!B15[13] routing sp4_v_t_46 sp4_h_l_46 -B12[12],!B13[11],!B13[13] routing sp4_v_t_46 sp4_h_r_11 -!B4[8],!B4[9],B4[10] routing sp4_v_t_46 sp4_h_r_4 -!B12[11],B12[13],!B13[12] routing sp4_v_t_46 sp4_v_b_11 -B0[11],!B0[13],B1[12] routing sp4_v_t_46 sp4_v_b_2 -!B9[8],B9[9],B9[10] routing sp4_v_t_46 sp4_v_b_7 -B6[8],B6[9],B6[10] routing sp4_v_t_47 sp4_h_l_41 -B14[8],B14[9],!B14[10] routing sp4_v_t_47 sp4_h_l_47 -!B12[8],B12[9],!B12[10] routing sp4_v_t_47 sp4_h_r_10 -!B4[5],B5[4],!B5[6] routing sp4_v_t_47 sp4_h_r_3 -B1[8],!B1[9],B1[10] routing sp4_v_t_47 sp4_v_b_1 -!B13[8],B13[9],!B13[10] routing sp4_v_t_47 sp4_v_b_10 -B8[4],B8[6],!B9[5] routing sp4_v_t_47 sp4_v_b_6 -""" database_ramb_8k_txt = """ B9[7] ColBufCtrl 8k_glb_netwk_0 B8[7] ColBufCtrl 8k_glb_netwk_1 diff --git a/icefuzz/Makefile b/icefuzz/Makefile index 0d9a8d9..12b7862 100644 --- a/icefuzz/Makefile +++ b/icefuzz/Makefile @@ -15,7 +15,7 @@ endif ifeq ($(DEVICECLASS), 5k) DEVICE := up5k-sg48 - RAM_SUFFIX := _5k + RAM_SUFFIX := _8k endif ifeq ($(DEVICECLASS), 8k) @@ -56,14 +56,11 @@ ifneq ($(RAM_SUFFIX),_8k) cp cached_ramt_8k.txt bitdata_ramt_8k.txt endif ifneq ($(RAM_SUFFIX),_5k) - cp cached_ramb_5k.txt bitdata_ramb_5k.txt - cp cached_ramt_5k.txt bitdata_ramt_5k.txt cp cached_dsp0_5k.txt bitdata_dsp0_5k.txt cp cached_dsp1_5k.txt bitdata_dsp1_5k.txt cp cached_dsp2_5k.txt bitdata_dsp2_5k.txt cp cached_dsp3_5k.txt bitdata_dsp3_5k.txt cp cached_ipcon_5k.txt bitdata_ipcon_5k.txt - endif ICEDEVICE=$(DEVICECLASS) python3 database.py python3 export.py diff --git a/icefuzz/cached_ramb_5k.txt b/icefuzz/cached_ramb_5k.txt deleted file mode 100644 index 85d0e11..0000000 --- a/icefuzz/cached_ramb_5k.txt +++ /dev/null @@ -1,3563 +0,0 @@ -(0 0) Negative Clock bit -(0 10) routing glb_netwk_2 glb2local_2 -(0 10) routing glb_netwk_3 glb2local_2 -(0 10) routing glb_netwk_6 glb2local_2 -(0 10) routing glb_netwk_7 glb2local_2 -(0 11) routing glb_netwk_1 glb2local_2 -(0 11) routing glb_netwk_3 glb2local_2 -(0 11) routing glb_netwk_5 glb2local_2 -(0 11) routing glb_netwk_7 glb2local_2 -(0 12) routing glb_netwk_2 glb2local_3 -(0 12) routing glb_netwk_3 glb2local_3 -(0 12) routing glb_netwk_6 glb2local_3 -(0 12) routing glb_netwk_7 glb2local_3 -(0 13) routing glb_netwk_1 glb2local_3 -(0 13) routing glb_netwk_3 glb2local_3 -(0 13) routing glb_netwk_5 glb2local_3 -(0 13) routing glb_netwk_7 glb2local_3 -(0 14) routing glb_netwk_4 wire_bram/ram/RE -(0 14) routing glb_netwk_6 wire_bram/ram/RE -(0 14) routing lc_trk_g2_4 wire_bram/ram/RE -(0 14) routing lc_trk_g3_5 wire_bram/ram/RE -(0 15) routing glb_netwk_2 wire_bram/ram/RE -(0 15) routing glb_netwk_6 wire_bram/ram/RE -(0 15) routing lc_trk_g1_5 wire_bram/ram/RE -(0 15) routing lc_trk_g3_5 wire_bram/ram/RE -(0 2) routing glb_netwk_2 wire_bram/ram/RCLK -(0 2) routing glb_netwk_3 wire_bram/ram/RCLK -(0 2) routing glb_netwk_6 wire_bram/ram/RCLK -(0 2) routing glb_netwk_7 wire_bram/ram/RCLK -(0 2) routing lc_trk_g2_0 wire_bram/ram/RCLK -(0 2) routing lc_trk_g3_1 wire_bram/ram/RCLK -(0 3) routing glb_netwk_1 wire_bram/ram/RCLK -(0 3) routing glb_netwk_3 wire_bram/ram/RCLK -(0 3) routing glb_netwk_5 wire_bram/ram/RCLK -(0 3) routing glb_netwk_7 wire_bram/ram/RCLK -(0 3) routing lc_trk_g1_1 wire_bram/ram/RCLK -(0 3) routing lc_trk_g3_1 wire_bram/ram/RCLK -(0 4) routing lc_trk_g2_2 wire_bram/ram/RCLKE -(0 4) routing lc_trk_g3_3 wire_bram/ram/RCLKE -(0 5) routing lc_trk_g1_3 wire_bram/ram/RCLKE -(0 5) routing lc_trk_g3_3 wire_bram/ram/RCLKE -(0 6) routing glb_netwk_3 glb2local_0 -(0 6) routing glb_netwk_6 glb2local_0 -(0 6) routing glb_netwk_7 glb2local_0 -(0 7) routing glb_netwk_1 glb2local_0 -(0 7) routing glb_netwk_3 glb2local_0 -(0 7) routing glb_netwk_5 glb2local_0 -(0 7) routing glb_netwk_7 glb2local_0 -(0 8) routing glb_netwk_3 glb2local_1 -(0 8) routing glb_netwk_6 glb2local_1 -(0 9) routing glb_netwk_1 glb2local_1 -(0 9) routing glb_netwk_3 glb2local_1 -(0 9) routing glb_netwk_5 glb2local_1 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_2 glb2local_2 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2 -(1 11) routing glb_netwk_4 glb2local_2 -(1 11) routing glb_netwk_5 glb2local_2 -(1 11) routing glb_netwk_6 glb2local_2 -(1 11) routing glb_netwk_7 glb2local_2 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_2 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3 -(1 13) routing glb_netwk_4 glb2local_3 -(1 13) routing glb_netwk_5 glb2local_3 -(1 13) routing glb_netwk_6 glb2local_3 -(1 13) routing glb_netwk_7 glb2local_3 -(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_bram/ram/RE -(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_bram/ram/RE -(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_bram/ram/RE -(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_bram/ram/RE -(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g1_5 wire_bram/ram/RE -(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_bram/ram/RE -(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g3_5 wire_bram/ram/RE -(1 15) routing lc_trk_g0_4 wire_bram/ram/RE -(1 15) routing lc_trk_g1_5 wire_bram/ram/RE -(1 15) routing lc_trk_g2_4 wire_bram/ram/RE -(1 15) routing lc_trk_g3_5 wire_bram/ram/RE -(1 2) routing glb_netwk_4 wire_bram/ram/RCLK -(1 2) routing glb_netwk_5 wire_bram/ram/RCLK -(1 2) routing glb_netwk_6 wire_bram/ram/RCLK -(1 2) routing glb_netwk_7 wire_bram/ram/RCLK -(1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_l_9 sp4_h_r_17 -(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g0_2 wire_bram/ram/RCLKE -(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g1_3 wire_bram/ram/RCLKE -(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g2_2 wire_bram/ram/RCLKE -(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g3_3 wire_bram/ram/RCLKE -(1 5) routing lc_trk_g0_2 wire_bram/ram/RCLKE -(1 5) routing lc_trk_g1_3 wire_bram/ram/RCLKE -(1 5) routing lc_trk_g2_2 wire_bram/ram/RCLKE -(1 5) routing lc_trk_g3_3 wire_bram/ram/RCLKE -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0 -(1 7) routing glb_netwk_4 glb2local_0 -(1 7) routing glb_netwk_5 glb2local_0 -(1 7) routing glb_netwk_6 glb2local_0 -(1 7) routing glb_netwk_7 glb2local_0 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1 -(1 9) routing glb_netwk_4 glb2local_1 -(1 9) routing glb_netwk_5 glb2local_1 -(1 9) routing glb_netwk_6 glb2local_1 -(10 0) routing sp4_h_l_40 sp4_h_r_1 -(10 0) routing sp4_h_l_47 sp4_h_r_1 -(10 0) routing sp4_v_b_7 sp4_h_r_1 -(10 0) routing sp4_v_t_45 sp4_h_r_1 -(10 1) routing sp4_h_l_42 sp4_v_b_1 -(10 1) routing sp4_h_r_8 sp4_v_b_1 -(10 1) routing sp4_v_t_40 sp4_v_b_1 -(10 1) routing sp4_v_t_47 sp4_v_b_1 -(10 10) routing sp4_h_r_11 sp4_h_l_42 -(10 10) routing sp4_h_r_4 sp4_h_l_42 -(10 10) routing sp4_v_b_2 sp4_h_l_42 -(10 10) routing sp4_v_t_36 sp4_h_l_42 -(10 11) routing sp4_h_l_39 sp4_v_t_42 -(10 11) routing sp4_h_r_1 sp4_v_t_42 -(10 11) routing sp4_v_b_11 sp4_v_t_42 -(10 11) routing sp4_v_b_4 sp4_v_t_42 -(10 12) routing sp4_h_l_39 sp4_h_r_10 -(10 12) routing sp4_h_l_42 sp4_h_r_10 -(10 12) routing sp4_v_b_4 sp4_h_r_10 -(10 12) routing sp4_v_t_40 sp4_h_r_10 -(10 13) routing sp4_h_l_41 sp4_v_b_10 -(10 13) routing sp4_h_r_5 sp4_v_b_10 -(10 13) routing sp4_v_t_39 sp4_v_b_10 -(10 13) routing sp4_v_t_42 sp4_v_b_10 -(10 14) routing sp4_h_r_2 sp4_h_l_47 -(10 14) routing sp4_h_r_7 sp4_h_l_47 -(10 14) routing sp4_v_b_5 sp4_h_l_47 -(10 14) routing sp4_v_t_41 sp4_h_l_47 -(10 15) routing sp4_h_l_40 sp4_v_t_47 -(10 15) routing sp4_h_r_4 sp4_v_t_47 -(10 15) routing sp4_v_b_2 sp4_v_t_47 -(10 15) routing sp4_v_b_7 sp4_v_t_47 -(10 2) routing sp4_h_r_10 sp4_h_l_36 -(10 2) routing sp4_h_r_5 sp4_h_l_36 -(10 2) routing sp4_v_b_8 sp4_h_l_36 -(10 2) routing sp4_v_t_42 sp4_h_l_36 -(10 3) routing sp4_h_l_45 sp4_v_t_36 -(10 3) routing sp4_h_r_7 sp4_v_t_36 -(10 3) routing sp4_v_b_10 sp4_v_t_36 -(10 3) routing sp4_v_b_5 sp4_v_t_36 -(10 4) routing sp4_h_l_36 sp4_h_r_4 -(10 4) routing sp4_h_l_45 sp4_h_r_4 -(10 4) routing sp4_v_b_10 sp4_h_r_4 -(10 4) routing sp4_v_t_46 sp4_h_r_4 -(10 5) routing sp4_h_l_47 sp4_v_b_4 -(10 5) routing sp4_h_r_11 sp4_v_b_4 -(10 5) routing sp4_v_t_36 sp4_v_b_4 -(10 5) routing sp4_v_t_45 sp4_v_b_4 -(10 6) routing sp4_h_r_1 sp4_h_l_41 -(10 6) routing sp4_h_r_8 sp4_h_l_41 -(10 6) routing sp4_v_b_11 sp4_h_l_41 -(10 6) routing sp4_v_t_47 sp4_h_l_41 -(10 7) routing sp4_h_l_46 sp4_v_t_41 -(10 7) routing sp4_h_r_10 sp4_v_t_41 -(10 7) routing sp4_v_b_1 sp4_v_t_41 -(10 7) routing sp4_v_b_8 sp4_v_t_41 -(10 8) routing sp4_h_l_41 sp4_h_r_7 -(10 8) routing sp4_h_l_46 sp4_h_r_7 -(10 8) routing sp4_v_b_1 sp4_h_r_7 -(10 8) routing sp4_v_t_39 sp4_h_r_7 -(10 9) routing sp4_h_l_36 sp4_v_b_7 -(10 9) routing sp4_h_r_2 sp4_v_b_7 -(10 9) routing sp4_v_t_41 sp4_v_b_7 -(10 9) routing sp4_v_t_46 sp4_v_b_7 -(11 0) routing sp4_h_l_45 sp4_v_b_2 -(11 0) routing sp4_h_r_9 sp4_v_b_2 -(11 0) routing sp4_v_t_43 sp4_v_b_2 -(11 0) routing sp4_v_t_46 sp4_v_b_2 -(11 1) routing sp4_h_l_39 sp4_h_r_2 -(11 1) routing sp4_h_l_43 sp4_h_r_2 -(11 1) routing sp4_v_b_2 sp4_h_r_2 -(11 1) routing sp4_v_b_8 sp4_h_r_2 -(11 10) routing sp4_h_l_38 sp4_v_t_45 -(11 10) routing sp4_h_r_2 sp4_v_t_45 -(11 10) routing sp4_v_b_0 sp4_v_t_45 -(11 10) routing sp4_v_b_5 sp4_v_t_45 -(11 11) routing sp4_h_r_0 sp4_h_l_45 -(11 11) routing sp4_h_r_8 sp4_h_l_45 -(11 11) routing sp4_v_t_39 sp4_h_l_45 -(11 11) routing sp4_v_t_45 sp4_h_l_45 -(11 12) routing sp4_h_l_40 sp4_v_b_11 -(11 12) routing sp4_h_r_6 sp4_v_b_11 -(11 12) routing sp4_v_t_38 sp4_v_b_11 -(11 12) routing sp4_v_t_45 sp4_v_b_11 -(11 13) routing sp4_h_l_38 sp4_h_r_11 -(11 13) routing sp4_h_l_46 sp4_h_r_11 -(11 13) routing sp4_v_b_11 sp4_h_r_11 -(11 13) routing sp4_v_b_5 sp4_h_r_11 -(11 14) routing sp4_h_l_43 sp4_v_t_46 -(11 14) routing sp4_h_r_5 sp4_v_t_46 -(11 14) routing sp4_v_b_3 sp4_v_t_46 -(11 14) routing sp4_v_b_8 sp4_v_t_46 -(11 15) routing sp4_h_r_11 sp4_h_l_46 -(11 15) routing sp4_h_r_3 sp4_h_l_46 -(11 15) routing sp4_v_t_40 sp4_h_l_46 -(11 15) routing sp4_v_t_46 sp4_h_l_46 -(11 2) routing sp4_h_l_44 sp4_v_t_39 -(11 2) routing sp4_h_r_8 sp4_v_t_39 -(11 2) routing sp4_v_b_11 sp4_v_t_39 -(11 2) routing sp4_v_b_6 sp4_v_t_39 -(11 3) routing sp4_h_r_2 sp4_h_l_39 -(11 3) routing sp4_h_r_6 sp4_h_l_39 -(11 3) routing sp4_v_t_39 sp4_h_l_39 -(11 3) routing sp4_v_t_45 sp4_h_l_39 -(11 4) routing sp4_h_l_46 sp4_v_b_5 -(11 4) routing sp4_h_r_0 sp4_v_b_5 -(11 4) routing sp4_v_t_39 sp4_v_b_5 -(11 4) routing sp4_v_t_44 sp4_v_b_5 -(11 5) routing sp4_h_l_40 sp4_h_r_5 -(11 5) routing sp4_h_l_44 sp4_h_r_5 -(11 5) routing sp4_v_b_11 sp4_h_r_5 -(11 5) routing sp4_v_b_5 sp4_h_r_5 -(11 6) routing sp4_h_l_37 sp4_v_t_40 -(11 6) routing sp4_h_r_11 sp4_v_t_40 -(11 6) routing sp4_v_b_2 sp4_v_t_40 -(11 6) routing sp4_v_b_9 sp4_v_t_40 -(11 7) routing sp4_h_r_5 sp4_h_l_40 -(11 7) routing sp4_h_r_9 sp4_h_l_40 -(11 7) routing sp4_v_t_40 sp4_h_l_40 -(11 7) routing sp4_v_t_46 sp4_h_l_40 -(11 8) routing sp4_h_l_39 sp4_v_b_8 -(11 8) routing sp4_h_r_3 sp4_v_b_8 -(11 8) routing sp4_v_t_37 sp4_v_b_8 -(11 8) routing sp4_v_t_40 sp4_v_b_8 -(11 9) routing sp4_h_l_37 sp4_h_r_8 -(11 9) routing sp4_h_l_45 sp4_h_r_8 -(11 9) routing sp4_v_b_2 sp4_h_r_8 -(11 9) routing sp4_v_b_8 sp4_h_r_8 -(12 0) routing sp4_h_l_46 sp4_h_r_2 -(12 0) routing sp4_v_b_2 sp4_h_r_2 -(12 0) routing sp4_v_b_8 sp4_h_r_2 -(12 0) routing sp4_v_t_39 sp4_h_r_2 -(12 1) routing sp4_h_l_39 sp4_v_b_2 -(12 1) routing sp4_h_l_45 sp4_v_b_2 -(12 1) routing sp4_h_r_2 sp4_v_b_2 -(12 1) routing sp4_v_t_46 sp4_v_b_2 -(12 10) routing sp4_h_r_5 sp4_h_l_45 -(12 10) routing sp4_v_b_8 sp4_h_l_45 -(12 10) routing sp4_v_t_39 sp4_h_l_45 -(12 10) routing sp4_v_t_45 sp4_h_l_45 -(12 11) routing sp4_h_l_45 sp4_v_t_45 -(12 11) routing sp4_h_r_2 sp4_v_t_45 -(12 11) routing sp4_h_r_8 sp4_v_t_45 -(12 11) routing sp4_v_b_5 sp4_v_t_45 -(12 12) routing sp4_h_l_45 sp4_h_r_11 -(12 12) routing sp4_v_b_11 sp4_h_r_11 -(12 12) routing sp4_v_b_5 sp4_h_r_11 -(12 12) routing sp4_v_t_46 sp4_h_r_11 -(12 13) routing sp4_h_l_40 sp4_v_b_11 -(12 13) routing sp4_h_l_46 sp4_v_b_11 -(12 13) routing sp4_h_r_11 sp4_v_b_11 -(12 13) routing sp4_v_t_45 sp4_v_b_11 -(12 14) routing sp4_h_r_8 sp4_h_l_46 -(12 14) routing sp4_v_b_11 sp4_h_l_46 -(12 14) routing sp4_v_t_40 sp4_h_l_46 -(12 14) routing sp4_v_t_46 sp4_h_l_46 -(12 15) routing sp4_h_l_46 sp4_v_t_46 -(12 15) routing sp4_h_r_11 sp4_v_t_46 -(12 15) routing sp4_h_r_5 sp4_v_t_46 -(12 15) routing sp4_v_b_8 sp4_v_t_46 -(12 2) routing sp4_h_r_11 sp4_h_l_39 -(12 2) routing sp4_v_b_2 sp4_h_l_39 -(12 2) routing sp4_v_t_39 sp4_h_l_39 -(12 2) routing sp4_v_t_45 sp4_h_l_39 -(12 3) routing sp4_h_l_39 sp4_v_t_39 -(12 3) routing sp4_h_r_2 sp4_v_t_39 -(12 3) routing sp4_h_r_8 sp4_v_t_39 -(12 3) routing sp4_v_b_11 sp4_v_t_39 -(12 4) routing sp4_h_l_39 sp4_h_r_5 -(12 4) routing sp4_v_b_11 sp4_h_r_5 -(12 4) routing sp4_v_b_5 sp4_h_r_5 -(12 4) routing sp4_v_t_40 sp4_h_r_5 -(12 5) routing sp4_h_l_40 sp4_v_b_5 -(12 5) routing sp4_h_l_46 sp4_v_b_5 -(12 5) routing sp4_h_r_5 sp4_v_b_5 -(12 5) routing sp4_v_t_39 sp4_v_b_5 -(12 6) routing sp4_h_r_2 sp4_h_l_40 -(12 6) routing sp4_v_b_5 sp4_h_l_40 -(12 6) routing sp4_v_t_40 sp4_h_l_40 -(12 6) routing sp4_v_t_46 sp4_h_l_40 -(12 7) routing sp4_h_l_40 sp4_v_t_40 -(12 7) routing sp4_h_r_11 sp4_v_t_40 -(12 7) routing sp4_h_r_5 sp4_v_t_40 -(12 7) routing sp4_v_b_2 sp4_v_t_40 -(12 8) routing sp4_h_l_40 sp4_h_r_8 -(12 8) routing sp4_v_b_2 sp4_h_r_8 -(12 8) routing sp4_v_b_8 sp4_h_r_8 -(12 8) routing sp4_v_t_45 sp4_h_r_8 -(12 9) routing sp4_h_l_39 sp4_v_b_8 -(12 9) routing sp4_h_l_45 sp4_v_b_8 -(12 9) routing sp4_h_r_8 sp4_v_b_8 -(12 9) routing sp4_v_t_40 sp4_v_b_8 -(13 0) routing sp4_h_l_39 sp4_v_b_2 -(13 0) routing sp4_h_l_45 sp4_v_b_2 -(13 0) routing sp4_v_t_39 sp4_v_b_2 -(13 0) routing sp4_v_t_43 sp4_v_b_2 -(13 1) routing sp4_h_l_43 sp4_h_r_2 -(13 1) routing sp4_h_l_46 sp4_h_r_2 -(13 1) routing sp4_v_b_8 sp4_h_r_2 -(13 1) routing sp4_v_t_44 sp4_h_r_2 -(13 10) routing sp4_h_r_2 sp4_v_t_45 -(13 10) routing sp4_h_r_8 sp4_v_t_45 -(13 10) routing sp4_v_b_0 sp4_v_t_45 -(13 10) routing sp4_v_b_8 sp4_v_t_45 -(13 11) routing sp4_h_r_0 sp4_h_l_45 -(13 11) routing sp4_h_r_5 sp4_h_l_45 -(13 11) routing sp4_v_b_3 sp4_h_l_45 -(13 11) routing sp4_v_t_39 sp4_h_l_45 -(13 12) routing sp4_h_l_40 sp4_v_b_11 -(13 12) routing sp4_h_l_46 sp4_v_b_11 -(13 12) routing sp4_v_t_38 sp4_v_b_11 -(13 12) routing sp4_v_t_46 sp4_v_b_11 -(13 13) routing sp4_h_l_38 sp4_h_r_11 -(13 13) routing sp4_h_l_45 sp4_h_r_11 -(13 13) routing sp4_v_b_5 sp4_h_r_11 -(13 13) routing sp4_v_t_43 sp4_h_r_11 -(13 14) routing sp4_h_r_11 sp4_v_t_46 -(13 14) routing sp4_h_r_5 sp4_v_t_46 -(13 14) routing sp4_v_b_11 sp4_v_t_46 -(13 14) routing sp4_v_b_3 sp4_v_t_46 -(13 15) routing sp4_h_r_3 sp4_h_l_46 -(13 15) routing sp4_h_r_8 sp4_h_l_46 -(13 15) routing sp4_v_b_6 sp4_h_l_46 -(13 15) routing sp4_v_t_40 sp4_h_l_46 -(13 2) routing sp4_h_r_2 sp4_v_t_39 -(13 2) routing sp4_h_r_8 sp4_v_t_39 -(13 2) routing sp4_v_b_2 sp4_v_t_39 -(13 2) routing sp4_v_b_6 sp4_v_t_39 -(13 3) routing sp4_h_r_11 sp4_h_l_39 -(13 3) routing sp4_h_r_6 sp4_h_l_39 -(13 3) routing sp4_v_b_9 sp4_h_l_39 -(13 3) routing sp4_v_t_45 sp4_h_l_39 -(13 4) routing sp4_h_l_40 sp4_v_b_5 -(13 4) routing sp4_h_l_46 sp4_v_b_5 -(13 4) routing sp4_v_t_40 sp4_v_b_5 -(13 4) routing sp4_v_t_44 sp4_v_b_5 -(13 5) routing sp4_h_l_39 sp4_h_r_5 -(13 5) routing sp4_h_l_44 sp4_h_r_5 -(13 5) routing sp4_v_b_11 sp4_h_r_5 -(13 5) routing sp4_v_t_37 sp4_h_r_5 -(13 6) routing sp4_h_r_11 sp4_v_t_40 -(13 6) routing sp4_h_r_5 sp4_v_t_40 -(13 6) routing sp4_v_b_5 sp4_v_t_40 -(13 6) routing sp4_v_b_9 sp4_v_t_40 -(13 7) routing sp4_h_r_2 sp4_h_l_40 -(13 7) routing sp4_h_r_9 sp4_h_l_40 -(13 7) routing sp4_v_b_0 sp4_h_l_40 -(13 7) routing sp4_v_t_46 sp4_h_l_40 -(13 8) routing sp4_h_l_39 sp4_v_b_8 -(13 8) routing sp4_h_l_45 sp4_v_b_8 -(13 8) routing sp4_v_t_37 sp4_v_b_8 -(13 8) routing sp4_v_t_45 sp4_v_b_8 -(13 9) routing sp4_h_l_37 sp4_h_r_8 -(13 9) routing sp4_h_l_40 sp4_h_r_8 -(13 9) routing sp4_v_b_2 sp4_h_r_8 -(13 9) routing sp4_v_t_38 sp4_h_r_8 -(14 0) routing bnr_op_0 lc_trk_g0_0 -(14 0) routing lft_op_0 lc_trk_g0_0 -(14 0) routing sp12_h_r_0 lc_trk_g0_0 -(14 0) routing sp4_h_r_16 lc_trk_g0_0 -(14 0) routing sp4_h_r_8 lc_trk_g0_0 -(14 0) routing sp4_v_b_0 lc_trk_g0_0 -(14 0) routing sp4_v_b_8 lc_trk_g0_0 -(14 1) routing bnr_op_0 lc_trk_g0_0 -(14 1) routing sp12_h_l_15 lc_trk_g0_0 -(14 1) routing sp12_h_r_0 lc_trk_g0_0 -(14 1) routing sp4_h_r_0 lc_trk_g0_0 -(14 1) routing sp4_h_r_16 lc_trk_g0_0 -(14 1) routing sp4_r_v_b_35 lc_trk_g0_0 -(14 1) routing sp4_v_b_8 lc_trk_g0_0 -(14 10) routing bnl_op_4 lc_trk_g2_4 -(14 10) routing rgt_op_4 lc_trk_g2_4 -(14 10) routing sp12_v_b_4 lc_trk_g2_4 -(14 10) routing sp4_h_r_36 lc_trk_g2_4 -(14 10) routing sp4_h_r_44 lc_trk_g2_4 -(14 10) routing sp4_v_b_28 lc_trk_g2_4 -(14 10) routing sp4_v_t_25 lc_trk_g2_4 -(14 11) routing bnl_op_4 lc_trk_g2_4 -(14 11) routing sp12_v_b_20 lc_trk_g2_4 -(14 11) routing sp12_v_b_4 lc_trk_g2_4 -(14 11) routing sp4_h_r_28 lc_trk_g2_4 -(14 11) routing sp4_h_r_44 lc_trk_g2_4 -(14 11) routing sp4_r_v_b_36 lc_trk_g2_4 -(14 11) routing sp4_v_t_25 lc_trk_g2_4 -(14 11) routing tnl_op_4 lc_trk_g2_4 -(14 12) routing bnl_op_0 lc_trk_g3_0 -(14 12) routing rgt_op_0 lc_trk_g3_0 -(14 12) routing sp12_v_b_0 lc_trk_g3_0 -(14 12) routing sp4_h_r_32 lc_trk_g3_0 -(14 12) routing sp4_h_r_40 lc_trk_g3_0 -(14 12) routing sp4_v_b_32 lc_trk_g3_0 -(14 12) routing sp4_v_t_13 lc_trk_g3_0 -(14 13) routing bnl_op_0 lc_trk_g3_0 -(14 13) routing sp12_v_b_0 lc_trk_g3_0 -(14 13) routing sp12_v_b_16 lc_trk_g3_0 -(14 13) routing sp4_h_r_24 lc_trk_g3_0 -(14 13) routing sp4_h_r_40 lc_trk_g3_0 -(14 13) routing sp4_r_v_b_40 lc_trk_g3_0 -(14 13) routing sp4_v_b_32 lc_trk_g3_0 -(14 13) routing tnl_op_0 lc_trk_g3_0 -(14 14) routing bnl_op_4 lc_trk_g3_4 -(14 14) routing rgt_op_4 lc_trk_g3_4 -(14 14) routing sp12_v_b_4 lc_trk_g3_4 -(14 14) routing sp4_h_r_36 lc_trk_g3_4 -(14 14) routing sp4_h_r_44 lc_trk_g3_4 -(14 14) routing sp4_v_b_28 lc_trk_g3_4 -(14 14) routing sp4_v_t_25 lc_trk_g3_4 -(14 15) routing bnl_op_4 lc_trk_g3_4 -(14 15) routing sp12_v_b_20 lc_trk_g3_4 -(14 15) routing sp12_v_b_4 lc_trk_g3_4 -(14 15) routing sp4_h_r_28 lc_trk_g3_4 -(14 15) routing sp4_h_r_44 lc_trk_g3_4 -(14 15) routing sp4_r_v_b_44 lc_trk_g3_4 -(14 15) routing sp4_v_t_25 lc_trk_g3_4 -(14 15) routing tnl_op_4 lc_trk_g3_4 -(14 2) routing bnr_op_4 lc_trk_g0_4 -(14 2) routing lft_op_4 lc_trk_g0_4 -(14 2) routing sp12_h_l_3 lc_trk_g0_4 -(14 2) routing sp4_h_l_1 lc_trk_g0_4 -(14 2) routing sp4_h_l_9 lc_trk_g0_4 -(14 2) routing sp4_v_b_12 lc_trk_g0_4 -(14 2) routing sp4_v_b_4 lc_trk_g0_4 -(14 3) routing bnr_op_4 lc_trk_g0_4 -(14 3) routing sp12_h_l_3 lc_trk_g0_4 -(14 3) routing sp12_h_r_20 lc_trk_g0_4 -(14 3) routing sp4_h_l_9 lc_trk_g0_4 -(14 3) routing sp4_h_r_4 lc_trk_g0_4 -(14 3) routing sp4_r_v_b_28 lc_trk_g0_4 -(14 3) routing sp4_v_b_12 lc_trk_g0_4 -(14 4) routing bnr_op_0 lc_trk_g1_0 -(14 4) routing lft_op_0 lc_trk_g1_0 -(14 4) routing sp12_h_r_0 lc_trk_g1_0 -(14 4) routing sp4_h_r_16 lc_trk_g1_0 -(14 4) routing sp4_h_r_8 lc_trk_g1_0 -(14 4) routing sp4_v_b_0 lc_trk_g1_0 -(14 4) routing sp4_v_b_8 lc_trk_g1_0 -(14 5) routing bnr_op_0 lc_trk_g1_0 -(14 5) routing sp12_h_l_15 lc_trk_g1_0 -(14 5) routing sp12_h_r_0 lc_trk_g1_0 -(14 5) routing sp4_h_r_0 lc_trk_g1_0 -(14 5) routing sp4_h_r_16 lc_trk_g1_0 -(14 5) routing sp4_r_v_b_24 lc_trk_g1_0 -(14 5) routing sp4_v_b_8 lc_trk_g1_0 -(14 6) routing bnr_op_4 lc_trk_g1_4 -(14 6) routing lft_op_4 lc_trk_g1_4 -(14 6) routing sp12_h_l_3 lc_trk_g1_4 -(14 6) routing sp4_h_l_1 lc_trk_g1_4 -(14 6) routing sp4_h_l_9 lc_trk_g1_4 -(14 6) routing sp4_v_b_12 lc_trk_g1_4 -(14 6) routing sp4_v_b_4 lc_trk_g1_4 -(14 7) routing bnr_op_4 lc_trk_g1_4 -(14 7) routing sp12_h_l_3 lc_trk_g1_4 -(14 7) routing sp12_h_r_20 lc_trk_g1_4 -(14 7) routing sp4_h_l_9 lc_trk_g1_4 -(14 7) routing sp4_h_r_4 lc_trk_g1_4 -(14 7) routing sp4_r_v_b_28 lc_trk_g1_4 -(14 7) routing sp4_v_b_12 lc_trk_g1_4 -(14 8) routing bnl_op_0 lc_trk_g2_0 -(14 8) routing rgt_op_0 lc_trk_g2_0 -(14 8) routing sp12_v_b_0 lc_trk_g2_0 -(14 8) routing sp4_h_r_32 lc_trk_g2_0 -(14 8) routing sp4_h_r_40 lc_trk_g2_0 -(14 8) routing sp4_v_b_32 lc_trk_g2_0 -(14 8) routing sp4_v_t_13 lc_trk_g2_0 -(14 9) routing bnl_op_0 lc_trk_g2_0 -(14 9) routing sp12_v_b_0 lc_trk_g2_0 -(14 9) routing sp12_v_b_16 lc_trk_g2_0 -(14 9) routing sp4_h_r_24 lc_trk_g2_0 -(14 9) routing sp4_h_r_40 lc_trk_g2_0 -(14 9) routing sp4_r_v_b_32 lc_trk_g2_0 -(14 9) routing sp4_v_b_32 lc_trk_g2_0 -(14 9) routing tnl_op_0 lc_trk_g2_0 -(15 0) routing lft_op_1 lc_trk_g0_1 -(15 0) routing sp12_h_r_1 lc_trk_g0_1 -(15 0) routing sp4_h_r_1 lc_trk_g0_1 -(15 0) routing sp4_h_r_17 lc_trk_g0_1 -(15 0) routing sp4_h_r_9 lc_trk_g0_1 -(15 0) routing sp4_v_t_4 lc_trk_g0_1 -(15 1) routing bot_op_0 lc_trk_g0_0 -(15 1) routing lft_op_0 lc_trk_g0_0 -(15 1) routing sp12_h_r_0 lc_trk_g0_0 -(15 1) routing sp4_h_r_0 lc_trk_g0_0 -(15 1) routing sp4_h_r_16 lc_trk_g0_0 -(15 1) routing sp4_h_r_8 lc_trk_g0_0 -(15 1) routing sp4_v_b_16 lc_trk_g0_0 -(15 10) routing rgt_op_5 lc_trk_g2_5 -(15 10) routing sp12_v_b_5 lc_trk_g2_5 -(15 10) routing sp4_h_r_29 lc_trk_g2_5 -(15 10) routing sp4_h_r_37 lc_trk_g2_5 -(15 10) routing sp4_h_r_45 lc_trk_g2_5 -(15 10) routing sp4_v_b_45 lc_trk_g2_5 -(15 10) routing tnl_op_5 lc_trk_g2_5 -(15 10) routing tnr_op_5 lc_trk_g2_5 -(15 11) routing rgt_op_4 lc_trk_g2_4 -(15 11) routing sp12_v_b_4 lc_trk_g2_4 -(15 11) routing sp4_h_r_28 lc_trk_g2_4 -(15 11) routing sp4_h_r_36 lc_trk_g2_4 -(15 11) routing sp4_h_r_44 lc_trk_g2_4 -(15 11) routing sp4_v_b_44 lc_trk_g2_4 -(15 11) routing tnl_op_4 lc_trk_g2_4 -(15 11) routing tnr_op_4 lc_trk_g2_4 -(15 12) routing rgt_op_1 lc_trk_g3_1 -(15 12) routing sp12_v_b_1 lc_trk_g3_1 -(15 12) routing sp4_h_l_28 lc_trk_g3_1 -(15 12) routing sp4_h_r_25 lc_trk_g3_1 -(15 12) routing sp4_h_r_33 lc_trk_g3_1 -(15 12) routing sp4_v_b_41 lc_trk_g3_1 -(15 12) routing tnl_op_1 lc_trk_g3_1 -(15 12) routing tnr_op_1 lc_trk_g3_1 -(15 13) routing rgt_op_0 lc_trk_g3_0 -(15 13) routing sp12_v_b_0 lc_trk_g3_0 -(15 13) routing sp4_h_r_24 lc_trk_g3_0 -(15 13) routing sp4_h_r_32 lc_trk_g3_0 -(15 13) routing sp4_h_r_40 lc_trk_g3_0 -(15 13) routing sp4_v_b_40 lc_trk_g3_0 -(15 13) routing tnl_op_0 lc_trk_g3_0 -(15 13) routing tnr_op_0 lc_trk_g3_0 -(15 14) routing rgt_op_5 lc_trk_g3_5 -(15 14) routing sp12_v_b_5 lc_trk_g3_5 -(15 14) routing sp4_h_r_29 lc_trk_g3_5 -(15 14) routing sp4_h_r_37 lc_trk_g3_5 -(15 14) routing sp4_h_r_45 lc_trk_g3_5 -(15 14) routing sp4_v_b_45 lc_trk_g3_5 -(15 14) routing tnl_op_5 lc_trk_g3_5 -(15 14) routing tnr_op_5 lc_trk_g3_5 -(15 15) routing rgt_op_4 lc_trk_g3_4 -(15 15) routing sp12_v_b_4 lc_trk_g3_4 -(15 15) routing sp4_h_r_28 lc_trk_g3_4 -(15 15) routing sp4_h_r_36 lc_trk_g3_4 -(15 15) routing sp4_h_r_44 lc_trk_g3_4 -(15 15) routing sp4_v_b_44 lc_trk_g3_4 -(15 15) routing tnl_op_4 lc_trk_g3_4 -(15 15) routing tnr_op_4 lc_trk_g3_4 -(15 2) routing lft_op_5 lc_trk_g0_5 -(15 2) routing sp12_h_l_2 lc_trk_g0_5 -(15 2) routing sp4_h_r_13 lc_trk_g0_5 -(15 2) routing sp4_h_r_21 lc_trk_g0_5 -(15 2) routing sp4_h_r_5 lc_trk_g0_5 -(15 2) routing sp4_v_t_8 lc_trk_g0_5 -(15 3) routing bot_op_4 lc_trk_g0_4 -(15 3) routing lft_op_4 lc_trk_g0_4 -(15 3) routing sp12_h_l_3 lc_trk_g0_4 -(15 3) routing sp4_h_l_1 lc_trk_g0_4 -(15 3) routing sp4_h_l_9 lc_trk_g0_4 -(15 3) routing sp4_h_r_4 lc_trk_g0_4 -(15 3) routing sp4_v_b_20 lc_trk_g0_4 -(15 4) routing lft_op_1 lc_trk_g1_1 -(15 4) routing sp12_h_r_1 lc_trk_g1_1 -(15 4) routing sp4_h_r_1 lc_trk_g1_1 -(15 4) routing sp4_h_r_17 lc_trk_g1_1 -(15 4) routing sp4_h_r_9 lc_trk_g1_1 -(15 4) routing sp4_v_t_4 lc_trk_g1_1 -(15 5) routing bot_op_0 lc_trk_g1_0 -(15 5) routing lft_op_0 lc_trk_g1_0 -(15 5) routing sp12_h_r_0 lc_trk_g1_0 -(15 5) routing sp4_h_r_0 lc_trk_g1_0 -(15 5) routing sp4_h_r_16 lc_trk_g1_0 -(15 5) routing sp4_h_r_8 lc_trk_g1_0 -(15 5) routing sp4_v_b_16 lc_trk_g1_0 -(15 6) routing lft_op_5 lc_trk_g1_5 -(15 6) routing sp12_h_l_2 lc_trk_g1_5 -(15 6) routing sp4_h_r_13 lc_trk_g1_5 -(15 6) routing sp4_h_r_21 lc_trk_g1_5 -(15 6) routing sp4_h_r_5 lc_trk_g1_5 -(15 6) routing sp4_v_t_8 lc_trk_g1_5 -(15 7) routing bot_op_4 lc_trk_g1_4 -(15 7) routing lft_op_4 lc_trk_g1_4 -(15 7) routing sp12_h_l_3 lc_trk_g1_4 -(15 7) routing sp4_h_l_1 lc_trk_g1_4 -(15 7) routing sp4_h_l_9 lc_trk_g1_4 -(15 7) routing sp4_h_r_4 lc_trk_g1_4 -(15 7) routing sp4_v_b_20 lc_trk_g1_4 -(15 8) routing rgt_op_1 lc_trk_g2_1 -(15 8) routing sp12_v_b_1 lc_trk_g2_1 -(15 8) routing sp4_h_l_28 lc_trk_g2_1 -(15 8) routing sp4_h_r_25 lc_trk_g2_1 -(15 8) routing sp4_h_r_33 lc_trk_g2_1 -(15 8) routing sp4_v_b_41 lc_trk_g2_1 -(15 8) routing tnl_op_1 lc_trk_g2_1 -(15 8) routing tnr_op_1 lc_trk_g2_1 -(15 9) routing rgt_op_0 lc_trk_g2_0 -(15 9) routing sp12_v_b_0 lc_trk_g2_0 -(15 9) routing sp4_h_r_24 lc_trk_g2_0 -(15 9) routing sp4_h_r_32 lc_trk_g2_0 -(15 9) routing sp4_h_r_40 lc_trk_g2_0 -(15 9) routing sp4_v_b_40 lc_trk_g2_0 -(15 9) routing tnl_op_0 lc_trk_g2_0 -(15 9) routing tnr_op_0 lc_trk_g2_0 -(16 0) routing sp12_h_l_14 lc_trk_g0_1 -(16 0) routing sp12_h_r_9 lc_trk_g0_1 -(16 0) routing sp4_h_r_1 lc_trk_g0_1 -(16 0) routing sp4_h_r_17 lc_trk_g0_1 -(16 0) routing sp4_h_r_9 lc_trk_g0_1 -(16 0) routing sp4_v_b_1 lc_trk_g0_1 -(16 0) routing sp4_v_b_9 lc_trk_g0_1 -(16 0) routing sp4_v_t_4 lc_trk_g0_1 -(16 1) routing sp12_h_l_15 lc_trk_g0_0 -(16 1) routing sp12_h_r_8 lc_trk_g0_0 -(16 1) routing sp4_h_r_0 lc_trk_g0_0 -(16 1) routing sp4_h_r_16 lc_trk_g0_0 -(16 1) routing sp4_h_r_8 lc_trk_g0_0 -(16 1) routing sp4_v_b_0 lc_trk_g0_0 -(16 1) routing sp4_v_b_16 lc_trk_g0_0 -(16 1) routing sp4_v_b_8 lc_trk_g0_0 -(16 10) routing sp12_v_b_13 lc_trk_g2_5 -(16 10) routing sp12_v_t_18 lc_trk_g2_5 -(16 10) routing sp4_h_r_29 lc_trk_g2_5 -(16 10) routing sp4_h_r_37 lc_trk_g2_5 -(16 10) routing sp4_h_r_45 lc_trk_g2_5 -(16 10) routing sp4_v_b_29 lc_trk_g2_5 -(16 10) routing sp4_v_b_45 lc_trk_g2_5 -(16 10) routing sp4_v_t_24 lc_trk_g2_5 -(16 11) routing sp12_v_b_20 lc_trk_g2_4 -(16 11) routing sp12_v_t_11 lc_trk_g2_4 -(16 11) routing sp4_h_r_28 lc_trk_g2_4 -(16 11) routing sp4_h_r_36 lc_trk_g2_4 -(16 11) routing sp4_h_r_44 lc_trk_g2_4 -(16 11) routing sp4_v_b_28 lc_trk_g2_4 -(16 11) routing sp4_v_b_44 lc_trk_g2_4 -(16 11) routing sp4_v_t_25 lc_trk_g2_4 -(16 12) routing sp12_v_b_9 lc_trk_g3_1 -(16 12) routing sp12_v_t_14 lc_trk_g3_1 -(16 12) routing sp4_h_l_28 lc_trk_g3_1 -(16 12) routing sp4_h_r_25 lc_trk_g3_1 -(16 12) routing sp4_h_r_33 lc_trk_g3_1 -(16 12) routing sp4_v_b_25 lc_trk_g3_1 -(16 12) routing sp4_v_b_41 lc_trk_g3_1 -(16 12) routing sp4_v_t_20 lc_trk_g3_1 -(16 13) routing sp12_v_b_16 lc_trk_g3_0 -(16 13) routing sp12_v_t_7 lc_trk_g3_0 -(16 13) routing sp4_h_r_24 lc_trk_g3_0 -(16 13) routing sp4_h_r_32 lc_trk_g3_0 -(16 13) routing sp4_h_r_40 lc_trk_g3_0 -(16 13) routing sp4_v_b_32 lc_trk_g3_0 -(16 13) routing sp4_v_b_40 lc_trk_g3_0 -(16 13) routing sp4_v_t_13 lc_trk_g3_0 -(16 14) routing sp12_v_b_13 lc_trk_g3_5 -(16 14) routing sp12_v_t_18 lc_trk_g3_5 -(16 14) routing sp4_h_r_29 lc_trk_g3_5 -(16 14) routing sp4_h_r_37 lc_trk_g3_5 -(16 14) routing sp4_h_r_45 lc_trk_g3_5 -(16 14) routing sp4_v_b_29 lc_trk_g3_5 -(16 14) routing sp4_v_b_45 lc_trk_g3_5 -(16 14) routing sp4_v_t_24 lc_trk_g3_5 -(16 15) routing sp12_v_b_20 lc_trk_g3_4 -(16 15) routing sp12_v_t_11 lc_trk_g3_4 -(16 15) routing sp4_h_r_28 lc_trk_g3_4 -(16 15) routing sp4_h_r_36 lc_trk_g3_4 -(16 15) routing sp4_h_r_44 lc_trk_g3_4 -(16 15) routing sp4_v_b_28 lc_trk_g3_4 -(16 15) routing sp4_v_b_44 lc_trk_g3_4 -(16 15) routing sp4_v_t_25 lc_trk_g3_4 -(16 2) routing sp12_h_l_10 lc_trk_g0_5 -(16 2) routing sp12_h_r_21 lc_trk_g0_5 -(16 2) routing sp4_h_r_13 lc_trk_g0_5 -(16 2) routing sp4_h_r_21 lc_trk_g0_5 -(16 2) routing sp4_h_r_5 lc_trk_g0_5 -(16 2) routing sp4_v_b_13 lc_trk_g0_5 -(16 2) routing sp4_v_b_5 lc_trk_g0_5 -(16 2) routing sp4_v_t_8 lc_trk_g0_5 -(16 3) routing sp12_h_r_12 lc_trk_g0_4 -(16 3) routing sp12_h_r_20 lc_trk_g0_4 -(16 3) routing sp4_h_l_1 lc_trk_g0_4 -(16 3) routing sp4_h_l_9 lc_trk_g0_4 -(16 3) routing sp4_h_r_4 lc_trk_g0_4 -(16 3) routing sp4_v_b_12 lc_trk_g0_4 -(16 3) routing sp4_v_b_20 lc_trk_g0_4 -(16 3) routing sp4_v_b_4 lc_trk_g0_4 -(16 4) routing sp12_h_l_14 lc_trk_g1_1 -(16 4) routing sp12_h_r_9 lc_trk_g1_1 -(16 4) routing sp4_h_r_1 lc_trk_g1_1 -(16 4) routing sp4_h_r_17 lc_trk_g1_1 -(16 4) routing sp4_h_r_9 lc_trk_g1_1 -(16 4) routing sp4_v_b_1 lc_trk_g1_1 -(16 4) routing sp4_v_b_9 lc_trk_g1_1 -(16 4) routing sp4_v_t_4 lc_trk_g1_1 -(16 5) routing sp12_h_l_15 lc_trk_g1_0 -(16 5) routing sp12_h_r_8 lc_trk_g1_0 -(16 5) routing sp4_h_r_0 lc_trk_g1_0 -(16 5) routing sp4_h_r_16 lc_trk_g1_0 -(16 5) routing sp4_h_r_8 lc_trk_g1_0 -(16 5) routing sp4_v_b_0 lc_trk_g1_0 -(16 5) routing sp4_v_b_16 lc_trk_g1_0 -(16 5) routing sp4_v_b_8 lc_trk_g1_0 -(16 6) routing sp12_h_l_10 lc_trk_g1_5 -(16 6) routing sp12_h_r_21 lc_trk_g1_5 -(16 6) routing sp4_h_r_13 lc_trk_g1_5 -(16 6) routing sp4_h_r_21 lc_trk_g1_5 -(16 6) routing sp4_h_r_5 lc_trk_g1_5 -(16 6) routing sp4_v_b_13 lc_trk_g1_5 -(16 6) routing sp4_v_b_5 lc_trk_g1_5 -(16 6) routing sp4_v_t_8 lc_trk_g1_5 -(16 7) routing sp12_h_r_12 lc_trk_g1_4 -(16 7) routing sp12_h_r_20 lc_trk_g1_4 -(16 7) routing sp4_h_l_1 lc_trk_g1_4 -(16 7) routing sp4_h_l_9 lc_trk_g1_4 -(16 7) routing sp4_h_r_4 lc_trk_g1_4 -(16 7) routing sp4_v_b_12 lc_trk_g1_4 -(16 7) routing sp4_v_b_20 lc_trk_g1_4 -(16 7) routing sp4_v_b_4 lc_trk_g1_4 -(16 8) routing sp12_v_b_9 lc_trk_g2_1 -(16 8) routing sp12_v_t_14 lc_trk_g2_1 -(16 8) routing sp4_h_l_28 lc_trk_g2_1 -(16 8) routing sp4_h_r_25 lc_trk_g2_1 -(16 8) routing sp4_h_r_33 lc_trk_g2_1 -(16 8) routing sp4_v_b_25 lc_trk_g2_1 -(16 8) routing sp4_v_b_41 lc_trk_g2_1 -(16 8) routing sp4_v_t_20 lc_trk_g2_1 -(16 9) routing sp12_v_b_16 lc_trk_g2_0 -(16 9) routing sp12_v_t_7 lc_trk_g2_0 -(16 9) routing sp4_h_r_24 lc_trk_g2_0 -(16 9) routing sp4_h_r_32 lc_trk_g2_0 -(16 9) routing sp4_h_r_40 lc_trk_g2_0 -(16 9) routing sp4_v_b_32 lc_trk_g2_0 -(16 9) routing sp4_v_b_40 lc_trk_g2_0 -(16 9) routing sp4_v_t_13 lc_trk_g2_0 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_l_14 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_9 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_34 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_t_4 lc_trk_g0_1 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => bot_op_0 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_l_15 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_8 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_16 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_8 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_24 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_35 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_0 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_16 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_8 lc_trk_g0_0 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => bnl_op_5 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => rgt_op_5 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_13 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_5 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_18 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_29 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_37 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_45 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_29 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_45 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_t_24 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_20 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_4 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_11 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_28 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_36 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_44 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_12 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_36 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_28 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_44 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_25 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnl_op_4 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnr_op_4 lc_trk_g2_4 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => rgt_op_1 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_9 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_t_14 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_28 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_25 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_33 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_17 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_41 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_25 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_41 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_t_20 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnl_op_1 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnr_op_1 lc_trk_g3_1 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_16 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_t_7 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_24 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_32 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_r_40 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_32 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_40 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_13 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnl_op_0 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnr_op_0 lc_trk_g3_0 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => bnl_op_5 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => rgt_op_5 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_13 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_5 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_18 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_29 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_37 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_45 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_29 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_45 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_t_24 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnl_op_5 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnr_op_5 lc_trk_g3_5 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => bnl_op_4 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => rgt_op_4 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_20 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_4 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_11 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_28 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_36 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_44 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_44 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_28 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_44 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_25 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnl_op_4 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnr_op_4 lc_trk_g3_4 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_10 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_2 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_21 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_13 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_21 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_5 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_r_v_b_29 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_13 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_8 lc_trk_g0_5 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => bnr_op_4 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => bot_op_4 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_3 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_12 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_20 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_l_1 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_l_9 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_4 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_r_v_b_28 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_12 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_20 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_4 lc_trk_g0_4 -(17 4) Enable bit of Mux _local_links/g1_mux_1 => bnr_op_1 lc_trk_g1_1 -(17 4) Enable bit of Mux _local_links/g1_mux_1 => lft_op_1 lc_trk_g1_1 -(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_l_14 lc_trk_g1_1 -(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_1 lc_trk_g1_1 -(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_9 lc_trk_g1_1 -(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1 -(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_17 lc_trk_g1_1 -(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_9 lc_trk_g1_1 -(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_1 lc_trk_g1_1 -(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_25 lc_trk_g1_1 -(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_1 lc_trk_g1_1 -(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_9 lc_trk_g1_1 -(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_t_4 lc_trk_g1_1 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => bot_op_0 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_l_15 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_8 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_16 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_8 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_0 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_24 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_0 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_16 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_10 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_2 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_21 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_13 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_21 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_29 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_5 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_13 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_5 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_8 lc_trk_g1_5 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => bot_op_4 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_3 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_12 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_20 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_1 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_l_9 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_28 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_4 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_12 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_20 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_t_14 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_28 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_25 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_33 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_33 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_9 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_25 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_41 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_t_20 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_16 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_t_7 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_24 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_32 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_r_40 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_32 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_8 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_32 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_40 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_13 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0 -(18 0) routing bnr_op_1 lc_trk_g0_1 -(18 0) routing lft_op_1 lc_trk_g0_1 -(18 0) routing sp12_h_r_1 lc_trk_g0_1 -(18 0) routing sp4_h_r_17 lc_trk_g0_1 -(18 0) routing sp4_h_r_9 lc_trk_g0_1 -(18 0) routing sp4_v_b_1 lc_trk_g0_1 -(18 0) routing sp4_v_b_9 lc_trk_g0_1 -(18 1) routing bnr_op_1 lc_trk_g0_1 -(18 1) routing sp12_h_l_14 lc_trk_g0_1 -(18 1) routing sp12_h_r_1 lc_trk_g0_1 -(18 1) routing sp4_h_r_1 lc_trk_g0_1 -(18 1) routing sp4_h_r_17 lc_trk_g0_1 -(18 1) routing sp4_r_v_b_34 lc_trk_g0_1 -(18 1) routing sp4_v_b_9 lc_trk_g0_1 -(18 10) routing bnl_op_5 lc_trk_g2_5 -(18 10) routing rgt_op_5 lc_trk_g2_5 -(18 10) routing sp12_v_b_5 lc_trk_g2_5 -(18 10) routing sp4_h_r_37 lc_trk_g2_5 -(18 10) routing sp4_h_r_45 lc_trk_g2_5 -(18 10) routing sp4_v_b_29 lc_trk_g2_5 -(18 10) routing sp4_v_t_24 lc_trk_g2_5 -(18 11) routing bnl_op_5 lc_trk_g2_5 -(18 11) routing sp12_v_b_5 lc_trk_g2_5 -(18 11) routing sp12_v_t_18 lc_trk_g2_5 -(18 11) routing sp4_h_r_29 lc_trk_g2_5 -(18 11) routing sp4_h_r_45 lc_trk_g2_5 -(18 11) routing sp4_r_v_b_37 lc_trk_g2_5 -(18 11) routing sp4_v_t_24 lc_trk_g2_5 -(18 11) routing tnl_op_5 lc_trk_g2_5 -(18 12) routing bnl_op_1 lc_trk_g3_1 -(18 12) routing rgt_op_1 lc_trk_g3_1 -(18 12) routing sp12_v_b_1 lc_trk_g3_1 -(18 12) routing sp4_h_l_28 lc_trk_g3_1 -(18 12) routing sp4_h_r_33 lc_trk_g3_1 -(18 12) routing sp4_v_b_25 lc_trk_g3_1 -(18 12) routing sp4_v_t_20 lc_trk_g3_1 -(18 13) routing bnl_op_1 lc_trk_g3_1 -(18 13) routing sp12_v_b_1 lc_trk_g3_1 -(18 13) routing sp12_v_t_14 lc_trk_g3_1 -(18 13) routing sp4_h_l_28 lc_trk_g3_1 -(18 13) routing sp4_h_r_25 lc_trk_g3_1 -(18 13) routing sp4_r_v_b_41 lc_trk_g3_1 -(18 13) routing sp4_v_t_20 lc_trk_g3_1 -(18 13) routing tnl_op_1 lc_trk_g3_1 -(18 14) routing bnl_op_5 lc_trk_g3_5 -(18 14) routing rgt_op_5 lc_trk_g3_5 -(18 14) routing sp12_v_b_5 lc_trk_g3_5 -(18 14) routing sp4_h_r_37 lc_trk_g3_5 -(18 14) routing sp4_h_r_45 lc_trk_g3_5 -(18 14) routing sp4_v_b_29 lc_trk_g3_5 -(18 14) routing sp4_v_t_24 lc_trk_g3_5 -(18 15) routing bnl_op_5 lc_trk_g3_5 -(18 15) routing sp12_v_b_5 lc_trk_g3_5 -(18 15) routing sp12_v_t_18 lc_trk_g3_5 -(18 15) routing sp4_h_r_29 lc_trk_g3_5 -(18 15) routing sp4_h_r_45 lc_trk_g3_5 -(18 15) routing sp4_r_v_b_45 lc_trk_g3_5 -(18 15) routing sp4_v_t_24 lc_trk_g3_5 -(18 15) routing tnl_op_5 lc_trk_g3_5 -(18 2) routing bnr_op_5 lc_trk_g0_5 -(18 2) routing lft_op_5 lc_trk_g0_5 -(18 2) routing sp12_h_l_2 lc_trk_g0_5 -(18 2) routing sp4_h_r_13 lc_trk_g0_5 -(18 2) routing sp4_h_r_21 lc_trk_g0_5 -(18 2) routing sp4_v_b_13 lc_trk_g0_5 -(18 2) routing sp4_v_b_5 lc_trk_g0_5 -(18 3) routing bnr_op_5 lc_trk_g0_5 -(18 3) routing sp12_h_l_2 lc_trk_g0_5 -(18 3) routing sp12_h_r_21 lc_trk_g0_5 -(18 3) routing sp4_h_r_21 lc_trk_g0_5 -(18 3) routing sp4_h_r_5 lc_trk_g0_5 -(18 3) routing sp4_r_v_b_29 lc_trk_g0_5 -(18 3) routing sp4_v_b_13 lc_trk_g0_5 -(18 4) routing bnr_op_1 lc_trk_g1_1 -(18 4) routing lft_op_1 lc_trk_g1_1 -(18 4) routing sp12_h_r_1 lc_trk_g1_1 -(18 4) routing sp4_h_r_17 lc_trk_g1_1 -(18 4) routing sp4_h_r_9 lc_trk_g1_1 -(18 4) routing sp4_v_b_1 lc_trk_g1_1 -(18 4) routing sp4_v_b_9 lc_trk_g1_1 -(18 5) routing bnr_op_1 lc_trk_g1_1 -(18 5) routing sp12_h_l_14 lc_trk_g1_1 -(18 5) routing sp12_h_r_1 lc_trk_g1_1 -(18 5) routing sp4_h_r_1 lc_trk_g1_1 -(18 5) routing sp4_h_r_17 lc_trk_g1_1 -(18 5) routing sp4_r_v_b_25 lc_trk_g1_1 -(18 5) routing sp4_v_b_9 lc_trk_g1_1 -(18 6) routing bnr_op_5 lc_trk_g1_5 -(18 6) routing lft_op_5 lc_trk_g1_5 -(18 6) routing sp12_h_l_2 lc_trk_g1_5 -(18 6) routing sp4_h_r_13 lc_trk_g1_5 -(18 6) routing sp4_h_r_21 lc_trk_g1_5 -(18 6) routing sp4_v_b_13 lc_trk_g1_5 -(18 6) routing sp4_v_b_5 lc_trk_g1_5 -(18 7) routing bnr_op_5 lc_trk_g1_5 -(18 7) routing sp12_h_l_2 lc_trk_g1_5 -(18 7) routing sp12_h_r_21 lc_trk_g1_5 -(18 7) routing sp4_h_r_21 lc_trk_g1_5 -(18 7) routing sp4_h_r_5 lc_trk_g1_5 -(18 7) routing sp4_r_v_b_29 lc_trk_g1_5 -(18 7) routing sp4_v_b_13 lc_trk_g1_5 -(18 8) routing bnl_op_1 lc_trk_g2_1 -(18 8) routing rgt_op_1 lc_trk_g2_1 -(18 8) routing sp12_v_b_1 lc_trk_g2_1 -(18 8) routing sp4_h_l_28 lc_trk_g2_1 -(18 8) routing sp4_h_r_33 lc_trk_g2_1 -(18 8) routing sp4_v_b_25 lc_trk_g2_1 -(18 8) routing sp4_v_t_20 lc_trk_g2_1 -(18 9) routing bnl_op_1 lc_trk_g2_1 -(18 9) routing sp12_v_b_1 lc_trk_g2_1 -(18 9) routing sp12_v_t_14 lc_trk_g2_1 -(18 9) routing sp4_h_l_28 lc_trk_g2_1 -(18 9) routing sp4_h_r_25 lc_trk_g2_1 -(18 9) routing sp4_r_v_b_33 lc_trk_g2_1 -(18 9) routing sp4_v_t_20 lc_trk_g2_1 -(18 9) routing tnl_op_1 lc_trk_g2_1 -(19 0) Enable bit of Mux _span_links/cross_mux_vert_1 => sp12_v_b_3 sp4_v_b_13 -(19 1) Enable bit of Mux _span_links/cross_mux_vert_0 => sp12_v_b_1 sp4_v_b_12 -(19 10) Enable bit of Mux _span_links/cross_mux_vert_11 => sp12_v_t_20 sp4_v_b_23 -(19 11) Enable bit of Mux _span_links/cross_mux_vert_10 => sp12_v_t_18 sp4_v_t_11 -(19 12) Enable bit of Mux _span_links/cross_mux_horz_1 => sp12_h_l_1 sp4_h_r_13 -(19 13) Enable bit of Mux _span_links/cross_mux_horz_0 => sp12_h_r_0 sp4_h_l_1 -(19 14) Enable bit of Mux _span_links/cross_mux_horz_3 => sp12_h_l_5 sp4_h_r_15 -(19 15) Enable bit of Mux _span_links/cross_mux_horz_2 => sp12_h_l_3 sp4_h_l_3 -(19 2) Enable bit of Mux _span_links/cross_mux_vert_3 => sp12_v_t_4 sp4_v_t_2 -(19 3) Enable bit of Mux _span_links/cross_mux_vert_2 => sp12_v_b_5 sp4_v_b_14 -(19 4) Enable bit of Mux _span_links/cross_mux_vert_5 => sp12_v_t_8 sp4_v_t_4 -(19 5) Enable bit of Mux _span_links/cross_mux_vert_4 => sp12_v_b_9 sp4_v_b_16 -(19 6) Enable bit of Mux _span_links/cross_mux_vert_7 => sp12_v_t_12 sp4_v_t_6 -(19 7) Enable bit of Mux _span_links/cross_mux_vert_6 => sp12_v_b_13 sp4_v_t_7 -(19 8) Enable bit of Mux _span_links/cross_mux_vert_9 => sp12_v_b_19 sp4_v_t_8 -(19 9) Enable bit of Mux _span_links/cross_mux_vert_8 => sp12_v_t_14 sp4_v_b_20 -(2 0) Enable bit of Mux _span_links/cross_mux_horz_4 => sp12_h_r_8 sp4_h_r_16 -(2 10) Enable bit of Mux _span_links/cross_mux_horz_9 => sp12_h_l_17 sp4_h_r_21 -(2 12) Enable bit of Mux _span_links/cross_mux_horz_10 => sp12_h_r_20 sp4_h_l_11 -(2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_r_22 sp4_h_r_23 -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_bram/ram/RCLK -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_2 wire_bram/ram/RCLK -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_3 wire_bram/ram/RCLK -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_bram/ram/RCLK -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_5 wire_bram/ram/RCLK -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_6 wire_bram/ram/RCLK -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_7 wire_bram/ram/RCLK -(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g0_0 wire_bram/ram/RCLK -(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g1_1 wire_bram/ram/RCLK -(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g2_0 wire_bram/ram/RCLK -(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g3_1 wire_bram/ram/RCLK -(2 3) routing lc_trk_g0_0 wire_bram/ram/RCLK -(2 3) routing lc_trk_g1_1 wire_bram/ram/RCLK -(2 3) routing lc_trk_g2_0 wire_bram/ram/RCLK -(2 3) routing lc_trk_g3_1 wire_bram/ram/RCLK -(2 4) Enable bit of Mux _span_links/cross_mux_horz_6 => sp12_h_r_12 sp4_h_r_18 -(2 6) Enable bit of Mux _span_links/cross_mux_horz_7 => sp12_h_r_14 sp4_h_l_6 -(2 8) Enable bit of Mux _span_links/cross_mux_horz_8 => sp12_h_l_15 sp4_h_l_9 -(21 0) routing bnr_op_3 lc_trk_g0_3 -(21 0) routing lft_op_3 lc_trk_g0_3 -(21 0) routing sp12_h_r_3 lc_trk_g0_3 -(21 0) routing sp4_h_l_6 lc_trk_g0_3 -(21 0) routing sp4_h_r_11 lc_trk_g0_3 -(21 0) routing sp4_v_b_11 lc_trk_g0_3 -(21 0) routing sp4_v_b_3 lc_trk_g0_3 -(21 1) routing bnr_op_3 lc_trk_g0_3 -(21 1) routing sp12_h_l_16 lc_trk_g0_3 -(21 1) routing sp12_h_r_3 lc_trk_g0_3 -(21 1) routing sp4_h_l_6 lc_trk_g0_3 -(21 1) routing sp4_h_r_3 lc_trk_g0_3 -(21 1) routing sp4_r_v_b_32 lc_trk_g0_3 -(21 1) routing sp4_v_b_11 lc_trk_g0_3 -(21 10) routing bnl_op_7 lc_trk_g2_7 -(21 10) routing rgt_op_7 lc_trk_g2_7 -(21 10) routing sp12_v_t_4 lc_trk_g2_7 -(21 10) routing sp4_h_l_26 lc_trk_g2_7 -(21 10) routing sp4_h_r_47 lc_trk_g2_7 -(21 10) routing sp4_v_b_31 lc_trk_g2_7 -(21 10) routing sp4_v_t_26 lc_trk_g2_7 -(21 11) routing bnl_op_7 lc_trk_g2_7 -(21 11) routing sp12_v_t_20 lc_trk_g2_7 -(21 11) routing sp12_v_t_4 lc_trk_g2_7 -(21 11) routing sp4_h_r_31 lc_trk_g2_7 -(21 11) routing sp4_h_r_47 lc_trk_g2_7 -(21 11) routing sp4_r_v_b_39 lc_trk_g2_7 -(21 11) routing sp4_v_t_26 lc_trk_g2_7 -(21 11) routing tnl_op_7 lc_trk_g2_7 -(21 12) routing bnl_op_3 lc_trk_g3_3 -(21 12) routing rgt_op_3 lc_trk_g3_3 -(21 12) routing sp12_v_b_3 lc_trk_g3_3 -(21 12) routing sp4_h_l_22 lc_trk_g3_3 -(21 12) routing sp4_h_r_43 lc_trk_g3_3 -(21 12) routing sp4_v_b_27 lc_trk_g3_3 -(21 12) routing sp4_v_b_35 lc_trk_g3_3 -(21 13) routing bnl_op_3 lc_trk_g3_3 -(21 13) routing sp12_v_b_19 lc_trk_g3_3 -(21 13) routing sp12_v_b_3 lc_trk_g3_3 -(21 13) routing sp4_h_l_14 lc_trk_g3_3 -(21 13) routing sp4_h_r_43 lc_trk_g3_3 -(21 13) routing sp4_r_v_b_43 lc_trk_g3_3 -(21 13) routing sp4_v_b_35 lc_trk_g3_3 -(21 13) routing tnl_op_3 lc_trk_g3_3 -(21 14) routing bnl_op_7 lc_trk_g3_7 -(21 14) routing rgt_op_7 lc_trk_g3_7 -(21 14) routing sp12_v_t_4 lc_trk_g3_7 -(21 14) routing sp4_h_l_26 lc_trk_g3_7 -(21 14) routing sp4_h_r_47 lc_trk_g3_7 -(21 14) routing sp4_v_b_31 lc_trk_g3_7 -(21 14) routing sp4_v_t_26 lc_trk_g3_7 -(21 15) routing bnl_op_7 lc_trk_g3_7 -(21 15) routing sp12_v_t_20 lc_trk_g3_7 -(21 15) routing sp12_v_t_4 lc_trk_g3_7 -(21 15) routing sp4_h_r_31 lc_trk_g3_7 -(21 15) routing sp4_h_r_47 lc_trk_g3_7 -(21 15) routing sp4_r_v_b_47 lc_trk_g3_7 -(21 15) routing sp4_v_t_26 lc_trk_g3_7 -(21 15) routing tnl_op_7 lc_trk_g3_7 -(21 2) routing bnr_op_7 lc_trk_g0_7 -(21 2) routing lft_op_7 lc_trk_g0_7 -(21 2) routing sp12_h_r_7 lc_trk_g0_7 -(21 2) routing sp4_h_r_15 lc_trk_g0_7 -(21 2) routing sp4_h_r_23 lc_trk_g0_7 -(21 2) routing sp4_v_b_7 lc_trk_g0_7 -(21 2) routing sp4_v_t_2 lc_trk_g0_7 -(21 3) routing bnr_op_7 lc_trk_g0_7 -(21 3) routing sp12_h_l_20 lc_trk_g0_7 -(21 3) routing sp12_h_r_7 lc_trk_g0_7 -(21 3) routing sp4_h_r_23 lc_trk_g0_7 -(21 3) routing sp4_h_r_7 lc_trk_g0_7 -(21 3) routing sp4_r_v_b_31 lc_trk_g0_7 -(21 3) routing sp4_v_t_2 lc_trk_g0_7 -(21 4) routing bnr_op_3 lc_trk_g1_3 -(21 4) routing lft_op_3 lc_trk_g1_3 -(21 4) routing sp12_h_r_3 lc_trk_g1_3 -(21 4) routing sp4_h_l_6 lc_trk_g1_3 -(21 4) routing sp4_h_r_11 lc_trk_g1_3 -(21 4) routing sp4_v_b_11 lc_trk_g1_3 -(21 4) routing sp4_v_b_3 lc_trk_g1_3 -(21 5) routing bnr_op_3 lc_trk_g1_3 -(21 5) routing sp12_h_l_16 lc_trk_g1_3 -(21 5) routing sp12_h_r_3 lc_trk_g1_3 -(21 5) routing sp4_h_l_6 lc_trk_g1_3 -(21 5) routing sp4_h_r_3 lc_trk_g1_3 -(21 5) routing sp4_r_v_b_27 lc_trk_g1_3 -(21 5) routing sp4_v_b_11 lc_trk_g1_3 -(21 6) routing bnr_op_7 lc_trk_g1_7 -(21 6) routing lft_op_7 lc_trk_g1_7 -(21 6) routing sp12_h_r_7 lc_trk_g1_7 -(21 6) routing sp4_h_r_15 lc_trk_g1_7 -(21 6) routing sp4_h_r_23 lc_trk_g1_7 -(21 6) routing sp4_v_b_7 lc_trk_g1_7 -(21 6) routing sp4_v_t_2 lc_trk_g1_7 -(21 7) routing bnr_op_7 lc_trk_g1_7 -(21 7) routing sp12_h_l_20 lc_trk_g1_7 -(21 7) routing sp12_h_r_7 lc_trk_g1_7 -(21 7) routing sp4_h_r_23 lc_trk_g1_7 -(21 7) routing sp4_h_r_7 lc_trk_g1_7 -(21 7) routing sp4_r_v_b_31 lc_trk_g1_7 -(21 7) routing sp4_v_t_2 lc_trk_g1_7 -(21 8) routing bnl_op_3 lc_trk_g2_3 -(21 8) routing rgt_op_3 lc_trk_g2_3 -(21 8) routing sp12_v_b_3 lc_trk_g2_3 -(21 8) routing sp4_h_l_22 lc_trk_g2_3 -(21 8) routing sp4_h_r_43 lc_trk_g2_3 -(21 8) routing sp4_v_b_27 lc_trk_g2_3 -(21 8) routing sp4_v_b_35 lc_trk_g2_3 -(21 9) routing bnl_op_3 lc_trk_g2_3 -(21 9) routing sp12_v_b_19 lc_trk_g2_3 -(21 9) routing sp12_v_b_3 lc_trk_g2_3 -(21 9) routing sp4_h_l_14 lc_trk_g2_3 -(21 9) routing sp4_h_r_43 lc_trk_g2_3 -(21 9) routing sp4_r_v_b_35 lc_trk_g2_3 -(21 9) routing sp4_v_b_35 lc_trk_g2_3 -(21 9) routing tnl_op_3 lc_trk_g2_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => bnr_op_3 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => lft_op_3 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_16 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_11 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_3 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_l_6 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_11 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_t_6 lc_trk_g0_3 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => bot_op_2 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_1 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_17 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_l_9 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_18 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_2 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_26 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_33 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_10 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_2 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_t_7 lc_trk_g0_2 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_20 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_4 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_26 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_31 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_47 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_39 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_31 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_26 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_34 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_14 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_22 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_5 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_19 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_27 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_46 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_14 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_38 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_46 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_t_19 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_t_27 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnl_op_6 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnr_op_6 lc_trk_g2_6 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => bnl_op_3 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => rgt_op_3 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_19 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_3 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_8 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_14 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_22 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_43 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_19 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_43 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_27 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_35 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_b_43 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnl_op_3 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnr_op_3 lc_trk_g3_3 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => bnl_op_2 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => rgt_op_2 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_10 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_18 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_1 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_l_15 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_34 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_42 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_18 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_42 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_b_34 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_15 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_31 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnl_op_2 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnr_op_2 lc_trk_g3_2 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => rgt_op_7 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_20 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_4 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_26 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_31 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_47 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_31 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_26 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_34 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_14 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_22 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_5 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_19 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_27 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_46 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_46 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_19 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_t_27 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnl_op_6 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnr_op_6 lc_trk_g3_6 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => bnr_op_7 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_12 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_20 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_7 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_15 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_23 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_r_v_b_31 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_23 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_2 lc_trk_g0_7 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => bot_op_6 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_14 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_r_22 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_11 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_6 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_r_v_b_30 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_14 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_t_11 lc_trk_g0_6 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_16 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_11 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_3 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_l_6 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_11 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_3 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_27 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_3 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_11 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_3 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_t_6 lc_trk_g1_3 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => bnr_op_2 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => bot_op_2 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => lft_op_2 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_1 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_17 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_l_9 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_10 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_18 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_2 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_t_7 lc_trk_g1_2 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_12 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_20 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_7 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_15 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_23 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_31 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_7 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_23 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_7 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_2 lc_trk_g1_7 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => bot_op_6 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_14 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_r_22 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_11 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_14 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_t_11 lc_trk_g1_6 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_19 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_3 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_8 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_14 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_22 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_43 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_27 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_35 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_b_43 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnl_op_3 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnr_op_3 lc_trk_g2_3 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => bnl_op_2 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => rgt_op_2 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_10 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_18 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_1 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_l_15 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_34 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_42 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_10 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_34 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_b_34 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_15 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_31 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2 -(23 0) routing sp12_h_l_16 lc_trk_g0_3 -(23 0) routing sp12_h_r_11 lc_trk_g0_3 -(23 0) routing sp4_h_l_6 lc_trk_g0_3 -(23 0) routing sp4_h_r_11 lc_trk_g0_3 -(23 0) routing sp4_h_r_3 lc_trk_g0_3 -(23 0) routing sp4_v_b_11 lc_trk_g0_3 -(23 0) routing sp4_v_b_3 lc_trk_g0_3 -(23 0) routing sp4_v_t_6 lc_trk_g0_3 -(23 1) routing sp12_h_l_17 lc_trk_g0_2 -(23 1) routing sp12_h_l_9 lc_trk_g0_2 -(23 1) routing sp4_h_r_10 lc_trk_g0_2 -(23 1) routing sp4_h_r_18 lc_trk_g0_2 -(23 1) routing sp4_h_r_2 lc_trk_g0_2 -(23 1) routing sp4_v_b_10 lc_trk_g0_2 -(23 1) routing sp4_v_b_2 lc_trk_g0_2 -(23 1) routing sp4_v_t_7 lc_trk_g0_2 -(23 10) routing sp12_v_t_12 lc_trk_g2_7 -(23 10) routing sp12_v_t_20 lc_trk_g2_7 -(23 10) routing sp4_h_l_26 lc_trk_g2_7 -(23 10) routing sp4_h_r_31 lc_trk_g2_7 -(23 10) routing sp4_h_r_47 lc_trk_g2_7 -(23 10) routing sp4_v_b_31 lc_trk_g2_7 -(23 10) routing sp4_v_t_26 lc_trk_g2_7 -(23 10) routing sp4_v_t_34 lc_trk_g2_7 -(23 11) routing sp12_v_b_14 lc_trk_g2_6 -(23 11) routing sp12_v_b_22 lc_trk_g2_6 -(23 11) routing sp4_h_l_19 lc_trk_g2_6 -(23 11) routing sp4_h_l_27 lc_trk_g2_6 -(23 11) routing sp4_h_r_46 lc_trk_g2_6 -(23 11) routing sp4_v_b_46 lc_trk_g2_6 -(23 11) routing sp4_v_t_19 lc_trk_g2_6 -(23 11) routing sp4_v_t_27 lc_trk_g2_6 -(23 12) routing sp12_v_b_19 lc_trk_g3_3 -(23 12) routing sp12_v_t_8 lc_trk_g3_3 -(23 12) routing sp4_h_l_14 lc_trk_g3_3 -(23 12) routing sp4_h_l_22 lc_trk_g3_3 -(23 12) routing sp4_h_r_43 lc_trk_g3_3 -(23 12) routing sp4_v_b_27 lc_trk_g3_3 -(23 12) routing sp4_v_b_35 lc_trk_g3_3 -(23 12) routing sp4_v_b_43 lc_trk_g3_3 -(23 13) routing sp12_v_b_10 lc_trk_g3_2 -(23 13) routing sp12_v_b_18 lc_trk_g3_2 -(23 13) routing sp4_h_l_15 lc_trk_g3_2 -(23 13) routing sp4_h_r_34 lc_trk_g3_2 -(23 13) routing sp4_h_r_42 lc_trk_g3_2 -(23 13) routing sp4_v_b_34 lc_trk_g3_2 -(23 13) routing sp4_v_t_15 lc_trk_g3_2 -(23 13) routing sp4_v_t_31 lc_trk_g3_2 -(23 14) routing sp12_v_t_12 lc_trk_g3_7 -(23 14) routing sp12_v_t_20 lc_trk_g3_7 -(23 14) routing sp4_h_l_26 lc_trk_g3_7 -(23 14) routing sp4_h_r_31 lc_trk_g3_7 -(23 14) routing sp4_h_r_47 lc_trk_g3_7 -(23 14) routing sp4_v_b_31 lc_trk_g3_7 -(23 14) routing sp4_v_t_26 lc_trk_g3_7 -(23 14) routing sp4_v_t_34 lc_trk_g3_7 -(23 15) routing sp12_v_b_14 lc_trk_g3_6 -(23 15) routing sp12_v_b_22 lc_trk_g3_6 -(23 15) routing sp4_h_l_19 lc_trk_g3_6 -(23 15) routing sp4_h_l_27 lc_trk_g3_6 -(23 15) routing sp4_h_r_46 lc_trk_g3_6 -(23 15) routing sp4_v_b_46 lc_trk_g3_6 -(23 15) routing sp4_v_t_19 lc_trk_g3_6 -(23 15) routing sp4_v_t_27 lc_trk_g3_6 -(23 2) routing sp12_h_l_12 lc_trk_g0_7 -(23 2) routing sp12_h_l_20 lc_trk_g0_7 -(23 2) routing sp4_h_r_15 lc_trk_g0_7 -(23 2) routing sp4_h_r_23 lc_trk_g0_7 -(23 2) routing sp4_h_r_7 lc_trk_g0_7 -(23 2) routing sp4_v_b_23 lc_trk_g0_7 -(23 2) routing sp4_v_b_7 lc_trk_g0_7 -(23 2) routing sp4_v_t_2 lc_trk_g0_7 -(23 3) routing sp12_h_r_14 lc_trk_g0_6 -(23 3) routing sp12_h_r_22 lc_trk_g0_6 -(23 3) routing sp4_h_l_11 lc_trk_g0_6 -(23 3) routing sp4_h_l_3 lc_trk_g0_6 -(23 3) routing sp4_h_r_6 lc_trk_g0_6 -(23 3) routing sp4_v_b_14 lc_trk_g0_6 -(23 3) routing sp4_v_b_6 lc_trk_g0_6 -(23 3) routing sp4_v_t_11 lc_trk_g0_6 -(23 4) routing sp12_h_l_16 lc_trk_g1_3 -(23 4) routing sp12_h_r_11 lc_trk_g1_3 -(23 4) routing sp4_h_l_6 lc_trk_g1_3 -(23 4) routing sp4_h_r_11 lc_trk_g1_3 -(23 4) routing sp4_h_r_3 lc_trk_g1_3 -(23 4) routing sp4_v_b_11 lc_trk_g1_3 -(23 4) routing sp4_v_b_3 lc_trk_g1_3 -(23 4) routing sp4_v_t_6 lc_trk_g1_3 -(23 5) routing sp12_h_l_17 lc_trk_g1_2 -(23 5) routing sp12_h_l_9 lc_trk_g1_2 -(23 5) routing sp4_h_r_10 lc_trk_g1_2 -(23 5) routing sp4_h_r_18 lc_trk_g1_2 -(23 5) routing sp4_h_r_2 lc_trk_g1_2 -(23 5) routing sp4_v_b_10 lc_trk_g1_2 -(23 5) routing sp4_v_b_2 lc_trk_g1_2 -(23 5) routing sp4_v_t_7 lc_trk_g1_2 -(23 6) routing sp12_h_l_12 lc_trk_g1_7 -(23 6) routing sp12_h_l_20 lc_trk_g1_7 -(23 6) routing sp4_h_r_15 lc_trk_g1_7 -(23 6) routing sp4_h_r_23 lc_trk_g1_7 -(23 6) routing sp4_h_r_7 lc_trk_g1_7 -(23 6) routing sp4_v_b_23 lc_trk_g1_7 -(23 6) routing sp4_v_b_7 lc_trk_g1_7 -(23 6) routing sp4_v_t_2 lc_trk_g1_7 -(23 7) routing sp12_h_r_14 lc_trk_g1_6 -(23 7) routing sp12_h_r_22 lc_trk_g1_6 -(23 7) routing sp4_h_l_11 lc_trk_g1_6 -(23 7) routing sp4_h_l_3 lc_trk_g1_6 -(23 7) routing sp4_h_r_6 lc_trk_g1_6 -(23 7) routing sp4_v_b_14 lc_trk_g1_6 -(23 7) routing sp4_v_b_6 lc_trk_g1_6 -(23 7) routing sp4_v_t_11 lc_trk_g1_6 -(23 8) routing sp12_v_b_19 lc_trk_g2_3 -(23 8) routing sp12_v_t_8 lc_trk_g2_3 -(23 8) routing sp4_h_l_14 lc_trk_g2_3 -(23 8) routing sp4_h_l_22 lc_trk_g2_3 -(23 8) routing sp4_h_r_43 lc_trk_g2_3 -(23 8) routing sp4_v_b_27 lc_trk_g2_3 -(23 8) routing sp4_v_b_35 lc_trk_g2_3 -(23 8) routing sp4_v_b_43 lc_trk_g2_3 -(23 9) routing sp12_v_b_10 lc_trk_g2_2 -(23 9) routing sp12_v_b_18 lc_trk_g2_2 -(23 9) routing sp4_h_l_15 lc_trk_g2_2 -(23 9) routing sp4_h_r_34 lc_trk_g2_2 -(23 9) routing sp4_h_r_42 lc_trk_g2_2 -(23 9) routing sp4_v_b_34 lc_trk_g2_2 -(23 9) routing sp4_v_t_15 lc_trk_g2_2 -(23 9) routing sp4_v_t_31 lc_trk_g2_2 -(24 0) routing lft_op_3 lc_trk_g0_3 -(24 0) routing sp12_h_r_3 lc_trk_g0_3 -(24 0) routing sp4_h_l_6 lc_trk_g0_3 -(24 0) routing sp4_h_r_11 lc_trk_g0_3 -(24 0) routing sp4_h_r_3 lc_trk_g0_3 -(24 0) routing sp4_v_t_6 lc_trk_g0_3 -(24 1) routing bot_op_2 lc_trk_g0_2 -(24 1) routing lft_op_2 lc_trk_g0_2 -(24 1) routing sp12_h_l_1 lc_trk_g0_2 -(24 1) routing sp4_h_r_10 lc_trk_g0_2 -(24 1) routing sp4_h_r_18 lc_trk_g0_2 -(24 1) routing sp4_h_r_2 lc_trk_g0_2 -(24 1) routing sp4_v_t_7 lc_trk_g0_2 -(24 10) routing rgt_op_7 lc_trk_g2_7 -(24 10) routing sp12_v_t_4 lc_trk_g2_7 -(24 10) routing sp4_h_l_26 lc_trk_g2_7 -(24 10) routing sp4_h_r_31 lc_trk_g2_7 -(24 10) routing sp4_h_r_47 lc_trk_g2_7 -(24 10) routing sp4_v_t_34 lc_trk_g2_7 -(24 10) routing tnl_op_7 lc_trk_g2_7 -(24 10) routing tnr_op_7 lc_trk_g2_7 -(24 11) routing rgt_op_6 lc_trk_g2_6 -(24 11) routing sp12_v_t_5 lc_trk_g2_6 -(24 11) routing sp4_h_l_19 lc_trk_g2_6 -(24 11) routing sp4_h_l_27 lc_trk_g2_6 -(24 11) routing sp4_h_r_46 lc_trk_g2_6 -(24 11) routing sp4_v_b_46 lc_trk_g2_6 -(24 11) routing tnl_op_6 lc_trk_g2_6 -(24 11) routing tnr_op_6 lc_trk_g2_6 -(24 12) routing rgt_op_3 lc_trk_g3_3 -(24 12) routing sp12_v_b_3 lc_trk_g3_3 -(24 12) routing sp4_h_l_14 lc_trk_g3_3 -(24 12) routing sp4_h_l_22 lc_trk_g3_3 -(24 12) routing sp4_h_r_43 lc_trk_g3_3 -(24 12) routing sp4_v_b_43 lc_trk_g3_3 -(24 12) routing tnl_op_3 lc_trk_g3_3 -(24 12) routing tnr_op_3 lc_trk_g3_3 -(24 13) routing rgt_op_2 lc_trk_g3_2 -(24 13) routing sp12_v_t_1 lc_trk_g3_2 -(24 13) routing sp4_h_l_15 lc_trk_g3_2 -(24 13) routing sp4_h_r_34 lc_trk_g3_2 -(24 13) routing sp4_h_r_42 lc_trk_g3_2 -(24 13) routing sp4_v_t_31 lc_trk_g3_2 -(24 13) routing tnl_op_2 lc_trk_g3_2 -(24 13) routing tnr_op_2 lc_trk_g3_2 -(24 14) routing rgt_op_7 lc_trk_g3_7 -(24 14) routing sp12_v_t_4 lc_trk_g3_7 -(24 14) routing sp4_h_l_26 lc_trk_g3_7 -(24 14) routing sp4_h_r_31 lc_trk_g3_7 -(24 14) routing sp4_h_r_47 lc_trk_g3_7 -(24 14) routing sp4_v_t_34 lc_trk_g3_7 -(24 14) routing tnl_op_7 lc_trk_g3_7 -(24 14) routing tnr_op_7 lc_trk_g3_7 -(24 15) routing rgt_op_6 lc_trk_g3_6 -(24 15) routing sp12_v_t_5 lc_trk_g3_6 -(24 15) routing sp4_h_l_19 lc_trk_g3_6 -(24 15) routing sp4_h_l_27 lc_trk_g3_6 -(24 15) routing sp4_h_r_46 lc_trk_g3_6 -(24 15) routing sp4_v_b_46 lc_trk_g3_6 -(24 15) routing tnl_op_6 lc_trk_g3_6 -(24 15) routing tnr_op_6 lc_trk_g3_6 -(24 2) routing lft_op_7 lc_trk_g0_7 -(24 2) routing sp12_h_r_7 lc_trk_g0_7 -(24 2) routing sp4_h_r_15 lc_trk_g0_7 -(24 2) routing sp4_h_r_23 lc_trk_g0_7 -(24 2) routing sp4_h_r_7 lc_trk_g0_7 -(24 2) routing sp4_v_b_23 lc_trk_g0_7 -(24 3) routing bot_op_6 lc_trk_g0_6 -(24 3) routing lft_op_6 lc_trk_g0_6 -(24 3) routing sp12_h_l_5 lc_trk_g0_6 -(24 3) routing sp4_h_l_11 lc_trk_g0_6 -(24 3) routing sp4_h_l_3 lc_trk_g0_6 -(24 3) routing sp4_h_r_6 lc_trk_g0_6 -(24 3) routing sp4_v_t_11 lc_trk_g0_6 -(24 4) routing lft_op_3 lc_trk_g1_3 -(24 4) routing sp12_h_r_3 lc_trk_g1_3 -(24 4) routing sp4_h_l_6 lc_trk_g1_3 -(24 4) routing sp4_h_r_11 lc_trk_g1_3 -(24 4) routing sp4_h_r_3 lc_trk_g1_3 -(24 4) routing sp4_v_t_6 lc_trk_g1_3 -(24 5) routing bot_op_2 lc_trk_g1_2 -(24 5) routing lft_op_2 lc_trk_g1_2 -(24 5) routing sp12_h_l_1 lc_trk_g1_2 -(24 5) routing sp4_h_r_10 lc_trk_g1_2 -(24 5) routing sp4_h_r_18 lc_trk_g1_2 -(24 5) routing sp4_h_r_2 lc_trk_g1_2 -(24 5) routing sp4_v_t_7 lc_trk_g1_2 -(24 6) routing lft_op_7 lc_trk_g1_7 -(24 6) routing sp12_h_r_7 lc_trk_g1_7 -(24 6) routing sp4_h_r_15 lc_trk_g1_7 -(24 6) routing sp4_h_r_23 lc_trk_g1_7 -(24 6) routing sp4_h_r_7 lc_trk_g1_7 -(24 6) routing sp4_v_b_23 lc_trk_g1_7 -(24 7) routing bot_op_6 lc_trk_g1_6 -(24 7) routing lft_op_6 lc_trk_g1_6 -(24 7) routing sp12_h_l_5 lc_trk_g1_6 -(24 7) routing sp4_h_l_11 lc_trk_g1_6 -(24 7) routing sp4_h_l_3 lc_trk_g1_6 -(24 7) routing sp4_h_r_6 lc_trk_g1_6 -(24 7) routing sp4_v_t_11 lc_trk_g1_6 -(24 8) routing rgt_op_3 lc_trk_g2_3 -(24 8) routing sp12_v_b_3 lc_trk_g2_3 -(24 8) routing sp4_h_l_14 lc_trk_g2_3 -(24 8) routing sp4_h_l_22 lc_trk_g2_3 -(24 8) routing sp4_h_r_43 lc_trk_g2_3 -(24 8) routing sp4_v_b_43 lc_trk_g2_3 -(24 8) routing tnl_op_3 lc_trk_g2_3 -(24 8) routing tnr_op_3 lc_trk_g2_3 -(24 9) routing rgt_op_2 lc_trk_g2_2 -(24 9) routing sp12_v_t_1 lc_trk_g2_2 -(24 9) routing sp4_h_l_15 lc_trk_g2_2 -(24 9) routing sp4_h_r_34 lc_trk_g2_2 -(24 9) routing sp4_h_r_42 lc_trk_g2_2 -(24 9) routing sp4_v_t_31 lc_trk_g2_2 -(24 9) routing tnl_op_2 lc_trk_g2_2 -(24 9) routing tnr_op_2 lc_trk_g2_2 -(25 0) routing bnr_op_2 lc_trk_g0_2 -(25 0) routing lft_op_2 lc_trk_g0_2 -(25 0) routing sp12_h_l_1 lc_trk_g0_2 -(25 0) routing sp4_h_r_10 lc_trk_g0_2 -(25 0) routing sp4_h_r_18 lc_trk_g0_2 -(25 0) routing sp4_v_b_10 lc_trk_g0_2 -(25 0) routing sp4_v_b_2 lc_trk_g0_2 -(25 1) routing bnr_op_2 lc_trk_g0_2 -(25 1) routing sp12_h_l_1 lc_trk_g0_2 -(25 1) routing sp12_h_l_17 lc_trk_g0_2 -(25 1) routing sp4_h_r_18 lc_trk_g0_2 -(25 1) routing sp4_h_r_2 lc_trk_g0_2 -(25 1) routing sp4_r_v_b_33 lc_trk_g0_2 -(25 1) routing sp4_v_b_10 lc_trk_g0_2 -(25 10) routing bnl_op_6 lc_trk_g2_6 -(25 10) routing rgt_op_6 lc_trk_g2_6 -(25 10) routing sp12_v_t_5 lc_trk_g2_6 -(25 10) routing sp4_h_l_27 lc_trk_g2_6 -(25 10) routing sp4_h_r_46 lc_trk_g2_6 -(25 10) routing sp4_v_t_19 lc_trk_g2_6 -(25 10) routing sp4_v_t_27 lc_trk_g2_6 -(25 11) routing bnl_op_6 lc_trk_g2_6 -(25 11) routing sp12_v_b_22 lc_trk_g2_6 -(25 11) routing sp12_v_t_5 lc_trk_g2_6 -(25 11) routing sp4_h_l_19 lc_trk_g2_6 -(25 11) routing sp4_h_r_46 lc_trk_g2_6 -(25 11) routing sp4_r_v_b_38 lc_trk_g2_6 -(25 11) routing sp4_v_t_27 lc_trk_g2_6 -(25 11) routing tnl_op_6 lc_trk_g2_6 -(25 12) routing bnl_op_2 lc_trk_g3_2 -(25 12) routing rgt_op_2 lc_trk_g3_2 -(25 12) routing sp12_v_t_1 lc_trk_g3_2 -(25 12) routing sp4_h_r_34 lc_trk_g3_2 -(25 12) routing sp4_h_r_42 lc_trk_g3_2 -(25 12) routing sp4_v_b_34 lc_trk_g3_2 -(25 12) routing sp4_v_t_15 lc_trk_g3_2 -(25 13) routing bnl_op_2 lc_trk_g3_2 -(25 13) routing sp12_v_b_18 lc_trk_g3_2 -(25 13) routing sp12_v_t_1 lc_trk_g3_2 -(25 13) routing sp4_h_l_15 lc_trk_g3_2 -(25 13) routing sp4_h_r_42 lc_trk_g3_2 -(25 13) routing sp4_r_v_b_42 lc_trk_g3_2 -(25 13) routing sp4_v_b_34 lc_trk_g3_2 -(25 13) routing tnl_op_2 lc_trk_g3_2 -(25 14) routing bnl_op_6 lc_trk_g3_6 -(25 14) routing rgt_op_6 lc_trk_g3_6 -(25 14) routing sp12_v_t_5 lc_trk_g3_6 -(25 14) routing sp4_h_l_27 lc_trk_g3_6 -(25 14) routing sp4_h_r_46 lc_trk_g3_6 -(25 14) routing sp4_v_t_19 lc_trk_g3_6 -(25 14) routing sp4_v_t_27 lc_trk_g3_6 -(25 15) routing bnl_op_6 lc_trk_g3_6 -(25 15) routing sp12_v_b_22 lc_trk_g3_6 -(25 15) routing sp12_v_t_5 lc_trk_g3_6 -(25 15) routing sp4_h_l_19 lc_trk_g3_6 -(25 15) routing sp4_h_r_46 lc_trk_g3_6 -(25 15) routing sp4_r_v_b_46 lc_trk_g3_6 -(25 15) routing sp4_v_t_27 lc_trk_g3_6 -(25 15) routing tnl_op_6 lc_trk_g3_6 -(25 2) routing bnr_op_6 lc_trk_g0_6 -(25 2) routing lft_op_6 lc_trk_g0_6 -(25 2) routing sp12_h_l_5 lc_trk_g0_6 -(25 2) routing sp4_h_l_11 lc_trk_g0_6 -(25 2) routing sp4_h_l_3 lc_trk_g0_6 -(25 2) routing sp4_v_b_14 lc_trk_g0_6 -(25 2) routing sp4_v_b_6 lc_trk_g0_6 -(25 3) routing bnr_op_6 lc_trk_g0_6 -(25 3) routing sp12_h_l_5 lc_trk_g0_6 -(25 3) routing sp12_h_r_22 lc_trk_g0_6 -(25 3) routing sp4_h_l_11 lc_trk_g0_6 -(25 3) routing sp4_h_r_6 lc_trk_g0_6 -(25 3) routing sp4_r_v_b_30 lc_trk_g0_6 -(25 3) routing sp4_v_b_14 lc_trk_g0_6 -(25 4) routing bnr_op_2 lc_trk_g1_2 -(25 4) routing lft_op_2 lc_trk_g1_2 -(25 4) routing sp12_h_l_1 lc_trk_g1_2 -(25 4) routing sp4_h_r_10 lc_trk_g1_2 -(25 4) routing sp4_h_r_18 lc_trk_g1_2 -(25 4) routing sp4_v_b_10 lc_trk_g1_2 -(25 4) routing sp4_v_b_2 lc_trk_g1_2 -(25 5) routing bnr_op_2 lc_trk_g1_2 -(25 5) routing sp12_h_l_1 lc_trk_g1_2 -(25 5) routing sp12_h_l_17 lc_trk_g1_2 -(25 5) routing sp4_h_r_18 lc_trk_g1_2 -(25 5) routing sp4_h_r_2 lc_trk_g1_2 -(25 5) routing sp4_r_v_b_26 lc_trk_g1_2 -(25 5) routing sp4_v_b_10 lc_trk_g1_2 -(25 6) routing bnr_op_6 lc_trk_g1_6 -(25 6) routing lft_op_6 lc_trk_g1_6 -(25 6) routing sp12_h_l_5 lc_trk_g1_6 -(25 6) routing sp4_h_l_11 lc_trk_g1_6 -(25 6) routing sp4_h_l_3 lc_trk_g1_6 -(25 6) routing sp4_v_b_14 lc_trk_g1_6 -(25 6) routing sp4_v_b_6 lc_trk_g1_6 -(25 7) routing bnr_op_6 lc_trk_g1_6 -(25 7) routing sp12_h_l_5 lc_trk_g1_6 -(25 7) routing sp12_h_r_22 lc_trk_g1_6 -(25 7) routing sp4_h_l_11 lc_trk_g1_6 -(25 7) routing sp4_h_r_6 lc_trk_g1_6 -(25 7) routing sp4_r_v_b_30 lc_trk_g1_6 -(25 7) routing sp4_v_b_14 lc_trk_g1_6 -(25 8) routing bnl_op_2 lc_trk_g2_2 -(25 8) routing rgt_op_2 lc_trk_g2_2 -(25 8) routing sp12_v_t_1 lc_trk_g2_2 -(25 8) routing sp4_h_r_34 lc_trk_g2_2 -(25 8) routing sp4_h_r_42 lc_trk_g2_2 -(25 8) routing sp4_v_b_34 lc_trk_g2_2 -(25 8) routing sp4_v_t_15 lc_trk_g2_2 -(25 9) routing bnl_op_2 lc_trk_g2_2 -(25 9) routing sp12_v_b_18 lc_trk_g2_2 -(25 9) routing sp12_v_t_1 lc_trk_g2_2 -(25 9) routing sp4_h_l_15 lc_trk_g2_2 -(25 9) routing sp4_h_r_42 lc_trk_g2_2 -(25 9) routing sp4_r_v_b_34 lc_trk_g2_2 -(25 9) routing sp4_v_b_34 lc_trk_g2_2 -(25 9) routing tnl_op_2 lc_trk_g2_2 -(26 0) routing lc_trk_g0_4 input0_0 -(26 0) routing lc_trk_g0_6 input0_0 -(26 0) routing lc_trk_g1_5 input0_0 -(26 0) routing lc_trk_g1_7 input0_0 -(26 0) routing lc_trk_g2_4 input0_0 -(26 0) routing lc_trk_g2_6 input0_0 -(26 0) routing lc_trk_g3_5 input0_0 -(26 0) routing lc_trk_g3_7 input0_0 -(26 1) routing lc_trk_g0_2 input0_0 -(26 1) routing lc_trk_g0_6 input0_0 -(26 1) routing lc_trk_g1_3 input0_0 -(26 1) routing lc_trk_g1_7 input0_0 -(26 1) routing lc_trk_g2_2 input0_0 -(26 1) routing lc_trk_g2_6 input0_0 -(26 1) routing lc_trk_g3_3 input0_0 -(26 1) routing lc_trk_g3_7 input0_0 -(26 10) routing lc_trk_g0_5 input0_5 -(26 10) routing lc_trk_g0_7 input0_5 -(26 10) routing lc_trk_g1_4 input0_5 -(26 10) routing lc_trk_g1_6 input0_5 -(26 10) routing lc_trk_g2_5 input0_5 -(26 10) routing lc_trk_g2_7 input0_5 -(26 10) routing lc_trk_g3_4 input0_5 -(26 10) routing lc_trk_g3_6 input0_5 -(26 11) routing lc_trk_g0_3 input0_5 -(26 11) routing lc_trk_g0_7 input0_5 -(26 11) routing lc_trk_g1_2 input0_5 -(26 11) routing lc_trk_g1_6 input0_5 -(26 11) routing lc_trk_g2_3 input0_5 -(26 11) routing lc_trk_g2_7 input0_5 -(26 11) routing lc_trk_g3_2 input0_5 -(26 11) routing lc_trk_g3_6 input0_5 -(26 12) routing lc_trk_g0_4 input0_6 -(26 12) routing lc_trk_g0_6 input0_6 -(26 12) routing lc_trk_g1_5 input0_6 -(26 12) routing lc_trk_g1_7 input0_6 -(26 12) routing lc_trk_g2_4 input0_6 -(26 12) routing lc_trk_g2_6 input0_6 -(26 12) routing lc_trk_g3_5 input0_6 -(26 12) routing lc_trk_g3_7 input0_6 -(26 13) routing lc_trk_g0_2 input0_6 -(26 13) routing lc_trk_g0_6 input0_6 -(26 13) routing lc_trk_g1_3 input0_6 -(26 13) routing lc_trk_g1_7 input0_6 -(26 13) routing lc_trk_g2_2 input0_6 -(26 13) routing lc_trk_g2_6 input0_6 -(26 13) routing lc_trk_g3_3 input0_6 -(26 13) routing lc_trk_g3_7 input0_6 -(26 14) routing lc_trk_g0_5 input0_7 -(26 14) routing lc_trk_g0_7 input0_7 -(26 14) routing lc_trk_g1_4 input0_7 -(26 14) routing lc_trk_g1_6 input0_7 -(26 14) routing lc_trk_g2_5 input0_7 -(26 14) routing lc_trk_g2_7 input0_7 -(26 14) routing lc_trk_g3_4 input0_7 -(26 14) routing lc_trk_g3_6 input0_7 -(26 15) routing lc_trk_g0_3 input0_7 -(26 15) routing lc_trk_g0_7 input0_7 -(26 15) routing lc_trk_g1_2 input0_7 -(26 15) routing lc_trk_g1_6 input0_7 -(26 15) routing lc_trk_g2_3 input0_7 -(26 15) routing lc_trk_g2_7 input0_7 -(26 15) routing lc_trk_g3_2 input0_7 -(26 15) routing lc_trk_g3_6 input0_7 -(26 2) routing lc_trk_g0_5 input0_1 -(26 2) routing lc_trk_g0_7 input0_1 -(26 2) routing lc_trk_g1_4 input0_1 -(26 2) routing lc_trk_g1_6 input0_1 -(26 2) routing lc_trk_g2_5 input0_1 -(26 2) routing lc_trk_g2_7 input0_1 -(26 2) routing lc_trk_g3_4 input0_1 -(26 2) routing lc_trk_g3_6 input0_1 -(26 3) routing lc_trk_g0_3 input0_1 -(26 3) routing lc_trk_g0_7 input0_1 -(26 3) routing lc_trk_g1_2 input0_1 -(26 3) routing lc_trk_g1_6 input0_1 -(26 3) routing lc_trk_g2_3 input0_1 -(26 3) routing lc_trk_g2_7 input0_1 -(26 3) routing lc_trk_g3_2 input0_1 -(26 3) routing lc_trk_g3_6 input0_1 -(26 4) routing lc_trk_g0_4 input0_2 -(26 4) routing lc_trk_g0_6 input0_2 -(26 4) routing lc_trk_g1_5 input0_2 -(26 4) routing lc_trk_g1_7 input0_2 -(26 4) routing lc_trk_g2_4 input0_2 -(26 4) routing lc_trk_g2_6 input0_2 -(26 4) routing lc_trk_g3_5 input0_2 -(26 4) routing lc_trk_g3_7 input0_2 -(26 5) routing lc_trk_g0_2 input0_2 -(26 5) routing lc_trk_g0_6 input0_2 -(26 5) routing lc_trk_g1_3 input0_2 -(26 5) routing lc_trk_g1_7 input0_2 -(26 5) routing lc_trk_g2_2 input0_2 -(26 5) routing lc_trk_g2_6 input0_2 -(26 5) routing lc_trk_g3_3 input0_2 -(26 5) routing lc_trk_g3_7 input0_2 -(26 6) routing lc_trk_g0_5 input0_3 -(26 6) routing lc_trk_g0_7 input0_3 -(26 6) routing lc_trk_g1_4 input0_3 -(26 6) routing lc_trk_g1_6 input0_3 -(26 6) routing lc_trk_g2_5 input0_3 -(26 6) routing lc_trk_g2_7 input0_3 -(26 6) routing lc_trk_g3_4 input0_3 -(26 6) routing lc_trk_g3_6 input0_3 -(26 7) routing lc_trk_g0_3 input0_3 -(26 7) routing lc_trk_g0_7 input0_3 -(26 7) routing lc_trk_g1_2 input0_3 -(26 7) routing lc_trk_g1_6 input0_3 -(26 7) routing lc_trk_g2_3 input0_3 -(26 7) routing lc_trk_g2_7 input0_3 -(26 7) routing lc_trk_g3_2 input0_3 -(26 7) routing lc_trk_g3_6 input0_3 -(26 8) routing lc_trk_g0_4 input0_4 -(26 8) routing lc_trk_g0_6 input0_4 -(26 8) routing lc_trk_g1_5 input0_4 -(26 8) routing lc_trk_g1_7 input0_4 -(26 8) routing lc_trk_g2_4 input0_4 -(26 8) routing lc_trk_g2_6 input0_4 -(26 8) routing lc_trk_g3_5 input0_4 -(26 8) routing lc_trk_g3_7 input0_4 -(26 9) routing lc_trk_g0_2 input0_4 -(26 9) routing lc_trk_g0_6 input0_4 -(26 9) routing lc_trk_g1_3 input0_4 -(26 9) routing lc_trk_g1_7 input0_4 -(26 9) routing lc_trk_g2_2 input0_4 -(26 9) routing lc_trk_g2_6 input0_4 -(26 9) routing lc_trk_g3_3 input0_4 -(26 9) routing lc_trk_g3_7 input0_4 -(27 0) routing lc_trk_g1_0 wire_bram/ram/WDATA_15 -(27 0) routing lc_trk_g1_2 wire_bram/ram/WDATA_15 -(27 0) routing lc_trk_g1_4 wire_bram/ram/WDATA_15 -(27 0) routing lc_trk_g1_6 wire_bram/ram/WDATA_15 -(27 0) routing lc_trk_g3_0 wire_bram/ram/WDATA_15 -(27 0) routing lc_trk_g3_2 wire_bram/ram/WDATA_15 -(27 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_15 -(27 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_15 -(27 1) routing lc_trk_g1_1 input0_0 -(27 1) routing lc_trk_g1_3 input0_0 -(27 1) routing lc_trk_g1_5 input0_0 -(27 1) routing lc_trk_g1_7 input0_0 -(27 1) routing lc_trk_g3_1 input0_0 -(27 1) routing lc_trk_g3_3 input0_0 -(27 1) routing lc_trk_g3_5 input0_0 -(27 1) routing lc_trk_g3_7 input0_0 -(27 10) routing lc_trk_g1_1 wire_bram/ram/WDATA_10 -(27 10) routing lc_trk_g1_3 wire_bram/ram/WDATA_10 -(27 10) routing lc_trk_g1_5 wire_bram/ram/WDATA_10 -(27 10) routing lc_trk_g1_7 wire_bram/ram/WDATA_10 -(27 10) routing lc_trk_g3_1 wire_bram/ram/WDATA_10 -(27 10) routing lc_trk_g3_3 wire_bram/ram/WDATA_10 -(27 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_10 -(27 10) routing lc_trk_g3_7 wire_bram/ram/WDATA_10 -(27 11) routing lc_trk_g1_0 input0_5 -(27 11) routing lc_trk_g1_2 input0_5 -(27 11) routing lc_trk_g1_4 input0_5 -(27 11) routing lc_trk_g1_6 input0_5 -(27 11) routing lc_trk_g3_0 input0_5 -(27 11) routing lc_trk_g3_2 input0_5 -(27 11) routing lc_trk_g3_4 input0_5 -(27 11) routing lc_trk_g3_6 input0_5 -(27 12) routing lc_trk_g1_0 wire_bram/ram/WDATA_9 -(27 12) routing lc_trk_g1_2 wire_bram/ram/WDATA_9 -(27 12) routing lc_trk_g1_4 wire_bram/ram/WDATA_9 -(27 12) routing lc_trk_g1_6 wire_bram/ram/WDATA_9 -(27 12) routing lc_trk_g3_0 wire_bram/ram/WDATA_9 -(27 12) routing lc_trk_g3_2 wire_bram/ram/WDATA_9 -(27 12) routing lc_trk_g3_4 wire_bram/ram/WDATA_9 -(27 12) routing lc_trk_g3_6 wire_bram/ram/WDATA_9 -(27 13) routing lc_trk_g1_1 input0_6 -(27 13) routing lc_trk_g1_3 input0_6 -(27 13) routing lc_trk_g1_5 input0_6 -(27 13) routing lc_trk_g1_7 input0_6 -(27 13) routing lc_trk_g3_1 input0_6 -(27 13) routing lc_trk_g3_3 input0_6 -(27 13) routing lc_trk_g3_5 input0_6 -(27 13) routing lc_trk_g3_7 input0_6 -(27 14) routing lc_trk_g1_1 wire_bram/ram/WDATA_8 -(27 14) routing lc_trk_g1_3 wire_bram/ram/WDATA_8 -(27 14) routing lc_trk_g1_5 wire_bram/ram/WDATA_8 -(27 14) routing lc_trk_g1_7 wire_bram/ram/WDATA_8 -(27 14) routing lc_trk_g3_1 wire_bram/ram/WDATA_8 -(27 14) routing lc_trk_g3_3 wire_bram/ram/WDATA_8 -(27 14) routing lc_trk_g3_5 wire_bram/ram/WDATA_8 -(27 14) routing lc_trk_g3_7 wire_bram/ram/WDATA_8 -(27 15) routing lc_trk_g1_0 input0_7 -(27 15) routing lc_trk_g1_2 input0_7 -(27 15) routing lc_trk_g1_4 input0_7 -(27 15) routing lc_trk_g1_6 input0_7 -(27 15) routing lc_trk_g3_0 input0_7 -(27 15) routing lc_trk_g3_2 input0_7 -(27 15) routing lc_trk_g3_4 input0_7 -(27 15) routing lc_trk_g3_6 input0_7 -(27 2) routing lc_trk_g1_1 wire_bram/ram/WDATA_14 -(27 2) routing lc_trk_g1_3 wire_bram/ram/WDATA_14 -(27 2) routing lc_trk_g1_5 wire_bram/ram/WDATA_14 -(27 2) routing lc_trk_g1_7 wire_bram/ram/WDATA_14 -(27 2) routing lc_trk_g3_1 wire_bram/ram/WDATA_14 -(27 2) routing lc_trk_g3_3 wire_bram/ram/WDATA_14 -(27 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_14 -(27 2) routing lc_trk_g3_7 wire_bram/ram/WDATA_14 -(27 3) routing lc_trk_g1_0 input0_1 -(27 3) routing lc_trk_g1_2 input0_1 -(27 3) routing lc_trk_g1_4 input0_1 -(27 3) routing lc_trk_g1_6 input0_1 -(27 3) routing lc_trk_g3_0 input0_1 -(27 3) routing lc_trk_g3_2 input0_1 -(27 3) routing lc_trk_g3_4 input0_1 -(27 3) routing lc_trk_g3_6 input0_1 -(27 4) routing lc_trk_g1_0 wire_bram/ram/WDATA_13 -(27 4) routing lc_trk_g1_2 wire_bram/ram/WDATA_13 -(27 4) routing lc_trk_g1_4 wire_bram/ram/WDATA_13 -(27 4) routing lc_trk_g1_6 wire_bram/ram/WDATA_13 -(27 4) routing lc_trk_g3_0 wire_bram/ram/WDATA_13 -(27 4) routing lc_trk_g3_2 wire_bram/ram/WDATA_13 -(27 4) routing lc_trk_g3_4 wire_bram/ram/WDATA_13 -(27 4) routing lc_trk_g3_6 wire_bram/ram/WDATA_13 -(27 5) routing lc_trk_g1_1 input0_2 -(27 5) routing lc_trk_g1_3 input0_2 -(27 5) routing lc_trk_g1_5 input0_2 -(27 5) routing lc_trk_g1_7 input0_2 -(27 5) routing lc_trk_g3_1 input0_2 -(27 5) routing lc_trk_g3_3 input0_2 -(27 5) routing lc_trk_g3_5 input0_2 -(27 5) routing lc_trk_g3_7 input0_2 -(27 6) routing lc_trk_g1_1 wire_bram/ram/WDATA_12 -(27 6) routing lc_trk_g1_3 wire_bram/ram/WDATA_12 -(27 6) routing lc_trk_g1_5 wire_bram/ram/WDATA_12 -(27 6) routing lc_trk_g1_7 wire_bram/ram/WDATA_12 -(27 6) routing lc_trk_g3_1 wire_bram/ram/WDATA_12 -(27 6) routing lc_trk_g3_3 wire_bram/ram/WDATA_12 -(27 6) routing lc_trk_g3_5 wire_bram/ram/WDATA_12 -(27 6) routing lc_trk_g3_7 wire_bram/ram/WDATA_12 -(27 7) routing lc_trk_g1_0 input0_3 -(27 7) routing lc_trk_g1_2 input0_3 -(27 7) routing lc_trk_g1_4 input0_3 -(27 7) routing lc_trk_g1_6 input0_3 -(27 7) routing lc_trk_g3_0 input0_3 -(27 7) routing lc_trk_g3_2 input0_3 -(27 7) routing lc_trk_g3_4 input0_3 -(27 7) routing lc_trk_g3_6 input0_3 -(27 8) routing lc_trk_g1_0 wire_bram/ram/WDATA_11 -(27 8) routing lc_trk_g1_2 wire_bram/ram/WDATA_11 -(27 8) routing lc_trk_g1_4 wire_bram/ram/WDATA_11 -(27 8) routing lc_trk_g1_6 wire_bram/ram/WDATA_11 -(27 8) routing lc_trk_g3_0 wire_bram/ram/WDATA_11 -(27 8) routing lc_trk_g3_2 wire_bram/ram/WDATA_11 -(27 8) routing lc_trk_g3_4 wire_bram/ram/WDATA_11 -(27 8) routing lc_trk_g3_6 wire_bram/ram/WDATA_11 -(27 9) routing lc_trk_g1_1 input0_4 -(27 9) routing lc_trk_g1_3 input0_4 -(27 9) routing lc_trk_g1_5 input0_4 -(27 9) routing lc_trk_g1_7 input0_4 -(27 9) routing lc_trk_g3_1 input0_4 -(27 9) routing lc_trk_g3_3 input0_4 -(27 9) routing lc_trk_g3_5 input0_4 -(27 9) routing lc_trk_g3_7 input0_4 -(28 0) routing lc_trk_g2_1 wire_bram/ram/WDATA_15 -(28 0) routing lc_trk_g2_3 wire_bram/ram/WDATA_15 -(28 0) routing lc_trk_g2_5 wire_bram/ram/WDATA_15 -(28 0) routing lc_trk_g2_7 wire_bram/ram/WDATA_15 -(28 0) routing lc_trk_g3_0 wire_bram/ram/WDATA_15 -(28 0) routing lc_trk_g3_2 wire_bram/ram/WDATA_15 -(28 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_15 -(28 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_15 -(28 1) routing lc_trk_g2_0 input0_0 -(28 1) routing lc_trk_g2_2 input0_0 -(28 1) routing lc_trk_g2_4 input0_0 -(28 1) routing lc_trk_g2_6 input0_0 -(28 1) routing lc_trk_g3_1 input0_0 -(28 1) routing lc_trk_g3_3 input0_0 -(28 1) routing lc_trk_g3_5 input0_0 -(28 1) routing lc_trk_g3_7 input0_0 -(28 10) routing lc_trk_g2_0 wire_bram/ram/WDATA_10 -(28 10) routing lc_trk_g2_2 wire_bram/ram/WDATA_10 -(28 10) routing lc_trk_g2_4 wire_bram/ram/WDATA_10 -(28 10) routing lc_trk_g2_6 wire_bram/ram/WDATA_10 -(28 10) routing lc_trk_g3_1 wire_bram/ram/WDATA_10 -(28 10) routing lc_trk_g3_3 wire_bram/ram/WDATA_10 -(28 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_10 -(28 10) routing lc_trk_g3_7 wire_bram/ram/WDATA_10 -(28 11) routing lc_trk_g2_1 input0_5 -(28 11) routing lc_trk_g2_3 input0_5 -(28 11) routing lc_trk_g2_5 input0_5 -(28 11) routing lc_trk_g2_7 input0_5 -(28 11) routing lc_trk_g3_0 input0_5 -(28 11) routing lc_trk_g3_2 input0_5 -(28 11) routing lc_trk_g3_4 input0_5 -(28 11) routing lc_trk_g3_6 input0_5 -(28 12) routing lc_trk_g2_1 wire_bram/ram/WDATA_9 -(28 12) routing lc_trk_g2_3 wire_bram/ram/WDATA_9 -(28 12) routing lc_trk_g2_5 wire_bram/ram/WDATA_9 -(28 12) routing lc_trk_g2_7 wire_bram/ram/WDATA_9 -(28 12) routing lc_trk_g3_0 wire_bram/ram/WDATA_9 -(28 12) routing lc_trk_g3_2 wire_bram/ram/WDATA_9 -(28 12) routing lc_trk_g3_4 wire_bram/ram/WDATA_9 -(28 12) routing lc_trk_g3_6 wire_bram/ram/WDATA_9 -(28 13) routing lc_trk_g2_0 input0_6 -(28 13) routing lc_trk_g2_2 input0_6 -(28 13) routing lc_trk_g2_4 input0_6 -(28 13) routing lc_trk_g2_6 input0_6 -(28 13) routing lc_trk_g3_1 input0_6 -(28 13) routing lc_trk_g3_3 input0_6 -(28 13) routing lc_trk_g3_5 input0_6 -(28 13) routing lc_trk_g3_7 input0_6 -(28 14) routing lc_trk_g2_0 wire_bram/ram/WDATA_8 -(28 14) routing lc_trk_g2_2 wire_bram/ram/WDATA_8 -(28 14) routing lc_trk_g2_4 wire_bram/ram/WDATA_8 -(28 14) routing lc_trk_g2_6 wire_bram/ram/WDATA_8 -(28 14) routing lc_trk_g3_1 wire_bram/ram/WDATA_8 -(28 14) routing lc_trk_g3_3 wire_bram/ram/WDATA_8 -(28 14) routing lc_trk_g3_5 wire_bram/ram/WDATA_8 -(28 14) routing lc_trk_g3_7 wire_bram/ram/WDATA_8 -(28 15) routing lc_trk_g2_1 input0_7 -(28 15) routing lc_trk_g2_3 input0_7 -(28 15) routing lc_trk_g2_5 input0_7 -(28 15) routing lc_trk_g2_7 input0_7 -(28 15) routing lc_trk_g3_0 input0_7 -(28 15) routing lc_trk_g3_2 input0_7 -(28 15) routing lc_trk_g3_4 input0_7 -(28 15) routing lc_trk_g3_6 input0_7 -(28 2) routing lc_trk_g2_0 wire_bram/ram/WDATA_14 -(28 2) routing lc_trk_g2_2 wire_bram/ram/WDATA_14 -(28 2) routing lc_trk_g2_4 wire_bram/ram/WDATA_14 -(28 2) routing lc_trk_g2_6 wire_bram/ram/WDATA_14 -(28 2) routing lc_trk_g3_1 wire_bram/ram/WDATA_14 -(28 2) routing lc_trk_g3_3 wire_bram/ram/WDATA_14 -(28 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_14 -(28 2) routing lc_trk_g3_7 wire_bram/ram/WDATA_14 -(28 3) routing lc_trk_g2_1 input0_1 -(28 3) routing lc_trk_g2_3 input0_1 -(28 3) routing lc_trk_g2_5 input0_1 -(28 3) routing lc_trk_g2_7 input0_1 -(28 3) routing lc_trk_g3_0 input0_1 -(28 3) routing lc_trk_g3_2 input0_1 -(28 3) routing lc_trk_g3_4 input0_1 -(28 3) routing lc_trk_g3_6 input0_1 -(28 4) routing lc_trk_g2_1 wire_bram/ram/WDATA_13 -(28 4) routing lc_trk_g2_3 wire_bram/ram/WDATA_13 -(28 4) routing lc_trk_g2_5 wire_bram/ram/WDATA_13 -(28 4) routing lc_trk_g2_7 wire_bram/ram/WDATA_13 -(28 4) routing lc_trk_g3_0 wire_bram/ram/WDATA_13 -(28 4) routing lc_trk_g3_2 wire_bram/ram/WDATA_13 -(28 4) routing lc_trk_g3_4 wire_bram/ram/WDATA_13 -(28 4) routing lc_trk_g3_6 wire_bram/ram/WDATA_13 -(28 5) routing lc_trk_g2_0 input0_2 -(28 5) routing lc_trk_g2_2 input0_2 -(28 5) routing lc_trk_g2_4 input0_2 -(28 5) routing lc_trk_g2_6 input0_2 -(28 5) routing lc_trk_g3_1 input0_2 -(28 5) routing lc_trk_g3_3 input0_2 -(28 5) routing lc_trk_g3_5 input0_2 -(28 5) routing lc_trk_g3_7 input0_2 -(28 6) routing lc_trk_g2_0 wire_bram/ram/WDATA_12 -(28 6) routing lc_trk_g2_2 wire_bram/ram/WDATA_12 -(28 6) routing lc_trk_g2_4 wire_bram/ram/WDATA_12 -(28 6) routing lc_trk_g2_6 wire_bram/ram/WDATA_12 -(28 6) routing lc_trk_g3_1 wire_bram/ram/WDATA_12 -(28 6) routing lc_trk_g3_3 wire_bram/ram/WDATA_12 -(28 6) routing lc_trk_g3_5 wire_bram/ram/WDATA_12 -(28 6) routing lc_trk_g3_7 wire_bram/ram/WDATA_12 -(28 7) routing lc_trk_g2_1 input0_3 -(28 7) routing lc_trk_g2_3 input0_3 -(28 7) routing lc_trk_g2_5 input0_3 -(28 7) routing lc_trk_g2_7 input0_3 -(28 7) routing lc_trk_g3_0 input0_3 -(28 7) routing lc_trk_g3_2 input0_3 -(28 7) routing lc_trk_g3_4 input0_3 -(28 7) routing lc_trk_g3_6 input0_3 -(28 8) routing lc_trk_g2_1 wire_bram/ram/WDATA_11 -(28 8) routing lc_trk_g2_3 wire_bram/ram/WDATA_11 -(28 8) routing lc_trk_g2_5 wire_bram/ram/WDATA_11 -(28 8) routing lc_trk_g2_7 wire_bram/ram/WDATA_11 -(28 8) routing lc_trk_g3_0 wire_bram/ram/WDATA_11 -(28 8) routing lc_trk_g3_2 wire_bram/ram/WDATA_11 -(28 8) routing lc_trk_g3_4 wire_bram/ram/WDATA_11 -(28 8) routing lc_trk_g3_6 wire_bram/ram/WDATA_11 -(28 9) routing lc_trk_g2_0 input0_4 -(28 9) routing lc_trk_g2_2 input0_4 -(28 9) routing lc_trk_g2_4 input0_4 -(28 9) routing lc_trk_g2_6 input0_4 -(28 9) routing lc_trk_g3_1 input0_4 -(28 9) routing lc_trk_g3_3 input0_4 -(28 9) routing lc_trk_g3_5 input0_4 -(28 9) routing lc_trk_g3_7 input0_4 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_1 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_3 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_5 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_7 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_0 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_2 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_4 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_6 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_1 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_3 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_5 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_7 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_0 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_2 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_4 wire_bram/ram/WDATA_15 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_6 wire_bram/ram/WDATA_15 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_0 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_2 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_4 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_6 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_1 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_3 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_5 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_7 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_0 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_2 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_4 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_6 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_1 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_3 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_5 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_7 input0_0 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_0 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_2 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_4 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_6 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_1 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_3 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_5 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_7 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_0 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_2 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_4 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_6 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_1 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_3 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_5 wire_bram/ram/WDATA_10 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_7 wire_bram/ram/WDATA_10 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_1 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_3 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_5 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_7 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_0 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_2 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_4 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_6 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_1 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_3 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_5 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_7 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_0 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_2 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_4 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_6 input0_5 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_1 wire_bram/ram/WDATA_9 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_3 wire_bram/ram/WDATA_9 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_5 wire_bram/ram/WDATA_9 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_7 wire_bram/ram/WDATA_9 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_0 wire_bram/ram/WDATA_9 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_2 wire_bram/ram/WDATA_9 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_4 wire_bram/ram/WDATA_9 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_6 wire_bram/ram/WDATA_9 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_1 wire_bram/ram/WDATA_9 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_3 wire_bram/ram/WDATA_9 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_5 wire_bram/ram/WDATA_9 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_7 wire_bram/ram/WDATA_9 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_0 wire_bram/ram/WDATA_9 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_2 wire_bram/ram/WDATA_9 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_4 wire_bram/ram/WDATA_9 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_6 wire_bram/ram/WDATA_9 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_0 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_2 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_4 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_6 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_1 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_3 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_5 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_7 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_0 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_2 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_4 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_6 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_1 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_3 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_5 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_7 input0_6 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_0 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_2 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_4 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_6 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_1 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_3 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_5 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_7 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_0 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_2 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_4 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_6 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_1 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_3 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_5 wire_bram/ram/WDATA_8 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_7 wire_bram/ram/WDATA_8 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_1 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_3 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_5 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_7 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_0 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_2 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_4 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_6 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_1 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_3 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_5 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_7 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_0 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_2 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_4 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_6 input0_7 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_0 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_2 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_4 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_6 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_1 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_3 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_5 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_7 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_0 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_2 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_4 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_6 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_1 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_3 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_5 wire_bram/ram/WDATA_14 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_7 wire_bram/ram/WDATA_14 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_1 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_3 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_5 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_7 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_0 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_2 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_4 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_6 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_1 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_3 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_5 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_7 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_0 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_2 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_4 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_6 input0_1 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_1 wire_bram/ram/WDATA_13 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_3 wire_bram/ram/WDATA_13 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_5 wire_bram/ram/WDATA_13 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_7 wire_bram/ram/WDATA_13 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_0 wire_bram/ram/WDATA_13 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_2 wire_bram/ram/WDATA_13 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_4 wire_bram/ram/WDATA_13 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_6 wire_bram/ram/WDATA_13 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_1 wire_bram/ram/WDATA_13 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_3 wire_bram/ram/WDATA_13 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_5 wire_bram/ram/WDATA_13 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_7 wire_bram/ram/WDATA_13 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_0 wire_bram/ram/WDATA_13 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_2 wire_bram/ram/WDATA_13 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_4 wire_bram/ram/WDATA_13 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_6 wire_bram/ram/WDATA_13 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_0 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_2 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_4 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_6 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_1 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_3 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_5 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_7 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_0 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_2 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_4 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_6 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_1 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_3 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_5 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_7 input0_2 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_0 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_2 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_4 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_6 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_1 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_3 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_5 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_7 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_0 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_2 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_4 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_6 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_1 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_3 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_5 wire_bram/ram/WDATA_12 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_7 wire_bram/ram/WDATA_12 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_1 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_3 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_5 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_7 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_0 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_2 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_4 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_6 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_1 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_3 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_5 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_7 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_0 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_2 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_4 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_6 input0_3 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_1 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_3 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_5 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_7 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_0 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_2 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_4 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_6 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_1 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_3 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_5 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_7 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_0 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_2 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_4 wire_bram/ram/WDATA_11 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_6 wire_bram/ram/WDATA_11 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_0 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_2 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_4 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_6 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_1 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_3 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_5 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_7 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_0 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_2 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_4 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_6 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_1 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_3 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_5 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_7 input0_4 -(3 0) routing sp12_h_r_0 sp12_v_b_0 -(3 0) routing sp12_v_t_23 sp12_v_b_0 -(3 1) routing sp12_h_l_23 sp12_v_b_0 -(3 1) routing sp12_h_r_0 sp12_v_b_0 -(3 10) routing sp12_h_r_1 sp12_h_l_22 -(3 10) routing sp12_v_t_22 sp12_h_l_22 -(3 11) routing sp12_h_r_1 sp12_h_l_22 -(3 11) routing sp12_v_b_1 sp12_h_l_22 -(3 12) routing sp12_v_b_1 sp12_h_r_1 -(3 12) routing sp12_v_t_22 sp12_h_r_1 -(3 13) routing sp12_h_l_22 sp12_h_r_1 -(3 13) routing sp12_v_b_1 sp12_h_r_1 -(3 14) routing sp12_h_r_1 sp12_v_t_22 -(3 14) routing sp12_v_b_1 sp12_v_t_22 -(3 15) routing sp12_h_l_22 sp12_v_t_22 -(3 15) routing sp12_h_r_1 sp12_v_t_22 -(3 2) routing sp12_h_r_0 sp12_h_l_23 -(3 2) routing sp12_v_t_23 sp12_h_l_23 -(3 3) routing sp12_h_r_0 sp12_h_l_23 -(3 3) routing sp12_v_b_0 sp12_h_l_23 -(3 4) routing sp12_v_b_0 sp12_h_r_0 -(3 4) routing sp12_v_t_23 sp12_h_r_0 -(3 5) routing sp12_h_l_23 sp12_h_r_0 -(3 5) routing sp12_v_b_0 sp12_h_r_0 -(3 6) routing sp12_h_r_0 sp12_v_t_23 -(3 6) routing sp12_v_b_0 sp12_v_t_23 -(3 7) routing sp12_h_l_23 sp12_v_t_23 -(3 7) routing sp12_h_r_0 sp12_v_t_23 -(3 8) routing sp12_h_r_1 sp12_v_b_1 -(3 8) routing sp12_v_t_22 sp12_v_b_1 -(3 9) routing sp12_h_l_22 sp12_v_b_1 -(3 9) routing sp12_h_r_1 sp12_v_b_1 -(30 0) routing lc_trk_g0_5 wire_bram/ram/WDATA_15 -(30 0) routing lc_trk_g0_7 wire_bram/ram/WDATA_15 -(30 0) routing lc_trk_g1_4 wire_bram/ram/WDATA_15 -(30 0) routing lc_trk_g1_6 wire_bram/ram/WDATA_15 -(30 0) routing lc_trk_g2_5 wire_bram/ram/WDATA_15 -(30 0) routing lc_trk_g2_7 wire_bram/ram/WDATA_15 -(30 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_15 -(30 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_15 -(30 1) routing lc_trk_g0_3 wire_bram/ram/WDATA_15 -(30 1) routing lc_trk_g0_7 wire_bram/ram/WDATA_15 -(30 1) routing lc_trk_g1_2 wire_bram/ram/WDATA_15 -(30 1) routing lc_trk_g1_6 wire_bram/ram/WDATA_15 -(30 1) routing lc_trk_g2_3 wire_bram/ram/WDATA_15 -(30 1) routing lc_trk_g2_7 wire_bram/ram/WDATA_15 -(30 1) routing lc_trk_g3_2 wire_bram/ram/WDATA_15 -(30 1) routing lc_trk_g3_6 wire_bram/ram/WDATA_15 -(30 10) routing lc_trk_g0_4 wire_bram/ram/WDATA_10 -(30 10) routing lc_trk_g0_6 wire_bram/ram/WDATA_10 -(30 10) routing lc_trk_g1_5 wire_bram/ram/WDATA_10 -(30 10) routing lc_trk_g1_7 wire_bram/ram/WDATA_10 -(30 10) routing lc_trk_g2_4 wire_bram/ram/WDATA_10 -(30 10) routing lc_trk_g2_6 wire_bram/ram/WDATA_10 -(30 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_10 -(30 10) routing lc_trk_g3_7 wire_bram/ram/WDATA_10 -(30 11) routing lc_trk_g0_2 wire_bram/ram/WDATA_10 -(30 11) routing lc_trk_g0_6 wire_bram/ram/WDATA_10 -(30 11) routing lc_trk_g1_3 wire_bram/ram/WDATA_10 -(30 11) routing lc_trk_g1_7 wire_bram/ram/WDATA_10 -(30 11) routing lc_trk_g2_2 wire_bram/ram/WDATA_10 -(30 11) routing lc_trk_g2_6 wire_bram/ram/WDATA_10 -(30 11) routing lc_trk_g3_3 wire_bram/ram/WDATA_10 -(30 11) routing lc_trk_g3_7 wire_bram/ram/WDATA_10 -(30 12) routing lc_trk_g0_5 wire_bram/ram/WDATA_9 -(30 12) routing lc_trk_g0_7 wire_bram/ram/WDATA_9 -(30 12) routing lc_trk_g1_4 wire_bram/ram/WDATA_9 -(30 12) routing lc_trk_g1_6 wire_bram/ram/WDATA_9 -(30 12) routing lc_trk_g2_5 wire_bram/ram/WDATA_9 -(30 12) routing lc_trk_g2_7 wire_bram/ram/WDATA_9 -(30 12) routing lc_trk_g3_4 wire_bram/ram/WDATA_9 -(30 12) routing lc_trk_g3_6 wire_bram/ram/WDATA_9 -(30 13) routing lc_trk_g0_3 wire_bram/ram/WDATA_9 -(30 13) routing lc_trk_g0_7 wire_bram/ram/WDATA_9 -(30 13) routing lc_trk_g1_2 wire_bram/ram/WDATA_9 -(30 13) routing lc_trk_g1_6 wire_bram/ram/WDATA_9 -(30 13) routing lc_trk_g2_3 wire_bram/ram/WDATA_9 -(30 13) routing lc_trk_g2_7 wire_bram/ram/WDATA_9 -(30 13) routing lc_trk_g3_2 wire_bram/ram/WDATA_9 -(30 13) routing lc_trk_g3_6 wire_bram/ram/WDATA_9 -(30 14) routing lc_trk_g0_4 wire_bram/ram/WDATA_8 -(30 14) routing lc_trk_g0_6 wire_bram/ram/WDATA_8 -(30 14) routing lc_trk_g1_5 wire_bram/ram/WDATA_8 -(30 14) routing lc_trk_g1_7 wire_bram/ram/WDATA_8 -(30 14) routing lc_trk_g2_4 wire_bram/ram/WDATA_8 -(30 14) routing lc_trk_g2_6 wire_bram/ram/WDATA_8 -(30 14) routing lc_trk_g3_5 wire_bram/ram/WDATA_8 -(30 14) routing lc_trk_g3_7 wire_bram/ram/WDATA_8 -(30 15) routing lc_trk_g0_2 wire_bram/ram/WDATA_8 -(30 15) routing lc_trk_g0_6 wire_bram/ram/WDATA_8 -(30 15) routing lc_trk_g1_3 wire_bram/ram/WDATA_8 -(30 15) routing lc_trk_g1_7 wire_bram/ram/WDATA_8 -(30 15) routing lc_trk_g2_2 wire_bram/ram/WDATA_8 -(30 15) routing lc_trk_g2_6 wire_bram/ram/WDATA_8 -(30 15) routing lc_trk_g3_3 wire_bram/ram/WDATA_8 -(30 15) routing lc_trk_g3_7 wire_bram/ram/WDATA_8 -(30 2) routing lc_trk_g0_4 wire_bram/ram/WDATA_14 -(30 2) routing lc_trk_g0_6 wire_bram/ram/WDATA_14 -(30 2) routing lc_trk_g1_5 wire_bram/ram/WDATA_14 -(30 2) routing lc_trk_g1_7 wire_bram/ram/WDATA_14 -(30 2) routing lc_trk_g2_4 wire_bram/ram/WDATA_14 -(30 2) routing lc_trk_g2_6 wire_bram/ram/WDATA_14 -(30 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_14 -(30 2) routing lc_trk_g3_7 wire_bram/ram/WDATA_14 -(30 3) routing lc_trk_g0_2 wire_bram/ram/WDATA_14 -(30 3) routing lc_trk_g0_6 wire_bram/ram/WDATA_14 -(30 3) routing lc_trk_g1_3 wire_bram/ram/WDATA_14 -(30 3) routing lc_trk_g1_7 wire_bram/ram/WDATA_14 -(30 3) routing lc_trk_g2_2 wire_bram/ram/WDATA_14 -(30 3) routing lc_trk_g2_6 wire_bram/ram/WDATA_14 -(30 3) routing lc_trk_g3_3 wire_bram/ram/WDATA_14 -(30 3) routing lc_trk_g3_7 wire_bram/ram/WDATA_14 -(30 4) routing lc_trk_g0_5 wire_bram/ram/WDATA_13 -(30 4) routing lc_trk_g0_7 wire_bram/ram/WDATA_13 -(30 4) routing lc_trk_g1_4 wire_bram/ram/WDATA_13 -(30 4) routing lc_trk_g1_6 wire_bram/ram/WDATA_13 -(30 4) routing lc_trk_g2_5 wire_bram/ram/WDATA_13 -(30 4) routing lc_trk_g2_7 wire_bram/ram/WDATA_13 -(30 4) routing lc_trk_g3_4 wire_bram/ram/WDATA_13 -(30 4) routing lc_trk_g3_6 wire_bram/ram/WDATA_13 -(30 5) routing lc_trk_g0_3 wire_bram/ram/WDATA_13 -(30 5) routing lc_trk_g0_7 wire_bram/ram/WDATA_13 -(30 5) routing lc_trk_g1_2 wire_bram/ram/WDATA_13 -(30 5) routing lc_trk_g1_6 wire_bram/ram/WDATA_13 -(30 5) routing lc_trk_g2_3 wire_bram/ram/WDATA_13 -(30 5) routing lc_trk_g2_7 wire_bram/ram/WDATA_13 -(30 5) routing lc_trk_g3_2 wire_bram/ram/WDATA_13 -(30 5) routing lc_trk_g3_6 wire_bram/ram/WDATA_13 -(30 6) routing lc_trk_g0_4 wire_bram/ram/WDATA_12 -(30 6) routing lc_trk_g0_6 wire_bram/ram/WDATA_12 -(30 6) routing lc_trk_g1_5 wire_bram/ram/WDATA_12 -(30 6) routing lc_trk_g1_7 wire_bram/ram/WDATA_12 -(30 6) routing lc_trk_g2_4 wire_bram/ram/WDATA_12 -(30 6) routing lc_trk_g2_6 wire_bram/ram/WDATA_12 -(30 6) routing lc_trk_g3_5 wire_bram/ram/WDATA_12 -(30 6) routing lc_trk_g3_7 wire_bram/ram/WDATA_12 -(30 7) routing lc_trk_g0_2 wire_bram/ram/WDATA_12 -(30 7) routing lc_trk_g0_6 wire_bram/ram/WDATA_12 -(30 7) routing lc_trk_g1_3 wire_bram/ram/WDATA_12 -(30 7) routing lc_trk_g1_7 wire_bram/ram/WDATA_12 -(30 7) routing lc_trk_g2_2 wire_bram/ram/WDATA_12 -(30 7) routing lc_trk_g2_6 wire_bram/ram/WDATA_12 -(30 7) routing lc_trk_g3_3 wire_bram/ram/WDATA_12 -(30 7) routing lc_trk_g3_7 wire_bram/ram/WDATA_12 -(30 8) routing lc_trk_g0_5 wire_bram/ram/WDATA_11 -(30 8) routing lc_trk_g0_7 wire_bram/ram/WDATA_11 -(30 8) routing lc_trk_g1_4 wire_bram/ram/WDATA_11 -(30 8) routing lc_trk_g1_6 wire_bram/ram/WDATA_11 -(30 8) routing lc_trk_g2_5 wire_bram/ram/WDATA_11 -(30 8) routing lc_trk_g2_7 wire_bram/ram/WDATA_11 -(30 8) routing lc_trk_g3_4 wire_bram/ram/WDATA_11 -(30 8) routing lc_trk_g3_6 wire_bram/ram/WDATA_11 -(30 9) routing lc_trk_g0_3 wire_bram/ram/WDATA_11 -(30 9) routing lc_trk_g0_7 wire_bram/ram/WDATA_11 -(30 9) routing lc_trk_g1_2 wire_bram/ram/WDATA_11 -(30 9) routing lc_trk_g1_6 wire_bram/ram/WDATA_11 -(30 9) routing lc_trk_g2_3 wire_bram/ram/WDATA_11 -(30 9) routing lc_trk_g2_7 wire_bram/ram/WDATA_11 -(30 9) routing lc_trk_g3_2 wire_bram/ram/WDATA_11 -(30 9) routing lc_trk_g3_6 wire_bram/ram/WDATA_11 -(31 0) routing lc_trk_g0_5 wire_bram/ram/MASK_15 -(31 0) routing lc_trk_g0_7 wire_bram/ram/MASK_15 -(31 0) routing lc_trk_g1_4 wire_bram/ram/MASK_15 -(31 0) routing lc_trk_g1_6 wire_bram/ram/MASK_15 -(31 0) routing lc_trk_g2_5 wire_bram/ram/MASK_15 -(31 0) routing lc_trk_g2_7 wire_bram/ram/MASK_15 -(31 0) routing lc_trk_g3_4 wire_bram/ram/MASK_15 -(31 0) routing lc_trk_g3_6 wire_bram/ram/MASK_15 -(31 1) routing lc_trk_g0_3 wire_bram/ram/MASK_15 -(31 1) routing lc_trk_g0_7 wire_bram/ram/MASK_15 -(31 1) routing lc_trk_g1_2 wire_bram/ram/MASK_15 -(31 1) routing lc_trk_g1_6 wire_bram/ram/MASK_15 -(31 1) routing lc_trk_g2_3 wire_bram/ram/MASK_15 -(31 1) routing lc_trk_g2_7 wire_bram/ram/MASK_15 -(31 1) routing lc_trk_g3_2 wire_bram/ram/MASK_15 -(31 1) routing lc_trk_g3_6 wire_bram/ram/MASK_15 -(31 10) routing lc_trk_g0_4 wire_bram/ram/MASK_10 -(31 10) routing lc_trk_g0_6 wire_bram/ram/MASK_10 -(31 10) routing lc_trk_g1_5 wire_bram/ram/MASK_10 -(31 10) routing lc_trk_g1_7 wire_bram/ram/MASK_10 -(31 10) routing lc_trk_g2_4 wire_bram/ram/MASK_10 -(31 10) routing lc_trk_g2_6 wire_bram/ram/MASK_10 -(31 10) routing lc_trk_g3_5 wire_bram/ram/MASK_10 -(31 10) routing lc_trk_g3_7 wire_bram/ram/MASK_10 -(31 11) routing lc_trk_g0_2 wire_bram/ram/MASK_10 -(31 11) routing lc_trk_g0_6 wire_bram/ram/MASK_10 -(31 11) routing lc_trk_g1_3 wire_bram/ram/MASK_10 -(31 11) routing lc_trk_g1_7 wire_bram/ram/MASK_10 -(31 11) routing lc_trk_g2_2 wire_bram/ram/MASK_10 -(31 11) routing lc_trk_g2_6 wire_bram/ram/MASK_10 -(31 11) routing lc_trk_g3_3 wire_bram/ram/MASK_10 -(31 11) routing lc_trk_g3_7 wire_bram/ram/MASK_10 -(31 12) routing lc_trk_g0_5 wire_bram/ram/MASK_9 -(31 12) routing lc_trk_g0_7 wire_bram/ram/MASK_9 -(31 12) routing lc_trk_g1_4 wire_bram/ram/MASK_9 -(31 12) routing lc_trk_g1_6 wire_bram/ram/MASK_9 -(31 12) routing lc_trk_g2_5 wire_bram/ram/MASK_9 -(31 12) routing lc_trk_g2_7 wire_bram/ram/MASK_9 -(31 12) routing lc_trk_g3_4 wire_bram/ram/MASK_9 -(31 12) routing lc_trk_g3_6 wire_bram/ram/MASK_9 -(31 13) routing lc_trk_g0_3 wire_bram/ram/MASK_9 -(31 13) routing lc_trk_g0_7 wire_bram/ram/MASK_9 -(31 13) routing lc_trk_g1_2 wire_bram/ram/MASK_9 -(31 13) routing lc_trk_g1_6 wire_bram/ram/MASK_9 -(31 13) routing lc_trk_g2_3 wire_bram/ram/MASK_9 -(31 13) routing lc_trk_g2_7 wire_bram/ram/MASK_9 -(31 13) routing lc_trk_g3_2 wire_bram/ram/MASK_9 -(31 13) routing lc_trk_g3_6 wire_bram/ram/MASK_9 -(31 14) routing lc_trk_g0_4 wire_bram/ram/MASK_8 -(31 14) routing lc_trk_g0_6 wire_bram/ram/MASK_8 -(31 14) routing lc_trk_g1_5 wire_bram/ram/MASK_8 -(31 14) routing lc_trk_g1_7 wire_bram/ram/MASK_8 -(31 14) routing lc_trk_g2_4 wire_bram/ram/MASK_8 -(31 14) routing lc_trk_g2_6 wire_bram/ram/MASK_8 -(31 14) routing lc_trk_g3_5 wire_bram/ram/MASK_8 -(31 14) routing lc_trk_g3_7 wire_bram/ram/MASK_8 -(31 15) routing lc_trk_g0_2 wire_bram/ram/MASK_8 -(31 15) routing lc_trk_g0_6 wire_bram/ram/MASK_8 -(31 15) routing lc_trk_g1_3 wire_bram/ram/MASK_8 -(31 15) routing lc_trk_g1_7 wire_bram/ram/MASK_8 -(31 15) routing lc_trk_g2_2 wire_bram/ram/MASK_8 -(31 15) routing lc_trk_g2_6 wire_bram/ram/MASK_8 -(31 15) routing lc_trk_g3_3 wire_bram/ram/MASK_8 -(31 15) routing lc_trk_g3_7 wire_bram/ram/MASK_8 -(31 2) routing lc_trk_g0_4 wire_bram/ram/MASK_14 -(31 2) routing lc_trk_g0_6 wire_bram/ram/MASK_14 -(31 2) routing lc_trk_g1_5 wire_bram/ram/MASK_14 -(31 2) routing lc_trk_g1_7 wire_bram/ram/MASK_14 -(31 2) routing lc_trk_g2_4 wire_bram/ram/MASK_14 -(31 2) routing lc_trk_g2_6 wire_bram/ram/MASK_14 -(31 2) routing lc_trk_g3_5 wire_bram/ram/MASK_14 -(31 2) routing lc_trk_g3_7 wire_bram/ram/MASK_14 -(31 3) routing lc_trk_g0_2 wire_bram/ram/MASK_14 -(31 3) routing lc_trk_g0_6 wire_bram/ram/MASK_14 -(31 3) routing lc_trk_g1_3 wire_bram/ram/MASK_14 -(31 3) routing lc_trk_g1_7 wire_bram/ram/MASK_14 -(31 3) routing lc_trk_g2_2 wire_bram/ram/MASK_14 -(31 3) routing lc_trk_g2_6 wire_bram/ram/MASK_14 -(31 3) routing lc_trk_g3_3 wire_bram/ram/MASK_14 -(31 3) routing lc_trk_g3_7 wire_bram/ram/MASK_14 -(31 4) routing lc_trk_g0_5 wire_bram/ram/MASK_13 -(31 4) routing lc_trk_g0_7 wire_bram/ram/MASK_13 -(31 4) routing lc_trk_g1_4 wire_bram/ram/MASK_13 -(31 4) routing lc_trk_g1_6 wire_bram/ram/MASK_13 -(31 4) routing lc_trk_g2_5 wire_bram/ram/MASK_13 -(31 4) routing lc_trk_g2_7 wire_bram/ram/MASK_13 -(31 4) routing lc_trk_g3_4 wire_bram/ram/MASK_13 -(31 4) routing lc_trk_g3_6 wire_bram/ram/MASK_13 -(31 5) routing lc_trk_g0_3 wire_bram/ram/MASK_13 -(31 5) routing lc_trk_g0_7 wire_bram/ram/MASK_13 -(31 5) routing lc_trk_g1_2 wire_bram/ram/MASK_13 -(31 5) routing lc_trk_g1_6 wire_bram/ram/MASK_13 -(31 5) routing lc_trk_g2_3 wire_bram/ram/MASK_13 -(31 5) routing lc_trk_g2_7 wire_bram/ram/MASK_13 -(31 5) routing lc_trk_g3_2 wire_bram/ram/MASK_13 -(31 5) routing lc_trk_g3_6 wire_bram/ram/MASK_13 -(31 6) routing lc_trk_g0_4 wire_bram/ram/MASK_12 -(31 6) routing lc_trk_g0_6 wire_bram/ram/MASK_12 -(31 6) routing lc_trk_g1_5 wire_bram/ram/MASK_12 -(31 6) routing lc_trk_g1_7 wire_bram/ram/MASK_12 -(31 6) routing lc_trk_g2_4 wire_bram/ram/MASK_12 -(31 6) routing lc_trk_g2_6 wire_bram/ram/MASK_12 -(31 6) routing lc_trk_g3_5 wire_bram/ram/MASK_12 -(31 6) routing lc_trk_g3_7 wire_bram/ram/MASK_12 -(31 7) routing lc_trk_g0_2 wire_bram/ram/MASK_12 -(31 7) routing lc_trk_g0_6 wire_bram/ram/MASK_12 -(31 7) routing lc_trk_g1_3 wire_bram/ram/MASK_12 -(31 7) routing lc_trk_g1_7 wire_bram/ram/MASK_12 -(31 7) routing lc_trk_g2_2 wire_bram/ram/MASK_12 -(31 7) routing lc_trk_g2_6 wire_bram/ram/MASK_12 -(31 7) routing lc_trk_g3_3 wire_bram/ram/MASK_12 -(31 7) routing lc_trk_g3_7 wire_bram/ram/MASK_12 -(31 8) routing lc_trk_g0_5 wire_bram/ram/MASK_11 -(31 8) routing lc_trk_g0_7 wire_bram/ram/MASK_11 -(31 8) routing lc_trk_g1_4 wire_bram/ram/MASK_11 -(31 8) routing lc_trk_g1_6 wire_bram/ram/MASK_11 -(31 8) routing lc_trk_g2_5 wire_bram/ram/MASK_11 -(31 8) routing lc_trk_g2_7 wire_bram/ram/MASK_11 -(31 8) routing lc_trk_g3_4 wire_bram/ram/MASK_11 -(31 8) routing lc_trk_g3_6 wire_bram/ram/MASK_11 -(31 9) routing lc_trk_g0_3 wire_bram/ram/MASK_11 -(31 9) routing lc_trk_g0_7 wire_bram/ram/MASK_11 -(31 9) routing lc_trk_g1_2 wire_bram/ram/MASK_11 -(31 9) routing lc_trk_g1_6 wire_bram/ram/MASK_11 -(31 9) routing lc_trk_g2_3 wire_bram/ram/MASK_11 -(31 9) routing lc_trk_g2_7 wire_bram/ram/MASK_11 -(31 9) routing lc_trk_g3_2 wire_bram/ram/MASK_11 -(31 9) routing lc_trk_g3_6 wire_bram/ram/MASK_11 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_3 wire_bram/ram/MASK_15 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_5 wire_bram/ram/MASK_15 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_7 wire_bram/ram/MASK_15 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_0 wire_bram/ram/MASK_15 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_2 wire_bram/ram/MASK_15 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_4 wire_bram/ram/MASK_15 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_6 wire_bram/ram/MASK_15 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_1 wire_bram/ram/MASK_15 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_3 wire_bram/ram/MASK_15 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_5 wire_bram/ram/MASK_15 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_7 wire_bram/ram/MASK_15 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_0 wire_bram/ram/MASK_15 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_2 wire_bram/ram/MASK_15 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_4 wire_bram/ram/MASK_15 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_6 wire_bram/ram/MASK_15 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_2 wire_bram/ram/MASK_10 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_4 wire_bram/ram/MASK_10 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_6 wire_bram/ram/MASK_10 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_1 wire_bram/ram/MASK_10 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_3 wire_bram/ram/MASK_10 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_5 wire_bram/ram/MASK_10 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_7 wire_bram/ram/MASK_10 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_0 wire_bram/ram/MASK_10 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_2 wire_bram/ram/MASK_10 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_4 wire_bram/ram/MASK_10 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_6 wire_bram/ram/MASK_10 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_1 wire_bram/ram/MASK_10 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_3 wire_bram/ram/MASK_10 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_5 wire_bram/ram/MASK_10 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_7 wire_bram/ram/MASK_10 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_1 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_3 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_5 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_7 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_0 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_2 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_4 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_6 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_1 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_3 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_5 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_7 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_0 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_2 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_4 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_6 input2_5 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_3 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_5 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_7 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_0 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_2 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_4 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_6 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_1 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_3 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_5 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_7 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_0 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_2 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_4 wire_bram/ram/MASK_9 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_6 wire_bram/ram/MASK_9 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_0 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_2 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_4 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_6 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_1 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_3 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_5 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_7 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_0 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_2 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_4 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_6 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_1 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_3 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_5 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_7 input2_6 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_2 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_4 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_6 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_1 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_3 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_5 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_7 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_0 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_2 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_4 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_6 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_1 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_3 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_5 wire_bram/ram/MASK_8 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_7 wire_bram/ram/MASK_8 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_1 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_3 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_5 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_7 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_0 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_2 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_4 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_6 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_1 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_3 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_5 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_7 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_0 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_2 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_4 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_6 input2_7 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_2 wire_bram/ram/MASK_14 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_4 wire_bram/ram/MASK_14 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_6 wire_bram/ram/MASK_14 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_1 wire_bram/ram/MASK_14 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_3 wire_bram/ram/MASK_14 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_5 wire_bram/ram/MASK_14 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_7 wire_bram/ram/MASK_14 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_0 wire_bram/ram/MASK_14 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_2 wire_bram/ram/MASK_14 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_4 wire_bram/ram/MASK_14 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_6 wire_bram/ram/MASK_14 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_1 wire_bram/ram/MASK_14 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_3 wire_bram/ram/MASK_14 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_5 wire_bram/ram/MASK_14 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_7 wire_bram/ram/MASK_14 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_3 wire_bram/ram/MASK_13 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_5 wire_bram/ram/MASK_13 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_7 wire_bram/ram/MASK_13 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_0 wire_bram/ram/MASK_13 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_2 wire_bram/ram/MASK_13 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_4 wire_bram/ram/MASK_13 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_6 wire_bram/ram/MASK_13 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_1 wire_bram/ram/MASK_13 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_3 wire_bram/ram/MASK_13 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_5 wire_bram/ram/MASK_13 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_7 wire_bram/ram/MASK_13 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_0 wire_bram/ram/MASK_13 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_2 wire_bram/ram/MASK_13 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_4 wire_bram/ram/MASK_13 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_6 wire_bram/ram/MASK_13 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_2 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_4 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_6 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_1 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_3 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_5 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_7 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_0 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_2 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_4 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_6 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_1 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_3 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_5 wire_bram/ram/MASK_12 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_7 wire_bram/ram/MASK_12 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_3 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_5 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_7 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_0 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_2 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_4 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_6 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_1 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_3 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_5 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_7 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_0 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_2 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_4 wire_bram/ram/MASK_11 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_6 wire_bram/ram/MASK_11 -(33 0) routing lc_trk_g2_1 wire_bram/ram/MASK_15 -(33 0) routing lc_trk_g2_3 wire_bram/ram/MASK_15 -(33 0) routing lc_trk_g2_5 wire_bram/ram/MASK_15 -(33 0) routing lc_trk_g2_7 wire_bram/ram/MASK_15 -(33 0) routing lc_trk_g3_0 wire_bram/ram/MASK_15 -(33 0) routing lc_trk_g3_2 wire_bram/ram/MASK_15 -(33 0) routing lc_trk_g3_4 wire_bram/ram/MASK_15 -(33 0) routing lc_trk_g3_6 wire_bram/ram/MASK_15 -(33 10) routing lc_trk_g2_0 wire_bram/ram/MASK_10 -(33 10) routing lc_trk_g2_2 wire_bram/ram/MASK_10 -(33 10) routing lc_trk_g2_4 wire_bram/ram/MASK_10 -(33 10) routing lc_trk_g2_6 wire_bram/ram/MASK_10 -(33 10) routing lc_trk_g3_1 wire_bram/ram/MASK_10 -(33 10) routing lc_trk_g3_3 wire_bram/ram/MASK_10 -(33 10) routing lc_trk_g3_5 wire_bram/ram/MASK_10 -(33 10) routing lc_trk_g3_7 wire_bram/ram/MASK_10 -(33 11) routing lc_trk_g2_1 input2_5 -(33 11) routing lc_trk_g2_3 input2_5 -(33 11) routing lc_trk_g2_5 input2_5 -(33 11) routing lc_trk_g2_7 input2_5 -(33 11) routing lc_trk_g3_0 input2_5 -(33 11) routing lc_trk_g3_2 input2_5 -(33 11) routing lc_trk_g3_4 input2_5 -(33 11) routing lc_trk_g3_6 input2_5 -(33 12) routing lc_trk_g2_1 wire_bram/ram/MASK_9 -(33 12) routing lc_trk_g2_3 wire_bram/ram/MASK_9 -(33 12) routing lc_trk_g2_5 wire_bram/ram/MASK_9 -(33 12) routing lc_trk_g2_7 wire_bram/ram/MASK_9 -(33 12) routing lc_trk_g3_0 wire_bram/ram/MASK_9 -(33 12) routing lc_trk_g3_2 wire_bram/ram/MASK_9 -(33 12) routing lc_trk_g3_4 wire_bram/ram/MASK_9 -(33 12) routing lc_trk_g3_6 wire_bram/ram/MASK_9 -(33 13) routing lc_trk_g2_0 input2_6 -(33 13) routing lc_trk_g2_2 input2_6 -(33 13) routing lc_trk_g2_4 input2_6 -(33 13) routing lc_trk_g2_6 input2_6 -(33 13) routing lc_trk_g3_1 input2_6 -(33 13) routing lc_trk_g3_3 input2_6 -(33 13) routing lc_trk_g3_5 input2_6 -(33 13) routing lc_trk_g3_7 input2_6 -(33 14) routing lc_trk_g2_0 wire_bram/ram/MASK_8 -(33 14) routing lc_trk_g2_2 wire_bram/ram/MASK_8 -(33 14) routing lc_trk_g2_4 wire_bram/ram/MASK_8 -(33 14) routing lc_trk_g2_6 wire_bram/ram/MASK_8 -(33 14) routing lc_trk_g3_1 wire_bram/ram/MASK_8 -(33 14) routing lc_trk_g3_3 wire_bram/ram/MASK_8 -(33 14) routing lc_trk_g3_5 wire_bram/ram/MASK_8 -(33 14) routing lc_trk_g3_7 wire_bram/ram/MASK_8 -(33 15) routing lc_trk_g2_1 input2_7 -(33 15) routing lc_trk_g2_3 input2_7 -(33 15) routing lc_trk_g2_5 input2_7 -(33 15) routing lc_trk_g2_7 input2_7 -(33 15) routing lc_trk_g3_0 input2_7 -(33 15) routing lc_trk_g3_2 input2_7 -(33 15) routing lc_trk_g3_4 input2_7 -(33 15) routing lc_trk_g3_6 input2_7 -(33 2) routing lc_trk_g2_0 wire_bram/ram/MASK_14 -(33 2) routing lc_trk_g2_2 wire_bram/ram/MASK_14 -(33 2) routing lc_trk_g2_4 wire_bram/ram/MASK_14 -(33 2) routing lc_trk_g2_6 wire_bram/ram/MASK_14 -(33 2) routing lc_trk_g3_1 wire_bram/ram/MASK_14 -(33 2) routing lc_trk_g3_3 wire_bram/ram/MASK_14 -(33 2) routing lc_trk_g3_5 wire_bram/ram/MASK_14 -(33 2) routing lc_trk_g3_7 wire_bram/ram/MASK_14 -(33 4) routing lc_trk_g2_1 wire_bram/ram/MASK_13 -(33 4) routing lc_trk_g2_3 wire_bram/ram/MASK_13 -(33 4) routing lc_trk_g2_5 wire_bram/ram/MASK_13 -(33 4) routing lc_trk_g2_7 wire_bram/ram/MASK_13 -(33 4) routing lc_trk_g3_0 wire_bram/ram/MASK_13 -(33 4) routing lc_trk_g3_2 wire_bram/ram/MASK_13 -(33 4) routing lc_trk_g3_4 wire_bram/ram/MASK_13 -(33 4) routing lc_trk_g3_6 wire_bram/ram/MASK_13 -(33 6) routing lc_trk_g2_0 wire_bram/ram/MASK_12 -(33 6) routing lc_trk_g2_2 wire_bram/ram/MASK_12 -(33 6) routing lc_trk_g2_4 wire_bram/ram/MASK_12 -(33 6) routing lc_trk_g2_6 wire_bram/ram/MASK_12 -(33 6) routing lc_trk_g3_1 wire_bram/ram/MASK_12 -(33 6) routing lc_trk_g3_3 wire_bram/ram/MASK_12 -(33 6) routing lc_trk_g3_5 wire_bram/ram/MASK_12 -(33 6) routing lc_trk_g3_7 wire_bram/ram/MASK_12 -(33 8) routing lc_trk_g2_1 wire_bram/ram/MASK_11 -(33 8) routing lc_trk_g2_3 wire_bram/ram/MASK_11 -(33 8) routing lc_trk_g2_5 wire_bram/ram/MASK_11 -(33 8) routing lc_trk_g2_7 wire_bram/ram/MASK_11 -(33 8) routing lc_trk_g3_0 wire_bram/ram/MASK_11 -(33 8) routing lc_trk_g3_2 wire_bram/ram/MASK_11 -(33 8) routing lc_trk_g3_4 wire_bram/ram/MASK_11 -(33 8) routing lc_trk_g3_6 wire_bram/ram/MASK_11 -(34 0) routing lc_trk_g1_0 wire_bram/ram/MASK_15 -(34 0) routing lc_trk_g1_2 wire_bram/ram/MASK_15 -(34 0) routing lc_trk_g1_4 wire_bram/ram/MASK_15 -(34 0) routing lc_trk_g1_6 wire_bram/ram/MASK_15 -(34 0) routing lc_trk_g3_0 wire_bram/ram/MASK_15 -(34 0) routing lc_trk_g3_2 wire_bram/ram/MASK_15 -(34 0) routing lc_trk_g3_4 wire_bram/ram/MASK_15 -(34 0) routing lc_trk_g3_6 wire_bram/ram/MASK_15 -(34 10) routing lc_trk_g1_1 wire_bram/ram/MASK_10 -(34 10) routing lc_trk_g1_3 wire_bram/ram/MASK_10 -(34 10) routing lc_trk_g1_5 wire_bram/ram/MASK_10 -(34 10) routing lc_trk_g1_7 wire_bram/ram/MASK_10 -(34 10) routing lc_trk_g3_1 wire_bram/ram/MASK_10 -(34 10) routing lc_trk_g3_3 wire_bram/ram/MASK_10 -(34 10) routing lc_trk_g3_5 wire_bram/ram/MASK_10 -(34 10) routing lc_trk_g3_7 wire_bram/ram/MASK_10 -(34 11) routing lc_trk_g1_0 input2_5 -(34 11) routing lc_trk_g1_2 input2_5 -(34 11) routing lc_trk_g1_4 input2_5 -(34 11) routing lc_trk_g1_6 input2_5 -(34 11) routing lc_trk_g3_0 input2_5 -(34 11) routing lc_trk_g3_2 input2_5 -(34 11) routing lc_trk_g3_4 input2_5 -(34 11) routing lc_trk_g3_6 input2_5 -(34 12) routing lc_trk_g1_0 wire_bram/ram/MASK_9 -(34 12) routing lc_trk_g1_2 wire_bram/ram/MASK_9 -(34 12) routing lc_trk_g1_4 wire_bram/ram/MASK_9 -(34 12) routing lc_trk_g1_6 wire_bram/ram/MASK_9 -(34 12) routing lc_trk_g3_0 wire_bram/ram/MASK_9 -(34 12) routing lc_trk_g3_2 wire_bram/ram/MASK_9 -(34 12) routing lc_trk_g3_4 wire_bram/ram/MASK_9 -(34 12) routing lc_trk_g3_6 wire_bram/ram/MASK_9 -(34 13) routing lc_trk_g1_1 input2_6 -(34 13) routing lc_trk_g1_3 input2_6 -(34 13) routing lc_trk_g1_5 input2_6 -(34 13) routing lc_trk_g1_7 input2_6 -(34 13) routing lc_trk_g3_1 input2_6 -(34 13) routing lc_trk_g3_3 input2_6 -(34 13) routing lc_trk_g3_5 input2_6 -(34 13) routing lc_trk_g3_7 input2_6 -(34 14) routing lc_trk_g1_1 wire_bram/ram/MASK_8 -(34 14) routing lc_trk_g1_3 wire_bram/ram/MASK_8 -(34 14) routing lc_trk_g1_5 wire_bram/ram/MASK_8 -(34 14) routing lc_trk_g1_7 wire_bram/ram/MASK_8 -(34 14) routing lc_trk_g3_1 wire_bram/ram/MASK_8 -(34 14) routing lc_trk_g3_3 wire_bram/ram/MASK_8 -(34 14) routing lc_trk_g3_5 wire_bram/ram/MASK_8 -(34 14) routing lc_trk_g3_7 wire_bram/ram/MASK_8 -(34 15) routing lc_trk_g1_0 input2_7 -(34 15) routing lc_trk_g1_2 input2_7 -(34 15) routing lc_trk_g1_4 input2_7 -(34 15) routing lc_trk_g1_6 input2_7 -(34 15) routing lc_trk_g3_0 input2_7 -(34 15) routing lc_trk_g3_2 input2_7 -(34 15) routing lc_trk_g3_4 input2_7 -(34 15) routing lc_trk_g3_6 input2_7 -(34 2) routing lc_trk_g1_1 wire_bram/ram/MASK_14 -(34 2) routing lc_trk_g1_3 wire_bram/ram/MASK_14 -(34 2) routing lc_trk_g1_5 wire_bram/ram/MASK_14 -(34 2) routing lc_trk_g1_7 wire_bram/ram/MASK_14 -(34 2) routing lc_trk_g3_1 wire_bram/ram/MASK_14 -(34 2) routing lc_trk_g3_3 wire_bram/ram/MASK_14 -(34 2) routing lc_trk_g3_5 wire_bram/ram/MASK_14 -(34 2) routing lc_trk_g3_7 wire_bram/ram/MASK_14 -(34 4) routing lc_trk_g1_0 wire_bram/ram/MASK_13 -(34 4) routing lc_trk_g1_2 wire_bram/ram/MASK_13 -(34 4) routing lc_trk_g1_4 wire_bram/ram/MASK_13 -(34 4) routing lc_trk_g1_6 wire_bram/ram/MASK_13 -(34 4) routing lc_trk_g3_0 wire_bram/ram/MASK_13 -(34 4) routing lc_trk_g3_2 wire_bram/ram/MASK_13 -(34 4) routing lc_trk_g3_4 wire_bram/ram/MASK_13 -(34 4) routing lc_trk_g3_6 wire_bram/ram/MASK_13 -(34 6) routing lc_trk_g1_1 wire_bram/ram/MASK_12 -(34 6) routing lc_trk_g1_3 wire_bram/ram/MASK_12 -(34 6) routing lc_trk_g1_5 wire_bram/ram/MASK_12 -(34 6) routing lc_trk_g1_7 wire_bram/ram/MASK_12 -(34 6) routing lc_trk_g3_1 wire_bram/ram/MASK_12 -(34 6) routing lc_trk_g3_3 wire_bram/ram/MASK_12 -(34 6) routing lc_trk_g3_5 wire_bram/ram/MASK_12 -(34 6) routing lc_trk_g3_7 wire_bram/ram/MASK_12 -(34 8) routing lc_trk_g1_0 wire_bram/ram/MASK_11 -(34 8) routing lc_trk_g1_2 wire_bram/ram/MASK_11 -(34 8) routing lc_trk_g1_4 wire_bram/ram/MASK_11 -(34 8) routing lc_trk_g1_6 wire_bram/ram/MASK_11 -(34 8) routing lc_trk_g3_0 wire_bram/ram/MASK_11 -(34 8) routing lc_trk_g3_2 wire_bram/ram/MASK_11 -(34 8) routing lc_trk_g3_4 wire_bram/ram/MASK_11 -(34 8) routing lc_trk_g3_6 wire_bram/ram/MASK_11 -(35 10) routing lc_trk_g0_5 input2_5 -(35 10) routing lc_trk_g0_7 input2_5 -(35 10) routing lc_trk_g1_4 input2_5 -(35 10) routing lc_trk_g1_6 input2_5 -(35 10) routing lc_trk_g2_5 input2_5 -(35 10) routing lc_trk_g2_7 input2_5 -(35 10) routing lc_trk_g3_4 input2_5 -(35 10) routing lc_trk_g3_6 input2_5 -(35 11) routing lc_trk_g0_3 input2_5 -(35 11) routing lc_trk_g0_7 input2_5 -(35 11) routing lc_trk_g1_2 input2_5 -(35 11) routing lc_trk_g1_6 input2_5 -(35 11) routing lc_trk_g2_3 input2_5 -(35 11) routing lc_trk_g2_7 input2_5 -(35 11) routing lc_trk_g3_2 input2_5 -(35 11) routing lc_trk_g3_6 input2_5 -(35 12) routing lc_trk_g0_4 input2_6 -(35 12) routing lc_trk_g0_6 input2_6 -(35 12) routing lc_trk_g1_5 input2_6 -(35 12) routing lc_trk_g1_7 input2_6 -(35 12) routing lc_trk_g2_4 input2_6 -(35 12) routing lc_trk_g2_6 input2_6 -(35 12) routing lc_trk_g3_5 input2_6 -(35 12) routing lc_trk_g3_7 input2_6 -(35 13) routing lc_trk_g0_2 input2_6 -(35 13) routing lc_trk_g0_6 input2_6 -(35 13) routing lc_trk_g1_3 input2_6 -(35 13) routing lc_trk_g1_7 input2_6 -(35 13) routing lc_trk_g2_2 input2_6 -(35 13) routing lc_trk_g2_6 input2_6 -(35 13) routing lc_trk_g3_3 input2_6 -(35 13) routing lc_trk_g3_7 input2_6 -(35 14) routing lc_trk_g0_5 input2_7 -(35 14) routing lc_trk_g0_7 input2_7 -(35 14) routing lc_trk_g1_4 input2_7 -(35 14) routing lc_trk_g1_6 input2_7 -(35 14) routing lc_trk_g2_5 input2_7 -(35 14) routing lc_trk_g2_7 input2_7 -(35 14) routing lc_trk_g3_4 input2_7 -(35 14) routing lc_trk_g3_6 input2_7 -(35 15) routing lc_trk_g0_3 input2_7 -(35 15) routing lc_trk_g0_7 input2_7 -(35 15) routing lc_trk_g1_2 input2_7 -(35 15) routing lc_trk_g1_6 input2_7 -(35 15) routing lc_trk_g2_3 input2_7 -(35 15) routing lc_trk_g2_7 input2_7 -(35 15) routing lc_trk_g3_2 input2_7 -(35 15) routing lc_trk_g3_6 input2_7 -(36 0) Enable bit of Mux _out_links/OutMux8_0 => wire_bram/ram/RDATA_15 sp4_h_r_32 -(36 1) Enable bit of Mux _out_links/OutMux6_0 => wire_bram/ram/RDATA_15 sp4_h_r_0 -(36 10) Enable bit of Mux _out_links/OutMux8_5 => wire_bram/ram/RDATA_10 sp4_h_r_42 -(36 11) Enable bit of Mux _out_links/OutMux6_5 => wire_bram/ram/RDATA_10 sp4_h_r_10 -(36 12) Enable bit of Mux _out_links/OutMux8_6 => wire_bram/ram/RDATA_9 sp4_h_r_44 -(36 13) Enable bit of Mux _out_links/OutMux6_6 => wire_bram/ram/RDATA_9 sp4_h_l_1 -(36 14) Enable bit of Mux _out_links/OutMux8_7 => wire_bram/ram/RDATA_8 sp4_h_r_46 -(36 15) Enable bit of Mux _out_links/OutMux6_7 => wire_bram/ram/RDATA_8 sp4_h_l_3 -(36 2) Enable bit of Mux _out_links/OutMux8_1 => wire_bram/ram/RDATA_14 sp4_h_r_34 -(36 3) Enable bit of Mux _out_links/OutMux6_1 => wire_bram/ram/RDATA_14 sp4_h_r_2 -(36 4) Enable bit of Mux _out_links/OutMux8_2 => wire_bram/ram/RDATA_13 sp4_h_r_36 -(36 5) Enable bit of Mux _out_links/OutMux6_2 => wire_bram/ram/RDATA_13 sp4_h_r_4 -(36 6) Enable bit of Mux _out_links/OutMux8_3 => wire_bram/ram/RDATA_12 sp4_h_l_27 -(36 7) Enable bit of Mux _out_links/OutMux6_3 => wire_bram/ram/RDATA_12 sp4_h_r_6 -(36 8) Enable bit of Mux _out_links/OutMux8_4 => wire_bram/ram/RDATA_11 sp4_h_r_40 -(36 9) Enable bit of Mux _out_links/OutMux6_4 => wire_bram/ram/RDATA_11 sp4_h_r_8 -(37 0) Enable bit of Mux _out_links/OutMux5_0 => wire_bram/ram/RDATA_15 sp12_h_r_8 -(37 1) Enable bit of Mux _out_links/OutMux7_0 => wire_bram/ram/RDATA_15 sp4_h_r_16 -(37 10) Enable bit of Mux _out_links/OutMux4_5 => wire_bram/ram/RDATA_10 sp12_h_l_1 -(37 11) Enable bit of Mux _out_links/OutMux7_5 => wire_bram/ram/RDATA_10 sp4_h_l_15 -(37 12) Enable bit of Mux _out_links/OutMux4_6 => wire_bram/ram/RDATA_9 sp12_h_l_3 -(37 13) Enable bit of Mux _out_links/OutMux7_6 => wire_bram/ram/RDATA_9 sp4_h_r_28 -(37 14) Enable bit of Mux _out_links/OutMux4_7 => wire_bram/ram/RDATA_8 sp12_h_l_5 -(37 15) Enable bit of Mux _out_links/OutMux7_7 => wire_bram/ram/RDATA_8 sp4_h_l_19 -(37 2) Enable bit of Mux _out_links/OutMux5_1 => wire_bram/ram/RDATA_14 sp12_h_l_9 -(37 3) Enable bit of Mux _out_links/OutMux7_1 => wire_bram/ram/RDATA_14 sp4_h_r_18 -(37 4) Enable bit of Mux _out_links/OutMux5_2 => wire_bram/ram/RDATA_13 sp12_h_r_12 -(37 5) Enable bit of Mux _out_links/OutMux7_2 => wire_bram/ram/RDATA_13 sp4_h_l_9 -(37 6) Enable bit of Mux _out_links/OutMux5_3 => wire_bram/ram/RDATA_12 sp12_h_r_14 -(37 7) Enable bit of Mux _out_links/OutMux7_3 => wire_bram/ram/RDATA_12 sp4_h_l_11 -(37 8) Enable bit of Mux _out_links/OutMux4_4 => wire_bram/ram/RDATA_11 sp12_h_r_0 -(37 9) Enable bit of Mux _out_links/OutMux7_4 => wire_bram/ram/RDATA_11 sp4_h_r_24 -(38 0) Enable bit of Mux _out_links/OutMux2_0 => wire_bram/ram/RDATA_15 sp4_v_b_32 -(38 1) Enable bit of Mux _out_links/OutMux0_0 => wire_bram/ram/RDATA_15 sp4_v_b_0 -(38 10) Enable bit of Mux _out_links/OutMux1_5 => wire_bram/ram/RDATA_10 sp4_v_t_15 -(38 11) Enable bit of Mux _out_links/OutMux5_5 => wire_bram/ram/RDATA_10 sp12_h_l_17 -(38 12) Enable bit of Mux _out_links/OutMux1_6 => wire_bram/ram/RDATA_9 sp4_v_b_28 -(38 13) Enable bit of Mux _out_links/OutMux5_6 => wire_bram/ram/RDATA_9 sp12_h_r_20 -(38 14) Enable bit of Mux _out_links/OutMux1_7 => wire_bram/ram/RDATA_8 sp4_v_t_19 -(38 15) Enable bit of Mux _out_links/OutMux5_7 => wire_bram/ram/RDATA_8 sp12_h_r_22 -(38 2) Enable bit of Mux _out_links/OutMux2_1 => wire_bram/ram/RDATA_14 sp4_v_b_34 -(38 3) Enable bit of Mux _out_links/OutMux0_1 => wire_bram/ram/RDATA_14 sp4_v_b_2 -(38 4) Enable bit of Mux _out_links/OutMux2_2 => wire_bram/ram/RDATA_13 sp4_v_t_25 -(38 5) Enable bit of Mux _out_links/OutMux0_2 => wire_bram/ram/RDATA_13 sp4_v_b_4 -(38 6) Enable bit of Mux _out_links/OutMux2_3 => wire_bram/ram/RDATA_12 sp4_v_t_27 -(38 7) Enable bit of Mux _out_links/OutMux0_3 => wire_bram/ram/RDATA_12 sp4_v_b_6 -(38 8) Enable bit of Mux _out_links/OutMux1_4 => wire_bram/ram/RDATA_11 sp4_v_t_13 -(38 9) Enable bit of Mux _out_links/OutMux5_4 => wire_bram/ram/RDATA_11 sp12_h_l_15 -(39 0) Enable bit of Mux _out_links/OutMux3_0 => wire_bram/ram/RDATA_15 sp12_v_b_0 -(39 1) Enable bit of Mux _out_links/OutMux1_0 => wire_bram/ram/RDATA_15 sp4_v_b_16 -(39 10) Enable bit of Mux _out_links/OutMux2_5 => wire_bram/ram/RDATA_10 sp4_v_t_31 -(39 11) Enable bit of Mux _out_links/OutMux0_5 => wire_bram/ram/RDATA_10 sp4_v_b_10 -(39 12) Enable bit of Mux _out_links/OutMux2_6 => wire_bram/ram/RDATA_9 sp4_v_b_44 -(39 13) Enable bit of Mux _out_links/OutMux0_6 => wire_bram/ram/RDATA_9 sp4_v_b_12 -(39 14) Enable bit of Mux _out_links/OutMux2_7 => wire_bram/ram/RDATA_8 sp4_v_b_46 -(39 15) Enable bit of Mux _out_links/OutMux0_7 => wire_bram/ram/RDATA_8 sp4_v_b_14 -(39 2) Enable bit of Mux _out_links/OutMux3_1 => wire_bram/ram/RDATA_14 sp12_v_t_1 -(39 3) Enable bit of Mux _out_links/OutMux1_1 => wire_bram/ram/RDATA_14 sp4_v_t_7 -(39 4) Enable bit of Mux _out_links/OutMux3_2 => wire_bram/ram/RDATA_13 sp12_v_b_4 -(39 5) Enable bit of Mux _out_links/OutMux1_2 => wire_bram/ram/RDATA_13 sp4_v_b_20 -(39 6) Enable bit of Mux _out_links/OutMux3_3 => wire_bram/ram/RDATA_12 sp12_v_t_5 -(39 7) Enable bit of Mux _out_links/OutMux1_3 => wire_bram/ram/RDATA_12 sp4_v_t_11 -(39 8) Enable bit of Mux _out_links/OutMux2_4 => wire_bram/ram/RDATA_11 sp4_v_b_40 -(39 9) Enable bit of Mux _out_links/OutMux0_4 => wire_bram/ram/RDATA_11 sp4_v_b_8 -(4 0) routing sp4_h_l_37 sp4_v_b_0 -(4 0) routing sp4_h_l_43 sp4_v_b_0 -(4 0) routing sp4_v_t_37 sp4_v_b_0 -(4 0) routing sp4_v_t_41 sp4_v_b_0 -(4 1) routing sp4_h_l_41 sp4_h_r_0 -(4 1) routing sp4_h_l_44 sp4_h_r_0 -(4 1) routing sp4_v_b_6 sp4_h_r_0 -(4 1) routing sp4_v_t_42 sp4_h_r_0 -(4 10) routing sp4_h_r_0 sp4_v_t_43 -(4 10) routing sp4_h_r_6 sp4_v_t_43 -(4 10) routing sp4_v_b_10 sp4_v_t_43 -(4 10) routing sp4_v_b_6 sp4_v_t_43 -(4 11) routing sp4_h_r_10 sp4_h_l_43 -(4 11) routing sp4_h_r_3 sp4_h_l_43 -(4 11) routing sp4_v_b_1 sp4_h_l_43 -(4 11) routing sp4_v_t_37 sp4_h_l_43 -(4 12) routing sp4_h_l_38 sp4_v_b_9 -(4 12) routing sp4_h_l_44 sp4_v_b_9 -(4 12) routing sp4_v_t_36 sp4_v_b_9 -(4 12) routing sp4_v_t_44 sp4_v_b_9 -(4 13) routing sp4_h_l_36 sp4_h_r_9 -(4 13) routing sp4_h_l_43 sp4_h_r_9 -(4 13) routing sp4_v_b_3 sp4_h_r_9 -(4 13) routing sp4_v_t_41 sp4_h_r_9 -(4 14) routing sp4_h_r_3 sp4_v_t_44 -(4 14) routing sp4_h_r_9 sp4_v_t_44 -(4 14) routing sp4_v_b_1 sp4_v_t_44 -(4 14) routing sp4_v_b_9 sp4_v_t_44 -(4 15) routing sp4_h_r_1 sp4_h_l_44 -(4 15) routing sp4_h_r_6 sp4_h_l_44 -(4 15) routing sp4_v_b_4 sp4_h_l_44 -(4 15) routing sp4_v_t_38 sp4_h_l_44 -(4 2) routing sp4_h_r_0 sp4_v_t_37 -(4 2) routing sp4_h_r_6 sp4_v_t_37 -(4 2) routing sp4_v_b_0 sp4_v_t_37 -(4 2) routing sp4_v_b_4 sp4_v_t_37 -(4 3) routing sp4_h_r_4 sp4_h_l_37 -(4 3) routing sp4_h_r_9 sp4_h_l_37 -(4 3) routing sp4_v_b_7 sp4_h_l_37 -(4 3) routing sp4_v_t_43 sp4_h_l_37 -(4 4) routing sp4_h_l_38 sp4_v_b_3 -(4 4) routing sp4_h_l_44 sp4_v_b_3 -(4 4) routing sp4_v_t_38 sp4_v_b_3 -(4 4) routing sp4_v_t_42 sp4_v_b_3 -(4 5) routing sp4_h_l_37 sp4_h_r_3 -(4 5) routing sp4_h_l_42 sp4_h_r_3 -(4 5) routing sp4_v_b_9 sp4_h_r_3 -(4 5) routing sp4_v_t_47 sp4_h_r_3 -(4 6) routing sp4_h_r_3 sp4_v_t_38 -(4 6) routing sp4_h_r_9 sp4_v_t_38 -(4 6) routing sp4_v_b_3 sp4_v_t_38 -(4 6) routing sp4_v_b_7 sp4_v_t_38 -(4 7) routing sp4_h_r_0 sp4_h_l_38 -(4 7) routing sp4_h_r_7 sp4_h_l_38 -(4 7) routing sp4_v_b_10 sp4_h_l_38 -(4 7) routing sp4_v_t_44 sp4_h_l_38 -(4 8) routing sp4_h_l_37 sp4_v_b_6 -(4 8) routing sp4_h_l_43 sp4_v_b_6 -(4 8) routing sp4_v_t_43 sp4_v_b_6 -(4 8) routing sp4_v_t_47 sp4_v_b_6 -(4 9) routing sp4_h_l_38 sp4_h_r_6 -(4 9) routing sp4_h_l_47 sp4_h_r_6 -(4 9) routing sp4_v_b_0 sp4_h_r_6 -(4 9) routing sp4_v_t_36 sp4_h_r_6 -(40 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_bram/ram/RDATA_15 sp4_r_v_b_17 -(40 1) Enable bit of Mux _out_links/OutMux4_0 => wire_bram/ram/RDATA_15 sp12_v_b_16 -(40 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_bram/ram/RDATA_10 sp4_r_v_b_27 -(40 11) Enable bit of Mux _out_links/OutMux3_5 => wire_bram/ram/RDATA_10 sp12_v_b_10 -(40 12) Enable bit of Mux _out_links/OutMuxa_6 => wire_bram/ram/RDATA_9 sp4_r_v_b_29 -(40 13) Enable bit of Mux _out_links/OutMux3_6 => wire_bram/ram/RDATA_9 sp12_v_t_11 -(40 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_bram/ram/RDATA_8 sp4_r_v_b_31 -(40 15) Enable bit of Mux _out_links/OutMux3_7 => wire_bram/ram/RDATA_8 sp12_v_b_14 -(40 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_bram/ram/RDATA_14 sp4_r_v_b_19 -(40 3) Enable bit of Mux _out_links/OutMux4_1 => wire_bram/ram/RDATA_14 sp12_v_b_18 -(40 4) Enable bit of Mux _out_links/OutMuxa_2 => wire_bram/ram/RDATA_13 sp4_r_v_b_21 -(40 5) Enable bit of Mux _out_links/OutMux4_2 => wire_bram/ram/RDATA_13 sp12_v_b_20 -(40 6) Enable bit of Mux _out_links/OutMuxa_3 => wire_bram/ram/RDATA_12 sp4_r_v_b_23 -(40 7) Enable bit of Mux _out_links/OutMux4_3 => wire_bram/ram/RDATA_12 sp12_v_b_22 -(40 8) Enable bit of Mux _out_links/OutMuxa_4 => wire_bram/ram/RDATA_11 sp4_r_v_b_25 -(40 9) Enable bit of Mux _out_links/OutMux3_4 => wire_bram/ram/RDATA_11 sp12_v_t_7 -(41 0) Enable bit of Mux _out_links/OutMuxb_0 => wire_bram/ram/RDATA_15 sp4_r_v_b_33 -(41 1) Enable bit of Mux _out_links/OutMux9_0 => wire_bram/ram/RDATA_15 sp4_r_v_b_1 -(41 10) Enable bit of Mux _out_links/OutMuxb_5 => wire_bram/ram/RDATA_10 sp4_r_v_b_43 -(41 11) Enable bit of Mux _out_links/OutMux9_5 => wire_bram/ram/RDATA_10 sp4_r_v_b_11 -(41 12) Enable bit of Mux _out_links/OutMuxb_6 => wire_bram/ram/RDATA_9 sp4_r_v_b_45 -(41 13) Enable bit of Mux _out_links/OutMux9_6 => wire_bram/ram/RDATA_9 sp4_r_v_b_13 -(41 14) Enable bit of Mux _out_links/OutMuxb_7 => wire_bram/ram/RDATA_8 sp4_r_v_b_47 -(41 15) Enable bit of Mux _out_links/OutMux9_7 => wire_bram/ram/RDATA_8 sp4_r_v_b_15 -(41 2) Enable bit of Mux _out_links/OutMuxb_1 => wire_bram/ram/RDATA_14 sp4_r_v_b_35 -(41 3) Enable bit of Mux _out_links/OutMux9_1 => wire_bram/ram/RDATA_14 sp4_r_v_b_3 -(41 4) Enable bit of Mux _out_links/OutMuxb_2 => wire_bram/ram/RDATA_13 sp4_r_v_b_37 -(41 5) Enable bit of Mux _out_links/OutMux9_2 => wire_bram/ram/RDATA_13 sp4_r_v_b_5 -(41 6) Enable bit of Mux _out_links/OutMuxb_3 => wire_bram/ram/RDATA_12 sp4_r_v_b_39 -(41 7) Enable bit of Mux _out_links/OutMux9_3 => wire_bram/ram/RDATA_12 sp4_r_v_b_7 -(41 8) Enable bit of Mux _out_links/OutMuxb_4 => wire_bram/ram/RDATA_11 sp4_r_v_b_41 -(41 9) Enable bit of Mux _out_links/OutMux9_4 => wire_bram/ram/RDATA_11 sp4_r_v_b_9 -(5 0) routing sp4_h_l_44 sp4_h_r_0 -(5 0) routing sp4_v_b_0 sp4_h_r_0 -(5 0) routing sp4_v_b_6 sp4_h_r_0 -(5 0) routing sp4_v_t_37 sp4_h_r_0 -(5 1) routing sp4_h_l_37 sp4_v_b_0 -(5 1) routing sp4_h_l_43 sp4_v_b_0 -(5 1) routing sp4_h_r_0 sp4_v_b_0 -(5 1) routing sp4_v_t_44 sp4_v_b_0 -(5 10) routing sp4_h_r_3 sp4_h_l_43 -(5 10) routing sp4_v_b_6 sp4_h_l_43 -(5 10) routing sp4_v_t_37 sp4_h_l_43 -(5 10) routing sp4_v_t_43 sp4_h_l_43 -(5 11) routing sp4_h_l_43 sp4_v_t_43 -(5 11) routing sp4_h_r_0 sp4_v_t_43 -(5 11) routing sp4_h_r_6 sp4_v_t_43 -(5 11) routing sp4_v_b_3 sp4_v_t_43 -(5 12) routing sp4_h_l_43 sp4_h_r_9 -(5 12) routing sp4_v_b_3 sp4_h_r_9 -(5 12) routing sp4_v_b_9 sp4_h_r_9 -(5 12) routing sp4_v_t_44 sp4_h_r_9 -(5 13) routing sp4_h_l_38 sp4_v_b_9 -(5 13) routing sp4_h_l_44 sp4_v_b_9 -(5 13) routing sp4_h_r_9 sp4_v_b_9 -(5 13) routing sp4_v_t_43 sp4_v_b_9 -(5 14) routing sp4_h_r_6 sp4_h_l_44 -(5 14) routing sp4_v_b_9 sp4_h_l_44 -(5 14) routing sp4_v_t_38 sp4_h_l_44 -(5 14) routing sp4_v_t_44 sp4_h_l_44 -(5 15) routing sp4_h_l_44 sp4_v_t_44 -(5 15) routing sp4_h_r_3 sp4_v_t_44 -(5 15) routing sp4_h_r_9 sp4_v_t_44 -(5 15) routing sp4_v_b_6 sp4_v_t_44 -(5 2) routing sp4_h_r_9 sp4_h_l_37 -(5 2) routing sp4_v_b_0 sp4_h_l_37 -(5 2) routing sp4_v_t_37 sp4_h_l_37 -(5 2) routing sp4_v_t_43 sp4_h_l_37 -(5 3) routing sp4_h_l_37 sp4_v_t_37 -(5 3) routing sp4_h_r_0 sp4_v_t_37 -(5 3) routing sp4_h_r_6 sp4_v_t_37 -(5 3) routing sp4_v_b_9 sp4_v_t_37 -(5 4) routing sp4_h_l_37 sp4_h_r_3 -(5 4) routing sp4_v_b_3 sp4_h_r_3 -(5 4) routing sp4_v_b_9 sp4_h_r_3 -(5 4) routing sp4_v_t_38 sp4_h_r_3 -(5 5) routing sp4_h_l_38 sp4_v_b_3 -(5 5) routing sp4_h_l_44 sp4_v_b_3 -(5 5) routing sp4_h_r_3 sp4_v_b_3 -(5 5) routing sp4_v_t_37 sp4_v_b_3 -(5 6) routing sp4_h_r_0 sp4_h_l_38 -(5 6) routing sp4_v_b_3 sp4_h_l_38 -(5 6) routing sp4_v_t_38 sp4_h_l_38 -(5 6) routing sp4_v_t_44 sp4_h_l_38 -(5 7) routing sp4_h_l_38 sp4_v_t_38 -(5 7) routing sp4_h_r_3 sp4_v_t_38 -(5 7) routing sp4_h_r_9 sp4_v_t_38 -(5 7) routing sp4_v_b_0 sp4_v_t_38 -(5 8) routing sp4_h_l_38 sp4_h_r_6 -(5 8) routing sp4_v_b_0 sp4_h_r_6 -(5 8) routing sp4_v_b_6 sp4_h_r_6 -(5 8) routing sp4_v_t_43 sp4_h_r_6 -(5 9) routing sp4_h_l_37 sp4_v_b_6 -(5 9) routing sp4_h_l_43 sp4_v_b_6 -(5 9) routing sp4_h_r_6 sp4_v_b_6 -(5 9) routing sp4_v_t_38 sp4_v_b_6 -(6 0) routing sp4_h_l_43 sp4_v_b_0 -(6 0) routing sp4_h_r_7 sp4_v_b_0 -(6 0) routing sp4_v_t_41 sp4_v_b_0 -(6 0) routing sp4_v_t_44 sp4_v_b_0 -(6 1) routing sp4_h_l_37 sp4_h_r_0 -(6 1) routing sp4_h_l_41 sp4_h_r_0 -(6 1) routing sp4_v_b_0 sp4_h_r_0 -(6 1) routing sp4_v_b_6 sp4_h_r_0 -(6 10) routing sp4_h_l_36 sp4_v_t_43 -(6 10) routing sp4_h_r_0 sp4_v_t_43 -(6 10) routing sp4_v_b_10 sp4_v_t_43 -(6 10) routing sp4_v_b_3 sp4_v_t_43 -(6 11) routing sp4_h_r_10 sp4_h_l_43 -(6 11) routing sp4_h_r_6 sp4_h_l_43 -(6 11) routing sp4_v_t_37 sp4_h_l_43 -(6 11) routing sp4_v_t_43 sp4_h_l_43 -(6 12) routing sp4_h_l_38 sp4_v_b_9 -(6 12) routing sp4_h_r_4 sp4_v_b_9 -(6 12) routing sp4_v_t_36 sp4_v_b_9 -(6 12) routing sp4_v_t_43 sp4_v_b_9 -(6 13) routing sp4_h_l_36 sp4_h_r_9 -(6 13) routing sp4_h_l_44 sp4_h_r_9 -(6 13) routing sp4_v_b_3 sp4_h_r_9 -(6 13) routing sp4_v_b_9 sp4_h_r_9 -(6 14) routing sp4_h_l_41 sp4_v_t_44 -(6 14) routing sp4_h_r_3 sp4_v_t_44 -(6 14) routing sp4_v_b_1 sp4_v_t_44 -(6 14) routing sp4_v_b_6 sp4_v_t_44 -(6 15) routing sp4_h_r_1 sp4_h_l_44 -(6 15) routing sp4_h_r_9 sp4_h_l_44 -(6 15) routing sp4_v_t_38 sp4_h_l_44 -(6 15) routing sp4_v_t_44 sp4_h_l_44 -(6 2) routing sp4_h_l_42 sp4_v_t_37 -(6 2) routing sp4_h_r_6 sp4_v_t_37 -(6 2) routing sp4_v_b_4 sp4_v_t_37 -(6 2) routing sp4_v_b_9 sp4_v_t_37 -(6 3) routing sp4_h_r_0 sp4_h_l_37 -(6 3) routing sp4_h_r_4 sp4_h_l_37 -(6 3) routing sp4_v_t_37 sp4_h_l_37 -(6 3) routing sp4_v_t_43 sp4_h_l_37 -(6 4) routing sp4_h_l_44 sp4_v_b_3 -(6 4) routing sp4_h_r_10 sp4_v_b_3 -(6 4) routing sp4_v_t_37 sp4_v_b_3 -(6 4) routing sp4_v_t_42 sp4_v_b_3 -(6 5) routing sp4_h_l_38 sp4_h_r_3 -(6 5) routing sp4_h_l_42 sp4_h_r_3 -(6 5) routing sp4_v_b_3 sp4_h_r_3 -(6 5) routing sp4_v_b_9 sp4_h_r_3 -(6 6) routing sp4_h_l_47 sp4_v_t_38 -(6 6) routing sp4_h_r_9 sp4_v_t_38 -(6 6) routing sp4_v_b_0 sp4_v_t_38 -(6 6) routing sp4_v_b_7 sp4_v_t_38 -(6 7) routing sp4_h_r_3 sp4_h_l_38 -(6 7) routing sp4_h_r_7 sp4_h_l_38 -(6 7) routing sp4_v_t_38 sp4_h_l_38 -(6 7) routing sp4_v_t_44 sp4_h_l_38 -(6 8) routing sp4_h_l_37 sp4_v_b_6 -(6 8) routing sp4_h_r_1 sp4_v_b_6 -(6 8) routing sp4_v_t_38 sp4_v_b_6 -(6 8) routing sp4_v_t_47 sp4_v_b_6 -(6 9) routing sp4_h_l_43 sp4_h_r_6 -(6 9) routing sp4_h_l_47 sp4_h_r_6 -(6 9) routing sp4_v_b_0 sp4_h_r_6 -(6 9) routing sp4_v_b_6 sp4_h_r_6 -(7 1) Ram config bit: MEMB_Power_Up_Control -(7 10) Column buffer control bit: MEMB_colbuf_cntl_3 -(7 11) Column buffer control bit: MEMB_colbuf_cntl_2 -(7 12) Column buffer control bit: MEMB_colbuf_cntl_5 -(7 13) Column buffer control bit: MEMB_colbuf_cntl_4 -(7 14) Column buffer control bit: MEMB_colbuf_cntl_7 -(7 15) Column buffer control bit: MEMB_colbuf_cntl_6 -(7 8) Column buffer control bit: MEMB_colbuf_cntl_1 -(8 0) routing sp4_h_l_36 sp4_h_r_1 -(8 0) routing sp4_h_l_40 sp4_h_r_1 -(8 0) routing sp4_v_b_1 sp4_h_r_1 -(8 0) routing sp4_v_b_7 sp4_h_r_1 -(8 1) routing sp4_h_l_36 sp4_v_b_1 -(8 1) routing sp4_h_l_42 sp4_v_b_1 -(8 1) routing sp4_h_r_1 sp4_v_b_1 -(8 1) routing sp4_v_t_47 sp4_v_b_1 -(8 10) routing sp4_h_r_11 sp4_h_l_42 -(8 10) routing sp4_h_r_7 sp4_h_l_42 -(8 10) routing sp4_v_t_36 sp4_h_l_42 -(8 10) routing sp4_v_t_42 sp4_h_l_42 -(8 11) routing sp4_h_l_42 sp4_v_t_42 -(8 11) routing sp4_h_r_1 sp4_v_t_42 -(8 11) routing sp4_h_r_7 sp4_v_t_42 -(8 11) routing sp4_v_b_4 sp4_v_t_42 -(8 12) routing sp4_h_l_39 sp4_h_r_10 -(8 12) routing sp4_h_l_47 sp4_h_r_10 -(8 12) routing sp4_v_b_10 sp4_h_r_10 -(8 12) routing sp4_v_b_4 sp4_h_r_10 -(8 13) routing sp4_h_l_41 sp4_v_b_10 -(8 13) routing sp4_h_l_47 sp4_v_b_10 -(8 13) routing sp4_h_r_10 sp4_v_b_10 -(8 13) routing sp4_v_t_42 sp4_v_b_10 -(8 14) routing sp4_h_r_10 sp4_h_l_47 -(8 14) routing sp4_h_r_2 sp4_h_l_47 -(8 14) routing sp4_v_t_41 sp4_h_l_47 -(8 14) routing sp4_v_t_47 sp4_h_l_47 -(8 15) routing sp4_h_l_47 sp4_v_t_47 -(8 15) routing sp4_h_r_10 sp4_v_t_47 -(8 15) routing sp4_h_r_4 sp4_v_t_47 -(8 15) routing sp4_v_b_7 sp4_v_t_47 -(8 2) routing sp4_h_r_1 sp4_h_l_36 -(8 2) routing sp4_h_r_5 sp4_h_l_36 -(8 2) routing sp4_v_t_36 sp4_h_l_36 -(8 2) routing sp4_v_t_42 sp4_h_l_36 -(8 3) routing sp4_h_l_36 sp4_v_t_36 -(8 3) routing sp4_h_r_1 sp4_v_t_36 -(8 3) routing sp4_h_r_7 sp4_v_t_36 -(8 3) routing sp4_v_b_10 sp4_v_t_36 -(8 4) routing sp4_h_l_41 sp4_h_r_4 -(8 4) routing sp4_h_l_45 sp4_h_r_4 -(8 4) routing sp4_v_b_10 sp4_h_r_4 -(8 4) routing sp4_v_b_4 sp4_h_r_4 -(8 5) routing sp4_h_l_41 sp4_v_b_4 -(8 5) routing sp4_h_l_47 sp4_v_b_4 -(8 5) routing sp4_h_r_4 sp4_v_b_4 -(8 5) routing sp4_v_t_36 sp4_v_b_4 -(8 6) routing sp4_h_r_4 sp4_h_l_41 -(8 6) routing sp4_h_r_8 sp4_h_l_41 -(8 6) routing sp4_v_t_41 sp4_h_l_41 -(8 6) routing sp4_v_t_47 sp4_h_l_41 -(8 7) routing sp4_h_l_41 sp4_v_t_41 -(8 7) routing sp4_h_r_10 sp4_v_t_41 -(8 7) routing sp4_h_r_4 sp4_v_t_41 -(8 7) routing sp4_v_b_1 sp4_v_t_41 -(8 8) routing sp4_h_l_42 sp4_h_r_7 -(8 8) routing sp4_h_l_46 sp4_h_r_7 -(8 8) routing sp4_v_b_1 sp4_h_r_7 -(8 8) routing sp4_v_b_7 sp4_h_r_7 -(8 9) routing sp4_h_l_36 sp4_v_b_7 -(8 9) routing sp4_h_l_42 sp4_v_b_7 -(8 9) routing sp4_h_r_7 sp4_v_b_7 -(8 9) routing sp4_v_t_41 sp4_v_b_7 -(9 0) routing sp4_h_l_47 sp4_h_r_1 -(9 0) routing sp4_v_b_1 sp4_h_r_1 -(9 0) routing sp4_v_b_7 sp4_h_r_1 -(9 0) routing sp4_v_t_36 sp4_h_r_1 -(9 1) routing sp4_h_l_36 sp4_v_b_1 -(9 1) routing sp4_h_l_42 sp4_v_b_1 -(9 1) routing sp4_v_t_36 sp4_v_b_1 -(9 1) routing sp4_v_t_40 sp4_v_b_1 -(9 10) routing sp4_h_r_4 sp4_h_l_42 -(9 10) routing sp4_v_b_7 sp4_h_l_42 -(9 10) routing sp4_v_t_36 sp4_h_l_42 -(9 10) routing sp4_v_t_42 sp4_h_l_42 -(9 11) routing sp4_h_r_1 sp4_v_t_42 -(9 11) routing sp4_h_r_7 sp4_v_t_42 -(9 11) routing sp4_v_b_11 sp4_v_t_42 -(9 11) routing sp4_v_b_7 sp4_v_t_42 -(9 12) routing sp4_h_l_42 sp4_h_r_10 -(9 12) routing sp4_v_b_10 sp4_h_r_10 -(9 12) routing sp4_v_b_4 sp4_h_r_10 -(9 12) routing sp4_v_t_47 sp4_h_r_10 -(9 13) routing sp4_h_l_41 sp4_v_b_10 -(9 13) routing sp4_h_l_47 sp4_v_b_10 -(9 13) routing sp4_v_t_39 sp4_v_b_10 -(9 13) routing sp4_v_t_47 sp4_v_b_10 -(9 14) routing sp4_h_r_7 sp4_h_l_47 -(9 14) routing sp4_v_b_10 sp4_h_l_47 -(9 14) routing sp4_v_t_41 sp4_h_l_47 -(9 14) routing sp4_v_t_47 sp4_h_l_47 -(9 15) routing sp4_h_r_10 sp4_v_t_47 -(9 15) routing sp4_h_r_4 sp4_v_t_47 -(9 15) routing sp4_v_b_10 sp4_v_t_47 -(9 15) routing sp4_v_b_2 sp4_v_t_47 -(9 2) routing sp4_h_r_10 sp4_h_l_36 -(9 2) routing sp4_v_b_1 sp4_h_l_36 -(9 2) routing sp4_v_t_36 sp4_h_l_36 -(9 2) routing sp4_v_t_42 sp4_h_l_36 -(9 3) routing sp4_h_r_1 sp4_v_t_36 -(9 3) routing sp4_h_r_7 sp4_v_t_36 -(9 3) routing sp4_v_b_1 sp4_v_t_36 -(9 3) routing sp4_v_b_5 sp4_v_t_36 -(9 4) routing sp4_h_l_36 sp4_h_r_4 -(9 4) routing sp4_v_b_10 sp4_h_r_4 -(9 4) routing sp4_v_b_4 sp4_h_r_4 -(9 4) routing sp4_v_t_41 sp4_h_r_4 -(9 5) routing sp4_h_l_41 sp4_v_b_4 -(9 5) routing sp4_h_l_47 sp4_v_b_4 -(9 5) routing sp4_v_t_41 sp4_v_b_4 -(9 5) routing sp4_v_t_45 sp4_v_b_4 -(9 6) routing sp4_h_r_1 sp4_h_l_41 -(9 6) routing sp4_v_b_4 sp4_h_l_41 -(9 6) routing sp4_v_t_41 sp4_h_l_41 -(9 6) routing sp4_v_t_47 sp4_h_l_41 -(9 7) routing sp4_h_r_10 sp4_v_t_41 -(9 7) routing sp4_h_r_4 sp4_v_t_41 -(9 7) routing sp4_v_b_4 sp4_v_t_41 -(9 7) routing sp4_v_b_8 sp4_v_t_41 -(9 8) routing sp4_h_l_41 sp4_h_r_7 -(9 8) routing sp4_v_b_1 sp4_h_r_7 -(9 8) routing sp4_v_b_7 sp4_h_r_7 -(9 8) routing sp4_v_t_42 sp4_h_r_7 -(9 9) routing sp4_h_l_36 sp4_v_b_7 -(9 9) routing sp4_h_l_42 sp4_v_b_7 -(9 9) routing sp4_v_t_42 sp4_v_b_7 -(9 9) routing sp4_v_t_46 sp4_v_b_7 diff --git a/icefuzz/cached_ramt_5k.txt b/icefuzz/cached_ramt_5k.txt deleted file mode 100644 index 8f2669c..0000000 --- a/icefuzz/cached_ramt_5k.txt +++ /dev/null @@ -1,3597 +0,0 @@ -(0 0) Negative Clock bit -(0 10) routing glb_netwk_3 glb2local_2 -(0 10) routing glb_netwk_6 glb2local_2 -(0 10) routing glb_netwk_7 glb2local_2 -(0 11) routing glb_netwk_1 glb2local_2 -(0 11) routing glb_netwk_3 glb2local_2 -(0 11) routing glb_netwk_5 glb2local_2 -(0 11) routing glb_netwk_7 glb2local_2 -(0 12) routing glb_netwk_3 glb2local_3 -(0 12) routing glb_netwk_6 glb2local_3 -(0 12) routing glb_netwk_7 glb2local_3 -(0 13) routing glb_netwk_1 glb2local_3 -(0 13) routing glb_netwk_3 glb2local_3 -(0 13) routing glb_netwk_5 glb2local_3 -(0 13) routing glb_netwk_7 glb2local_3 -(0 14) routing glb_netwk_4 wire_bram/ram/WE -(0 14) routing glb_netwk_6 wire_bram/ram/WE -(0 14) routing lc_trk_g2_4 wire_bram/ram/WE -(0 14) routing lc_trk_g3_5 wire_bram/ram/WE -(0 15) routing glb_netwk_2 wire_bram/ram/WE -(0 15) routing glb_netwk_6 wire_bram/ram/WE -(0 15) routing lc_trk_g1_5 wire_bram/ram/WE -(0 15) routing lc_trk_g3_5 wire_bram/ram/WE -(0 2) routing glb_netwk_2 wire_bram/ram/WCLK -(0 2) routing glb_netwk_3 wire_bram/ram/WCLK -(0 2) routing glb_netwk_6 wire_bram/ram/WCLK -(0 2) routing glb_netwk_7 wire_bram/ram/WCLK -(0 2) routing lc_trk_g2_0 wire_bram/ram/WCLK -(0 2) routing lc_trk_g3_1 wire_bram/ram/WCLK -(0 3) routing glb_netwk_1 wire_bram/ram/WCLK -(0 3) routing glb_netwk_3 wire_bram/ram/WCLK -(0 3) routing glb_netwk_5 wire_bram/ram/WCLK -(0 3) routing glb_netwk_7 wire_bram/ram/WCLK -(0 3) routing lc_trk_g1_1 wire_bram/ram/WCLK -(0 3) routing lc_trk_g3_1 wire_bram/ram/WCLK -(0 4) routing lc_trk_g2_2 wire_bram/ram/WCLKE -(0 4) routing lc_trk_g3_3 wire_bram/ram/WCLKE -(0 5) routing lc_trk_g1_3 wire_bram/ram/WCLKE -(0 5) routing lc_trk_g3_3 wire_bram/ram/WCLKE -(0 6) routing glb_netwk_3 glb2local_0 -(0 6) routing glb_netwk_6 glb2local_0 -(0 6) routing glb_netwk_7 glb2local_0 -(0 7) routing glb_netwk_1 glb2local_0 -(0 7) routing glb_netwk_3 glb2local_0 -(0 7) routing glb_netwk_5 glb2local_0 -(0 7) routing glb_netwk_7 glb2local_0 -(0 8) routing glb_netwk_3 glb2local_1 -(0 8) routing glb_netwk_6 glb2local_1 -(0 9) routing glb_netwk_1 glb2local_1 -(0 9) routing glb_netwk_3 glb2local_1 -(0 9) routing glb_netwk_5 glb2local_1 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_3 glb2local_2 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_4 glb2local_2 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_5 glb2local_2 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_6 glb2local_2 -(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_7 glb2local_2 -(1 11) routing glb_netwk_4 glb2local_2 -(1 11) routing glb_netwk_5 glb2local_2 -(1 11) routing glb_netwk_6 glb2local_2 -(1 11) routing glb_netwk_7 glb2local_2 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_1 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_3 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_4 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_5 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_6 glb2local_3 -(1 12) Enable bit of Mux _local_links/global_mux_3 => glb_netwk_7 glb2local_3 -(1 13) routing glb_netwk_4 glb2local_3 -(1 13) routing glb_netwk_5 glb2local_3 -(1 13) routing glb_netwk_6 glb2local_3 -(1 13) routing glb_netwk_7 glb2local_3 -(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_bram/ram/WE -(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_bram/ram/WE -(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_bram/ram/WE -(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_bram/ram/WE -(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g1_5 wire_bram/ram/WE -(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_bram/ram/WE -(1 14) Enable bit of Mux _global_links/set_rst_mux => lc_trk_g3_5 wire_bram/ram/WE -(1 15) routing lc_trk_g0_4 wire_bram/ram/WE -(1 15) routing lc_trk_g1_5 wire_bram/ram/WE -(1 15) routing lc_trk_g2_4 wire_bram/ram/WE -(1 15) routing lc_trk_g3_5 wire_bram/ram/WE -(1 2) routing glb_netwk_4 wire_bram/ram/WCLK -(1 2) routing glb_netwk_5 wire_bram/ram/WCLK -(1 2) routing glb_netwk_6 wire_bram/ram/WCLK -(1 2) routing glb_netwk_7 wire_bram/ram/WCLK -(1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_r_10 sp4_h_r_17 -(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g0_2 wire_bram/ram/WCLKE -(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g1_3 wire_bram/ram/WCLKE -(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g2_2 wire_bram/ram/WCLKE -(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g3_3 wire_bram/ram/WCLKE -(1 5) routing lc_trk_g0_2 wire_bram/ram/WCLKE -(1 5) routing lc_trk_g1_3 wire_bram/ram/WCLKE -(1 5) routing lc_trk_g2_2 wire_bram/ram/WCLKE -(1 5) routing lc_trk_g3_3 wire_bram/ram/WCLKE -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_1 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_3 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_4 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_5 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_6 glb2local_0 -(1 6) Enable bit of Mux _local_links/global_mux_0 => glb_netwk_7 glb2local_0 -(1 7) routing glb_netwk_4 glb2local_0 -(1 7) routing glb_netwk_5 glb2local_0 -(1 7) routing glb_netwk_6 glb2local_0 -(1 7) routing glb_netwk_7 glb2local_0 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_1 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1 -(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1 -(1 9) routing glb_netwk_4 glb2local_1 -(1 9) routing glb_netwk_5 glb2local_1 -(1 9) routing glb_netwk_6 glb2local_1 -(10 0) routing sp4_h_l_40 sp4_h_r_1 -(10 0) routing sp4_h_l_47 sp4_h_r_1 -(10 0) routing sp4_v_b_7 sp4_h_r_1 -(10 0) routing sp4_v_t_45 sp4_h_r_1 -(10 1) routing sp4_h_l_42 sp4_v_b_1 -(10 1) routing sp4_h_r_8 sp4_v_b_1 -(10 1) routing sp4_v_t_40 sp4_v_b_1 -(10 1) routing sp4_v_t_47 sp4_v_b_1 -(10 10) routing sp4_h_r_11 sp4_h_l_42 -(10 10) routing sp4_h_r_4 sp4_h_l_42 -(10 10) routing sp4_v_b_2 sp4_h_l_42 -(10 10) routing sp4_v_t_36 sp4_h_l_42 -(10 11) routing sp4_h_l_39 sp4_v_t_42 -(10 11) routing sp4_h_r_1 sp4_v_t_42 -(10 11) routing sp4_v_b_11 sp4_v_t_42 -(10 11) routing sp4_v_b_4 sp4_v_t_42 -(10 12) routing sp4_h_l_39 sp4_h_r_10 -(10 12) routing sp4_h_l_42 sp4_h_r_10 -(10 12) routing sp4_v_b_4 sp4_h_r_10 -(10 12) routing sp4_v_t_40 sp4_h_r_10 -(10 13) routing sp4_h_l_41 sp4_v_b_10 -(10 13) routing sp4_h_r_5 sp4_v_b_10 -(10 13) routing sp4_v_t_39 sp4_v_b_10 -(10 13) routing sp4_v_t_42 sp4_v_b_10 -(10 14) routing sp4_h_r_2 sp4_h_l_47 -(10 14) routing sp4_h_r_7 sp4_h_l_47 -(10 14) routing sp4_v_b_5 sp4_h_l_47 -(10 14) routing sp4_v_t_41 sp4_h_l_47 -(10 15) routing sp4_h_l_40 sp4_v_t_47 -(10 15) routing sp4_h_r_4 sp4_v_t_47 -(10 15) routing sp4_v_b_2 sp4_v_t_47 -(10 15) routing sp4_v_b_7 sp4_v_t_47 -(10 2) routing sp4_h_r_10 sp4_h_l_36 -(10 2) routing sp4_h_r_5 sp4_h_l_36 -(10 2) routing sp4_v_b_8 sp4_h_l_36 -(10 2) routing sp4_v_t_42 sp4_h_l_36 -(10 3) routing sp4_h_l_45 sp4_v_t_36 -(10 3) routing sp4_h_r_7 sp4_v_t_36 -(10 3) routing sp4_v_b_10 sp4_v_t_36 -(10 3) routing sp4_v_b_5 sp4_v_t_36 -(10 4) routing sp4_h_l_36 sp4_h_r_4 -(10 4) routing sp4_h_l_45 sp4_h_r_4 -(10 4) routing sp4_v_b_10 sp4_h_r_4 -(10 4) routing sp4_v_t_46 sp4_h_r_4 -(10 5) routing sp4_h_l_47 sp4_v_b_4 -(10 5) routing sp4_h_r_11 sp4_v_b_4 -(10 5) routing sp4_v_t_36 sp4_v_b_4 -(10 5) routing sp4_v_t_45 sp4_v_b_4 -(10 6) routing sp4_h_r_1 sp4_h_l_41 -(10 6) routing sp4_h_r_8 sp4_h_l_41 -(10 6) routing sp4_v_b_11 sp4_h_l_41 -(10 6) routing sp4_v_t_47 sp4_h_l_41 -(10 7) routing sp4_h_l_46 sp4_v_t_41 -(10 7) routing sp4_h_r_10 sp4_v_t_41 -(10 7) routing sp4_v_b_1 sp4_v_t_41 -(10 7) routing sp4_v_b_8 sp4_v_t_41 -(10 8) routing sp4_h_l_41 sp4_h_r_7 -(10 8) routing sp4_h_l_46 sp4_h_r_7 -(10 8) routing sp4_v_b_1 sp4_h_r_7 -(10 8) routing sp4_v_t_39 sp4_h_r_7 -(10 9) routing sp4_h_l_36 sp4_v_b_7 -(10 9) routing sp4_h_r_2 sp4_v_b_7 -(10 9) routing sp4_v_t_41 sp4_v_b_7 -(10 9) routing sp4_v_t_46 sp4_v_b_7 -(11 0) routing sp4_h_l_45 sp4_v_b_2 -(11 0) routing sp4_h_r_9 sp4_v_b_2 -(11 0) routing sp4_v_t_43 sp4_v_b_2 -(11 0) routing sp4_v_t_46 sp4_v_b_2 -(11 1) routing sp4_h_l_39 sp4_h_r_2 -(11 1) routing sp4_h_l_43 sp4_h_r_2 -(11 1) routing sp4_v_b_2 sp4_h_r_2 -(11 1) routing sp4_v_b_8 sp4_h_r_2 -(11 10) routing sp4_h_l_38 sp4_v_t_45 -(11 10) routing sp4_h_r_2 sp4_v_t_45 -(11 10) routing sp4_v_b_0 sp4_v_t_45 -(11 10) routing sp4_v_b_5 sp4_v_t_45 -(11 11) routing sp4_h_r_0 sp4_h_l_45 -(11 11) routing sp4_h_r_8 sp4_h_l_45 -(11 11) routing sp4_v_t_39 sp4_h_l_45 -(11 11) routing sp4_v_t_45 sp4_h_l_45 -(11 12) routing sp4_h_l_40 sp4_v_b_11 -(11 12) routing sp4_h_r_6 sp4_v_b_11 -(11 12) routing sp4_v_t_38 sp4_v_b_11 -(11 12) routing sp4_v_t_45 sp4_v_b_11 -(11 13) routing sp4_h_l_38 sp4_h_r_11 -(11 13) routing sp4_h_l_46 sp4_h_r_11 -(11 13) routing sp4_v_b_11 sp4_h_r_11 -(11 13) routing sp4_v_b_5 sp4_h_r_11 -(11 14) routing sp4_h_l_43 sp4_v_t_46 -(11 14) routing sp4_h_r_5 sp4_v_t_46 -(11 14) routing sp4_v_b_3 sp4_v_t_46 -(11 14) routing sp4_v_b_8 sp4_v_t_46 -(11 15) routing sp4_h_r_11 sp4_h_l_46 -(11 15) routing sp4_h_r_3 sp4_h_l_46 -(11 15) routing sp4_v_t_40 sp4_h_l_46 -(11 15) routing sp4_v_t_46 sp4_h_l_46 -(11 2) routing sp4_h_l_44 sp4_v_t_39 -(11 2) routing sp4_h_r_8 sp4_v_t_39 -(11 2) routing sp4_v_b_11 sp4_v_t_39 -(11 2) routing sp4_v_b_6 sp4_v_t_39 -(11 3) routing sp4_h_r_2 sp4_h_l_39 -(11 3) routing sp4_h_r_6 sp4_h_l_39 -(11 3) routing sp4_v_t_39 sp4_h_l_39 -(11 3) routing sp4_v_t_45 sp4_h_l_39 -(11 4) routing sp4_h_l_46 sp4_v_b_5 -(11 4) routing sp4_h_r_0 sp4_v_b_5 -(11 4) routing sp4_v_t_39 sp4_v_b_5 -(11 4) routing sp4_v_t_44 sp4_v_b_5 -(11 5) routing sp4_h_l_40 sp4_h_r_5 -(11 5) routing sp4_h_l_44 sp4_h_r_5 -(11 5) routing sp4_v_b_11 sp4_h_r_5 -(11 5) routing sp4_v_b_5 sp4_h_r_5 -(11 6) routing sp4_h_l_37 sp4_v_t_40 -(11 6) routing sp4_h_r_11 sp4_v_t_40 -(11 6) routing sp4_v_b_2 sp4_v_t_40 -(11 6) routing sp4_v_b_9 sp4_v_t_40 -(11 7) routing sp4_h_r_5 sp4_h_l_40 -(11 7) routing sp4_h_r_9 sp4_h_l_40 -(11 7) routing sp4_v_t_40 sp4_h_l_40 -(11 7) routing sp4_v_t_46 sp4_h_l_40 -(11 8) routing sp4_h_l_39 sp4_v_b_8 -(11 8) routing sp4_h_r_3 sp4_v_b_8 -(11 8) routing sp4_v_t_37 sp4_v_b_8 -(11 8) routing sp4_v_t_40 sp4_v_b_8 -(11 9) routing sp4_h_l_37 sp4_h_r_8 -(11 9) routing sp4_h_l_45 sp4_h_r_8 -(11 9) routing sp4_v_b_2 sp4_h_r_8 -(11 9) routing sp4_v_b_8 sp4_h_r_8 -(12 0) routing sp4_h_l_46 sp4_h_r_2 -(12 0) routing sp4_v_b_2 sp4_h_r_2 -(12 0) routing sp4_v_b_8 sp4_h_r_2 -(12 0) routing sp4_v_t_39 sp4_h_r_2 -(12 1) routing sp4_h_l_39 sp4_v_b_2 -(12 1) routing sp4_h_l_45 sp4_v_b_2 -(12 1) routing sp4_h_r_2 sp4_v_b_2 -(12 1) routing sp4_v_t_46 sp4_v_b_2 -(12 10) routing sp4_h_r_5 sp4_h_l_45 -(12 10) routing sp4_v_b_8 sp4_h_l_45 -(12 10) routing sp4_v_t_39 sp4_h_l_45 -(12 10) routing sp4_v_t_45 sp4_h_l_45 -(12 11) routing sp4_h_l_45 sp4_v_t_45 -(12 11) routing sp4_h_r_2 sp4_v_t_45 -(12 11) routing sp4_h_r_8 sp4_v_t_45 -(12 11) routing sp4_v_b_5 sp4_v_t_45 -(12 12) routing sp4_h_l_45 sp4_h_r_11 -(12 12) routing sp4_v_b_11 sp4_h_r_11 -(12 12) routing sp4_v_b_5 sp4_h_r_11 -(12 12) routing sp4_v_t_46 sp4_h_r_11 -(12 13) routing sp4_h_l_40 sp4_v_b_11 -(12 13) routing sp4_h_l_46 sp4_v_b_11 -(12 13) routing sp4_h_r_11 sp4_v_b_11 -(12 13) routing sp4_v_t_45 sp4_v_b_11 -(12 14) routing sp4_h_r_8 sp4_h_l_46 -(12 14) routing sp4_v_b_11 sp4_h_l_46 -(12 14) routing sp4_v_t_40 sp4_h_l_46 -(12 14) routing sp4_v_t_46 sp4_h_l_46 -(12 15) routing sp4_h_l_46 sp4_v_t_46 -(12 15) routing sp4_h_r_11 sp4_v_t_46 -(12 15) routing sp4_h_r_5 sp4_v_t_46 -(12 15) routing sp4_v_b_8 sp4_v_t_46 -(12 2) routing sp4_h_r_11 sp4_h_l_39 -(12 2) routing sp4_v_b_2 sp4_h_l_39 -(12 2) routing sp4_v_t_39 sp4_h_l_39 -(12 2) routing sp4_v_t_45 sp4_h_l_39 -(12 3) routing sp4_h_l_39 sp4_v_t_39 -(12 3) routing sp4_h_r_2 sp4_v_t_39 -(12 3) routing sp4_h_r_8 sp4_v_t_39 -(12 3) routing sp4_v_b_11 sp4_v_t_39 -(12 4) routing sp4_h_l_39 sp4_h_r_5 -(12 4) routing sp4_v_b_11 sp4_h_r_5 -(12 4) routing sp4_v_b_5 sp4_h_r_5 -(12 4) routing sp4_v_t_40 sp4_h_r_5 -(12 5) routing sp4_h_l_40 sp4_v_b_5 -(12 5) routing sp4_h_l_46 sp4_v_b_5 -(12 5) routing sp4_h_r_5 sp4_v_b_5 -(12 5) routing sp4_v_t_39 sp4_v_b_5 -(12 6) routing sp4_h_r_2 sp4_h_l_40 -(12 6) routing sp4_v_b_5 sp4_h_l_40 -(12 6) routing sp4_v_t_40 sp4_h_l_40 -(12 6) routing sp4_v_t_46 sp4_h_l_40 -(12 7) routing sp4_h_l_40 sp4_v_t_40 -(12 7) routing sp4_h_r_11 sp4_v_t_40 -(12 7) routing sp4_h_r_5 sp4_v_t_40 -(12 7) routing sp4_v_b_2 sp4_v_t_40 -(12 8) routing sp4_h_l_40 sp4_h_r_8 -(12 8) routing sp4_v_b_2 sp4_h_r_8 -(12 8) routing sp4_v_b_8 sp4_h_r_8 -(12 8) routing sp4_v_t_45 sp4_h_r_8 -(12 9) routing sp4_h_l_39 sp4_v_b_8 -(12 9) routing sp4_h_l_45 sp4_v_b_8 -(12 9) routing sp4_h_r_8 sp4_v_b_8 -(12 9) routing sp4_v_t_40 sp4_v_b_8 -(13 0) routing sp4_h_l_39 sp4_v_b_2 -(13 0) routing sp4_h_l_45 sp4_v_b_2 -(13 0) routing sp4_v_t_39 sp4_v_b_2 -(13 0) routing sp4_v_t_43 sp4_v_b_2 -(13 1) routing sp4_h_l_43 sp4_h_r_2 -(13 1) routing sp4_h_l_46 sp4_h_r_2 -(13 1) routing sp4_v_b_8 sp4_h_r_2 -(13 1) routing sp4_v_t_44 sp4_h_r_2 -(13 10) routing sp4_h_r_2 sp4_v_t_45 -(13 10) routing sp4_h_r_8 sp4_v_t_45 -(13 10) routing sp4_v_b_0 sp4_v_t_45 -(13 10) routing sp4_v_b_8 sp4_v_t_45 -(13 11) routing sp4_h_r_0 sp4_h_l_45 -(13 11) routing sp4_h_r_5 sp4_h_l_45 -(13 11) routing sp4_v_b_3 sp4_h_l_45 -(13 11) routing sp4_v_t_39 sp4_h_l_45 -(13 12) routing sp4_h_l_40 sp4_v_b_11 -(13 12) routing sp4_h_l_46 sp4_v_b_11 -(13 12) routing sp4_v_t_38 sp4_v_b_11 -(13 12) routing sp4_v_t_46 sp4_v_b_11 -(13 13) routing sp4_h_l_38 sp4_h_r_11 -(13 13) routing sp4_h_l_45 sp4_h_r_11 -(13 13) routing sp4_v_b_5 sp4_h_r_11 -(13 13) routing sp4_v_t_43 sp4_h_r_11 -(13 14) routing sp4_h_r_11 sp4_v_t_46 -(13 14) routing sp4_h_r_5 sp4_v_t_46 -(13 14) routing sp4_v_b_11 sp4_v_t_46 -(13 14) routing sp4_v_b_3 sp4_v_t_46 -(13 15) routing sp4_h_r_3 sp4_h_l_46 -(13 15) routing sp4_h_r_8 sp4_h_l_46 -(13 15) routing sp4_v_b_6 sp4_h_l_46 -(13 15) routing sp4_v_t_40 sp4_h_l_46 -(13 2) routing sp4_h_r_2 sp4_v_t_39 -(13 2) routing sp4_h_r_8 sp4_v_t_39 -(13 2) routing sp4_v_b_2 sp4_v_t_39 -(13 2) routing sp4_v_b_6 sp4_v_t_39 -(13 3) routing sp4_h_r_11 sp4_h_l_39 -(13 3) routing sp4_h_r_6 sp4_h_l_39 -(13 3) routing sp4_v_b_9 sp4_h_l_39 -(13 3) routing sp4_v_t_45 sp4_h_l_39 -(13 4) routing sp4_h_l_40 sp4_v_b_5 -(13 4) routing sp4_h_l_46 sp4_v_b_5 -(13 4) routing sp4_v_t_40 sp4_v_b_5 -(13 4) routing sp4_v_t_44 sp4_v_b_5 -(13 5) routing sp4_h_l_39 sp4_h_r_5 -(13 5) routing sp4_h_l_44 sp4_h_r_5 -(13 5) routing sp4_v_b_11 sp4_h_r_5 -(13 5) routing sp4_v_t_37 sp4_h_r_5 -(13 6) routing sp4_h_r_11 sp4_v_t_40 -(13 6) routing sp4_h_r_5 sp4_v_t_40 -(13 6) routing sp4_v_b_5 sp4_v_t_40 -(13 6) routing sp4_v_b_9 sp4_v_t_40 -(13 7) routing sp4_h_r_2 sp4_h_l_40 -(13 7) routing sp4_h_r_9 sp4_h_l_40 -(13 7) routing sp4_v_b_0 sp4_h_l_40 -(13 7) routing sp4_v_t_46 sp4_h_l_40 -(13 8) routing sp4_h_l_39 sp4_v_b_8 -(13 8) routing sp4_h_l_45 sp4_v_b_8 -(13 8) routing sp4_v_t_37 sp4_v_b_8 -(13 8) routing sp4_v_t_45 sp4_v_b_8 -(13 9) routing sp4_h_l_37 sp4_h_r_8 -(13 9) routing sp4_h_l_40 sp4_h_r_8 -(13 9) routing sp4_v_b_2 sp4_h_r_8 -(13 9) routing sp4_v_t_38 sp4_h_r_8 -(14 0) routing bnr_op_0 lc_trk_g0_0 -(14 0) routing lft_op_0 lc_trk_g0_0 -(14 0) routing sp12_h_r_0 lc_trk_g0_0 -(14 0) routing sp4_h_l_5 lc_trk_g0_0 -(14 0) routing sp4_h_r_8 lc_trk_g0_0 -(14 0) routing sp4_v_b_0 lc_trk_g0_0 -(14 0) routing sp4_v_b_8 lc_trk_g0_0 -(14 1) routing bnr_op_0 lc_trk_g0_0 -(14 1) routing sp12_h_r_0 lc_trk_g0_0 -(14 1) routing sp12_h_r_16 lc_trk_g0_0 -(14 1) routing sp4_h_l_5 lc_trk_g0_0 -(14 1) routing sp4_h_r_0 lc_trk_g0_0 -(14 1) routing sp4_r_v_b_35 lc_trk_g0_0 -(14 1) routing sp4_v_b_8 lc_trk_g0_0 -(14 10) routing bnl_op_4 lc_trk_g2_4 -(14 10) routing rgt_op_4 lc_trk_g2_4 -(14 10) routing sp12_v_t_3 lc_trk_g2_4 -(14 10) routing sp4_h_r_36 lc_trk_g2_4 -(14 10) routing sp4_h_r_44 lc_trk_g2_4 -(14 10) routing sp4_v_b_28 lc_trk_g2_4 -(14 10) routing sp4_v_t_25 lc_trk_g2_4 -(14 11) routing bnl_op_4 lc_trk_g2_4 -(14 11) routing sp12_v_t_19 lc_trk_g2_4 -(14 11) routing sp12_v_t_3 lc_trk_g2_4 -(14 11) routing sp4_h_l_17 lc_trk_g2_4 -(14 11) routing sp4_h_r_44 lc_trk_g2_4 -(14 11) routing sp4_r_v_b_36 lc_trk_g2_4 -(14 11) routing sp4_v_t_25 lc_trk_g2_4 -(14 11) routing tnl_op_4 lc_trk_g2_4 -(14 12) routing bnl_op_0 lc_trk_g3_0 -(14 12) routing rgt_op_0 lc_trk_g3_0 -(14 12) routing sp12_v_b_0 lc_trk_g3_0 -(14 12) routing sp4_h_l_21 lc_trk_g3_0 -(14 12) routing sp4_h_l_29 lc_trk_g3_0 -(14 12) routing sp4_v_t_13 lc_trk_g3_0 -(14 12) routing sp4_v_t_21 lc_trk_g3_0 -(14 13) routing bnl_op_0 lc_trk_g3_0 -(14 13) routing sp12_v_b_0 lc_trk_g3_0 -(14 13) routing sp12_v_b_16 lc_trk_g3_0 -(14 13) routing sp4_h_l_13 lc_trk_g3_0 -(14 13) routing sp4_h_l_29 lc_trk_g3_0 -(14 13) routing sp4_r_v_b_40 lc_trk_g3_0 -(14 13) routing sp4_v_t_21 lc_trk_g3_0 -(14 13) routing tnl_op_0 lc_trk_g3_0 -(14 14) routing bnl_op_4 lc_trk_g3_4 -(14 14) routing rgt_op_4 lc_trk_g3_4 -(14 14) routing sp12_v_t_3 lc_trk_g3_4 -(14 14) routing sp4_h_r_36 lc_trk_g3_4 -(14 14) routing sp4_h_r_44 lc_trk_g3_4 -(14 14) routing sp4_v_b_28 lc_trk_g3_4 -(14 14) routing sp4_v_t_25 lc_trk_g3_4 -(14 15) routing bnl_op_4 lc_trk_g3_4 -(14 15) routing sp12_v_t_19 lc_trk_g3_4 -(14 15) routing sp12_v_t_3 lc_trk_g3_4 -(14 15) routing sp4_h_l_17 lc_trk_g3_4 -(14 15) routing sp4_h_r_44 lc_trk_g3_4 -(14 15) routing sp4_r_v_b_44 lc_trk_g3_4 -(14 15) routing sp4_v_t_25 lc_trk_g3_4 -(14 15) routing tnl_op_4 lc_trk_g3_4 -(14 2) routing bnr_op_4 lc_trk_g0_4 -(14 2) routing lft_op_4 lc_trk_g0_4 -(14 2) routing sp12_h_l_3 lc_trk_g0_4 -(14 2) routing sp4_h_r_12 lc_trk_g0_4 -(14 2) routing sp4_h_r_20 lc_trk_g0_4 -(14 2) routing sp4_v_b_4 lc_trk_g0_4 -(14 2) routing sp4_v_t_1 lc_trk_g0_4 -(14 3) routing bnr_op_4 lc_trk_g0_4 -(14 3) routing sp12_h_l_3 lc_trk_g0_4 -(14 3) routing sp12_h_r_20 lc_trk_g0_4 -(14 3) routing sp4_h_r_20 lc_trk_g0_4 -(14 3) routing sp4_h_r_4 lc_trk_g0_4 -(14 3) routing sp4_r_v_b_28 lc_trk_g0_4 -(14 3) routing sp4_v_t_1 lc_trk_g0_4 -(14 4) routing bnr_op_0 lc_trk_g1_0 -(14 4) routing lft_op_0 lc_trk_g1_0 -(14 4) routing sp12_h_r_0 lc_trk_g1_0 -(14 4) routing sp4_h_l_5 lc_trk_g1_0 -(14 4) routing sp4_h_r_8 lc_trk_g1_0 -(14 4) routing sp4_v_b_0 lc_trk_g1_0 -(14 4) routing sp4_v_b_8 lc_trk_g1_0 -(14 5) routing bnr_op_0 lc_trk_g1_0 -(14 5) routing sp12_h_r_0 lc_trk_g1_0 -(14 5) routing sp12_h_r_16 lc_trk_g1_0 -(14 5) routing sp4_h_l_5 lc_trk_g1_0 -(14 5) routing sp4_h_r_0 lc_trk_g1_0 -(14 5) routing sp4_r_v_b_24 lc_trk_g1_0 -(14 5) routing sp4_v_b_8 lc_trk_g1_0 -(14 6) routing bnr_op_4 lc_trk_g1_4 -(14 6) routing lft_op_4 lc_trk_g1_4 -(14 6) routing sp12_h_l_3 lc_trk_g1_4 -(14 6) routing sp4_h_r_12 lc_trk_g1_4 -(14 6) routing sp4_h_r_20 lc_trk_g1_4 -(14 6) routing sp4_v_b_4 lc_trk_g1_4 -(14 6) routing sp4_v_t_1 lc_trk_g1_4 -(14 7) routing bnr_op_4 lc_trk_g1_4 -(14 7) routing sp12_h_l_3 lc_trk_g1_4 -(14 7) routing sp12_h_r_20 lc_trk_g1_4 -(14 7) routing sp4_h_r_20 lc_trk_g1_4 -(14 7) routing sp4_h_r_4 lc_trk_g1_4 -(14 7) routing sp4_r_v_b_28 lc_trk_g1_4 -(14 7) routing sp4_v_t_1 lc_trk_g1_4 -(14 8) routing bnl_op_0 lc_trk_g2_0 -(14 8) routing rgt_op_0 lc_trk_g2_0 -(14 8) routing sp12_v_b_0 lc_trk_g2_0 -(14 8) routing sp4_h_l_21 lc_trk_g2_0 -(14 8) routing sp4_h_l_29 lc_trk_g2_0 -(14 8) routing sp4_v_t_13 lc_trk_g2_0 -(14 8) routing sp4_v_t_21 lc_trk_g2_0 -(14 9) routing bnl_op_0 lc_trk_g2_0 -(14 9) routing sp12_v_b_0 lc_trk_g2_0 -(14 9) routing sp12_v_b_16 lc_trk_g2_0 -(14 9) routing sp4_h_l_13 lc_trk_g2_0 -(14 9) routing sp4_h_l_29 lc_trk_g2_0 -(14 9) routing sp4_r_v_b_32 lc_trk_g2_0 -(14 9) routing sp4_v_t_21 lc_trk_g2_0 -(14 9) routing tnl_op_0 lc_trk_g2_0 -(15 0) routing lft_op_1 lc_trk_g0_1 -(15 0) routing sp12_h_r_1 lc_trk_g0_1 -(15 0) routing sp4_h_r_1 lc_trk_g0_1 -(15 0) routing sp4_h_r_17 lc_trk_g0_1 -(15 0) routing sp4_h_r_9 lc_trk_g0_1 -(15 0) routing sp4_v_b_17 lc_trk_g0_1 -(15 1) routing lft_op_0 lc_trk_g0_0 -(15 1) routing sp12_h_r_0 lc_trk_g0_0 -(15 1) routing sp4_h_l_5 lc_trk_g0_0 -(15 1) routing sp4_h_r_0 lc_trk_g0_0 -(15 1) routing sp4_h_r_8 lc_trk_g0_0 -(15 1) routing sp4_v_b_16 lc_trk_g0_0 -(15 10) routing rgt_op_5 lc_trk_g2_5 -(15 10) routing sp12_v_b_5 lc_trk_g2_5 -(15 10) routing sp4_h_l_16 lc_trk_g2_5 -(15 10) routing sp4_h_r_37 lc_trk_g2_5 -(15 10) routing sp4_h_r_45 lc_trk_g2_5 -(15 10) routing sp4_v_b_45 lc_trk_g2_5 -(15 10) routing tnl_op_5 lc_trk_g2_5 -(15 10) routing tnr_op_5 lc_trk_g2_5 -(15 11) routing rgt_op_4 lc_trk_g2_4 -(15 11) routing sp12_v_t_3 lc_trk_g2_4 -(15 11) routing sp4_h_l_17 lc_trk_g2_4 -(15 11) routing sp4_h_r_36 lc_trk_g2_4 -(15 11) routing sp4_h_r_44 lc_trk_g2_4 -(15 11) routing sp4_v_t_33 lc_trk_g2_4 -(15 11) routing tnl_op_4 lc_trk_g2_4 -(15 11) routing tnr_op_4 lc_trk_g2_4 -(15 12) routing rgt_op_1 lc_trk_g3_1 -(15 12) routing sp12_v_b_1 lc_trk_g3_1 -(15 12) routing sp4_h_l_20 lc_trk_g3_1 -(15 12) routing sp4_h_l_28 lc_trk_g3_1 -(15 12) routing sp4_h_r_25 lc_trk_g3_1 -(15 12) routing sp4_v_b_41 lc_trk_g3_1 -(15 12) routing tnl_op_1 lc_trk_g3_1 -(15 12) routing tnr_op_1 lc_trk_g3_1 -(15 13) routing rgt_op_0 lc_trk_g3_0 -(15 13) routing sp12_v_b_0 lc_trk_g3_0 -(15 13) routing sp4_h_l_13 lc_trk_g3_0 -(15 13) routing sp4_h_l_21 lc_trk_g3_0 -(15 13) routing sp4_h_l_29 lc_trk_g3_0 -(15 13) routing sp4_v_b_40 lc_trk_g3_0 -(15 13) routing tnl_op_0 lc_trk_g3_0 -(15 13) routing tnr_op_0 lc_trk_g3_0 -(15 14) routing rgt_op_5 lc_trk_g3_5 -(15 14) routing sp12_v_b_5 lc_trk_g3_5 -(15 14) routing sp4_h_l_16 lc_trk_g3_5 -(15 14) routing sp4_h_r_37 lc_trk_g3_5 -(15 14) routing sp4_h_r_45 lc_trk_g3_5 -(15 14) routing sp4_v_b_45 lc_trk_g3_5 -(15 14) routing tnl_op_5 lc_trk_g3_5 -(15 14) routing tnr_op_5 lc_trk_g3_5 -(15 15) routing rgt_op_4 lc_trk_g3_4 -(15 15) routing sp12_v_t_3 lc_trk_g3_4 -(15 15) routing sp4_h_l_17 lc_trk_g3_4 -(15 15) routing sp4_h_r_36 lc_trk_g3_4 -(15 15) routing sp4_h_r_44 lc_trk_g3_4 -(15 15) routing sp4_v_t_33 lc_trk_g3_4 -(15 15) routing tnl_op_4 lc_trk_g3_4 -(15 15) routing tnr_op_4 lc_trk_g3_4 -(15 2) routing lft_op_5 lc_trk_g0_5 -(15 2) routing sp12_h_r_5 lc_trk_g0_5 -(15 2) routing sp4_h_l_8 lc_trk_g0_5 -(15 2) routing sp4_h_r_13 lc_trk_g0_5 -(15 2) routing sp4_h_r_5 lc_trk_g0_5 -(15 2) routing sp4_v_t_8 lc_trk_g0_5 -(15 3) routing lft_op_4 lc_trk_g0_4 -(15 3) routing sp12_h_l_3 lc_trk_g0_4 -(15 3) routing sp4_h_r_12 lc_trk_g0_4 -(15 3) routing sp4_h_r_20 lc_trk_g0_4 -(15 3) routing sp4_h_r_4 lc_trk_g0_4 -(15 3) routing sp4_v_b_20 lc_trk_g0_4 -(15 4) routing lft_op_1 lc_trk_g1_1 -(15 4) routing sp12_h_r_1 lc_trk_g1_1 -(15 4) routing sp4_h_r_1 lc_trk_g1_1 -(15 4) routing sp4_h_r_17 lc_trk_g1_1 -(15 4) routing sp4_h_r_9 lc_trk_g1_1 -(15 4) routing sp4_v_b_17 lc_trk_g1_1 -(15 5) routing lft_op_0 lc_trk_g1_0 -(15 5) routing sp12_h_r_0 lc_trk_g1_0 -(15 5) routing sp4_h_l_5 lc_trk_g1_0 -(15 5) routing sp4_h_r_0 lc_trk_g1_0 -(15 5) routing sp4_h_r_8 lc_trk_g1_0 -(15 5) routing sp4_v_b_16 lc_trk_g1_0 -(15 6) routing lft_op_5 lc_trk_g1_5 -(15 6) routing sp12_h_r_5 lc_trk_g1_5 -(15 6) routing sp4_h_l_8 lc_trk_g1_5 -(15 6) routing sp4_h_r_13 lc_trk_g1_5 -(15 6) routing sp4_h_r_5 lc_trk_g1_5 -(15 6) routing sp4_v_t_8 lc_trk_g1_5 -(15 7) routing lft_op_4 lc_trk_g1_4 -(15 7) routing sp12_h_l_3 lc_trk_g1_4 -(15 7) routing sp4_h_r_12 lc_trk_g1_4 -(15 7) routing sp4_h_r_20 lc_trk_g1_4 -(15 7) routing sp4_h_r_4 lc_trk_g1_4 -(15 7) routing sp4_v_b_20 lc_trk_g1_4 -(15 8) routing rgt_op_1 lc_trk_g2_1 -(15 8) routing sp12_v_b_1 lc_trk_g2_1 -(15 8) routing sp4_h_l_20 lc_trk_g2_1 -(15 8) routing sp4_h_l_28 lc_trk_g2_1 -(15 8) routing sp4_h_r_25 lc_trk_g2_1 -(15 8) routing sp4_v_b_41 lc_trk_g2_1 -(15 8) routing tnl_op_1 lc_trk_g2_1 -(15 8) routing tnr_op_1 lc_trk_g2_1 -(15 9) routing rgt_op_0 lc_trk_g2_0 -(15 9) routing sp12_v_b_0 lc_trk_g2_0 -(15 9) routing sp4_h_l_13 lc_trk_g2_0 -(15 9) routing sp4_h_l_21 lc_trk_g2_0 -(15 9) routing sp4_h_l_29 lc_trk_g2_0 -(15 9) routing sp4_v_b_40 lc_trk_g2_0 -(15 9) routing tnl_op_0 lc_trk_g2_0 -(15 9) routing tnr_op_0 lc_trk_g2_0 -(16 0) routing sp12_h_l_6 lc_trk_g0_1 -(16 0) routing sp12_h_r_17 lc_trk_g0_1 -(16 0) routing sp4_h_r_1 lc_trk_g0_1 -(16 0) routing sp4_h_r_17 lc_trk_g0_1 -(16 0) routing sp4_h_r_9 lc_trk_g0_1 -(16 0) routing sp4_v_b_1 lc_trk_g0_1 -(16 0) routing sp4_v_b_17 lc_trk_g0_1 -(16 0) routing sp4_v_b_9 lc_trk_g0_1 -(16 1) routing sp12_h_r_16 lc_trk_g0_0 -(16 1) routing sp12_h_r_8 lc_trk_g0_0 -(16 1) routing sp4_h_l_5 lc_trk_g0_0 -(16 1) routing sp4_h_r_0 lc_trk_g0_0 -(16 1) routing sp4_h_r_8 lc_trk_g0_0 -(16 1) routing sp4_v_b_0 lc_trk_g0_0 -(16 1) routing sp4_v_b_16 lc_trk_g0_0 -(16 1) routing sp4_v_b_8 lc_trk_g0_0 -(16 10) routing sp12_v_b_21 lc_trk_g2_5 -(16 10) routing sp12_v_t_10 lc_trk_g2_5 -(16 10) routing sp4_h_l_16 lc_trk_g2_5 -(16 10) routing sp4_h_r_37 lc_trk_g2_5 -(16 10) routing sp4_h_r_45 lc_trk_g2_5 -(16 10) routing sp4_v_b_29 lc_trk_g2_5 -(16 10) routing sp4_v_b_37 lc_trk_g2_5 -(16 10) routing sp4_v_b_45 lc_trk_g2_5 -(16 11) routing sp12_v_b_12 lc_trk_g2_4 -(16 11) routing sp12_v_t_19 lc_trk_g2_4 -(16 11) routing sp4_h_l_17 lc_trk_g2_4 -(16 11) routing sp4_h_r_36 lc_trk_g2_4 -(16 11) routing sp4_h_r_44 lc_trk_g2_4 -(16 11) routing sp4_v_b_28 lc_trk_g2_4 -(16 11) routing sp4_v_t_25 lc_trk_g2_4 -(16 11) routing sp4_v_t_33 lc_trk_g2_4 -(16 12) routing sp12_v_b_17 lc_trk_g3_1 -(16 12) routing sp12_v_b_9 lc_trk_g3_1 -(16 12) routing sp4_h_l_20 lc_trk_g3_1 -(16 12) routing sp4_h_l_28 lc_trk_g3_1 -(16 12) routing sp4_h_r_25 lc_trk_g3_1 -(16 12) routing sp4_v_b_25 lc_trk_g3_1 -(16 12) routing sp4_v_b_33 lc_trk_g3_1 -(16 12) routing sp4_v_b_41 lc_trk_g3_1 -(16 13) routing sp12_v_b_16 lc_trk_g3_0 -(16 13) routing sp12_v_t_7 lc_trk_g3_0 -(16 13) routing sp4_h_l_13 lc_trk_g3_0 -(16 13) routing sp4_h_l_21 lc_trk_g3_0 -(16 13) routing sp4_h_l_29 lc_trk_g3_0 -(16 13) routing sp4_v_b_40 lc_trk_g3_0 -(16 13) routing sp4_v_t_13 lc_trk_g3_0 -(16 13) routing sp4_v_t_21 lc_trk_g3_0 -(16 14) routing sp12_v_b_21 lc_trk_g3_5 -(16 14) routing sp12_v_t_10 lc_trk_g3_5 -(16 14) routing sp4_h_l_16 lc_trk_g3_5 -(16 14) routing sp4_h_r_37 lc_trk_g3_5 -(16 14) routing sp4_h_r_45 lc_trk_g3_5 -(16 14) routing sp4_v_b_29 lc_trk_g3_5 -(16 14) routing sp4_v_b_37 lc_trk_g3_5 -(16 14) routing sp4_v_b_45 lc_trk_g3_5 -(16 15) routing sp12_v_b_12 lc_trk_g3_4 -(16 15) routing sp12_v_t_19 lc_trk_g3_4 -(16 15) routing sp4_h_l_17 lc_trk_g3_4 -(16 15) routing sp4_h_r_36 lc_trk_g3_4 -(16 15) routing sp4_h_r_44 lc_trk_g3_4 -(16 15) routing sp4_v_b_28 lc_trk_g3_4 -(16 15) routing sp4_v_t_25 lc_trk_g3_4 -(16 15) routing sp4_v_t_33 lc_trk_g3_4 -(16 2) routing sp12_h_l_18 lc_trk_g0_5 -(16 2) routing sp12_h_r_13 lc_trk_g0_5 -(16 2) routing sp4_h_l_8 lc_trk_g0_5 -(16 2) routing sp4_h_r_13 lc_trk_g0_5 -(16 2) routing sp4_h_r_5 lc_trk_g0_5 -(16 2) routing sp4_v_b_13 lc_trk_g0_5 -(16 2) routing sp4_v_b_5 lc_trk_g0_5 -(16 2) routing sp4_v_t_8 lc_trk_g0_5 -(16 3) routing sp12_h_r_12 lc_trk_g0_4 -(16 3) routing sp12_h_r_20 lc_trk_g0_4 -(16 3) routing sp4_h_r_12 lc_trk_g0_4 -(16 3) routing sp4_h_r_20 lc_trk_g0_4 -(16 3) routing sp4_h_r_4 lc_trk_g0_4 -(16 3) routing sp4_v_b_20 lc_trk_g0_4 -(16 3) routing sp4_v_b_4 lc_trk_g0_4 -(16 3) routing sp4_v_t_1 lc_trk_g0_4 -(16 4) routing sp12_h_l_6 lc_trk_g1_1 -(16 4) routing sp12_h_r_17 lc_trk_g1_1 -(16 4) routing sp4_h_r_1 lc_trk_g1_1 -(16 4) routing sp4_h_r_17 lc_trk_g1_1 -(16 4) routing sp4_h_r_9 lc_trk_g1_1 -(16 4) routing sp4_v_b_1 lc_trk_g1_1 -(16 4) routing sp4_v_b_17 lc_trk_g1_1 -(16 4) routing sp4_v_b_9 lc_trk_g1_1 -(16 5) routing sp12_h_r_16 lc_trk_g1_0 -(16 5) routing sp12_h_r_8 lc_trk_g1_0 -(16 5) routing sp4_h_l_5 lc_trk_g1_0 -(16 5) routing sp4_h_r_0 lc_trk_g1_0 -(16 5) routing sp4_h_r_8 lc_trk_g1_0 -(16 5) routing sp4_v_b_0 lc_trk_g1_0 -(16 5) routing sp4_v_b_16 lc_trk_g1_0 -(16 5) routing sp4_v_b_8 lc_trk_g1_0 -(16 6) routing sp12_h_l_18 lc_trk_g1_5 -(16 6) routing sp12_h_r_13 lc_trk_g1_5 -(16 6) routing sp4_h_l_8 lc_trk_g1_5 -(16 6) routing sp4_h_r_13 lc_trk_g1_5 -(16 6) routing sp4_h_r_5 lc_trk_g1_5 -(16 6) routing sp4_v_b_13 lc_trk_g1_5 -(16 6) routing sp4_v_b_5 lc_trk_g1_5 -(16 6) routing sp4_v_t_8 lc_trk_g1_5 -(16 7) routing sp12_h_r_12 lc_trk_g1_4 -(16 7) routing sp12_h_r_20 lc_trk_g1_4 -(16 7) routing sp4_h_r_12 lc_trk_g1_4 -(16 7) routing sp4_h_r_20 lc_trk_g1_4 -(16 7) routing sp4_h_r_4 lc_trk_g1_4 -(16 7) routing sp4_v_b_20 lc_trk_g1_4 -(16 7) routing sp4_v_b_4 lc_trk_g1_4 -(16 7) routing sp4_v_t_1 lc_trk_g1_4 -(16 8) routing sp12_v_b_17 lc_trk_g2_1 -(16 8) routing sp12_v_b_9 lc_trk_g2_1 -(16 8) routing sp4_h_l_20 lc_trk_g2_1 -(16 8) routing sp4_h_l_28 lc_trk_g2_1 -(16 8) routing sp4_h_r_25 lc_trk_g2_1 -(16 8) routing sp4_v_b_25 lc_trk_g2_1 -(16 8) routing sp4_v_b_33 lc_trk_g2_1 -(16 8) routing sp4_v_b_41 lc_trk_g2_1 -(16 9) routing sp12_v_b_16 lc_trk_g2_0 -(16 9) routing sp12_v_t_7 lc_trk_g2_0 -(16 9) routing sp4_h_l_13 lc_trk_g2_0 -(16 9) routing sp4_h_l_21 lc_trk_g2_0 -(16 9) routing sp4_h_l_29 lc_trk_g2_0 -(16 9) routing sp4_v_b_40 lc_trk_g2_0 -(16 9) routing sp4_v_t_13 lc_trk_g2_0 -(16 9) routing sp4_v_t_21 lc_trk_g2_0 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => bnr_op_1 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => lft_op_1 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_l_6 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_1 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp12_h_r_17 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_1 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_17 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_h_r_9 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_34 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_1 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_17 lc_trk_g0_1 -(17 0) Enable bit of Mux _local_links/g0_mux_1 => sp4_v_b_9 lc_trk_g0_1 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => bnr_op_0 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => lft_op_0 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_16 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_8 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_l_5 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_8 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_24 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_35 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_0 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_16 lc_trk_g0_0 -(17 1) Enable bit of Mux _local_links/g0_mux_0 => sp4_v_b_8 lc_trk_g0_0 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => bnl_op_5 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => rgt_op_5 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_21 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_b_5 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp12_v_t_10 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_16 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_37 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_h_r_45 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_13 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_r_v_b_37 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_29 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_37 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => sp4_v_b_45 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnl_op_5 lc_trk_g2_5 -(17 10) Enable bit of Mux _local_links/g2_mux_5 => tnr_op_5 lc_trk_g2_5 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => bnl_op_4 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => rgt_op_4 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_12 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_19 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp12_v_t_3 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_l_17 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_36 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_44 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_12 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_r_v_b_36 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_28 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_25 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_33 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnl_op_4 lc_trk_g2_4 -(17 11) Enable bit of Mux _local_links/g2_mux_4 => tnr_op_4 lc_trk_g2_4 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => bnl_op_1 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => rgt_op_1 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_1 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_17 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp12_v_b_9 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_20 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_28 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_h_r_25 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_17 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_r_v_b_41 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_25 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_33 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => sp4_v_b_41 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnl_op_1 lc_trk_g3_1 -(17 12) Enable bit of Mux _local_links/g3_mux_1 => tnr_op_1 lc_trk_g3_1 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => bnl_op_0 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => rgt_op_0 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_0 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_b_16 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp12_v_t_7 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_13 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_21 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_h_l_29 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_16 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_r_v_b_40 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_b_40 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_13 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_21 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnl_op_0 lc_trk_g3_0 -(17 13) Enable bit of Mux _local_links/g3_mux_0 => tnr_op_0 lc_trk_g3_0 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => bnl_op_5 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => rgt_op_5 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_21 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_b_5 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp12_v_t_10 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_l_16 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_37 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_h_r_45 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_29 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_37 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_45 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnl_op_5 lc_trk_g3_5 -(17 14) Enable bit of Mux _local_links/g3_mux_5 => tnr_op_5 lc_trk_g3_5 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => bnl_op_4 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => rgt_op_4 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_b_12 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_19 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp12_v_t_3 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_l_17 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_36 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_h_r_44 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_20 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_r_v_b_44 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_28 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_25 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_33 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnl_op_4 lc_trk_g3_4 -(17 15) Enable bit of Mux _local_links/g3_mux_4 => tnr_op_4 lc_trk_g3_4 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => bnr_op_5 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => glb2local_1 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => lft_op_5 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_l_18 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_13 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp12_h_r_5 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_l_8 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_13 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_5 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_r_v_b_29 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_13 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_b_5 lc_trk_g0_5 -(17 2) Enable bit of Mux _local_links/g0_mux_5 => sp4_v_t_8 lc_trk_g0_5 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => bnr_op_4 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => glb2local_0 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => lft_op_4 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_l_3 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_12 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp12_h_r_20 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_12 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_20 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_4 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_r_v_b_28 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_20 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_4 lc_trk_g0_4 -(17 3) Enable bit of Mux _local_links/g0_mux_4 => sp4_v_t_1 lc_trk_g0_4 -(17 4) Enable bit of Mux _local_links/g1_mux_1 => bnr_op_1 lc_trk_g1_1 -(17 4) Enable bit of Mux _local_links/g1_mux_1 => lft_op_1 lc_trk_g1_1 -(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_l_6 lc_trk_g1_1 -(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_1 lc_trk_g1_1 -(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp12_h_r_17 lc_trk_g1_1 -(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1 -(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_17 lc_trk_g1_1 -(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_9 lc_trk_g1_1 -(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_1 lc_trk_g1_1 -(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_25 lc_trk_g1_1 -(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_1 lc_trk_g1_1 -(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_17 lc_trk_g1_1 -(17 4) Enable bit of Mux _local_links/g1_mux_1 => sp4_v_b_9 lc_trk_g1_1 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => bnr_op_0 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => lft_op_0 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_16 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_8 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_l_5 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_0 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_h_r_8 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_0 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_r_v_b_24 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_0 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_16 lc_trk_g1_0 -(17 5) Enable bit of Mux _local_links/g1_mux_0 => sp4_v_b_8 lc_trk_g1_0 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => bnr_op_5 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => lft_op_5 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_l_18 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_13 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp12_h_r_5 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_l_8 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_13 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_5 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_29 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_5 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_13 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_b_5 lc_trk_g1_5 -(17 6) Enable bit of Mux _local_links/g1_mux_5 => sp4_v_t_8 lc_trk_g1_5 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => bnr_op_4 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => lft_op_4 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_l_3 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_12 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp12_h_r_20 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_12 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_20 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_h_r_4 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_28 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_r_v_b_4 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_20 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_b_4 lc_trk_g1_4 -(17 7) Enable bit of Mux _local_links/g1_mux_4 => sp4_v_t_1 lc_trk_g1_4 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => bnl_op_1 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => rgt_op_1 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_1 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_17 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp12_v_b_9 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_20 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_l_28 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_h_r_25 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_33 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_r_v_b_9 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_25 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_33 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => sp4_v_b_41 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnl_op_1 lc_trk_g2_1 -(17 8) Enable bit of Mux _local_links/g2_mux_1 => tnr_op_1 lc_trk_g2_1 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => bnl_op_0 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => rgt_op_0 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_16 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp12_v_t_7 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_13 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_21 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_29 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_32 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_r_v_b_8 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_40 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_13 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => sp4_v_t_21 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnl_op_0 lc_trk_g2_0 -(17 9) Enable bit of Mux _local_links/g2_mux_0 => tnr_op_0 lc_trk_g2_0 -(18 0) routing bnr_op_1 lc_trk_g0_1 -(18 0) routing lft_op_1 lc_trk_g0_1 -(18 0) routing sp12_h_r_1 lc_trk_g0_1 -(18 0) routing sp4_h_r_17 lc_trk_g0_1 -(18 0) routing sp4_h_r_9 lc_trk_g0_1 -(18 0) routing sp4_v_b_1 lc_trk_g0_1 -(18 0) routing sp4_v_b_9 lc_trk_g0_1 -(18 1) routing bnr_op_1 lc_trk_g0_1 -(18 1) routing sp12_h_r_1 lc_trk_g0_1 -(18 1) routing sp12_h_r_17 lc_trk_g0_1 -(18 1) routing sp4_h_r_1 lc_trk_g0_1 -(18 1) routing sp4_h_r_17 lc_trk_g0_1 -(18 1) routing sp4_r_v_b_34 lc_trk_g0_1 -(18 1) routing sp4_v_b_9 lc_trk_g0_1 -(18 10) routing bnl_op_5 lc_trk_g2_5 -(18 10) routing rgt_op_5 lc_trk_g2_5 -(18 10) routing sp12_v_b_5 lc_trk_g2_5 -(18 10) routing sp4_h_r_37 lc_trk_g2_5 -(18 10) routing sp4_h_r_45 lc_trk_g2_5 -(18 10) routing sp4_v_b_29 lc_trk_g2_5 -(18 10) routing sp4_v_b_37 lc_trk_g2_5 -(18 11) routing bnl_op_5 lc_trk_g2_5 -(18 11) routing sp12_v_b_21 lc_trk_g2_5 -(18 11) routing sp12_v_b_5 lc_trk_g2_5 -(18 11) routing sp4_h_l_16 lc_trk_g2_5 -(18 11) routing sp4_h_r_45 lc_trk_g2_5 -(18 11) routing sp4_r_v_b_37 lc_trk_g2_5 -(18 11) routing sp4_v_b_37 lc_trk_g2_5 -(18 11) routing tnl_op_5 lc_trk_g2_5 -(18 12) routing bnl_op_1 lc_trk_g3_1 -(18 12) routing rgt_op_1 lc_trk_g3_1 -(18 12) routing sp12_v_b_1 lc_trk_g3_1 -(18 12) routing sp4_h_l_20 lc_trk_g3_1 -(18 12) routing sp4_h_l_28 lc_trk_g3_1 -(18 12) routing sp4_v_b_25 lc_trk_g3_1 -(18 12) routing sp4_v_b_33 lc_trk_g3_1 -(18 13) routing bnl_op_1 lc_trk_g3_1 -(18 13) routing sp12_v_b_1 lc_trk_g3_1 -(18 13) routing sp12_v_b_17 lc_trk_g3_1 -(18 13) routing sp4_h_l_28 lc_trk_g3_1 -(18 13) routing sp4_h_r_25 lc_trk_g3_1 -(18 13) routing sp4_r_v_b_41 lc_trk_g3_1 -(18 13) routing sp4_v_b_33 lc_trk_g3_1 -(18 13) routing tnl_op_1 lc_trk_g3_1 -(18 14) routing bnl_op_5 lc_trk_g3_5 -(18 14) routing rgt_op_5 lc_trk_g3_5 -(18 14) routing sp12_v_b_5 lc_trk_g3_5 -(18 14) routing sp4_h_r_37 lc_trk_g3_5 -(18 14) routing sp4_h_r_45 lc_trk_g3_5 -(18 14) routing sp4_v_b_29 lc_trk_g3_5 -(18 14) routing sp4_v_b_37 lc_trk_g3_5 -(18 15) routing bnl_op_5 lc_trk_g3_5 -(18 15) routing sp12_v_b_21 lc_trk_g3_5 -(18 15) routing sp12_v_b_5 lc_trk_g3_5 -(18 15) routing sp4_h_l_16 lc_trk_g3_5 -(18 15) routing sp4_h_r_45 lc_trk_g3_5 -(18 15) routing sp4_r_v_b_45 lc_trk_g3_5 -(18 15) routing sp4_v_b_37 lc_trk_g3_5 -(18 15) routing tnl_op_5 lc_trk_g3_5 -(18 2) routing bnr_op_5 lc_trk_g0_5 -(18 2) routing lft_op_5 lc_trk_g0_5 -(18 2) routing sp12_h_r_5 lc_trk_g0_5 -(18 2) routing sp4_h_l_8 lc_trk_g0_5 -(18 2) routing sp4_h_r_13 lc_trk_g0_5 -(18 2) routing sp4_v_b_13 lc_trk_g0_5 -(18 2) routing sp4_v_b_5 lc_trk_g0_5 -(18 3) routing bnr_op_5 lc_trk_g0_5 -(18 3) routing sp12_h_l_18 lc_trk_g0_5 -(18 3) routing sp12_h_r_5 lc_trk_g0_5 -(18 3) routing sp4_h_l_8 lc_trk_g0_5 -(18 3) routing sp4_h_r_5 lc_trk_g0_5 -(18 3) routing sp4_r_v_b_29 lc_trk_g0_5 -(18 3) routing sp4_v_b_13 lc_trk_g0_5 -(18 4) routing bnr_op_1 lc_trk_g1_1 -(18 4) routing lft_op_1 lc_trk_g1_1 -(18 4) routing sp12_h_r_1 lc_trk_g1_1 -(18 4) routing sp4_h_r_17 lc_trk_g1_1 -(18 4) routing sp4_h_r_9 lc_trk_g1_1 -(18 4) routing sp4_v_b_1 lc_trk_g1_1 -(18 4) routing sp4_v_b_9 lc_trk_g1_1 -(18 5) routing bnr_op_1 lc_trk_g1_1 -(18 5) routing sp12_h_r_1 lc_trk_g1_1 -(18 5) routing sp12_h_r_17 lc_trk_g1_1 -(18 5) routing sp4_h_r_1 lc_trk_g1_1 -(18 5) routing sp4_h_r_17 lc_trk_g1_1 -(18 5) routing sp4_r_v_b_25 lc_trk_g1_1 -(18 5) routing sp4_v_b_9 lc_trk_g1_1 -(18 6) routing bnr_op_5 lc_trk_g1_5 -(18 6) routing lft_op_5 lc_trk_g1_5 -(18 6) routing sp12_h_r_5 lc_trk_g1_5 -(18 6) routing sp4_h_l_8 lc_trk_g1_5 -(18 6) routing sp4_h_r_13 lc_trk_g1_5 -(18 6) routing sp4_v_b_13 lc_trk_g1_5 -(18 6) routing sp4_v_b_5 lc_trk_g1_5 -(18 7) routing bnr_op_5 lc_trk_g1_5 -(18 7) routing sp12_h_l_18 lc_trk_g1_5 -(18 7) routing sp12_h_r_5 lc_trk_g1_5 -(18 7) routing sp4_h_l_8 lc_trk_g1_5 -(18 7) routing sp4_h_r_5 lc_trk_g1_5 -(18 7) routing sp4_r_v_b_29 lc_trk_g1_5 -(18 7) routing sp4_v_b_13 lc_trk_g1_5 -(18 8) routing bnl_op_1 lc_trk_g2_1 -(18 8) routing rgt_op_1 lc_trk_g2_1 -(18 8) routing sp12_v_b_1 lc_trk_g2_1 -(18 8) routing sp4_h_l_20 lc_trk_g2_1 -(18 8) routing sp4_h_l_28 lc_trk_g2_1 -(18 8) routing sp4_v_b_25 lc_trk_g2_1 -(18 8) routing sp4_v_b_33 lc_trk_g2_1 -(18 9) routing bnl_op_1 lc_trk_g2_1 -(18 9) routing sp12_v_b_1 lc_trk_g2_1 -(18 9) routing sp12_v_b_17 lc_trk_g2_1 -(18 9) routing sp4_h_l_28 lc_trk_g2_1 -(18 9) routing sp4_h_r_25 lc_trk_g2_1 -(18 9) routing sp4_r_v_b_33 lc_trk_g2_1 -(18 9) routing sp4_v_b_33 lc_trk_g2_1 -(18 9) routing tnl_op_1 lc_trk_g2_1 -(19 0) Enable bit of Mux _span_links/cross_mux_vert_1 => sp12_v_t_0 sp4_v_b_13 -(19 1) Enable bit of Mux _span_links/cross_mux_vert_0 => sp12_v_b_1 sp4_v_t_1 -(19 10) Enable bit of Mux _span_links/cross_mux_vert_11 => sp12_v_b_23 sp4_v_t_10 -(19 11) Enable bit of Mux _span_links/cross_mux_vert_10 => sp12_v_b_21 sp4_v_b_22 -(19 12) Enable bit of Mux _span_links/cross_mux_horz_1 => sp12_h_r_2 sp4_h_r_13 -(19 13) Enable bit of Mux _span_links/cross_mux_horz_0 => sp12_h_r_0 sp4_h_r_12 -(19 14) Enable bit of Mux _span_links/cross_mux_horz_3 => sp12_h_l_5 sp4_h_l_2 -(19 15) Enable bit of Mux _span_links/cross_mux_horz_2 => sp12_h_l_3 sp4_h_l_3 -(19 2) Enable bit of Mux _span_links/cross_mux_vert_3 => sp12_v_b_7 sp4_v_t_2 -(19 3) Enable bit of Mux _span_links/cross_mux_vert_2 => sp12_v_b_5 sp4_v_b_14 -(19 4) Enable bit of Mux _span_links/cross_mux_vert_5 => sp12_v_b_11 sp4_v_b_17 -(19 5) Enable bit of Mux _span_links/cross_mux_vert_4 => sp12_v_b_9 sp4_v_b_16 -(19 6) Enable bit of Mux _span_links/cross_mux_vert_7 => sp12_v_t_12 sp4_v_b_19 -(19 7) Enable bit of Mux _span_links/cross_mux_vert_6 => sp12_v_t_10 sp4_v_t_7 -(19 8) Enable bit of Mux _span_links/cross_mux_vert_9 => sp12_v_t_16 sp4_v_t_8 -(19 9) Enable bit of Mux _span_links/cross_mux_vert_8 => sp12_v_b_17 sp4_v_b_20 -(2 0) Enable bit of Mux _span_links/cross_mux_horz_4 => sp12_h_r_8 sp4_h_l_5 -(2 10) Enable bit of Mux _span_links/cross_mux_horz_9 => sp12_h_r_18 sp4_h_l_8 -(2 12) Enable bit of Mux _span_links/cross_mux_horz_10 => sp12_h_r_20 sp4_h_r_22 -(2 14) Enable bit of Mux _span_links/cross_mux_horz_11 => sp12_h_l_21 sp4_h_l_10 -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_bram/ram/WCLK -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_2 wire_bram/ram/WCLK -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_3 wire_bram/ram/WCLK -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_bram/ram/WCLK -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_5 wire_bram/ram/WCLK -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_6 wire_bram/ram/WCLK -(2 2) Enable bit of Mux _global_links/clk_mux => glb_netwk_7 wire_bram/ram/WCLK -(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g0_0 wire_bram/ram/WCLK -(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g1_1 wire_bram/ram/WCLK -(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g2_0 wire_bram/ram/WCLK -(2 2) Enable bit of Mux _global_links/clk_mux => lc_trk_g3_1 wire_bram/ram/WCLK -(2 3) routing lc_trk_g0_0 wire_bram/ram/WCLK -(2 3) routing lc_trk_g1_1 wire_bram/ram/WCLK -(2 3) routing lc_trk_g2_0 wire_bram/ram/WCLK -(2 3) routing lc_trk_g3_1 wire_bram/ram/WCLK -(2 4) Enable bit of Mux _span_links/cross_mux_horz_6 => sp12_h_r_12 sp4_h_l_7 -(2 6) Enable bit of Mux _span_links/cross_mux_horz_7 => sp12_h_l_13 sp4_h_r_19 -(2 8) Enable bit of Mux _span_links/cross_mux_horz_8 => sp12_h_r_16 sp4_h_r_20 -(21 0) routing bnr_op_3 lc_trk_g0_3 -(21 0) routing lft_op_3 lc_trk_g0_3 -(21 0) routing sp12_h_l_0 lc_trk_g0_3 -(21 0) routing sp4_h_r_11 lc_trk_g0_3 -(21 0) routing sp4_h_r_19 lc_trk_g0_3 -(21 0) routing sp4_v_b_11 lc_trk_g0_3 -(21 0) routing sp4_v_b_3 lc_trk_g0_3 -(21 1) routing bnr_op_3 lc_trk_g0_3 -(21 1) routing sp12_h_l_0 lc_trk_g0_3 -(21 1) routing sp12_h_l_16 lc_trk_g0_3 -(21 1) routing sp4_h_r_19 lc_trk_g0_3 -(21 1) routing sp4_h_r_3 lc_trk_g0_3 -(21 1) routing sp4_r_v_b_32 lc_trk_g0_3 -(21 1) routing sp4_v_b_11 lc_trk_g0_3 -(21 10) routing bnl_op_7 lc_trk_g2_7 -(21 10) routing rgt_op_7 lc_trk_g2_7 -(21 10) routing sp12_v_b_7 lc_trk_g2_7 -(21 10) routing sp4_h_l_26 lc_trk_g2_7 -(21 10) routing sp4_h_r_47 lc_trk_g2_7 -(21 10) routing sp4_v_t_18 lc_trk_g2_7 -(21 10) routing sp4_v_t_26 lc_trk_g2_7 -(21 11) routing bnl_op_7 lc_trk_g2_7 -(21 11) routing sp12_v_b_23 lc_trk_g2_7 -(21 11) routing sp12_v_b_7 lc_trk_g2_7 -(21 11) routing sp4_h_l_18 lc_trk_g2_7 -(21 11) routing sp4_h_r_47 lc_trk_g2_7 -(21 11) routing sp4_r_v_b_39 lc_trk_g2_7 -(21 11) routing sp4_v_t_26 lc_trk_g2_7 -(21 11) routing tnl_op_7 lc_trk_g2_7 -(21 12) routing bnl_op_3 lc_trk_g3_3 -(21 12) routing rgt_op_3 lc_trk_g3_3 -(21 12) routing sp12_v_t_0 lc_trk_g3_3 -(21 12) routing sp4_h_l_30 lc_trk_g3_3 -(21 12) routing sp4_h_r_35 lc_trk_g3_3 -(21 12) routing sp4_v_t_14 lc_trk_g3_3 -(21 12) routing sp4_v_t_22 lc_trk_g3_3 -(21 13) routing bnl_op_3 lc_trk_g3_3 -(21 13) routing sp12_v_t_0 lc_trk_g3_3 -(21 13) routing sp12_v_t_16 lc_trk_g3_3 -(21 13) routing sp4_h_l_30 lc_trk_g3_3 -(21 13) routing sp4_h_r_27 lc_trk_g3_3 -(21 13) routing sp4_r_v_b_43 lc_trk_g3_3 -(21 13) routing sp4_v_t_22 lc_trk_g3_3 -(21 13) routing tnl_op_3 lc_trk_g3_3 -(21 14) routing bnl_op_7 lc_trk_g3_7 -(21 14) routing rgt_op_7 lc_trk_g3_7 -(21 14) routing sp12_v_b_7 lc_trk_g3_7 -(21 14) routing sp4_h_l_26 lc_trk_g3_7 -(21 14) routing sp4_h_r_47 lc_trk_g3_7 -(21 14) routing sp4_v_t_18 lc_trk_g3_7 -(21 14) routing sp4_v_t_26 lc_trk_g3_7 -(21 15) routing bnl_op_7 lc_trk_g3_7 -(21 15) routing sp12_v_b_23 lc_trk_g3_7 -(21 15) routing sp12_v_b_7 lc_trk_g3_7 -(21 15) routing sp4_h_l_18 lc_trk_g3_7 -(21 15) routing sp4_h_r_47 lc_trk_g3_7 -(21 15) routing sp4_r_v_b_47 lc_trk_g3_7 -(21 15) routing sp4_v_t_26 lc_trk_g3_7 -(21 15) routing tnl_op_7 lc_trk_g3_7 -(21 2) routing bnr_op_7 lc_trk_g0_7 -(21 2) routing lft_op_7 lc_trk_g0_7 -(21 2) routing sp12_h_l_4 lc_trk_g0_7 -(21 2) routing sp4_h_l_10 lc_trk_g0_7 -(21 2) routing sp4_h_l_2 lc_trk_g0_7 -(21 2) routing sp4_v_b_7 lc_trk_g0_7 -(21 2) routing sp4_v_t_2 lc_trk_g0_7 -(21 3) routing bnr_op_7 lc_trk_g0_7 -(21 3) routing sp12_h_l_4 lc_trk_g0_7 -(21 3) routing sp12_h_r_23 lc_trk_g0_7 -(21 3) routing sp4_h_l_10 lc_trk_g0_7 -(21 3) routing sp4_h_r_7 lc_trk_g0_7 -(21 3) routing sp4_r_v_b_31 lc_trk_g0_7 -(21 3) routing sp4_v_t_2 lc_trk_g0_7 -(21 4) routing bnr_op_3 lc_trk_g1_3 -(21 4) routing lft_op_3 lc_trk_g1_3 -(21 4) routing sp12_h_l_0 lc_trk_g1_3 -(21 4) routing sp4_h_r_11 lc_trk_g1_3 -(21 4) routing sp4_h_r_19 lc_trk_g1_3 -(21 4) routing sp4_v_b_11 lc_trk_g1_3 -(21 4) routing sp4_v_b_3 lc_trk_g1_3 -(21 5) routing bnr_op_3 lc_trk_g1_3 -(21 5) routing sp12_h_l_0 lc_trk_g1_3 -(21 5) routing sp12_h_l_16 lc_trk_g1_3 -(21 5) routing sp4_h_r_19 lc_trk_g1_3 -(21 5) routing sp4_h_r_3 lc_trk_g1_3 -(21 5) routing sp4_r_v_b_27 lc_trk_g1_3 -(21 5) routing sp4_v_b_11 lc_trk_g1_3 -(21 6) routing bnr_op_7 lc_trk_g1_7 -(21 6) routing lft_op_7 lc_trk_g1_7 -(21 6) routing sp12_h_l_4 lc_trk_g1_7 -(21 6) routing sp4_h_l_10 lc_trk_g1_7 -(21 6) routing sp4_h_l_2 lc_trk_g1_7 -(21 6) routing sp4_v_b_7 lc_trk_g1_7 -(21 6) routing sp4_v_t_2 lc_trk_g1_7 -(21 7) routing bnr_op_7 lc_trk_g1_7 -(21 7) routing sp12_h_l_4 lc_trk_g1_7 -(21 7) routing sp12_h_r_23 lc_trk_g1_7 -(21 7) routing sp4_h_l_10 lc_trk_g1_7 -(21 7) routing sp4_h_r_7 lc_trk_g1_7 -(21 7) routing sp4_r_v_b_31 lc_trk_g1_7 -(21 7) routing sp4_v_t_2 lc_trk_g1_7 -(21 8) routing bnl_op_3 lc_trk_g2_3 -(21 8) routing rgt_op_3 lc_trk_g2_3 -(21 8) routing sp12_v_t_0 lc_trk_g2_3 -(21 8) routing sp4_h_l_30 lc_trk_g2_3 -(21 8) routing sp4_h_r_35 lc_trk_g2_3 -(21 8) routing sp4_v_t_14 lc_trk_g2_3 -(21 8) routing sp4_v_t_22 lc_trk_g2_3 -(21 9) routing bnl_op_3 lc_trk_g2_3 -(21 9) routing sp12_v_t_0 lc_trk_g2_3 -(21 9) routing sp12_v_t_16 lc_trk_g2_3 -(21 9) routing sp4_h_l_30 lc_trk_g2_3 -(21 9) routing sp4_h_r_27 lc_trk_g2_3 -(21 9) routing sp4_r_v_b_35 lc_trk_g2_3 -(21 9) routing sp4_v_t_22 lc_trk_g2_3 -(21 9) routing tnl_op_3 lc_trk_g2_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => bnr_op_3 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => lft_op_3 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_0 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_l_16 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp12_h_r_11 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_11 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_19 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_h_r_3 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_27 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_r_v_b_32 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_11 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_19 lc_trk_g0_3 -(22 0) Enable bit of Mux _local_links/g0_mux_3 => sp4_v_b_3 lc_trk_g0_3 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => bnr_op_2 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => lft_op_2 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_10 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_18 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp12_h_r_2 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_l_7 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_10 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_h_r_2 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_26 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_r_v_b_33 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_10 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_b_2 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => sp4_v_t_7 lc_trk_g0_2 -(22 1) Enable bit of Mux _local_links/g0_mux_2 => top_op_2 lc_trk_g0_2 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => bnl_op_7 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => rgt_op_7 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_23 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_b_7 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp12_v_t_12 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_18 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_l_26 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_h_r_47 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_15 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_r_v_b_39 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_b_47 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_18 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_26 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnl_op_7 lc_trk_g2_7 -(22 10) Enable bit of Mux _local_links/g2_mux_7 => tnr_op_7 lc_trk_g2_7 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => bnl_op_6 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => rgt_op_6 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_14 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_b_6 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp12_v_t_21 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_l_27 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_30 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_h_r_46 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_14 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_r_v_b_38 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_30 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_38 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => sp4_v_b_46 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnl_op_6 lc_trk_g2_6 -(22 11) Enable bit of Mux _local_links/g2_mux_6 => tnr_op_6 lc_trk_g2_6 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => bnl_op_3 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => rgt_op_3 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_b_11 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_0 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp12_v_t_16 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_l_30 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_27 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_h_r_35 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_19 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_r_v_b_43 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_14 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_22 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => sp4_v_t_30 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnl_op_3 lc_trk_g3_3 -(22 12) Enable bit of Mux _local_links/g3_mux_3 => tnr_op_3 lc_trk_g3_3 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => bnl_op_2 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => rgt_op_2 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_b_2 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_17 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp12_v_t_9 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_l_15 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_34 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_h_r_42 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_18 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_r_v_b_42 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_b_26 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_23 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => sp4_v_t_31 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnl_op_2 lc_trk_g3_2 -(22 13) Enable bit of Mux _local_links/g3_mux_2 => tnr_op_2 lc_trk_g3_2 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => bnl_op_7 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => rgt_op_7 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_23 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_b_7 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_18 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_l_26 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_h_r_47 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_23 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_b_47 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_18 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => sp4_v_t_26 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnl_op_7 lc_trk_g3_7 -(22 14) Enable bit of Mux _local_links/g3_mux_7 => tnr_op_7 lc_trk_g3_7 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => bnl_op_6 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => rgt_op_6 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_14 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_b_6 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp12_v_t_21 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_l_27 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_30 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_h_r_46 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_22 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_r_v_b_46 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_30 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_38 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => sp4_v_b_46 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnl_op_6 lc_trk_g3_6 -(22 15) Enable bit of Mux _local_links/g3_mux_6 => tnr_op_6 lc_trk_g3_6 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => bnr_op_7 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => glb2local_3 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => lft_op_7 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_12 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_l_4 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp12_h_r_23 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_10 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_l_2 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_h_r_7 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_r_v_b_31 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_b_7 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_10 lc_trk_g0_7 -(22 2) Enable bit of Mux _local_links/g0_mux_7 => sp4_v_t_2 lc_trk_g0_7 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => bnr_op_6 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => glb2local_2 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => lft_op_6 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_13 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_21 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp12_h_l_5 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_l_3 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_22 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_h_r_6 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_r_v_b_30 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_14 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_22 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => sp4_v_b_6 lc_trk_g0_6 -(22 3) Enable bit of Mux _local_links/g0_mux_6 => top_op_6 lc_trk_g0_6 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => bnr_op_3 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => lft_op_3 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_0 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_l_16 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_11 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_11 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_19 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_h_r_3 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_27 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_r_v_b_3 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_11 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_19 lc_trk_g1_3 -(22 4) Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_3 lc_trk_g1_3 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => bnr_op_2 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => lft_op_2 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_10 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_18 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp12_h_r_2 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_l_7 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_10 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_h_r_2 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_2 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_r_v_b_26 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_10 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_b_2 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => sp4_v_t_7 lc_trk_g1_2 -(22 5) Enable bit of Mux _local_links/g1_mux_2 => top_op_2 lc_trk_g1_2 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => bnr_op_7 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => lft_op_7 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_12 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_4 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_23 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_10 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_l_2 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_h_r_7 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_31 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_r_v_b_7 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_b_7 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_10 lc_trk_g1_7 -(22 6) Enable bit of Mux _local_links/g1_mux_7 => sp4_v_t_2 lc_trk_g1_7 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => bnr_op_6 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => lft_op_6 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_13 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_21 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp12_h_l_5 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_l_3 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_22 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_h_r_6 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_30 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_r_v_b_6 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_14 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_22 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => sp4_v_b_6 lc_trk_g1_6 -(22 7) Enable bit of Mux _local_links/g1_mux_6 => top_op_6 lc_trk_g1_6 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => bnl_op_3 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => rgt_op_3 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_b_11 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_0 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp12_v_t_16 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_l_30 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_27 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_h_r_35 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_11 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_r_v_b_35 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_14 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_22 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => sp4_v_t_30 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnl_op_3 lc_trk_g2_3 -(22 8) Enable bit of Mux _local_links/g2_mux_3 => tnr_op_3 lc_trk_g2_3 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => bnl_op_2 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => rgt_op_2 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_b_2 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_17 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp12_v_t_9 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_l_15 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_34 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_42 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_10 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_r_v_b_34 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_b_26 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_23 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => sp4_v_t_31 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnl_op_2 lc_trk_g2_2 -(22 9) Enable bit of Mux _local_links/g2_mux_2 => tnr_op_2 lc_trk_g2_2 -(23 0) routing sp12_h_l_16 lc_trk_g0_3 -(23 0) routing sp12_h_r_11 lc_trk_g0_3 -(23 0) routing sp4_h_r_11 lc_trk_g0_3 -(23 0) routing sp4_h_r_19 lc_trk_g0_3 -(23 0) routing sp4_h_r_3 lc_trk_g0_3 -(23 0) routing sp4_v_b_11 lc_trk_g0_3 -(23 0) routing sp4_v_b_19 lc_trk_g0_3 -(23 0) routing sp4_v_b_3 lc_trk_g0_3 -(23 1) routing sp12_h_r_10 lc_trk_g0_2 -(23 1) routing sp12_h_r_18 lc_trk_g0_2 -(23 1) routing sp4_h_l_7 lc_trk_g0_2 -(23 1) routing sp4_h_r_10 lc_trk_g0_2 -(23 1) routing sp4_h_r_2 lc_trk_g0_2 -(23 1) routing sp4_v_b_10 lc_trk_g0_2 -(23 1) routing sp4_v_b_2 lc_trk_g0_2 -(23 1) routing sp4_v_t_7 lc_trk_g0_2 -(23 10) routing sp12_v_b_23 lc_trk_g2_7 -(23 10) routing sp12_v_t_12 lc_trk_g2_7 -(23 10) routing sp4_h_l_18 lc_trk_g2_7 -(23 10) routing sp4_h_l_26 lc_trk_g2_7 -(23 10) routing sp4_h_r_47 lc_trk_g2_7 -(23 10) routing sp4_v_b_47 lc_trk_g2_7 -(23 10) routing sp4_v_t_18 lc_trk_g2_7 -(23 10) routing sp4_v_t_26 lc_trk_g2_7 -(23 11) routing sp12_v_b_14 lc_trk_g2_6 -(23 11) routing sp12_v_t_21 lc_trk_g2_6 -(23 11) routing sp4_h_l_27 lc_trk_g2_6 -(23 11) routing sp4_h_r_30 lc_trk_g2_6 -(23 11) routing sp4_h_r_46 lc_trk_g2_6 -(23 11) routing sp4_v_b_30 lc_trk_g2_6 -(23 11) routing sp4_v_b_38 lc_trk_g2_6 -(23 11) routing sp4_v_b_46 lc_trk_g2_6 -(23 12) routing sp12_v_b_11 lc_trk_g3_3 -(23 12) routing sp12_v_t_16 lc_trk_g3_3 -(23 12) routing sp4_h_l_30 lc_trk_g3_3 -(23 12) routing sp4_h_r_27 lc_trk_g3_3 -(23 12) routing sp4_h_r_35 lc_trk_g3_3 -(23 12) routing sp4_v_t_14 lc_trk_g3_3 -(23 12) routing sp4_v_t_22 lc_trk_g3_3 -(23 12) routing sp4_v_t_30 lc_trk_g3_3 -(23 13) routing sp12_v_t_17 lc_trk_g3_2 -(23 13) routing sp12_v_t_9 lc_trk_g3_2 -(23 13) routing sp4_h_l_15 lc_trk_g3_2 -(23 13) routing sp4_h_r_34 lc_trk_g3_2 -(23 13) routing sp4_h_r_42 lc_trk_g3_2 -(23 13) routing sp4_v_b_26 lc_trk_g3_2 -(23 13) routing sp4_v_t_23 lc_trk_g3_2 -(23 13) routing sp4_v_t_31 lc_trk_g3_2 -(23 14) routing sp12_v_b_23 lc_trk_g3_7 -(23 14) routing sp12_v_t_12 lc_trk_g3_7 -(23 14) routing sp4_h_l_18 lc_trk_g3_7 -(23 14) routing sp4_h_l_26 lc_trk_g3_7 -(23 14) routing sp4_h_r_47 lc_trk_g3_7 -(23 14) routing sp4_v_b_47 lc_trk_g3_7 -(23 14) routing sp4_v_t_18 lc_trk_g3_7 -(23 14) routing sp4_v_t_26 lc_trk_g3_7 -(23 15) routing sp12_v_b_14 lc_trk_g3_6 -(23 15) routing sp12_v_t_21 lc_trk_g3_6 -(23 15) routing sp4_h_l_27 lc_trk_g3_6 -(23 15) routing sp4_h_r_30 lc_trk_g3_6 -(23 15) routing sp4_h_r_46 lc_trk_g3_6 -(23 15) routing sp4_v_b_30 lc_trk_g3_6 -(23 15) routing sp4_v_b_38 lc_trk_g3_6 -(23 15) routing sp4_v_b_46 lc_trk_g3_6 -(23 2) routing sp12_h_l_12 lc_trk_g0_7 -(23 2) routing sp12_h_r_23 lc_trk_g0_7 -(23 2) routing sp4_h_l_10 lc_trk_g0_7 -(23 2) routing sp4_h_l_2 lc_trk_g0_7 -(23 2) routing sp4_h_r_7 lc_trk_g0_7 -(23 2) routing sp4_v_b_7 lc_trk_g0_7 -(23 2) routing sp4_v_t_10 lc_trk_g0_7 -(23 2) routing sp4_v_t_2 lc_trk_g0_7 -(23 3) routing sp12_h_l_13 lc_trk_g0_6 -(23 3) routing sp12_h_l_21 lc_trk_g0_6 -(23 3) routing sp4_h_l_3 lc_trk_g0_6 -(23 3) routing sp4_h_r_22 lc_trk_g0_6 -(23 3) routing sp4_h_r_6 lc_trk_g0_6 -(23 3) routing sp4_v_b_14 lc_trk_g0_6 -(23 3) routing sp4_v_b_22 lc_trk_g0_6 -(23 3) routing sp4_v_b_6 lc_trk_g0_6 -(23 4) routing sp12_h_l_16 lc_trk_g1_3 -(23 4) routing sp12_h_r_11 lc_trk_g1_3 -(23 4) routing sp4_h_r_11 lc_trk_g1_3 -(23 4) routing sp4_h_r_19 lc_trk_g1_3 -(23 4) routing sp4_h_r_3 lc_trk_g1_3 -(23 4) routing sp4_v_b_11 lc_trk_g1_3 -(23 4) routing sp4_v_b_19 lc_trk_g1_3 -(23 4) routing sp4_v_b_3 lc_trk_g1_3 -(23 5) routing sp12_h_r_10 lc_trk_g1_2 -(23 5) routing sp12_h_r_18 lc_trk_g1_2 -(23 5) routing sp4_h_l_7 lc_trk_g1_2 -(23 5) routing sp4_h_r_10 lc_trk_g1_2 -(23 5) routing sp4_h_r_2 lc_trk_g1_2 -(23 5) routing sp4_v_b_10 lc_trk_g1_2 -(23 5) routing sp4_v_b_2 lc_trk_g1_2 -(23 5) routing sp4_v_t_7 lc_trk_g1_2 -(23 6) routing sp12_h_l_12 lc_trk_g1_7 -(23 6) routing sp12_h_r_23 lc_trk_g1_7 -(23 6) routing sp4_h_l_10 lc_trk_g1_7 -(23 6) routing sp4_h_l_2 lc_trk_g1_7 -(23 6) routing sp4_h_r_7 lc_trk_g1_7 -(23 6) routing sp4_v_b_7 lc_trk_g1_7 -(23 6) routing sp4_v_t_10 lc_trk_g1_7 -(23 6) routing sp4_v_t_2 lc_trk_g1_7 -(23 7) routing sp12_h_l_13 lc_trk_g1_6 -(23 7) routing sp12_h_l_21 lc_trk_g1_6 -(23 7) routing sp4_h_l_3 lc_trk_g1_6 -(23 7) routing sp4_h_r_22 lc_trk_g1_6 -(23 7) routing sp4_h_r_6 lc_trk_g1_6 -(23 7) routing sp4_v_b_14 lc_trk_g1_6 -(23 7) routing sp4_v_b_22 lc_trk_g1_6 -(23 7) routing sp4_v_b_6 lc_trk_g1_6 -(23 8) routing sp12_v_b_11 lc_trk_g2_3 -(23 8) routing sp12_v_t_16 lc_trk_g2_3 -(23 8) routing sp4_h_l_30 lc_trk_g2_3 -(23 8) routing sp4_h_r_27 lc_trk_g2_3 -(23 8) routing sp4_h_r_35 lc_trk_g2_3 -(23 8) routing sp4_v_t_14 lc_trk_g2_3 -(23 8) routing sp4_v_t_22 lc_trk_g2_3 -(23 8) routing sp4_v_t_30 lc_trk_g2_3 -(23 9) routing sp12_v_t_17 lc_trk_g2_2 -(23 9) routing sp12_v_t_9 lc_trk_g2_2 -(23 9) routing sp4_h_l_15 lc_trk_g2_2 -(23 9) routing sp4_h_r_34 lc_trk_g2_2 -(23 9) routing sp4_h_r_42 lc_trk_g2_2 -(23 9) routing sp4_v_b_26 lc_trk_g2_2 -(23 9) routing sp4_v_t_23 lc_trk_g2_2 -(23 9) routing sp4_v_t_31 lc_trk_g2_2 -(24 0) routing lft_op_3 lc_trk_g0_3 -(24 0) routing sp12_h_l_0 lc_trk_g0_3 -(24 0) routing sp4_h_r_11 lc_trk_g0_3 -(24 0) routing sp4_h_r_19 lc_trk_g0_3 -(24 0) routing sp4_h_r_3 lc_trk_g0_3 -(24 0) routing sp4_v_b_19 lc_trk_g0_3 -(24 1) routing lft_op_2 lc_trk_g0_2 -(24 1) routing sp12_h_r_2 lc_trk_g0_2 -(24 1) routing sp4_h_l_7 lc_trk_g0_2 -(24 1) routing sp4_h_r_10 lc_trk_g0_2 -(24 1) routing sp4_h_r_2 lc_trk_g0_2 -(24 1) routing sp4_v_t_7 lc_trk_g0_2 -(24 1) routing top_op_2 lc_trk_g0_2 -(24 10) routing rgt_op_7 lc_trk_g2_7 -(24 10) routing sp12_v_b_7 lc_trk_g2_7 -(24 10) routing sp4_h_l_18 lc_trk_g2_7 -(24 10) routing sp4_h_l_26 lc_trk_g2_7 -(24 10) routing sp4_h_r_47 lc_trk_g2_7 -(24 10) routing sp4_v_b_47 lc_trk_g2_7 -(24 10) routing tnl_op_7 lc_trk_g2_7 -(24 10) routing tnr_op_7 lc_trk_g2_7 -(24 11) routing rgt_op_6 lc_trk_g2_6 -(24 11) routing sp12_v_b_6 lc_trk_g2_6 -(24 11) routing sp4_h_l_27 lc_trk_g2_6 -(24 11) routing sp4_h_r_30 lc_trk_g2_6 -(24 11) routing sp4_h_r_46 lc_trk_g2_6 -(24 11) routing sp4_v_b_46 lc_trk_g2_6 -(24 11) routing tnl_op_6 lc_trk_g2_6 -(24 11) routing tnr_op_6 lc_trk_g2_6 -(24 12) routing rgt_op_3 lc_trk_g3_3 -(24 12) routing sp12_v_t_0 lc_trk_g3_3 -(24 12) routing sp4_h_l_30 lc_trk_g3_3 -(24 12) routing sp4_h_r_27 lc_trk_g3_3 -(24 12) routing sp4_h_r_35 lc_trk_g3_3 -(24 12) routing sp4_v_t_30 lc_trk_g3_3 -(24 12) routing tnl_op_3 lc_trk_g3_3 -(24 12) routing tnr_op_3 lc_trk_g3_3 -(24 13) routing rgt_op_2 lc_trk_g3_2 -(24 13) routing sp12_v_b_2 lc_trk_g3_2 -(24 13) routing sp4_h_l_15 lc_trk_g3_2 -(24 13) routing sp4_h_r_34 lc_trk_g3_2 -(24 13) routing sp4_h_r_42 lc_trk_g3_2 -(24 13) routing sp4_v_t_31 lc_trk_g3_2 -(24 13) routing tnl_op_2 lc_trk_g3_2 -(24 13) routing tnr_op_2 lc_trk_g3_2 -(24 14) routing rgt_op_7 lc_trk_g3_7 -(24 14) routing sp12_v_b_7 lc_trk_g3_7 -(24 14) routing sp4_h_l_18 lc_trk_g3_7 -(24 14) routing sp4_h_l_26 lc_trk_g3_7 -(24 14) routing sp4_h_r_47 lc_trk_g3_7 -(24 14) routing sp4_v_b_47 lc_trk_g3_7 -(24 14) routing tnl_op_7 lc_trk_g3_7 -(24 14) routing tnr_op_7 lc_trk_g3_7 -(24 15) routing rgt_op_6 lc_trk_g3_6 -(24 15) routing sp12_v_b_6 lc_trk_g3_6 -(24 15) routing sp4_h_l_27 lc_trk_g3_6 -(24 15) routing sp4_h_r_30 lc_trk_g3_6 -(24 15) routing sp4_h_r_46 lc_trk_g3_6 -(24 15) routing sp4_v_b_46 lc_trk_g3_6 -(24 15) routing tnl_op_6 lc_trk_g3_6 -(24 15) routing tnr_op_6 lc_trk_g3_6 -(24 2) routing lft_op_7 lc_trk_g0_7 -(24 2) routing sp12_h_l_4 lc_trk_g0_7 -(24 2) routing sp4_h_l_10 lc_trk_g0_7 -(24 2) routing sp4_h_l_2 lc_trk_g0_7 -(24 2) routing sp4_h_r_7 lc_trk_g0_7 -(24 2) routing sp4_v_t_10 lc_trk_g0_7 -(24 3) routing lft_op_6 lc_trk_g0_6 -(24 3) routing sp12_h_l_5 lc_trk_g0_6 -(24 3) routing sp4_h_l_3 lc_trk_g0_6 -(24 3) routing sp4_h_r_22 lc_trk_g0_6 -(24 3) routing sp4_h_r_6 lc_trk_g0_6 -(24 3) routing sp4_v_b_22 lc_trk_g0_6 -(24 3) routing top_op_6 lc_trk_g0_6 -(24 4) routing lft_op_3 lc_trk_g1_3 -(24 4) routing sp12_h_l_0 lc_trk_g1_3 -(24 4) routing sp4_h_r_11 lc_trk_g1_3 -(24 4) routing sp4_h_r_19 lc_trk_g1_3 -(24 4) routing sp4_h_r_3 lc_trk_g1_3 -(24 4) routing sp4_v_b_19 lc_trk_g1_3 -(24 5) routing lft_op_2 lc_trk_g1_2 -(24 5) routing sp12_h_r_2 lc_trk_g1_2 -(24 5) routing sp4_h_l_7 lc_trk_g1_2 -(24 5) routing sp4_h_r_10 lc_trk_g1_2 -(24 5) routing sp4_h_r_2 lc_trk_g1_2 -(24 5) routing sp4_v_t_7 lc_trk_g1_2 -(24 5) routing top_op_2 lc_trk_g1_2 -(24 6) routing lft_op_7 lc_trk_g1_7 -(24 6) routing sp12_h_l_4 lc_trk_g1_7 -(24 6) routing sp4_h_l_10 lc_trk_g1_7 -(24 6) routing sp4_h_l_2 lc_trk_g1_7 -(24 6) routing sp4_h_r_7 lc_trk_g1_7 -(24 6) routing sp4_v_t_10 lc_trk_g1_7 -(24 7) routing lft_op_6 lc_trk_g1_6 -(24 7) routing sp12_h_l_5 lc_trk_g1_6 -(24 7) routing sp4_h_l_3 lc_trk_g1_6 -(24 7) routing sp4_h_r_22 lc_trk_g1_6 -(24 7) routing sp4_h_r_6 lc_trk_g1_6 -(24 7) routing sp4_v_b_22 lc_trk_g1_6 -(24 7) routing top_op_6 lc_trk_g1_6 -(24 8) routing rgt_op_3 lc_trk_g2_3 -(24 8) routing sp12_v_t_0 lc_trk_g2_3 -(24 8) routing sp4_h_l_30 lc_trk_g2_3 -(24 8) routing sp4_h_r_27 lc_trk_g2_3 -(24 8) routing sp4_h_r_35 lc_trk_g2_3 -(24 8) routing sp4_v_t_30 lc_trk_g2_3 -(24 8) routing tnl_op_3 lc_trk_g2_3 -(24 8) routing tnr_op_3 lc_trk_g2_3 -(24 9) routing rgt_op_2 lc_trk_g2_2 -(24 9) routing sp12_v_b_2 lc_trk_g2_2 -(24 9) routing sp4_h_l_15 lc_trk_g2_2 -(24 9) routing sp4_h_r_34 lc_trk_g2_2 -(24 9) routing sp4_h_r_42 lc_trk_g2_2 -(24 9) routing sp4_v_t_31 lc_trk_g2_2 -(24 9) routing tnl_op_2 lc_trk_g2_2 -(24 9) routing tnr_op_2 lc_trk_g2_2 -(25 0) routing bnr_op_2 lc_trk_g0_2 -(25 0) routing lft_op_2 lc_trk_g0_2 -(25 0) routing sp12_h_r_2 lc_trk_g0_2 -(25 0) routing sp4_h_l_7 lc_trk_g0_2 -(25 0) routing sp4_h_r_10 lc_trk_g0_2 -(25 0) routing sp4_v_b_10 lc_trk_g0_2 -(25 0) routing sp4_v_b_2 lc_trk_g0_2 -(25 1) routing bnr_op_2 lc_trk_g0_2 -(25 1) routing sp12_h_r_18 lc_trk_g0_2 -(25 1) routing sp12_h_r_2 lc_trk_g0_2 -(25 1) routing sp4_h_l_7 lc_trk_g0_2 -(25 1) routing sp4_h_r_2 lc_trk_g0_2 -(25 1) routing sp4_r_v_b_33 lc_trk_g0_2 -(25 1) routing sp4_v_b_10 lc_trk_g0_2 -(25 1) routing top_op_2 lc_trk_g0_2 -(25 10) routing bnl_op_6 lc_trk_g2_6 -(25 10) routing rgt_op_6 lc_trk_g2_6 -(25 10) routing sp12_v_b_6 lc_trk_g2_6 -(25 10) routing sp4_h_l_27 lc_trk_g2_6 -(25 10) routing sp4_h_r_46 lc_trk_g2_6 -(25 10) routing sp4_v_b_30 lc_trk_g2_6 -(25 10) routing sp4_v_b_38 lc_trk_g2_6 -(25 11) routing bnl_op_6 lc_trk_g2_6 -(25 11) routing sp12_v_b_6 lc_trk_g2_6 -(25 11) routing sp12_v_t_21 lc_trk_g2_6 -(25 11) routing sp4_h_r_30 lc_trk_g2_6 -(25 11) routing sp4_h_r_46 lc_trk_g2_6 -(25 11) routing sp4_r_v_b_38 lc_trk_g2_6 -(25 11) routing sp4_v_b_38 lc_trk_g2_6 -(25 11) routing tnl_op_6 lc_trk_g2_6 -(25 12) routing bnl_op_2 lc_trk_g3_2 -(25 12) routing rgt_op_2 lc_trk_g3_2 -(25 12) routing sp12_v_b_2 lc_trk_g3_2 -(25 12) routing sp4_h_r_34 lc_trk_g3_2 -(25 12) routing sp4_h_r_42 lc_trk_g3_2 -(25 12) routing sp4_v_b_26 lc_trk_g3_2 -(25 12) routing sp4_v_t_23 lc_trk_g3_2 -(25 13) routing bnl_op_2 lc_trk_g3_2 -(25 13) routing sp12_v_b_2 lc_trk_g3_2 -(25 13) routing sp12_v_t_17 lc_trk_g3_2 -(25 13) routing sp4_h_l_15 lc_trk_g3_2 -(25 13) routing sp4_h_r_42 lc_trk_g3_2 -(25 13) routing sp4_r_v_b_42 lc_trk_g3_2 -(25 13) routing sp4_v_t_23 lc_trk_g3_2 -(25 13) routing tnl_op_2 lc_trk_g3_2 -(25 14) routing bnl_op_6 lc_trk_g3_6 -(25 14) routing rgt_op_6 lc_trk_g3_6 -(25 14) routing sp12_v_b_6 lc_trk_g3_6 -(25 14) routing sp4_h_l_27 lc_trk_g3_6 -(25 14) routing sp4_h_r_46 lc_trk_g3_6 -(25 14) routing sp4_v_b_30 lc_trk_g3_6 -(25 14) routing sp4_v_b_38 lc_trk_g3_6 -(25 15) routing bnl_op_6 lc_trk_g3_6 -(25 15) routing sp12_v_b_6 lc_trk_g3_6 -(25 15) routing sp12_v_t_21 lc_trk_g3_6 -(25 15) routing sp4_h_r_30 lc_trk_g3_6 -(25 15) routing sp4_h_r_46 lc_trk_g3_6 -(25 15) routing sp4_r_v_b_46 lc_trk_g3_6 -(25 15) routing sp4_v_b_38 lc_trk_g3_6 -(25 15) routing tnl_op_6 lc_trk_g3_6 -(25 2) routing bnr_op_6 lc_trk_g0_6 -(25 2) routing lft_op_6 lc_trk_g0_6 -(25 2) routing sp12_h_l_5 lc_trk_g0_6 -(25 2) routing sp4_h_l_3 lc_trk_g0_6 -(25 2) routing sp4_h_r_22 lc_trk_g0_6 -(25 2) routing sp4_v_b_14 lc_trk_g0_6 -(25 2) routing sp4_v_b_6 lc_trk_g0_6 -(25 3) routing bnr_op_6 lc_trk_g0_6 -(25 3) routing sp12_h_l_21 lc_trk_g0_6 -(25 3) routing sp12_h_l_5 lc_trk_g0_6 -(25 3) routing sp4_h_r_22 lc_trk_g0_6 -(25 3) routing sp4_h_r_6 lc_trk_g0_6 -(25 3) routing sp4_r_v_b_30 lc_trk_g0_6 -(25 3) routing sp4_v_b_14 lc_trk_g0_6 -(25 3) routing top_op_6 lc_trk_g0_6 -(25 4) routing bnr_op_2 lc_trk_g1_2 -(25 4) routing lft_op_2 lc_trk_g1_2 -(25 4) routing sp12_h_r_2 lc_trk_g1_2 -(25 4) routing sp4_h_l_7 lc_trk_g1_2 -(25 4) routing sp4_h_r_10 lc_trk_g1_2 -(25 4) routing sp4_v_b_10 lc_trk_g1_2 -(25 4) routing sp4_v_b_2 lc_trk_g1_2 -(25 5) routing bnr_op_2 lc_trk_g1_2 -(25 5) routing sp12_h_r_18 lc_trk_g1_2 -(25 5) routing sp12_h_r_2 lc_trk_g1_2 -(25 5) routing sp4_h_l_7 lc_trk_g1_2 -(25 5) routing sp4_h_r_2 lc_trk_g1_2 -(25 5) routing sp4_r_v_b_26 lc_trk_g1_2 -(25 5) routing sp4_v_b_10 lc_trk_g1_2 -(25 5) routing top_op_2 lc_trk_g1_2 -(25 6) routing bnr_op_6 lc_trk_g1_6 -(25 6) routing lft_op_6 lc_trk_g1_6 -(25 6) routing sp12_h_l_5 lc_trk_g1_6 -(25 6) routing sp4_h_l_3 lc_trk_g1_6 -(25 6) routing sp4_h_r_22 lc_trk_g1_6 -(25 6) routing sp4_v_b_14 lc_trk_g1_6 -(25 6) routing sp4_v_b_6 lc_trk_g1_6 -(25 7) routing bnr_op_6 lc_trk_g1_6 -(25 7) routing sp12_h_l_21 lc_trk_g1_6 -(25 7) routing sp12_h_l_5 lc_trk_g1_6 -(25 7) routing sp4_h_r_22 lc_trk_g1_6 -(25 7) routing sp4_h_r_6 lc_trk_g1_6 -(25 7) routing sp4_r_v_b_30 lc_trk_g1_6 -(25 7) routing sp4_v_b_14 lc_trk_g1_6 -(25 7) routing top_op_6 lc_trk_g1_6 -(25 8) routing bnl_op_2 lc_trk_g2_2 -(25 8) routing rgt_op_2 lc_trk_g2_2 -(25 8) routing sp12_v_b_2 lc_trk_g2_2 -(25 8) routing sp4_h_r_34 lc_trk_g2_2 -(25 8) routing sp4_h_r_42 lc_trk_g2_2 -(25 8) routing sp4_v_b_26 lc_trk_g2_2 -(25 8) routing sp4_v_t_23 lc_trk_g2_2 -(25 9) routing bnl_op_2 lc_trk_g2_2 -(25 9) routing sp12_v_b_2 lc_trk_g2_2 -(25 9) routing sp12_v_t_17 lc_trk_g2_2 -(25 9) routing sp4_h_l_15 lc_trk_g2_2 -(25 9) routing sp4_h_r_42 lc_trk_g2_2 -(25 9) routing sp4_r_v_b_34 lc_trk_g2_2 -(25 9) routing sp4_v_t_23 lc_trk_g2_2 -(25 9) routing tnl_op_2 lc_trk_g2_2 -(26 0) routing lc_trk_g0_4 input0_0 -(26 0) routing lc_trk_g0_6 input0_0 -(26 0) routing lc_trk_g1_5 input0_0 -(26 0) routing lc_trk_g1_7 input0_0 -(26 0) routing lc_trk_g2_4 input0_0 -(26 0) routing lc_trk_g2_6 input0_0 -(26 0) routing lc_trk_g3_5 input0_0 -(26 0) routing lc_trk_g3_7 input0_0 -(26 1) routing lc_trk_g0_2 input0_0 -(26 1) routing lc_trk_g0_6 input0_0 -(26 1) routing lc_trk_g1_3 input0_0 -(26 1) routing lc_trk_g1_7 input0_0 -(26 1) routing lc_trk_g2_2 input0_0 -(26 1) routing lc_trk_g2_6 input0_0 -(26 1) routing lc_trk_g3_3 input0_0 -(26 1) routing lc_trk_g3_7 input0_0 -(26 10) routing lc_trk_g0_5 input0_5 -(26 10) routing lc_trk_g0_7 input0_5 -(26 10) routing lc_trk_g1_4 input0_5 -(26 10) routing lc_trk_g1_6 input0_5 -(26 10) routing lc_trk_g2_5 input0_5 -(26 10) routing lc_trk_g2_7 input0_5 -(26 10) routing lc_trk_g3_4 input0_5 -(26 10) routing lc_trk_g3_6 input0_5 -(26 11) routing lc_trk_g0_3 input0_5 -(26 11) routing lc_trk_g0_7 input0_5 -(26 11) routing lc_trk_g1_2 input0_5 -(26 11) routing lc_trk_g1_6 input0_5 -(26 11) routing lc_trk_g2_3 input0_5 -(26 11) routing lc_trk_g2_7 input0_5 -(26 11) routing lc_trk_g3_2 input0_5 -(26 11) routing lc_trk_g3_6 input0_5 -(26 12) routing lc_trk_g0_4 input0_6 -(26 12) routing lc_trk_g0_6 input0_6 -(26 12) routing lc_trk_g1_5 input0_6 -(26 12) routing lc_trk_g1_7 input0_6 -(26 12) routing lc_trk_g2_4 input0_6 -(26 12) routing lc_trk_g2_6 input0_6 -(26 12) routing lc_trk_g3_5 input0_6 -(26 12) routing lc_trk_g3_7 input0_6 -(26 13) routing lc_trk_g0_2 input0_6 -(26 13) routing lc_trk_g0_6 input0_6 -(26 13) routing lc_trk_g1_3 input0_6 -(26 13) routing lc_trk_g1_7 input0_6 -(26 13) routing lc_trk_g2_2 input0_6 -(26 13) routing lc_trk_g2_6 input0_6 -(26 13) routing lc_trk_g3_3 input0_6 -(26 13) routing lc_trk_g3_7 input0_6 -(26 14) routing lc_trk_g0_5 input0_7 -(26 14) routing lc_trk_g0_7 input0_7 -(26 14) routing lc_trk_g1_4 input0_7 -(26 14) routing lc_trk_g1_6 input0_7 -(26 14) routing lc_trk_g2_5 input0_7 -(26 14) routing lc_trk_g2_7 input0_7 -(26 14) routing lc_trk_g3_4 input0_7 -(26 14) routing lc_trk_g3_6 input0_7 -(26 15) routing lc_trk_g0_3 input0_7 -(26 15) routing lc_trk_g0_7 input0_7 -(26 15) routing lc_trk_g1_2 input0_7 -(26 15) routing lc_trk_g1_6 input0_7 -(26 15) routing lc_trk_g2_3 input0_7 -(26 15) routing lc_trk_g2_7 input0_7 -(26 15) routing lc_trk_g3_2 input0_7 -(26 15) routing lc_trk_g3_6 input0_7 -(26 2) routing lc_trk_g0_5 input0_1 -(26 2) routing lc_trk_g0_7 input0_1 -(26 2) routing lc_trk_g1_4 input0_1 -(26 2) routing lc_trk_g1_6 input0_1 -(26 2) routing lc_trk_g2_5 input0_1 -(26 2) routing lc_trk_g2_7 input0_1 -(26 2) routing lc_trk_g3_4 input0_1 -(26 2) routing lc_trk_g3_6 input0_1 -(26 3) routing lc_trk_g0_3 input0_1 -(26 3) routing lc_trk_g0_7 input0_1 -(26 3) routing lc_trk_g1_2 input0_1 -(26 3) routing lc_trk_g1_6 input0_1 -(26 3) routing lc_trk_g2_3 input0_1 -(26 3) routing lc_trk_g2_7 input0_1 -(26 3) routing lc_trk_g3_2 input0_1 -(26 3) routing lc_trk_g3_6 input0_1 -(26 4) routing lc_trk_g0_4 input0_2 -(26 4) routing lc_trk_g0_6 input0_2 -(26 4) routing lc_trk_g1_5 input0_2 -(26 4) routing lc_trk_g1_7 input0_2 -(26 4) routing lc_trk_g2_4 input0_2 -(26 4) routing lc_trk_g2_6 input0_2 -(26 4) routing lc_trk_g3_5 input0_2 -(26 4) routing lc_trk_g3_7 input0_2 -(26 5) routing lc_trk_g0_2 input0_2 -(26 5) routing lc_trk_g0_6 input0_2 -(26 5) routing lc_trk_g1_3 input0_2 -(26 5) routing lc_trk_g1_7 input0_2 -(26 5) routing lc_trk_g2_2 input0_2 -(26 5) routing lc_trk_g2_6 input0_2 -(26 5) routing lc_trk_g3_3 input0_2 -(26 5) routing lc_trk_g3_7 input0_2 -(26 6) routing lc_trk_g0_5 input0_3 -(26 6) routing lc_trk_g0_7 input0_3 -(26 6) routing lc_trk_g1_4 input0_3 -(26 6) routing lc_trk_g1_6 input0_3 -(26 6) routing lc_trk_g2_5 input0_3 -(26 6) routing lc_trk_g2_7 input0_3 -(26 6) routing lc_trk_g3_4 input0_3 -(26 6) routing lc_trk_g3_6 input0_3 -(26 7) routing lc_trk_g0_3 input0_3 -(26 7) routing lc_trk_g0_7 input0_3 -(26 7) routing lc_trk_g1_2 input0_3 -(26 7) routing lc_trk_g1_6 input0_3 -(26 7) routing lc_trk_g2_3 input0_3 -(26 7) routing lc_trk_g2_7 input0_3 -(26 7) routing lc_trk_g3_2 input0_3 -(26 7) routing lc_trk_g3_6 input0_3 -(26 8) routing lc_trk_g0_4 input0_4 -(26 8) routing lc_trk_g0_6 input0_4 -(26 8) routing lc_trk_g1_5 input0_4 -(26 8) routing lc_trk_g1_7 input0_4 -(26 8) routing lc_trk_g2_4 input0_4 -(26 8) routing lc_trk_g2_6 input0_4 -(26 8) routing lc_trk_g3_5 input0_4 -(26 8) routing lc_trk_g3_7 input0_4 -(26 9) routing lc_trk_g0_2 input0_4 -(26 9) routing lc_trk_g0_6 input0_4 -(26 9) routing lc_trk_g1_3 input0_4 -(26 9) routing lc_trk_g1_7 input0_4 -(26 9) routing lc_trk_g2_2 input0_4 -(26 9) routing lc_trk_g2_6 input0_4 -(26 9) routing lc_trk_g3_3 input0_4 -(26 9) routing lc_trk_g3_7 input0_4 -(27 0) routing lc_trk_g1_0 wire_bram/ram/WDATA_7 -(27 0) routing lc_trk_g1_2 wire_bram/ram/WDATA_7 -(27 0) routing lc_trk_g1_4 wire_bram/ram/WDATA_7 -(27 0) routing lc_trk_g1_6 wire_bram/ram/WDATA_7 -(27 0) routing lc_trk_g3_0 wire_bram/ram/WDATA_7 -(27 0) routing lc_trk_g3_2 wire_bram/ram/WDATA_7 -(27 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_7 -(27 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_7 -(27 1) routing lc_trk_g1_1 input0_0 -(27 1) routing lc_trk_g1_3 input0_0 -(27 1) routing lc_trk_g1_5 input0_0 -(27 1) routing lc_trk_g1_7 input0_0 -(27 1) routing lc_trk_g3_1 input0_0 -(27 1) routing lc_trk_g3_3 input0_0 -(27 1) routing lc_trk_g3_5 input0_0 -(27 1) routing lc_trk_g3_7 input0_0 -(27 10) routing lc_trk_g1_1 wire_bram/ram/WDATA_2 -(27 10) routing lc_trk_g1_3 wire_bram/ram/WDATA_2 -(27 10) routing lc_trk_g1_5 wire_bram/ram/WDATA_2 -(27 10) routing lc_trk_g1_7 wire_bram/ram/WDATA_2 -(27 10) routing lc_trk_g3_1 wire_bram/ram/WDATA_2 -(27 10) routing lc_trk_g3_3 wire_bram/ram/WDATA_2 -(27 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_2 -(27 10) routing lc_trk_g3_7 wire_bram/ram/WDATA_2 -(27 11) routing lc_trk_g1_0 input0_5 -(27 11) routing lc_trk_g1_2 input0_5 -(27 11) routing lc_trk_g1_4 input0_5 -(27 11) routing lc_trk_g1_6 input0_5 -(27 11) routing lc_trk_g3_0 input0_5 -(27 11) routing lc_trk_g3_2 input0_5 -(27 11) routing lc_trk_g3_4 input0_5 -(27 11) routing lc_trk_g3_6 input0_5 -(27 12) routing lc_trk_g1_0 wire_bram/ram/WDATA_1 -(27 12) routing lc_trk_g1_2 wire_bram/ram/WDATA_1 -(27 12) routing lc_trk_g1_4 wire_bram/ram/WDATA_1 -(27 12) routing lc_trk_g1_6 wire_bram/ram/WDATA_1 -(27 12) routing lc_trk_g3_0 wire_bram/ram/WDATA_1 -(27 12) routing lc_trk_g3_2 wire_bram/ram/WDATA_1 -(27 12) routing lc_trk_g3_4 wire_bram/ram/WDATA_1 -(27 12) routing lc_trk_g3_6 wire_bram/ram/WDATA_1 -(27 13) routing lc_trk_g1_1 input0_6 -(27 13) routing lc_trk_g1_3 input0_6 -(27 13) routing lc_trk_g1_5 input0_6 -(27 13) routing lc_trk_g1_7 input0_6 -(27 13) routing lc_trk_g3_1 input0_6 -(27 13) routing lc_trk_g3_3 input0_6 -(27 13) routing lc_trk_g3_5 input0_6 -(27 13) routing lc_trk_g3_7 input0_6 -(27 14) routing lc_trk_g1_1 wire_bram/ram/WDATA_0 -(27 14) routing lc_trk_g1_3 wire_bram/ram/WDATA_0 -(27 14) routing lc_trk_g1_5 wire_bram/ram/WDATA_0 -(27 14) routing lc_trk_g1_7 wire_bram/ram/WDATA_0 -(27 14) routing lc_trk_g3_1 wire_bram/ram/WDATA_0 -(27 14) routing lc_trk_g3_3 wire_bram/ram/WDATA_0 -(27 14) routing lc_trk_g3_5 wire_bram/ram/WDATA_0 -(27 14) routing lc_trk_g3_7 wire_bram/ram/WDATA_0 -(27 15) routing lc_trk_g1_0 input0_7 -(27 15) routing lc_trk_g1_2 input0_7 -(27 15) routing lc_trk_g1_4 input0_7 -(27 15) routing lc_trk_g1_6 input0_7 -(27 15) routing lc_trk_g3_0 input0_7 -(27 15) routing lc_trk_g3_2 input0_7 -(27 15) routing lc_trk_g3_4 input0_7 -(27 15) routing lc_trk_g3_6 input0_7 -(27 2) routing lc_trk_g1_1 wire_bram/ram/WDATA_6 -(27 2) routing lc_trk_g1_3 wire_bram/ram/WDATA_6 -(27 2) routing lc_trk_g1_5 wire_bram/ram/WDATA_6 -(27 2) routing lc_trk_g1_7 wire_bram/ram/WDATA_6 -(27 2) routing lc_trk_g3_1 wire_bram/ram/WDATA_6 -(27 2) routing lc_trk_g3_3 wire_bram/ram/WDATA_6 -(27 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_6 -(27 2) routing lc_trk_g3_7 wire_bram/ram/WDATA_6 -(27 3) routing lc_trk_g1_0 input0_1 -(27 3) routing lc_trk_g1_2 input0_1 -(27 3) routing lc_trk_g1_4 input0_1 -(27 3) routing lc_trk_g1_6 input0_1 -(27 3) routing lc_trk_g3_0 input0_1 -(27 3) routing lc_trk_g3_2 input0_1 -(27 3) routing lc_trk_g3_4 input0_1 -(27 3) routing lc_trk_g3_6 input0_1 -(27 4) routing lc_trk_g1_0 wire_bram/ram/WDATA_5 -(27 4) routing lc_trk_g1_2 wire_bram/ram/WDATA_5 -(27 4) routing lc_trk_g1_4 wire_bram/ram/WDATA_5 -(27 4) routing lc_trk_g1_6 wire_bram/ram/WDATA_5 -(27 4) routing lc_trk_g3_0 wire_bram/ram/WDATA_5 -(27 4) routing lc_trk_g3_2 wire_bram/ram/WDATA_5 -(27 4) routing lc_trk_g3_4 wire_bram/ram/WDATA_5 -(27 4) routing lc_trk_g3_6 wire_bram/ram/WDATA_5 -(27 5) routing lc_trk_g1_1 input0_2 -(27 5) routing lc_trk_g1_3 input0_2 -(27 5) routing lc_trk_g1_5 input0_2 -(27 5) routing lc_trk_g1_7 input0_2 -(27 5) routing lc_trk_g3_1 input0_2 -(27 5) routing lc_trk_g3_3 input0_2 -(27 5) routing lc_trk_g3_5 input0_2 -(27 5) routing lc_trk_g3_7 input0_2 -(27 6) routing lc_trk_g1_1 wire_bram/ram/WDATA_4 -(27 6) routing lc_trk_g1_3 wire_bram/ram/WDATA_4 -(27 6) routing lc_trk_g1_5 wire_bram/ram/WDATA_4 -(27 6) routing lc_trk_g1_7 wire_bram/ram/WDATA_4 -(27 6) routing lc_trk_g3_1 wire_bram/ram/WDATA_4 -(27 6) routing lc_trk_g3_3 wire_bram/ram/WDATA_4 -(27 6) routing lc_trk_g3_5 wire_bram/ram/WDATA_4 -(27 6) routing lc_trk_g3_7 wire_bram/ram/WDATA_4 -(27 7) routing lc_trk_g1_0 input0_3 -(27 7) routing lc_trk_g1_2 input0_3 -(27 7) routing lc_trk_g1_4 input0_3 -(27 7) routing lc_trk_g1_6 input0_3 -(27 7) routing lc_trk_g3_0 input0_3 -(27 7) routing lc_trk_g3_2 input0_3 -(27 7) routing lc_trk_g3_4 input0_3 -(27 7) routing lc_trk_g3_6 input0_3 -(27 8) routing lc_trk_g1_0 wire_bram/ram/WDATA_3 -(27 8) routing lc_trk_g1_2 wire_bram/ram/WDATA_3 -(27 8) routing lc_trk_g1_4 wire_bram/ram/WDATA_3 -(27 8) routing lc_trk_g1_6 wire_bram/ram/WDATA_3 -(27 8) routing lc_trk_g3_0 wire_bram/ram/WDATA_3 -(27 8) routing lc_trk_g3_2 wire_bram/ram/WDATA_3 -(27 8) routing lc_trk_g3_4 wire_bram/ram/WDATA_3 -(27 8) routing lc_trk_g3_6 wire_bram/ram/WDATA_3 -(27 9) routing lc_trk_g1_1 input0_4 -(27 9) routing lc_trk_g1_3 input0_4 -(27 9) routing lc_trk_g1_5 input0_4 -(27 9) routing lc_trk_g1_7 input0_4 -(27 9) routing lc_trk_g3_1 input0_4 -(27 9) routing lc_trk_g3_3 input0_4 -(27 9) routing lc_trk_g3_5 input0_4 -(27 9) routing lc_trk_g3_7 input0_4 -(28 0) routing lc_trk_g2_1 wire_bram/ram/WDATA_7 -(28 0) routing lc_trk_g2_3 wire_bram/ram/WDATA_7 -(28 0) routing lc_trk_g2_5 wire_bram/ram/WDATA_7 -(28 0) routing lc_trk_g2_7 wire_bram/ram/WDATA_7 -(28 0) routing lc_trk_g3_0 wire_bram/ram/WDATA_7 -(28 0) routing lc_trk_g3_2 wire_bram/ram/WDATA_7 -(28 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_7 -(28 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_7 -(28 1) routing lc_trk_g2_0 input0_0 -(28 1) routing lc_trk_g2_2 input0_0 -(28 1) routing lc_trk_g2_4 input0_0 -(28 1) routing lc_trk_g2_6 input0_0 -(28 1) routing lc_trk_g3_1 input0_0 -(28 1) routing lc_trk_g3_3 input0_0 -(28 1) routing lc_trk_g3_5 input0_0 -(28 1) routing lc_trk_g3_7 input0_0 -(28 10) routing lc_trk_g2_0 wire_bram/ram/WDATA_2 -(28 10) routing lc_trk_g2_2 wire_bram/ram/WDATA_2 -(28 10) routing lc_trk_g2_4 wire_bram/ram/WDATA_2 -(28 10) routing lc_trk_g2_6 wire_bram/ram/WDATA_2 -(28 10) routing lc_trk_g3_1 wire_bram/ram/WDATA_2 -(28 10) routing lc_trk_g3_3 wire_bram/ram/WDATA_2 -(28 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_2 -(28 10) routing lc_trk_g3_7 wire_bram/ram/WDATA_2 -(28 11) routing lc_trk_g2_1 input0_5 -(28 11) routing lc_trk_g2_3 input0_5 -(28 11) routing lc_trk_g2_5 input0_5 -(28 11) routing lc_trk_g2_7 input0_5 -(28 11) routing lc_trk_g3_0 input0_5 -(28 11) routing lc_trk_g3_2 input0_5 -(28 11) routing lc_trk_g3_4 input0_5 -(28 11) routing lc_trk_g3_6 input0_5 -(28 12) routing lc_trk_g2_1 wire_bram/ram/WDATA_1 -(28 12) routing lc_trk_g2_3 wire_bram/ram/WDATA_1 -(28 12) routing lc_trk_g2_5 wire_bram/ram/WDATA_1 -(28 12) routing lc_trk_g2_7 wire_bram/ram/WDATA_1 -(28 12) routing lc_trk_g3_0 wire_bram/ram/WDATA_1 -(28 12) routing lc_trk_g3_2 wire_bram/ram/WDATA_1 -(28 12) routing lc_trk_g3_4 wire_bram/ram/WDATA_1 -(28 12) routing lc_trk_g3_6 wire_bram/ram/WDATA_1 -(28 13) routing lc_trk_g2_0 input0_6 -(28 13) routing lc_trk_g2_2 input0_6 -(28 13) routing lc_trk_g2_4 input0_6 -(28 13) routing lc_trk_g2_6 input0_6 -(28 13) routing lc_trk_g3_1 input0_6 -(28 13) routing lc_trk_g3_3 input0_6 -(28 13) routing lc_trk_g3_5 input0_6 -(28 13) routing lc_trk_g3_7 input0_6 -(28 14) routing lc_trk_g2_0 wire_bram/ram/WDATA_0 -(28 14) routing lc_trk_g2_2 wire_bram/ram/WDATA_0 -(28 14) routing lc_trk_g2_4 wire_bram/ram/WDATA_0 -(28 14) routing lc_trk_g2_6 wire_bram/ram/WDATA_0 -(28 14) routing lc_trk_g3_1 wire_bram/ram/WDATA_0 -(28 14) routing lc_trk_g3_3 wire_bram/ram/WDATA_0 -(28 14) routing lc_trk_g3_5 wire_bram/ram/WDATA_0 -(28 14) routing lc_trk_g3_7 wire_bram/ram/WDATA_0 -(28 15) routing lc_trk_g2_1 input0_7 -(28 15) routing lc_trk_g2_3 input0_7 -(28 15) routing lc_trk_g2_5 input0_7 -(28 15) routing lc_trk_g2_7 input0_7 -(28 15) routing lc_trk_g3_0 input0_7 -(28 15) routing lc_trk_g3_2 input0_7 -(28 15) routing lc_trk_g3_4 input0_7 -(28 15) routing lc_trk_g3_6 input0_7 -(28 2) routing lc_trk_g2_0 wire_bram/ram/WDATA_6 -(28 2) routing lc_trk_g2_2 wire_bram/ram/WDATA_6 -(28 2) routing lc_trk_g2_4 wire_bram/ram/WDATA_6 -(28 2) routing lc_trk_g2_6 wire_bram/ram/WDATA_6 -(28 2) routing lc_trk_g3_1 wire_bram/ram/WDATA_6 -(28 2) routing lc_trk_g3_3 wire_bram/ram/WDATA_6 -(28 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_6 -(28 2) routing lc_trk_g3_7 wire_bram/ram/WDATA_6 -(28 3) routing lc_trk_g2_1 input0_1 -(28 3) routing lc_trk_g2_3 input0_1 -(28 3) routing lc_trk_g2_5 input0_1 -(28 3) routing lc_trk_g2_7 input0_1 -(28 3) routing lc_trk_g3_0 input0_1 -(28 3) routing lc_trk_g3_2 input0_1 -(28 3) routing lc_trk_g3_4 input0_1 -(28 3) routing lc_trk_g3_6 input0_1 -(28 4) routing lc_trk_g2_1 wire_bram/ram/WDATA_5 -(28 4) routing lc_trk_g2_3 wire_bram/ram/WDATA_5 -(28 4) routing lc_trk_g2_5 wire_bram/ram/WDATA_5 -(28 4) routing lc_trk_g2_7 wire_bram/ram/WDATA_5 -(28 4) routing lc_trk_g3_0 wire_bram/ram/WDATA_5 -(28 4) routing lc_trk_g3_2 wire_bram/ram/WDATA_5 -(28 4) routing lc_trk_g3_4 wire_bram/ram/WDATA_5 -(28 4) routing lc_trk_g3_6 wire_bram/ram/WDATA_5 -(28 5) routing lc_trk_g2_0 input0_2 -(28 5) routing lc_trk_g2_2 input0_2 -(28 5) routing lc_trk_g2_4 input0_2 -(28 5) routing lc_trk_g2_6 input0_2 -(28 5) routing lc_trk_g3_1 input0_2 -(28 5) routing lc_trk_g3_3 input0_2 -(28 5) routing lc_trk_g3_5 input0_2 -(28 5) routing lc_trk_g3_7 input0_2 -(28 6) routing lc_trk_g2_0 wire_bram/ram/WDATA_4 -(28 6) routing lc_trk_g2_2 wire_bram/ram/WDATA_4 -(28 6) routing lc_trk_g2_4 wire_bram/ram/WDATA_4 -(28 6) routing lc_trk_g2_6 wire_bram/ram/WDATA_4 -(28 6) routing lc_trk_g3_1 wire_bram/ram/WDATA_4 -(28 6) routing lc_trk_g3_3 wire_bram/ram/WDATA_4 -(28 6) routing lc_trk_g3_5 wire_bram/ram/WDATA_4 -(28 6) routing lc_trk_g3_7 wire_bram/ram/WDATA_4 -(28 7) routing lc_trk_g2_1 input0_3 -(28 7) routing lc_trk_g2_3 input0_3 -(28 7) routing lc_trk_g2_5 input0_3 -(28 7) routing lc_trk_g2_7 input0_3 -(28 7) routing lc_trk_g3_0 input0_3 -(28 7) routing lc_trk_g3_2 input0_3 -(28 7) routing lc_trk_g3_4 input0_3 -(28 7) routing lc_trk_g3_6 input0_3 -(28 8) routing lc_trk_g2_1 wire_bram/ram/WDATA_3 -(28 8) routing lc_trk_g2_3 wire_bram/ram/WDATA_3 -(28 8) routing lc_trk_g2_5 wire_bram/ram/WDATA_3 -(28 8) routing lc_trk_g2_7 wire_bram/ram/WDATA_3 -(28 8) routing lc_trk_g3_0 wire_bram/ram/WDATA_3 -(28 8) routing lc_trk_g3_2 wire_bram/ram/WDATA_3 -(28 8) routing lc_trk_g3_4 wire_bram/ram/WDATA_3 -(28 8) routing lc_trk_g3_6 wire_bram/ram/WDATA_3 -(28 9) routing lc_trk_g2_0 input0_4 -(28 9) routing lc_trk_g2_2 input0_4 -(28 9) routing lc_trk_g2_4 input0_4 -(28 9) routing lc_trk_g2_6 input0_4 -(28 9) routing lc_trk_g3_1 input0_4 -(28 9) routing lc_trk_g3_3 input0_4 -(28 9) routing lc_trk_g3_5 input0_4 -(28 9) routing lc_trk_g3_7 input0_4 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_1 wire_bram/ram/WDATA_7 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_3 wire_bram/ram/WDATA_7 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_5 wire_bram/ram/WDATA_7 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g0_7 wire_bram/ram/WDATA_7 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_0 wire_bram/ram/WDATA_7 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_2 wire_bram/ram/WDATA_7 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_4 wire_bram/ram/WDATA_7 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g1_6 wire_bram/ram/WDATA_7 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_1 wire_bram/ram/WDATA_7 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_3 wire_bram/ram/WDATA_7 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_5 wire_bram/ram/WDATA_7 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g2_7 wire_bram/ram/WDATA_7 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_0 wire_bram/ram/WDATA_7 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_2 wire_bram/ram/WDATA_7 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_4 wire_bram/ram/WDATA_7 -(29 0) Enable bit of Mux _bram/lcb1_0 => lc_trk_g3_6 wire_bram/ram/WDATA_7 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_0 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_2 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_4 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g0_6 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_1 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_3 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_5 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_7 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_0 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_2 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_4 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_6 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_1 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_3 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_5 input0_0 -(29 1) Enable bit of Mux _bram/lcb0_0 => lc_trk_g3_7 input0_0 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_0 wire_bram/ram/WDATA_2 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_2 wire_bram/ram/WDATA_2 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_4 wire_bram/ram/WDATA_2 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g0_6 wire_bram/ram/WDATA_2 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_1 wire_bram/ram/WDATA_2 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_3 wire_bram/ram/WDATA_2 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_5 wire_bram/ram/WDATA_2 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g1_7 wire_bram/ram/WDATA_2 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_0 wire_bram/ram/WDATA_2 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_2 wire_bram/ram/WDATA_2 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_4 wire_bram/ram/WDATA_2 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g2_6 wire_bram/ram/WDATA_2 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_1 wire_bram/ram/WDATA_2 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_3 wire_bram/ram/WDATA_2 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_5 wire_bram/ram/WDATA_2 -(29 10) Enable bit of Mux _bram/lcb1_5 => lc_trk_g3_7 wire_bram/ram/WDATA_2 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_1 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_3 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_5 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g0_7 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_0 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_2 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_4 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_6 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_1 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_3 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_5 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g2_7 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_0 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_2 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_4 input0_5 -(29 11) Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_6 input0_5 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_1 wire_bram/ram/WDATA_1 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_3 wire_bram/ram/WDATA_1 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_5 wire_bram/ram/WDATA_1 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g0_7 wire_bram/ram/WDATA_1 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_0 wire_bram/ram/WDATA_1 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_2 wire_bram/ram/WDATA_1 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_4 wire_bram/ram/WDATA_1 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g1_6 wire_bram/ram/WDATA_1 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_1 wire_bram/ram/WDATA_1 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_3 wire_bram/ram/WDATA_1 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_5 wire_bram/ram/WDATA_1 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g2_7 wire_bram/ram/WDATA_1 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_0 wire_bram/ram/WDATA_1 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_2 wire_bram/ram/WDATA_1 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_4 wire_bram/ram/WDATA_1 -(29 12) Enable bit of Mux _bram/lcb1_6 => lc_trk_g3_6 wire_bram/ram/WDATA_1 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_0 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_2 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_4 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g0_6 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_1 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_3 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_5 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_7 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_0 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_2 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_4 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g2_6 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_1 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_3 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_5 input0_6 -(29 13) Enable bit of Mux _bram/lcb0_6 => lc_trk_g3_7 input0_6 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_0 wire_bram/ram/WDATA_0 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_2 wire_bram/ram/WDATA_0 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_4 wire_bram/ram/WDATA_0 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g0_6 wire_bram/ram/WDATA_0 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_1 wire_bram/ram/WDATA_0 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_3 wire_bram/ram/WDATA_0 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_5 wire_bram/ram/WDATA_0 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g1_7 wire_bram/ram/WDATA_0 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_0 wire_bram/ram/WDATA_0 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_2 wire_bram/ram/WDATA_0 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_4 wire_bram/ram/WDATA_0 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g2_6 wire_bram/ram/WDATA_0 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_1 wire_bram/ram/WDATA_0 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_3 wire_bram/ram/WDATA_0 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_5 wire_bram/ram/WDATA_0 -(29 14) Enable bit of Mux _bram/lcb1_7 => lc_trk_g3_7 wire_bram/ram/WDATA_0 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_1 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_3 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_5 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_7 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_0 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_2 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_4 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_6 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_1 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_3 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_5 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g2_7 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_0 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_2 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_4 input0_7 -(29 15) Enable bit of Mux _bram/lcb0_7 => lc_trk_g3_6 input0_7 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_0 wire_bram/ram/WDATA_6 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_2 wire_bram/ram/WDATA_6 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_4 wire_bram/ram/WDATA_6 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g0_6 wire_bram/ram/WDATA_6 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_1 wire_bram/ram/WDATA_6 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_3 wire_bram/ram/WDATA_6 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_5 wire_bram/ram/WDATA_6 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g1_7 wire_bram/ram/WDATA_6 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_0 wire_bram/ram/WDATA_6 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_2 wire_bram/ram/WDATA_6 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_4 wire_bram/ram/WDATA_6 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g2_6 wire_bram/ram/WDATA_6 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_1 wire_bram/ram/WDATA_6 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_3 wire_bram/ram/WDATA_6 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_5 wire_bram/ram/WDATA_6 -(29 2) Enable bit of Mux _bram/lcb1_1 => lc_trk_g3_7 wire_bram/ram/WDATA_6 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_1 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_3 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_5 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_7 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_0 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_2 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_4 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g1_6 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_1 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_3 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_5 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g2_7 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_0 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_2 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_4 input0_1 -(29 3) Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_6 input0_1 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_1 wire_bram/ram/WDATA_5 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_3 wire_bram/ram/WDATA_5 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_5 wire_bram/ram/WDATA_5 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g0_7 wire_bram/ram/WDATA_5 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_0 wire_bram/ram/WDATA_5 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_2 wire_bram/ram/WDATA_5 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_4 wire_bram/ram/WDATA_5 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g1_6 wire_bram/ram/WDATA_5 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_1 wire_bram/ram/WDATA_5 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_3 wire_bram/ram/WDATA_5 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_5 wire_bram/ram/WDATA_5 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g2_7 wire_bram/ram/WDATA_5 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_0 wire_bram/ram/WDATA_5 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_2 wire_bram/ram/WDATA_5 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_4 wire_bram/ram/WDATA_5 -(29 4) Enable bit of Mux _bram/lcb1_2 => lc_trk_g3_6 wire_bram/ram/WDATA_5 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_0 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_2 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_4 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g0_6 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_1 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_3 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_5 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g1_7 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_0 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_2 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_4 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_6 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_1 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_3 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_5 input0_2 -(29 5) Enable bit of Mux _bram/lcb0_2 => lc_trk_g3_7 input0_2 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_0 wire_bram/ram/WDATA_4 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_2 wire_bram/ram/WDATA_4 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_4 wire_bram/ram/WDATA_4 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_6 wire_bram/ram/WDATA_4 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_1 wire_bram/ram/WDATA_4 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_3 wire_bram/ram/WDATA_4 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_5 wire_bram/ram/WDATA_4 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_7 wire_bram/ram/WDATA_4 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_0 wire_bram/ram/WDATA_4 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_2 wire_bram/ram/WDATA_4 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_4 wire_bram/ram/WDATA_4 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_6 wire_bram/ram/WDATA_4 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_1 wire_bram/ram/WDATA_4 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_3 wire_bram/ram/WDATA_4 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_5 wire_bram/ram/WDATA_4 -(29 6) Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_7 wire_bram/ram/WDATA_4 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_1 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_3 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_5 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g0_7 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_0 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_2 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_4 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g1_6 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_1 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_3 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_5 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_7 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_0 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_2 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_4 input0_3 -(29 7) Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_6 input0_3 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_1 wire_bram/ram/WDATA_3 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_3 wire_bram/ram/WDATA_3 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_5 wire_bram/ram/WDATA_3 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g0_7 wire_bram/ram/WDATA_3 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_0 wire_bram/ram/WDATA_3 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_2 wire_bram/ram/WDATA_3 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_4 wire_bram/ram/WDATA_3 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g1_6 wire_bram/ram/WDATA_3 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_1 wire_bram/ram/WDATA_3 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_3 wire_bram/ram/WDATA_3 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_5 wire_bram/ram/WDATA_3 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g2_7 wire_bram/ram/WDATA_3 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_0 wire_bram/ram/WDATA_3 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_2 wire_bram/ram/WDATA_3 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_4 wire_bram/ram/WDATA_3 -(29 8) Enable bit of Mux _bram/lcb1_4 => lc_trk_g3_6 wire_bram/ram/WDATA_3 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_0 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_2 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_4 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_6 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_1 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_3 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_5 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_7 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_0 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_2 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_4 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g2_6 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_1 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_3 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_5 input0_4 -(29 9) Enable bit of Mux _bram/lcb0_4 => lc_trk_g3_7 input0_4 -(3 0) routing sp12_h_r_0 sp12_v_b_0 -(3 0) routing sp12_v_t_23 sp12_v_b_0 -(3 1) routing sp12_h_l_23 sp12_v_b_0 -(3 1) routing sp12_h_r_0 sp12_v_b_0 -(3 10) routing sp12_h_r_1 sp12_h_l_22 -(3 10) routing sp12_v_t_22 sp12_h_l_22 -(3 11) routing sp12_h_r_1 sp12_h_l_22 -(3 11) routing sp12_v_b_1 sp12_h_l_22 -(3 12) routing sp12_v_b_1 sp12_h_r_1 -(3 12) routing sp12_v_t_22 sp12_h_r_1 -(3 13) routing sp12_h_l_22 sp12_h_r_1 -(3 13) routing sp12_v_b_1 sp12_h_r_1 -(3 14) routing sp12_h_r_1 sp12_v_t_22 -(3 14) routing sp12_v_b_1 sp12_v_t_22 -(3 15) routing sp12_h_l_22 sp12_v_t_22 -(3 15) routing sp12_h_r_1 sp12_v_t_22 -(3 2) routing sp12_h_r_0 sp12_h_l_23 -(3 2) routing sp12_v_t_23 sp12_h_l_23 -(3 3) routing sp12_h_r_0 sp12_h_l_23 -(3 3) routing sp12_v_b_0 sp12_h_l_23 -(3 4) routing sp12_v_b_0 sp12_h_r_0 -(3 4) routing sp12_v_t_23 sp12_h_r_0 -(3 5) routing sp12_h_l_23 sp12_h_r_0 -(3 5) routing sp12_v_b_0 sp12_h_r_0 -(3 6) routing sp12_h_r_0 sp12_v_t_23 -(3 6) routing sp12_v_b_0 sp12_v_t_23 -(3 7) routing sp12_h_l_23 sp12_v_t_23 -(3 7) routing sp12_h_r_0 sp12_v_t_23 -(3 8) routing sp12_h_r_1 sp12_v_b_1 -(3 8) routing sp12_v_t_22 sp12_v_b_1 -(3 9) routing sp12_h_l_22 sp12_v_b_1 -(3 9) routing sp12_h_r_1 sp12_v_b_1 -(30 0) routing lc_trk_g0_5 wire_bram/ram/WDATA_7 -(30 0) routing lc_trk_g0_7 wire_bram/ram/WDATA_7 -(30 0) routing lc_trk_g1_4 wire_bram/ram/WDATA_7 -(30 0) routing lc_trk_g1_6 wire_bram/ram/WDATA_7 -(30 0) routing lc_trk_g2_5 wire_bram/ram/WDATA_7 -(30 0) routing lc_trk_g2_7 wire_bram/ram/WDATA_7 -(30 0) routing lc_trk_g3_4 wire_bram/ram/WDATA_7 -(30 0) routing lc_trk_g3_6 wire_bram/ram/WDATA_7 -(30 1) routing lc_trk_g0_3 wire_bram/ram/WDATA_7 -(30 1) routing lc_trk_g0_7 wire_bram/ram/WDATA_7 -(30 1) routing lc_trk_g1_2 wire_bram/ram/WDATA_7 -(30 1) routing lc_trk_g1_6 wire_bram/ram/WDATA_7 -(30 1) routing lc_trk_g2_3 wire_bram/ram/WDATA_7 -(30 1) routing lc_trk_g2_7 wire_bram/ram/WDATA_7 -(30 1) routing lc_trk_g3_2 wire_bram/ram/WDATA_7 -(30 1) routing lc_trk_g3_6 wire_bram/ram/WDATA_7 -(30 10) routing lc_trk_g0_4 wire_bram/ram/WDATA_2 -(30 10) routing lc_trk_g0_6 wire_bram/ram/WDATA_2 -(30 10) routing lc_trk_g1_5 wire_bram/ram/WDATA_2 -(30 10) routing lc_trk_g1_7 wire_bram/ram/WDATA_2 -(30 10) routing lc_trk_g2_4 wire_bram/ram/WDATA_2 -(30 10) routing lc_trk_g2_6 wire_bram/ram/WDATA_2 -(30 10) routing lc_trk_g3_5 wire_bram/ram/WDATA_2 -(30 10) routing lc_trk_g3_7 wire_bram/ram/WDATA_2 -(30 11) routing lc_trk_g0_2 wire_bram/ram/WDATA_2 -(30 11) routing lc_trk_g0_6 wire_bram/ram/WDATA_2 -(30 11) routing lc_trk_g1_3 wire_bram/ram/WDATA_2 -(30 11) routing lc_trk_g1_7 wire_bram/ram/WDATA_2 -(30 11) routing lc_trk_g2_2 wire_bram/ram/WDATA_2 -(30 11) routing lc_trk_g2_6 wire_bram/ram/WDATA_2 -(30 11) routing lc_trk_g3_3 wire_bram/ram/WDATA_2 -(30 11) routing lc_trk_g3_7 wire_bram/ram/WDATA_2 -(30 12) routing lc_trk_g0_5 wire_bram/ram/WDATA_1 -(30 12) routing lc_trk_g0_7 wire_bram/ram/WDATA_1 -(30 12) routing lc_trk_g1_4 wire_bram/ram/WDATA_1 -(30 12) routing lc_trk_g1_6 wire_bram/ram/WDATA_1 -(30 12) routing lc_trk_g2_5 wire_bram/ram/WDATA_1 -(30 12) routing lc_trk_g2_7 wire_bram/ram/WDATA_1 -(30 12) routing lc_trk_g3_4 wire_bram/ram/WDATA_1 -(30 12) routing lc_trk_g3_6 wire_bram/ram/WDATA_1 -(30 13) routing lc_trk_g0_3 wire_bram/ram/WDATA_1 -(30 13) routing lc_trk_g0_7 wire_bram/ram/WDATA_1 -(30 13) routing lc_trk_g1_2 wire_bram/ram/WDATA_1 -(30 13) routing lc_trk_g1_6 wire_bram/ram/WDATA_1 -(30 13) routing lc_trk_g2_3 wire_bram/ram/WDATA_1 -(30 13) routing lc_trk_g2_7 wire_bram/ram/WDATA_1 -(30 13) routing lc_trk_g3_2 wire_bram/ram/WDATA_1 -(30 13) routing lc_trk_g3_6 wire_bram/ram/WDATA_1 -(30 14) routing lc_trk_g0_4 wire_bram/ram/WDATA_0 -(30 14) routing lc_trk_g0_6 wire_bram/ram/WDATA_0 -(30 14) routing lc_trk_g1_5 wire_bram/ram/WDATA_0 -(30 14) routing lc_trk_g1_7 wire_bram/ram/WDATA_0 -(30 14) routing lc_trk_g2_4 wire_bram/ram/WDATA_0 -(30 14) routing lc_trk_g2_6 wire_bram/ram/WDATA_0 -(30 14) routing lc_trk_g3_5 wire_bram/ram/WDATA_0 -(30 14) routing lc_trk_g3_7 wire_bram/ram/WDATA_0 -(30 15) routing lc_trk_g0_2 wire_bram/ram/WDATA_0 -(30 15) routing lc_trk_g0_6 wire_bram/ram/WDATA_0 -(30 15) routing lc_trk_g1_3 wire_bram/ram/WDATA_0 -(30 15) routing lc_trk_g1_7 wire_bram/ram/WDATA_0 -(30 15) routing lc_trk_g2_2 wire_bram/ram/WDATA_0 -(30 15) routing lc_trk_g2_6 wire_bram/ram/WDATA_0 -(30 15) routing lc_trk_g3_3 wire_bram/ram/WDATA_0 -(30 15) routing lc_trk_g3_7 wire_bram/ram/WDATA_0 -(30 2) routing lc_trk_g0_4 wire_bram/ram/WDATA_6 -(30 2) routing lc_trk_g0_6 wire_bram/ram/WDATA_6 -(30 2) routing lc_trk_g1_5 wire_bram/ram/WDATA_6 -(30 2) routing lc_trk_g1_7 wire_bram/ram/WDATA_6 -(30 2) routing lc_trk_g2_4 wire_bram/ram/WDATA_6 -(30 2) routing lc_trk_g2_6 wire_bram/ram/WDATA_6 -(30 2) routing lc_trk_g3_5 wire_bram/ram/WDATA_6 -(30 2) routing lc_trk_g3_7 wire_bram/ram/WDATA_6 -(30 3) routing lc_trk_g0_2 wire_bram/ram/WDATA_6 -(30 3) routing lc_trk_g0_6 wire_bram/ram/WDATA_6 -(30 3) routing lc_trk_g1_3 wire_bram/ram/WDATA_6 -(30 3) routing lc_trk_g1_7 wire_bram/ram/WDATA_6 -(30 3) routing lc_trk_g2_2 wire_bram/ram/WDATA_6 -(30 3) routing lc_trk_g2_6 wire_bram/ram/WDATA_6 -(30 3) routing lc_trk_g3_3 wire_bram/ram/WDATA_6 -(30 3) routing lc_trk_g3_7 wire_bram/ram/WDATA_6 -(30 4) routing lc_trk_g0_5 wire_bram/ram/WDATA_5 -(30 4) routing lc_trk_g0_7 wire_bram/ram/WDATA_5 -(30 4) routing lc_trk_g1_4 wire_bram/ram/WDATA_5 -(30 4) routing lc_trk_g1_6 wire_bram/ram/WDATA_5 -(30 4) routing lc_trk_g2_5 wire_bram/ram/WDATA_5 -(30 4) routing lc_trk_g2_7 wire_bram/ram/WDATA_5 -(30 4) routing lc_trk_g3_4 wire_bram/ram/WDATA_5 -(30 4) routing lc_trk_g3_6 wire_bram/ram/WDATA_5 -(30 5) routing lc_trk_g0_3 wire_bram/ram/WDATA_5 -(30 5) routing lc_trk_g0_7 wire_bram/ram/WDATA_5 -(30 5) routing lc_trk_g1_2 wire_bram/ram/WDATA_5 -(30 5) routing lc_trk_g1_6 wire_bram/ram/WDATA_5 -(30 5) routing lc_trk_g2_3 wire_bram/ram/WDATA_5 -(30 5) routing lc_trk_g2_7 wire_bram/ram/WDATA_5 -(30 5) routing lc_trk_g3_2 wire_bram/ram/WDATA_5 -(30 5) routing lc_trk_g3_6 wire_bram/ram/WDATA_5 -(30 6) routing lc_trk_g0_4 wire_bram/ram/WDATA_4 -(30 6) routing lc_trk_g0_6 wire_bram/ram/WDATA_4 -(30 6) routing lc_trk_g1_5 wire_bram/ram/WDATA_4 -(30 6) routing lc_trk_g1_7 wire_bram/ram/WDATA_4 -(30 6) routing lc_trk_g2_4 wire_bram/ram/WDATA_4 -(30 6) routing lc_trk_g2_6 wire_bram/ram/WDATA_4 -(30 6) routing lc_trk_g3_5 wire_bram/ram/WDATA_4 -(30 6) routing lc_trk_g3_7 wire_bram/ram/WDATA_4 -(30 7) routing lc_trk_g0_2 wire_bram/ram/WDATA_4 -(30 7) routing lc_trk_g0_6 wire_bram/ram/WDATA_4 -(30 7) routing lc_trk_g1_3 wire_bram/ram/WDATA_4 -(30 7) routing lc_trk_g1_7 wire_bram/ram/WDATA_4 -(30 7) routing lc_trk_g2_2 wire_bram/ram/WDATA_4 -(30 7) routing lc_trk_g2_6 wire_bram/ram/WDATA_4 -(30 7) routing lc_trk_g3_3 wire_bram/ram/WDATA_4 -(30 7) routing lc_trk_g3_7 wire_bram/ram/WDATA_4 -(30 8) routing lc_trk_g0_5 wire_bram/ram/WDATA_3 -(30 8) routing lc_trk_g0_7 wire_bram/ram/WDATA_3 -(30 8) routing lc_trk_g1_4 wire_bram/ram/WDATA_3 -(30 8) routing lc_trk_g1_6 wire_bram/ram/WDATA_3 -(30 8) routing lc_trk_g2_5 wire_bram/ram/WDATA_3 -(30 8) routing lc_trk_g2_7 wire_bram/ram/WDATA_3 -(30 8) routing lc_trk_g3_4 wire_bram/ram/WDATA_3 -(30 8) routing lc_trk_g3_6 wire_bram/ram/WDATA_3 -(30 9) routing lc_trk_g0_3 wire_bram/ram/WDATA_3 -(30 9) routing lc_trk_g0_7 wire_bram/ram/WDATA_3 -(30 9) routing lc_trk_g1_2 wire_bram/ram/WDATA_3 -(30 9) routing lc_trk_g1_6 wire_bram/ram/WDATA_3 -(30 9) routing lc_trk_g2_3 wire_bram/ram/WDATA_3 -(30 9) routing lc_trk_g2_7 wire_bram/ram/WDATA_3 -(30 9) routing lc_trk_g3_2 wire_bram/ram/WDATA_3 -(30 9) routing lc_trk_g3_6 wire_bram/ram/WDATA_3 -(31 0) routing lc_trk_g0_5 wire_bram/ram/MASK_7 -(31 0) routing lc_trk_g0_7 wire_bram/ram/MASK_7 -(31 0) routing lc_trk_g1_4 wire_bram/ram/MASK_7 -(31 0) routing lc_trk_g1_6 wire_bram/ram/MASK_7 -(31 0) routing lc_trk_g2_5 wire_bram/ram/MASK_7 -(31 0) routing lc_trk_g2_7 wire_bram/ram/MASK_7 -(31 0) routing lc_trk_g3_4 wire_bram/ram/MASK_7 -(31 0) routing lc_trk_g3_6 wire_bram/ram/MASK_7 -(31 1) routing lc_trk_g0_3 wire_bram/ram/MASK_7 -(31 1) routing lc_trk_g0_7 wire_bram/ram/MASK_7 -(31 1) routing lc_trk_g1_2 wire_bram/ram/MASK_7 -(31 1) routing lc_trk_g1_6 wire_bram/ram/MASK_7 -(31 1) routing lc_trk_g2_3 wire_bram/ram/MASK_7 -(31 1) routing lc_trk_g2_7 wire_bram/ram/MASK_7 -(31 1) routing lc_trk_g3_2 wire_bram/ram/MASK_7 -(31 1) routing lc_trk_g3_6 wire_bram/ram/MASK_7 -(31 10) routing lc_trk_g0_4 wire_bram/ram/MASK_2 -(31 10) routing lc_trk_g0_6 wire_bram/ram/MASK_2 -(31 10) routing lc_trk_g1_5 wire_bram/ram/MASK_2 -(31 10) routing lc_trk_g1_7 wire_bram/ram/MASK_2 -(31 10) routing lc_trk_g2_4 wire_bram/ram/MASK_2 -(31 10) routing lc_trk_g2_6 wire_bram/ram/MASK_2 -(31 10) routing lc_trk_g3_5 wire_bram/ram/MASK_2 -(31 10) routing lc_trk_g3_7 wire_bram/ram/MASK_2 -(31 11) routing lc_trk_g0_2 wire_bram/ram/MASK_2 -(31 11) routing lc_trk_g0_6 wire_bram/ram/MASK_2 -(31 11) routing lc_trk_g1_3 wire_bram/ram/MASK_2 -(31 11) routing lc_trk_g1_7 wire_bram/ram/MASK_2 -(31 11) routing lc_trk_g2_2 wire_bram/ram/MASK_2 -(31 11) routing lc_trk_g2_6 wire_bram/ram/MASK_2 -(31 11) routing lc_trk_g3_3 wire_bram/ram/MASK_2 -(31 11) routing lc_trk_g3_7 wire_bram/ram/MASK_2 -(31 12) routing lc_trk_g0_5 wire_bram/ram/MASK_1 -(31 12) routing lc_trk_g0_7 wire_bram/ram/MASK_1 -(31 12) routing lc_trk_g1_4 wire_bram/ram/MASK_1 -(31 12) routing lc_trk_g1_6 wire_bram/ram/MASK_1 -(31 12) routing lc_trk_g2_5 wire_bram/ram/MASK_1 -(31 12) routing lc_trk_g2_7 wire_bram/ram/MASK_1 -(31 12) routing lc_trk_g3_4 wire_bram/ram/MASK_1 -(31 12) routing lc_trk_g3_6 wire_bram/ram/MASK_1 -(31 13) routing lc_trk_g0_3 wire_bram/ram/MASK_1 -(31 13) routing lc_trk_g0_7 wire_bram/ram/MASK_1 -(31 13) routing lc_trk_g1_2 wire_bram/ram/MASK_1 -(31 13) routing lc_trk_g1_6 wire_bram/ram/MASK_1 -(31 13) routing lc_trk_g2_3 wire_bram/ram/MASK_1 -(31 13) routing lc_trk_g2_7 wire_bram/ram/MASK_1 -(31 13) routing lc_trk_g3_2 wire_bram/ram/MASK_1 -(31 13) routing lc_trk_g3_6 wire_bram/ram/MASK_1 -(31 14) routing lc_trk_g0_4 wire_bram/ram/MASK_0 -(31 14) routing lc_trk_g0_6 wire_bram/ram/MASK_0 -(31 14) routing lc_trk_g1_5 wire_bram/ram/MASK_0 -(31 14) routing lc_trk_g1_7 wire_bram/ram/MASK_0 -(31 14) routing lc_trk_g2_4 wire_bram/ram/MASK_0 -(31 14) routing lc_trk_g2_6 wire_bram/ram/MASK_0 -(31 14) routing lc_trk_g3_5 wire_bram/ram/MASK_0 -(31 14) routing lc_trk_g3_7 wire_bram/ram/MASK_0 -(31 15) routing lc_trk_g0_2 wire_bram/ram/MASK_0 -(31 15) routing lc_trk_g0_6 wire_bram/ram/MASK_0 -(31 15) routing lc_trk_g1_3 wire_bram/ram/MASK_0 -(31 15) routing lc_trk_g1_7 wire_bram/ram/MASK_0 -(31 15) routing lc_trk_g2_2 wire_bram/ram/MASK_0 -(31 15) routing lc_trk_g2_6 wire_bram/ram/MASK_0 -(31 15) routing lc_trk_g3_3 wire_bram/ram/MASK_0 -(31 15) routing lc_trk_g3_7 wire_bram/ram/MASK_0 -(31 2) routing lc_trk_g0_4 wire_bram/ram/MASK_6 -(31 2) routing lc_trk_g0_6 wire_bram/ram/MASK_6 -(31 2) routing lc_trk_g1_5 wire_bram/ram/MASK_6 -(31 2) routing lc_trk_g1_7 wire_bram/ram/MASK_6 -(31 2) routing lc_trk_g2_4 wire_bram/ram/MASK_6 -(31 2) routing lc_trk_g2_6 wire_bram/ram/MASK_6 -(31 2) routing lc_trk_g3_5 wire_bram/ram/MASK_6 -(31 2) routing lc_trk_g3_7 wire_bram/ram/MASK_6 -(31 3) routing lc_trk_g0_2 wire_bram/ram/MASK_6 -(31 3) routing lc_trk_g0_6 wire_bram/ram/MASK_6 -(31 3) routing lc_trk_g1_3 wire_bram/ram/MASK_6 -(31 3) routing lc_trk_g1_7 wire_bram/ram/MASK_6 -(31 3) routing lc_trk_g2_2 wire_bram/ram/MASK_6 -(31 3) routing lc_trk_g2_6 wire_bram/ram/MASK_6 -(31 3) routing lc_trk_g3_3 wire_bram/ram/MASK_6 -(31 3) routing lc_trk_g3_7 wire_bram/ram/MASK_6 -(31 4) routing lc_trk_g0_5 wire_bram/ram/MASK_5 -(31 4) routing lc_trk_g0_7 wire_bram/ram/MASK_5 -(31 4) routing lc_trk_g1_4 wire_bram/ram/MASK_5 -(31 4) routing lc_trk_g1_6 wire_bram/ram/MASK_5 -(31 4) routing lc_trk_g2_5 wire_bram/ram/MASK_5 -(31 4) routing lc_trk_g2_7 wire_bram/ram/MASK_5 -(31 4) routing lc_trk_g3_4 wire_bram/ram/MASK_5 -(31 4) routing lc_trk_g3_6 wire_bram/ram/MASK_5 -(31 5) routing lc_trk_g0_3 wire_bram/ram/MASK_5 -(31 5) routing lc_trk_g0_7 wire_bram/ram/MASK_5 -(31 5) routing lc_trk_g1_2 wire_bram/ram/MASK_5 -(31 5) routing lc_trk_g1_6 wire_bram/ram/MASK_5 -(31 5) routing lc_trk_g2_3 wire_bram/ram/MASK_5 -(31 5) routing lc_trk_g2_7 wire_bram/ram/MASK_5 -(31 5) routing lc_trk_g3_2 wire_bram/ram/MASK_5 -(31 5) routing lc_trk_g3_6 wire_bram/ram/MASK_5 -(31 6) routing lc_trk_g0_4 wire_bram/ram/MASK_4 -(31 6) routing lc_trk_g0_6 wire_bram/ram/MASK_4 -(31 6) routing lc_trk_g1_5 wire_bram/ram/MASK_4 -(31 6) routing lc_trk_g1_7 wire_bram/ram/MASK_4 -(31 6) routing lc_trk_g2_4 wire_bram/ram/MASK_4 -(31 6) routing lc_trk_g2_6 wire_bram/ram/MASK_4 -(31 6) routing lc_trk_g3_5 wire_bram/ram/MASK_4 -(31 6) routing lc_trk_g3_7 wire_bram/ram/MASK_4 -(31 7) routing lc_trk_g0_2 wire_bram/ram/MASK_4 -(31 7) routing lc_trk_g0_6 wire_bram/ram/MASK_4 -(31 7) routing lc_trk_g1_3 wire_bram/ram/MASK_4 -(31 7) routing lc_trk_g1_7 wire_bram/ram/MASK_4 -(31 7) routing lc_trk_g2_2 wire_bram/ram/MASK_4 -(31 7) routing lc_trk_g2_6 wire_bram/ram/MASK_4 -(31 7) routing lc_trk_g3_3 wire_bram/ram/MASK_4 -(31 7) routing lc_trk_g3_7 wire_bram/ram/MASK_4 -(31 8) routing lc_trk_g0_5 wire_bram/ram/MASK_3 -(31 8) routing lc_trk_g0_7 wire_bram/ram/MASK_3 -(31 8) routing lc_trk_g1_4 wire_bram/ram/MASK_3 -(31 8) routing lc_trk_g1_6 wire_bram/ram/MASK_3 -(31 8) routing lc_trk_g2_5 wire_bram/ram/MASK_3 -(31 8) routing lc_trk_g2_7 wire_bram/ram/MASK_3 -(31 8) routing lc_trk_g3_4 wire_bram/ram/MASK_3 -(31 8) routing lc_trk_g3_6 wire_bram/ram/MASK_3 -(31 9) routing lc_trk_g0_3 wire_bram/ram/MASK_3 -(31 9) routing lc_trk_g0_7 wire_bram/ram/MASK_3 -(31 9) routing lc_trk_g1_2 wire_bram/ram/MASK_3 -(31 9) routing lc_trk_g1_6 wire_bram/ram/MASK_3 -(31 9) routing lc_trk_g2_3 wire_bram/ram/MASK_3 -(31 9) routing lc_trk_g2_7 wire_bram/ram/MASK_3 -(31 9) routing lc_trk_g3_2 wire_bram/ram/MASK_3 -(31 9) routing lc_trk_g3_6 wire_bram/ram/MASK_3 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_3 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_5 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g0_7 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_0 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_2 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_4 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g1_6 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_1 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_3 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_5 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g2_7 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_0 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_2 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_4 wire_bram/ram/MASK_7 -(32 0) Enable bit of Mux _bram/lcb3_0 => lc_trk_g3_6 wire_bram/ram/MASK_7 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_2 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_4 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g0_6 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_1 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_3 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_5 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g1_7 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_0 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_2 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_4 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g2_6 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_1 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_3 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_5 wire_bram/ram/MASK_2 -(32 10) Enable bit of Mux _bram/lcb3_5 => lc_trk_g3_7 wire_bram/ram/MASK_2 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_1 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_3 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_5 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g0_7 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_0 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_2 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_4 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g1_6 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_1 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_3 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_5 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g2_7 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_0 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_2 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_4 input2_5 -(32 11) Enable bit of Mux _bram/lcb2_5 => lc_trk_g3_6 input2_5 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_3 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_5 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g0_7 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_0 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_2 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_4 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g1_6 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_1 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_3 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_5 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g2_7 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_0 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_2 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_4 wire_bram/ram/MASK_1 -(32 12) Enable bit of Mux _bram/lcb3_6 => lc_trk_g3_6 wire_bram/ram/MASK_1 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_0 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_2 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_4 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g0_6 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_1 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_3 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_5 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g1_7 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_0 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_2 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_4 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g2_6 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_1 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_3 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_5 input2_6 -(32 13) Enable bit of Mux _bram/lcb2_6 => lc_trk_g3_7 input2_6 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_2 wire_bram/ram/MASK_0 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_4 wire_bram/ram/MASK_0 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g0_6 wire_bram/ram/MASK_0 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_1 wire_bram/ram/MASK_0 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_3 wire_bram/ram/MASK_0 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_5 wire_bram/ram/MASK_0 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g1_7 wire_bram/ram/MASK_0 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_0 wire_bram/ram/MASK_0 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_2 wire_bram/ram/MASK_0 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_4 wire_bram/ram/MASK_0 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g2_6 wire_bram/ram/MASK_0 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_1 wire_bram/ram/MASK_0 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_3 wire_bram/ram/MASK_0 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_5 wire_bram/ram/MASK_0 -(32 14) Enable bit of Mux _bram/lcb3_7 => lc_trk_g3_7 wire_bram/ram/MASK_0 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_1 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_3 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_5 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g0_7 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_0 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_2 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_4 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g1_6 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_1 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_3 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_5 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g2_7 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_0 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_2 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_4 input2_7 -(32 15) Enable bit of Mux _bram/lcb2_7 => lc_trk_g3_6 input2_7 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_2 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_4 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g0_6 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_1 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_3 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_5 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g1_7 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_0 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_2 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_4 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g2_6 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_1 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_3 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_5 wire_bram/ram/MASK_6 -(32 2) Enable bit of Mux _bram/lcb3_1 => lc_trk_g3_7 wire_bram/ram/MASK_6 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_3 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_5 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g0_7 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_0 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_2 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_4 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g1_6 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_1 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_3 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_5 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g2_7 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_0 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_2 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_4 wire_bram/ram/MASK_5 -(32 4) Enable bit of Mux _bram/lcb3_2 => lc_trk_g3_6 wire_bram/ram/MASK_5 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_2 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_4 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g0_6 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_1 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_3 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_5 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g1_7 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_0 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_2 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_4 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g2_6 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_1 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_3 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_5 wire_bram/ram/MASK_4 -(32 6) Enable bit of Mux _bram/lcb3_3 => lc_trk_g3_7 wire_bram/ram/MASK_4 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_3 wire_bram/ram/MASK_3 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_5 wire_bram/ram/MASK_3 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g0_7 wire_bram/ram/MASK_3 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_0 wire_bram/ram/MASK_3 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_2 wire_bram/ram/MASK_3 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_4 wire_bram/ram/MASK_3 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g1_6 wire_bram/ram/MASK_3 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_1 wire_bram/ram/MASK_3 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_3 wire_bram/ram/MASK_3 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_5 wire_bram/ram/MASK_3 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g2_7 wire_bram/ram/MASK_3 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_0 wire_bram/ram/MASK_3 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_2 wire_bram/ram/MASK_3 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_4 wire_bram/ram/MASK_3 -(32 8) Enable bit of Mux _bram/lcb3_4 => lc_trk_g3_6 wire_bram/ram/MASK_3 -(33 0) routing lc_trk_g2_1 wire_bram/ram/MASK_7 -(33 0) routing lc_trk_g2_3 wire_bram/ram/MASK_7 -(33 0) routing lc_trk_g2_5 wire_bram/ram/MASK_7 -(33 0) routing lc_trk_g2_7 wire_bram/ram/MASK_7 -(33 0) routing lc_trk_g3_0 wire_bram/ram/MASK_7 -(33 0) routing lc_trk_g3_2 wire_bram/ram/MASK_7 -(33 0) routing lc_trk_g3_4 wire_bram/ram/MASK_7 -(33 0) routing lc_trk_g3_6 wire_bram/ram/MASK_7 -(33 10) routing lc_trk_g2_0 wire_bram/ram/MASK_2 -(33 10) routing lc_trk_g2_2 wire_bram/ram/MASK_2 -(33 10) routing lc_trk_g2_4 wire_bram/ram/MASK_2 -(33 10) routing lc_trk_g2_6 wire_bram/ram/MASK_2 -(33 10) routing lc_trk_g3_1 wire_bram/ram/MASK_2 -(33 10) routing lc_trk_g3_3 wire_bram/ram/MASK_2 -(33 10) routing lc_trk_g3_5 wire_bram/ram/MASK_2 -(33 10) routing lc_trk_g3_7 wire_bram/ram/MASK_2 -(33 11) routing lc_trk_g2_1 input2_5 -(33 11) routing lc_trk_g2_3 input2_5 -(33 11) routing lc_trk_g2_5 input2_5 -(33 11) routing lc_trk_g2_7 input2_5 -(33 11) routing lc_trk_g3_0 input2_5 -(33 11) routing lc_trk_g3_2 input2_5 -(33 11) routing lc_trk_g3_4 input2_5 -(33 11) routing lc_trk_g3_6 input2_5 -(33 12) routing lc_trk_g2_1 wire_bram/ram/MASK_1 -(33 12) routing lc_trk_g2_3 wire_bram/ram/MASK_1 -(33 12) routing lc_trk_g2_5 wire_bram/ram/MASK_1 -(33 12) routing lc_trk_g2_7 wire_bram/ram/MASK_1 -(33 12) routing lc_trk_g3_0 wire_bram/ram/MASK_1 -(33 12) routing lc_trk_g3_2 wire_bram/ram/MASK_1 -(33 12) routing lc_trk_g3_4 wire_bram/ram/MASK_1 -(33 12) routing lc_trk_g3_6 wire_bram/ram/MASK_1 -(33 13) routing lc_trk_g2_0 input2_6 -(33 13) routing lc_trk_g2_2 input2_6 -(33 13) routing lc_trk_g2_4 input2_6 -(33 13) routing lc_trk_g2_6 input2_6 -(33 13) routing lc_trk_g3_1 input2_6 -(33 13) routing lc_trk_g3_3 input2_6 -(33 13) routing lc_trk_g3_5 input2_6 -(33 13) routing lc_trk_g3_7 input2_6 -(33 14) routing lc_trk_g2_0 wire_bram/ram/MASK_0 -(33 14) routing lc_trk_g2_2 wire_bram/ram/MASK_0 -(33 14) routing lc_trk_g2_4 wire_bram/ram/MASK_0 -(33 14) routing lc_trk_g2_6 wire_bram/ram/MASK_0 -(33 14) routing lc_trk_g3_1 wire_bram/ram/MASK_0 -(33 14) routing lc_trk_g3_3 wire_bram/ram/MASK_0 -(33 14) routing lc_trk_g3_5 wire_bram/ram/MASK_0 -(33 14) routing lc_trk_g3_7 wire_bram/ram/MASK_0 -(33 15) routing lc_trk_g2_1 input2_7 -(33 15) routing lc_trk_g2_3 input2_7 -(33 15) routing lc_trk_g2_5 input2_7 -(33 15) routing lc_trk_g2_7 input2_7 -(33 15) routing lc_trk_g3_0 input2_7 -(33 15) routing lc_trk_g3_2 input2_7 -(33 15) routing lc_trk_g3_4 input2_7 -(33 15) routing lc_trk_g3_6 input2_7 -(33 2) routing lc_trk_g2_0 wire_bram/ram/MASK_6 -(33 2) routing lc_trk_g2_2 wire_bram/ram/MASK_6 -(33 2) routing lc_trk_g2_4 wire_bram/ram/MASK_6 -(33 2) routing lc_trk_g2_6 wire_bram/ram/MASK_6 -(33 2) routing lc_trk_g3_1 wire_bram/ram/MASK_6 -(33 2) routing lc_trk_g3_3 wire_bram/ram/MASK_6 -(33 2) routing lc_trk_g3_5 wire_bram/ram/MASK_6 -(33 2) routing lc_trk_g3_7 wire_bram/ram/MASK_6 -(33 4) routing lc_trk_g2_1 wire_bram/ram/MASK_5 -(33 4) routing lc_trk_g2_3 wire_bram/ram/MASK_5 -(33 4) routing lc_trk_g2_5 wire_bram/ram/MASK_5 -(33 4) routing lc_trk_g2_7 wire_bram/ram/MASK_5 -(33 4) routing lc_trk_g3_0 wire_bram/ram/MASK_5 -(33 4) routing lc_trk_g3_2 wire_bram/ram/MASK_5 -(33 4) routing lc_trk_g3_4 wire_bram/ram/MASK_5 -(33 4) routing lc_trk_g3_6 wire_bram/ram/MASK_5 -(33 6) routing lc_trk_g2_0 wire_bram/ram/MASK_4 -(33 6) routing lc_trk_g2_2 wire_bram/ram/MASK_4 -(33 6) routing lc_trk_g2_4 wire_bram/ram/MASK_4 -(33 6) routing lc_trk_g2_6 wire_bram/ram/MASK_4 -(33 6) routing lc_trk_g3_1 wire_bram/ram/MASK_4 -(33 6) routing lc_trk_g3_3 wire_bram/ram/MASK_4 -(33 6) routing lc_trk_g3_5 wire_bram/ram/MASK_4 -(33 6) routing lc_trk_g3_7 wire_bram/ram/MASK_4 -(33 8) routing lc_trk_g2_1 wire_bram/ram/MASK_3 -(33 8) routing lc_trk_g2_3 wire_bram/ram/MASK_3 -(33 8) routing lc_trk_g2_5 wire_bram/ram/MASK_3 -(33 8) routing lc_trk_g2_7 wire_bram/ram/MASK_3 -(33 8) routing lc_trk_g3_0 wire_bram/ram/MASK_3 -(33 8) routing lc_trk_g3_2 wire_bram/ram/MASK_3 -(33 8) routing lc_trk_g3_4 wire_bram/ram/MASK_3 -(33 8) routing lc_trk_g3_6 wire_bram/ram/MASK_3 -(34 0) routing lc_trk_g1_0 wire_bram/ram/MASK_7 -(34 0) routing lc_trk_g1_2 wire_bram/ram/MASK_7 -(34 0) routing lc_trk_g1_4 wire_bram/ram/MASK_7 -(34 0) routing lc_trk_g1_6 wire_bram/ram/MASK_7 -(34 0) routing lc_trk_g3_0 wire_bram/ram/MASK_7 -(34 0) routing lc_trk_g3_2 wire_bram/ram/MASK_7 -(34 0) routing lc_trk_g3_4 wire_bram/ram/MASK_7 -(34 0) routing lc_trk_g3_6 wire_bram/ram/MASK_7 -(34 10) routing lc_trk_g1_1 wire_bram/ram/MASK_2 -(34 10) routing lc_trk_g1_3 wire_bram/ram/MASK_2 -(34 10) routing lc_trk_g1_5 wire_bram/ram/MASK_2 -(34 10) routing lc_trk_g1_7 wire_bram/ram/MASK_2 -(34 10) routing lc_trk_g3_1 wire_bram/ram/MASK_2 -(34 10) routing lc_trk_g3_3 wire_bram/ram/MASK_2 -(34 10) routing lc_trk_g3_5 wire_bram/ram/MASK_2 -(34 10) routing lc_trk_g3_7 wire_bram/ram/MASK_2 -(34 11) routing lc_trk_g1_0 input2_5 -(34 11) routing lc_trk_g1_2 input2_5 -(34 11) routing lc_trk_g1_4 input2_5 -(34 11) routing lc_trk_g1_6 input2_5 -(34 11) routing lc_trk_g3_0 input2_5 -(34 11) routing lc_trk_g3_2 input2_5 -(34 11) routing lc_trk_g3_4 input2_5 -(34 11) routing lc_trk_g3_6 input2_5 -(34 12) routing lc_trk_g1_0 wire_bram/ram/MASK_1 -(34 12) routing lc_trk_g1_2 wire_bram/ram/MASK_1 -(34 12) routing lc_trk_g1_4 wire_bram/ram/MASK_1 -(34 12) routing lc_trk_g1_6 wire_bram/ram/MASK_1 -(34 12) routing lc_trk_g3_0 wire_bram/ram/MASK_1 -(34 12) routing lc_trk_g3_2 wire_bram/ram/MASK_1 -(34 12) routing lc_trk_g3_4 wire_bram/ram/MASK_1 -(34 12) routing lc_trk_g3_6 wire_bram/ram/MASK_1 -(34 13) routing lc_trk_g1_1 input2_6 -(34 13) routing lc_trk_g1_3 input2_6 -(34 13) routing lc_trk_g1_5 input2_6 -(34 13) routing lc_trk_g1_7 input2_6 -(34 13) routing lc_trk_g3_1 input2_6 -(34 13) routing lc_trk_g3_3 input2_6 -(34 13) routing lc_trk_g3_5 input2_6 -(34 13) routing lc_trk_g3_7 input2_6 -(34 14) routing lc_trk_g1_1 wire_bram/ram/MASK_0 -(34 14) routing lc_trk_g1_3 wire_bram/ram/MASK_0 -(34 14) routing lc_trk_g1_5 wire_bram/ram/MASK_0 -(34 14) routing lc_trk_g1_7 wire_bram/ram/MASK_0 -(34 14) routing lc_trk_g3_1 wire_bram/ram/MASK_0 -(34 14) routing lc_trk_g3_3 wire_bram/ram/MASK_0 -(34 14) routing lc_trk_g3_5 wire_bram/ram/MASK_0 -(34 14) routing lc_trk_g3_7 wire_bram/ram/MASK_0 -(34 15) routing lc_trk_g1_0 input2_7 -(34 15) routing lc_trk_g1_2 input2_7 -(34 15) routing lc_trk_g1_4 input2_7 -(34 15) routing lc_trk_g1_6 input2_7 -(34 15) routing lc_trk_g3_0 input2_7 -(34 15) routing lc_trk_g3_2 input2_7 -(34 15) routing lc_trk_g3_4 input2_7 -(34 15) routing lc_trk_g3_6 input2_7 -(34 2) routing lc_trk_g1_1 wire_bram/ram/MASK_6 -(34 2) routing lc_trk_g1_3 wire_bram/ram/MASK_6 -(34 2) routing lc_trk_g1_5 wire_bram/ram/MASK_6 -(34 2) routing lc_trk_g1_7 wire_bram/ram/MASK_6 -(34 2) routing lc_trk_g3_1 wire_bram/ram/MASK_6 -(34 2) routing lc_trk_g3_3 wire_bram/ram/MASK_6 -(34 2) routing lc_trk_g3_5 wire_bram/ram/MASK_6 -(34 2) routing lc_trk_g3_7 wire_bram/ram/MASK_6 -(34 4) routing lc_trk_g1_0 wire_bram/ram/MASK_5 -(34 4) routing lc_trk_g1_2 wire_bram/ram/MASK_5 -(34 4) routing lc_trk_g1_4 wire_bram/ram/MASK_5 -(34 4) routing lc_trk_g1_6 wire_bram/ram/MASK_5 -(34 4) routing lc_trk_g3_0 wire_bram/ram/MASK_5 -(34 4) routing lc_trk_g3_2 wire_bram/ram/MASK_5 -(34 4) routing lc_trk_g3_4 wire_bram/ram/MASK_5 -(34 4) routing lc_trk_g3_6 wire_bram/ram/MASK_5 -(34 6) routing lc_trk_g1_1 wire_bram/ram/MASK_4 -(34 6) routing lc_trk_g1_3 wire_bram/ram/MASK_4 -(34 6) routing lc_trk_g1_5 wire_bram/ram/MASK_4 -(34 6) routing lc_trk_g1_7 wire_bram/ram/MASK_4 -(34 6) routing lc_trk_g3_1 wire_bram/ram/MASK_4 -(34 6) routing lc_trk_g3_3 wire_bram/ram/MASK_4 -(34 6) routing lc_trk_g3_5 wire_bram/ram/MASK_4 -(34 6) routing lc_trk_g3_7 wire_bram/ram/MASK_4 -(34 8) routing lc_trk_g1_0 wire_bram/ram/MASK_3 -(34 8) routing lc_trk_g1_2 wire_bram/ram/MASK_3 -(34 8) routing lc_trk_g1_4 wire_bram/ram/MASK_3 -(34 8) routing lc_trk_g1_6 wire_bram/ram/MASK_3 -(34 8) routing lc_trk_g3_0 wire_bram/ram/MASK_3 -(34 8) routing lc_trk_g3_2 wire_bram/ram/MASK_3 -(34 8) routing lc_trk_g3_4 wire_bram/ram/MASK_3 -(34 8) routing lc_trk_g3_6 wire_bram/ram/MASK_3 -(35 10) routing lc_trk_g0_5 input2_5 -(35 10) routing lc_trk_g0_7 input2_5 -(35 10) routing lc_trk_g1_4 input2_5 -(35 10) routing lc_trk_g1_6 input2_5 -(35 10) routing lc_trk_g2_5 input2_5 -(35 10) routing lc_trk_g2_7 input2_5 -(35 10) routing lc_trk_g3_4 input2_5 -(35 10) routing lc_trk_g3_6 input2_5 -(35 11) routing lc_trk_g0_3 input2_5 -(35 11) routing lc_trk_g0_7 input2_5 -(35 11) routing lc_trk_g1_2 input2_5 -(35 11) routing lc_trk_g1_6 input2_5 -(35 11) routing lc_trk_g2_3 input2_5 -(35 11) routing lc_trk_g2_7 input2_5 -(35 11) routing lc_trk_g3_2 input2_5 -(35 11) routing lc_trk_g3_6 input2_5 -(35 12) routing lc_trk_g0_4 input2_6 -(35 12) routing lc_trk_g0_6 input2_6 -(35 12) routing lc_trk_g1_5 input2_6 -(35 12) routing lc_trk_g1_7 input2_6 -(35 12) routing lc_trk_g2_4 input2_6 -(35 12) routing lc_trk_g2_6 input2_6 -(35 12) routing lc_trk_g3_5 input2_6 -(35 12) routing lc_trk_g3_7 input2_6 -(35 13) routing lc_trk_g0_2 input2_6 -(35 13) routing lc_trk_g0_6 input2_6 -(35 13) routing lc_trk_g1_3 input2_6 -(35 13) routing lc_trk_g1_7 input2_6 -(35 13) routing lc_trk_g2_2 input2_6 -(35 13) routing lc_trk_g2_6 input2_6 -(35 13) routing lc_trk_g3_3 input2_6 -(35 13) routing lc_trk_g3_7 input2_6 -(35 14) routing lc_trk_g0_5 input2_7 -(35 14) routing lc_trk_g0_7 input2_7 -(35 14) routing lc_trk_g1_4 input2_7 -(35 14) routing lc_trk_g1_6 input2_7 -(35 14) routing lc_trk_g2_5 input2_7 -(35 14) routing lc_trk_g2_7 input2_7 -(35 14) routing lc_trk_g3_4 input2_7 -(35 14) routing lc_trk_g3_6 input2_7 -(35 15) routing lc_trk_g0_3 input2_7 -(35 15) routing lc_trk_g0_7 input2_7 -(35 15) routing lc_trk_g1_2 input2_7 -(35 15) routing lc_trk_g1_6 input2_7 -(35 15) routing lc_trk_g2_3 input2_7 -(35 15) routing lc_trk_g2_7 input2_7 -(35 15) routing lc_trk_g3_2 input2_7 -(35 15) routing lc_trk_g3_6 input2_7 -(36 0) Enable bit of Mux _out_links/OutMux8_0 => wire_bram/ram/RDATA_7 sp4_h_l_21 -(36 1) Enable bit of Mux _out_links/OutMux6_0 => wire_bram/ram/RDATA_7 sp4_h_r_0 -(36 10) Enable bit of Mux _out_links/OutMux8_5 => wire_bram/ram/RDATA_2 sp4_h_r_42 -(36 11) Enable bit of Mux _out_links/OutMux6_5 => wire_bram/ram/RDATA_2 sp4_h_r_10 -(36 12) Enable bit of Mux _out_links/OutMux8_6 => wire_bram/ram/RDATA_1 sp4_h_r_44 -(36 13) Enable bit of Mux _out_links/OutMux6_6 => wire_bram/ram/RDATA_1 sp4_h_r_12 -(36 14) Enable bit of Mux _out_links/OutMux8_7 => wire_bram/ram/RDATA_0 sp4_h_r_46 -(36 15) Enable bit of Mux _out_links/OutMux6_7 => wire_bram/ram/RDATA_0 sp4_h_l_3 -(36 2) Enable bit of Mux _out_links/OutMux8_1 => wire_bram/ram/RDATA_6 sp4_h_r_34 -(36 3) Enable bit of Mux _out_links/OutMux6_1 => wire_bram/ram/RDATA_6 sp4_h_r_2 -(36 4) Enable bit of Mux _out_links/OutMux8_2 => wire_bram/ram/RDATA_5 sp4_h_r_36 -(36 5) Enable bit of Mux _out_links/OutMux6_2 => wire_bram/ram/RDATA_5 sp4_h_r_4 -(36 6) Enable bit of Mux _out_links/OutMux8_3 => wire_bram/ram/RDATA_4 sp4_h_l_27 -(36 7) Enable bit of Mux _out_links/OutMux6_3 => wire_bram/ram/RDATA_4 sp4_h_r_6 -(36 8) Enable bit of Mux _out_links/OutMux8_4 => wire_bram/ram/RDATA_3 sp4_h_l_29 -(36 9) Enable bit of Mux _out_links/OutMux6_4 => wire_bram/ram/RDATA_3 sp4_h_r_8 -(37 0) Enable bit of Mux _out_links/OutMux5_0 => wire_bram/ram/RDATA_7 sp12_h_r_8 -(37 1) Enable bit of Mux _out_links/OutMux7_0 => wire_bram/ram/RDATA_7 sp4_h_l_5 -(37 10) Enable bit of Mux _out_links/OutMux4_5 => wire_bram/ram/RDATA_2 sp12_h_r_2 -(37 11) Enable bit of Mux _out_links/OutMux7_5 => wire_bram/ram/RDATA_2 sp4_h_l_15 -(37 12) Enable bit of Mux _out_links/OutMux4_6 => wire_bram/ram/RDATA_1 sp12_h_l_3 -(37 13) Enable bit of Mux _out_links/OutMux7_6 => wire_bram/ram/RDATA_1 sp4_h_l_17 -(37 14) Enable bit of Mux _out_links/OutMux4_7 => wire_bram/ram/RDATA_0 sp12_h_l_5 -(37 15) Enable bit of Mux _out_links/OutMux7_7 => wire_bram/ram/RDATA_0 sp4_h_r_30 -(37 2) Enable bit of Mux _out_links/OutMux5_1 => wire_bram/ram/RDATA_6 sp12_h_r_10 -(37 3) Enable bit of Mux _out_links/OutMux7_1 => wire_bram/ram/RDATA_6 sp4_h_l_7 -(37 4) Enable bit of Mux _out_links/OutMux5_2 => wire_bram/ram/RDATA_5 sp12_h_r_12 -(37 5) Enable bit of Mux _out_links/OutMux7_2 => wire_bram/ram/RDATA_5 sp4_h_r_20 -(37 6) Enable bit of Mux _out_links/OutMux5_3 => wire_bram/ram/RDATA_4 sp12_h_l_13 -(37 7) Enable bit of Mux _out_links/OutMux7_3 => wire_bram/ram/RDATA_4 sp4_h_r_22 -(37 8) Enable bit of Mux _out_links/OutMux4_4 => wire_bram/ram/RDATA_3 sp12_h_r_0 -(37 9) Enable bit of Mux _out_links/OutMux7_4 => wire_bram/ram/RDATA_3 sp4_h_l_13 -(38 0) Enable bit of Mux _out_links/OutMux2_0 => wire_bram/ram/RDATA_7 sp4_v_t_21 -(38 1) Enable bit of Mux _out_links/OutMux0_0 => wire_bram/ram/RDATA_7 sp4_v_b_0 -(38 10) Enable bit of Mux _out_links/OutMux1_5 => wire_bram/ram/RDATA_2 sp4_v_b_26 -(38 11) Enable bit of Mux _out_links/OutMux5_5 => wire_bram/ram/RDATA_2 sp12_h_r_18 -(38 12) Enable bit of Mux _out_links/OutMux1_6 => wire_bram/ram/RDATA_1 sp4_v_b_28 -(38 13) Enable bit of Mux _out_links/OutMux5_6 => wire_bram/ram/RDATA_1 sp12_h_r_20 -(38 14) Enable bit of Mux _out_links/OutMux1_7 => wire_bram/ram/RDATA_0 sp4_v_b_30 -(38 15) Enable bit of Mux _out_links/OutMux5_7 => wire_bram/ram/RDATA_0 sp12_h_l_21 -(38 2) Enable bit of Mux _out_links/OutMux2_1 => wire_bram/ram/RDATA_6 sp4_v_t_23 -(38 3) Enable bit of Mux _out_links/OutMux0_1 => wire_bram/ram/RDATA_6 sp4_v_b_2 -(38 4) Enable bit of Mux _out_links/OutMux2_2 => wire_bram/ram/RDATA_5 sp4_v_t_25 -(38 5) Enable bit of Mux _out_links/OutMux0_2 => wire_bram/ram/RDATA_5 sp4_v_b_4 -(38 6) Enable bit of Mux _out_links/OutMux2_3 => wire_bram/ram/RDATA_4 sp4_v_b_38 -(38 7) Enable bit of Mux _out_links/OutMux0_3 => wire_bram/ram/RDATA_4 sp4_v_b_6 -(38 8) Enable bit of Mux _out_links/OutMux1_4 => wire_bram/ram/RDATA_3 sp4_v_t_13 -(38 9) Enable bit of Mux _out_links/OutMux5_4 => wire_bram/ram/RDATA_3 sp12_h_r_16 -(39 0) Enable bit of Mux _out_links/OutMux3_0 => wire_bram/ram/RDATA_7 sp12_v_b_0 -(39 1) Enable bit of Mux _out_links/OutMux1_0 => wire_bram/ram/RDATA_7 sp4_v_b_16 -(39 10) Enable bit of Mux _out_links/OutMux2_5 => wire_bram/ram/RDATA_2 sp4_v_t_31 -(39 11) Enable bit of Mux _out_links/OutMux0_5 => wire_bram/ram/RDATA_2 sp4_v_b_10 -(39 12) Enable bit of Mux _out_links/OutMux2_6 => wire_bram/ram/RDATA_1 sp4_v_t_33 -(39 13) Enable bit of Mux _out_links/OutMux0_6 => wire_bram/ram/RDATA_1 sp4_v_t_1 -(39 14) Enable bit of Mux _out_links/OutMux2_7 => wire_bram/ram/RDATA_0 sp4_v_b_46 -(39 15) Enable bit of Mux _out_links/OutMux0_7 => wire_bram/ram/RDATA_0 sp4_v_b_14 -(39 2) Enable bit of Mux _out_links/OutMux3_1 => wire_bram/ram/RDATA_6 sp12_v_b_2 -(39 3) Enable bit of Mux _out_links/OutMux1_1 => wire_bram/ram/RDATA_6 sp4_v_t_7 -(39 4) Enable bit of Mux _out_links/OutMux3_2 => wire_bram/ram/RDATA_5 sp12_v_t_3 -(39 5) Enable bit of Mux _out_links/OutMux1_2 => wire_bram/ram/RDATA_5 sp4_v_b_20 -(39 6) Enable bit of Mux _out_links/OutMux3_3 => wire_bram/ram/RDATA_4 sp12_v_b_6 -(39 7) Enable bit of Mux _out_links/OutMux1_3 => wire_bram/ram/RDATA_4 sp4_v_b_22 -(39 8) Enable bit of Mux _out_links/OutMux2_4 => wire_bram/ram/RDATA_3 sp4_v_b_40 -(39 9) Enable bit of Mux _out_links/OutMux0_4 => wire_bram/ram/RDATA_3 sp4_v_b_8 -(4 0) routing sp4_h_l_37 sp4_v_b_0 -(4 0) routing sp4_h_l_43 sp4_v_b_0 -(4 0) routing sp4_v_t_37 sp4_v_b_0 -(4 0) routing sp4_v_t_41 sp4_v_b_0 -(4 1) routing sp4_h_l_41 sp4_h_r_0 -(4 1) routing sp4_h_l_44 sp4_h_r_0 -(4 1) routing sp4_v_b_6 sp4_h_r_0 -(4 1) routing sp4_v_t_42 sp4_h_r_0 -(4 10) routing sp4_h_r_0 sp4_v_t_43 -(4 10) routing sp4_h_r_6 sp4_v_t_43 -(4 10) routing sp4_v_b_10 sp4_v_t_43 -(4 10) routing sp4_v_b_6 sp4_v_t_43 -(4 11) routing sp4_h_r_10 sp4_h_l_43 -(4 11) routing sp4_h_r_3 sp4_h_l_43 -(4 11) routing sp4_v_b_1 sp4_h_l_43 -(4 11) routing sp4_v_t_37 sp4_h_l_43 -(4 12) routing sp4_h_l_38 sp4_v_b_9 -(4 12) routing sp4_h_l_44 sp4_v_b_9 -(4 12) routing sp4_v_t_36 sp4_v_b_9 -(4 12) routing sp4_v_t_44 sp4_v_b_9 -(4 13) routing sp4_h_l_36 sp4_h_r_9 -(4 13) routing sp4_h_l_43 sp4_h_r_9 -(4 13) routing sp4_v_b_3 sp4_h_r_9 -(4 13) routing sp4_v_t_41 sp4_h_r_9 -(4 14) routing sp4_h_r_3 sp4_v_t_44 -(4 14) routing sp4_h_r_9 sp4_v_t_44 -(4 14) routing sp4_v_b_1 sp4_v_t_44 -(4 14) routing sp4_v_b_9 sp4_v_t_44 -(4 15) routing sp4_h_r_1 sp4_h_l_44 -(4 15) routing sp4_h_r_6 sp4_h_l_44 -(4 15) routing sp4_v_b_4 sp4_h_l_44 -(4 15) routing sp4_v_t_38 sp4_h_l_44 -(4 2) routing sp4_h_r_0 sp4_v_t_37 -(4 2) routing sp4_h_r_6 sp4_v_t_37 -(4 2) routing sp4_v_b_0 sp4_v_t_37 -(4 2) routing sp4_v_b_4 sp4_v_t_37 -(4 3) routing sp4_h_r_4 sp4_h_l_37 -(4 3) routing sp4_h_r_9 sp4_h_l_37 -(4 3) routing sp4_v_b_7 sp4_h_l_37 -(4 3) routing sp4_v_t_43 sp4_h_l_37 -(4 4) routing sp4_h_l_38 sp4_v_b_3 -(4 4) routing sp4_h_l_44 sp4_v_b_3 -(4 4) routing sp4_v_t_38 sp4_v_b_3 -(4 4) routing sp4_v_t_42 sp4_v_b_3 -(4 5) routing sp4_h_l_37 sp4_h_r_3 -(4 5) routing sp4_h_l_42 sp4_h_r_3 -(4 5) routing sp4_v_b_9 sp4_h_r_3 -(4 5) routing sp4_v_t_47 sp4_h_r_3 -(4 6) routing sp4_h_r_3 sp4_v_t_38 -(4 6) routing sp4_h_r_9 sp4_v_t_38 -(4 6) routing sp4_v_b_3 sp4_v_t_38 -(4 6) routing sp4_v_b_7 sp4_v_t_38 -(4 7) routing sp4_h_r_0 sp4_h_l_38 -(4 7) routing sp4_h_r_7 sp4_h_l_38 -(4 7) routing sp4_v_b_10 sp4_h_l_38 -(4 7) routing sp4_v_t_44 sp4_h_l_38 -(4 8) routing sp4_h_l_37 sp4_v_b_6 -(4 8) routing sp4_h_l_43 sp4_v_b_6 -(4 8) routing sp4_v_t_43 sp4_v_b_6 -(4 8) routing sp4_v_t_47 sp4_v_b_6 -(4 9) routing sp4_h_l_38 sp4_h_r_6 -(4 9) routing sp4_h_l_47 sp4_h_r_6 -(4 9) routing sp4_v_b_0 sp4_h_r_6 -(4 9) routing sp4_v_t_36 sp4_h_r_6 -(40 0) Enable bit of Mux _out_links/OutMuxa_0 => wire_bram/ram/RDATA_7 sp4_r_v_b_17 -(40 1) Enable bit of Mux _out_links/OutMux4_0 => wire_bram/ram/RDATA_7 sp12_v_b_16 -(40 10) Enable bit of Mux _out_links/OutMuxa_5 => wire_bram/ram/RDATA_2 sp4_r_v_b_27 -(40 11) Enable bit of Mux _out_links/OutMux3_5 => wire_bram/ram/RDATA_2 sp12_v_t_9 -(40 12) Enable bit of Mux _out_links/OutMuxa_6 => wire_bram/ram/RDATA_1 sp4_r_v_b_29 -(40 13) Enable bit of Mux _out_links/OutMux3_6 => wire_bram/ram/RDATA_1 sp12_v_b_12 -(40 14) Enable bit of Mux _out_links/OutMuxa_7 => wire_bram/ram/RDATA_0 sp4_r_v_b_31 -(40 15) Enable bit of Mux _out_links/OutMux3_7 => wire_bram/ram/RDATA_0 sp12_v_b_14 -(40 2) Enable bit of Mux _out_links/OutMuxa_1 => wire_bram/ram/RDATA_6 sp4_r_v_b_19 -(40 3) Enable bit of Mux _out_links/OutMux4_1 => wire_bram/ram/RDATA_6 sp12_v_t_17 -(40 4) Enable bit of Mux _out_links/OutMuxa_2 => wire_bram/ram/RDATA_5 sp4_r_v_b_21 -(40 5) Enable bit of Mux _out_links/OutMux4_2 => wire_bram/ram/RDATA_5 sp12_v_t_19 -(40 6) Enable bit of Mux _out_links/OutMuxa_3 => wire_bram/ram/RDATA_4 sp4_r_v_b_23 -(40 7) Enable bit of Mux _out_links/OutMux4_3 => wire_bram/ram/RDATA_4 sp12_v_t_21 -(40 8) Enable bit of Mux _out_links/OutMuxa_4 => wire_bram/ram/RDATA_3 sp4_r_v_b_25 -(40 9) Enable bit of Mux _out_links/OutMux3_4 => wire_bram/ram/RDATA_3 sp12_v_t_7 -(41 0) Enable bit of Mux _out_links/OutMuxb_0 => wire_bram/ram/RDATA_7 sp4_r_v_b_33 -(41 1) Enable bit of Mux _out_links/OutMux9_0 => wire_bram/ram/RDATA_7 sp4_r_v_b_1 -(41 10) Enable bit of Mux _out_links/OutMuxb_5 => wire_bram/ram/RDATA_2 sp4_r_v_b_43 -(41 11) Enable bit of Mux _out_links/OutMux9_5 => wire_bram/ram/RDATA_2 sp4_r_v_b_11 -(41 12) Enable bit of Mux _out_links/OutMuxb_6 => wire_bram/ram/RDATA_1 sp4_r_v_b_45 -(41 13) Enable bit of Mux _out_links/OutMux9_6 => wire_bram/ram/RDATA_1 sp4_r_v_b_13 -(41 14) Enable bit of Mux _out_links/OutMuxb_7 => wire_bram/ram/RDATA_0 sp4_r_v_b_47 -(41 15) Enable bit of Mux _out_links/OutMux9_7 => wire_bram/ram/RDATA_0 sp4_r_v_b_15 -(41 2) Enable bit of Mux _out_links/OutMuxb_1 => wire_bram/ram/RDATA_6 sp4_r_v_b_35 -(41 3) Enable bit of Mux _out_links/OutMux9_1 => wire_bram/ram/RDATA_6 sp4_r_v_b_3 -(41 4) Enable bit of Mux _out_links/OutMuxb_2 => wire_bram/ram/RDATA_5 sp4_r_v_b_37 -(41 5) Enable bit of Mux _out_links/OutMux9_2 => wire_bram/ram/RDATA_5 sp4_r_v_b_5 -(41 6) Enable bit of Mux _out_links/OutMuxb_3 => wire_bram/ram/RDATA_4 sp4_r_v_b_39 -(41 7) Enable bit of Mux _out_links/OutMux9_3 => wire_bram/ram/RDATA_4 sp4_r_v_b_7 -(41 8) Enable bit of Mux _out_links/OutMuxb_4 => wire_bram/ram/RDATA_3 sp4_r_v_b_41 -(41 9) Enable bit of Mux _out_links/OutMux9_4 => wire_bram/ram/RDATA_3 sp4_r_v_b_9 -(5 0) routing sp4_h_l_44 sp4_h_r_0 -(5 0) routing sp4_v_b_0 sp4_h_r_0 -(5 0) routing sp4_v_b_6 sp4_h_r_0 -(5 0) routing sp4_v_t_37 sp4_h_r_0 -(5 1) routing sp4_h_l_37 sp4_v_b_0 -(5 1) routing sp4_h_l_43 sp4_v_b_0 -(5 1) routing sp4_h_r_0 sp4_v_b_0 -(5 1) routing sp4_v_t_44 sp4_v_b_0 -(5 10) routing sp4_h_r_3 sp4_h_l_43 -(5 10) routing sp4_v_b_6 sp4_h_l_43 -(5 10) routing sp4_v_t_37 sp4_h_l_43 -(5 10) routing sp4_v_t_43 sp4_h_l_43 -(5 11) routing sp4_h_l_43 sp4_v_t_43 -(5 11) routing sp4_h_r_0 sp4_v_t_43 -(5 11) routing sp4_h_r_6 sp4_v_t_43 -(5 11) routing sp4_v_b_3 sp4_v_t_43 -(5 12) routing sp4_h_l_43 sp4_h_r_9 -(5 12) routing sp4_v_b_3 sp4_h_r_9 -(5 12) routing sp4_v_b_9 sp4_h_r_9 -(5 12) routing sp4_v_t_44 sp4_h_r_9 -(5 13) routing sp4_h_l_38 sp4_v_b_9 -(5 13) routing sp4_h_l_44 sp4_v_b_9 -(5 13) routing sp4_h_r_9 sp4_v_b_9 -(5 13) routing sp4_v_t_43 sp4_v_b_9 -(5 14) routing sp4_h_r_6 sp4_h_l_44 -(5 14) routing sp4_v_b_9 sp4_h_l_44 -(5 14) routing sp4_v_t_38 sp4_h_l_44 -(5 14) routing sp4_v_t_44 sp4_h_l_44 -(5 15) routing sp4_h_l_44 sp4_v_t_44 -(5 15) routing sp4_h_r_3 sp4_v_t_44 -(5 15) routing sp4_h_r_9 sp4_v_t_44 -(5 15) routing sp4_v_b_6 sp4_v_t_44 -(5 2) routing sp4_h_r_9 sp4_h_l_37 -(5 2) routing sp4_v_b_0 sp4_h_l_37 -(5 2) routing sp4_v_t_37 sp4_h_l_37 -(5 2) routing sp4_v_t_43 sp4_h_l_37 -(5 3) routing sp4_h_l_37 sp4_v_t_37 -(5 3) routing sp4_h_r_0 sp4_v_t_37 -(5 3) routing sp4_h_r_6 sp4_v_t_37 -(5 3) routing sp4_v_b_9 sp4_v_t_37 -(5 4) routing sp4_h_l_37 sp4_h_r_3 -(5 4) routing sp4_v_b_3 sp4_h_r_3 -(5 4) routing sp4_v_b_9 sp4_h_r_3 -(5 4) routing sp4_v_t_38 sp4_h_r_3 -(5 5) routing sp4_h_l_38 sp4_v_b_3 -(5 5) routing sp4_h_l_44 sp4_v_b_3 -(5 5) routing sp4_h_r_3 sp4_v_b_3 -(5 5) routing sp4_v_t_37 sp4_v_b_3 -(5 6) routing sp4_h_r_0 sp4_h_l_38 -(5 6) routing sp4_v_b_3 sp4_h_l_38 -(5 6) routing sp4_v_t_38 sp4_h_l_38 -(5 6) routing sp4_v_t_44 sp4_h_l_38 -(5 7) routing sp4_h_l_38 sp4_v_t_38 -(5 7) routing sp4_h_r_3 sp4_v_t_38 -(5 7) routing sp4_h_r_9 sp4_v_t_38 -(5 7) routing sp4_v_b_0 sp4_v_t_38 -(5 8) routing sp4_h_l_38 sp4_h_r_6 -(5 8) routing sp4_v_b_0 sp4_h_r_6 -(5 8) routing sp4_v_b_6 sp4_h_r_6 -(5 8) routing sp4_v_t_43 sp4_h_r_6 -(5 9) routing sp4_h_l_37 sp4_v_b_6 -(5 9) routing sp4_h_l_43 sp4_v_b_6 -(5 9) routing sp4_h_r_6 sp4_v_b_6 -(5 9) routing sp4_v_t_38 sp4_v_b_6 -(6 0) routing sp4_h_l_43 sp4_v_b_0 -(6 0) routing sp4_h_r_7 sp4_v_b_0 -(6 0) routing sp4_v_t_41 sp4_v_b_0 -(6 0) routing sp4_v_t_44 sp4_v_b_0 -(6 1) routing sp4_h_l_37 sp4_h_r_0 -(6 1) routing sp4_h_l_41 sp4_h_r_0 -(6 1) routing sp4_v_b_0 sp4_h_r_0 -(6 1) routing sp4_v_b_6 sp4_h_r_0 -(6 10) routing sp4_h_l_36 sp4_v_t_43 -(6 10) routing sp4_h_r_0 sp4_v_t_43 -(6 10) routing sp4_v_b_10 sp4_v_t_43 -(6 10) routing sp4_v_b_3 sp4_v_t_43 -(6 11) routing sp4_h_r_10 sp4_h_l_43 -(6 11) routing sp4_h_r_6 sp4_h_l_43 -(6 11) routing sp4_v_t_37 sp4_h_l_43 -(6 11) routing sp4_v_t_43 sp4_h_l_43 -(6 12) routing sp4_h_l_38 sp4_v_b_9 -(6 12) routing sp4_h_r_4 sp4_v_b_9 -(6 12) routing sp4_v_t_36 sp4_v_b_9 -(6 12) routing sp4_v_t_43 sp4_v_b_9 -(6 13) routing sp4_h_l_36 sp4_h_r_9 -(6 13) routing sp4_h_l_44 sp4_h_r_9 -(6 13) routing sp4_v_b_3 sp4_h_r_9 -(6 13) routing sp4_v_b_9 sp4_h_r_9 -(6 14) routing sp4_h_l_41 sp4_v_t_44 -(6 14) routing sp4_h_r_3 sp4_v_t_44 -(6 14) routing sp4_v_b_1 sp4_v_t_44 -(6 14) routing sp4_v_b_6 sp4_v_t_44 -(6 15) routing sp4_h_r_1 sp4_h_l_44 -(6 15) routing sp4_h_r_9 sp4_h_l_44 -(6 15) routing sp4_v_t_38 sp4_h_l_44 -(6 15) routing sp4_v_t_44 sp4_h_l_44 -(6 2) routing sp4_h_l_42 sp4_v_t_37 -(6 2) routing sp4_h_r_6 sp4_v_t_37 -(6 2) routing sp4_v_b_4 sp4_v_t_37 -(6 2) routing sp4_v_b_9 sp4_v_t_37 -(6 3) routing sp4_h_r_0 sp4_h_l_37 -(6 3) routing sp4_h_r_4 sp4_h_l_37 -(6 3) routing sp4_v_t_37 sp4_h_l_37 -(6 3) routing sp4_v_t_43 sp4_h_l_37 -(6 4) routing sp4_h_l_44 sp4_v_b_3 -(6 4) routing sp4_h_r_10 sp4_v_b_3 -(6 4) routing sp4_v_t_37 sp4_v_b_3 -(6 4) routing sp4_v_t_42 sp4_v_b_3 -(6 5) routing sp4_h_l_38 sp4_h_r_3 -(6 5) routing sp4_h_l_42 sp4_h_r_3 -(6 5) routing sp4_v_b_3 sp4_h_r_3 -(6 5) routing sp4_v_b_9 sp4_h_r_3 -(6 6) routing sp4_h_l_47 sp4_v_t_38 -(6 6) routing sp4_h_r_9 sp4_v_t_38 -(6 6) routing sp4_v_b_0 sp4_v_t_38 -(6 6) routing sp4_v_b_7 sp4_v_t_38 -(6 7) routing sp4_h_r_3 sp4_h_l_38 -(6 7) routing sp4_h_r_7 sp4_h_l_38 -(6 7) routing sp4_v_t_38 sp4_h_l_38 -(6 7) routing sp4_v_t_44 sp4_h_l_38 -(6 8) routing sp4_h_l_37 sp4_v_b_6 -(6 8) routing sp4_h_r_1 sp4_v_b_6 -(6 8) routing sp4_v_t_38 sp4_v_b_6 -(6 8) routing sp4_v_t_47 sp4_v_b_6 -(6 9) routing sp4_h_l_43 sp4_h_r_6 -(6 9) routing sp4_h_l_47 sp4_h_r_6 -(6 9) routing sp4_v_b_0 sp4_h_r_6 -(6 9) routing sp4_v_b_6 sp4_h_r_6 -(7 0) Ram config bit: MEMT_bram_cbit_1 -(7 1) Ram config bit: MEMT_bram_cbit_0 -(7 10) Column buffer control bit: MEMT_colbuf_cntl_3 -(7 11) Column buffer control bit: MEMT_colbuf_cntl_2 -(7 12) Column buffer control bit: MEMT_colbuf_cntl_5 -(7 13) Column buffer control bit: MEMT_colbuf_cntl_4 -(7 14) Column buffer control bit: MEMT_colbuf_cntl_7 -(7 15) Column buffer control bit: MEMT_colbuf_cntl_6 -(7 2) Ram config bit: MEMT_bram_cbit_3 -(7 3) Ram config bit: MEMT_bram_cbit_2 -(7 4) Cascade buffer Enable bit: MEMT_LC00_inmux00_bram_cbit_5 -(7 4) Cascade buffer Enable bit: MEMT_LC01_inmux00_bram_cbit_5 -(7 4) Cascade buffer Enable bit: MEMT_LC02_inmux00_bram_cbit_5 -(7 4) Cascade buffer Enable bit: MEMT_LC04_inmux00_bram_cbit_5 -(7 4) Cascade buffer Enable bit: MEMT_LC05_inmux00_bram_cbit_5 -(7 4) Cascade buffer Enable bit: MEMT_LC06_inmux00_bram_cbit_5 -(7 4) Cascade buffer Enable bit: MEMT_LC06_inmux02_bram_cbit_5 -(7 4) Cascade buffer Enable bit: MEMT_LC07_inmux00_bram_cbit_5 -(7 4) Cascade buffer Enable bit: MEMT_LC07_inmux02_bram_cbit_5 -(7 5) Cascade bit: MEMT_LC00_inmux00_bram_cbit_4 -(7 5) Cascade bit: MEMT_LC01_inmux00_bram_cbit_4 -(7 5) Cascade bit: MEMT_LC02_inmux00_bram_cbit_4 -(7 5) Cascade bit: MEMT_LC04_inmux00_bram_cbit_4 -(7 5) Cascade bit: MEMT_LC05_inmux00_bram_cbit_4 -(7 5) Cascade bit: MEMT_LC06_inmux00_bram_cbit_4 -(7 5) Cascade bit: MEMT_LC06_inmux02_bram_cbit_4 -(7 5) Cascade bit: MEMT_LC07_inmux00_bram_cbit_4 -(7 5) Cascade bit: MEMT_LC07_inmux02_bram_cbit_4 -(7 6) Cascade buffer Enable bit: MEMT_LC00_inmux00_bram_cbit_7 -(7 6) Cascade buffer Enable bit: MEMT_LC01_inmux00_bram_cbit_7 -(7 6) Cascade buffer Enable bit: MEMT_LC02_inmux00_bram_cbit_7 -(7 6) Cascade buffer Enable bit: MEMT_LC03_inmux00_bram_cbit_7 -(7 6) Cascade buffer Enable bit: MEMT_LC04_inmux00_bram_cbit_7 -(7 6) Cascade buffer Enable bit: MEMT_LC05_inmux00_bram_cbit_7 -(7 6) Cascade buffer Enable bit: MEMT_LC06_inmux00_bram_cbit_7 -(7 6) Cascade buffer Enable bit: MEMT_LC06_inmux02_bram_cbit_7 -(7 6) Cascade buffer Enable bit: MEMT_LC07_inmux00_bram_cbit_7 -(7 6) Cascade buffer Enable bit: MEMT_LC07_inmux02_bram_cbit_7 -(7 7) Cascade bit: MEMT_LC00_inmux00_bram_cbit_6 -(7 7) Cascade bit: MEMT_LC01_inmux00_bram_cbit_6 -(7 7) Cascade bit: MEMT_LC02_inmux00_bram_cbit_6 -(7 7) Cascade bit: MEMT_LC03_inmux00_bram_cbit_6 -(7 7) Cascade bit: MEMT_LC04_inmux00_bram_cbit_6 -(7 7) Cascade bit: MEMT_LC05_inmux00_bram_cbit_6 -(7 7) Cascade bit: MEMT_LC06_inmux00_bram_cbit_6 -(7 7) Cascade bit: MEMT_LC06_inmux02_bram_cbit_6 -(7 7) Cascade bit: MEMT_LC07_inmux00_bram_cbit_6 -(7 7) Cascade bit: MEMT_LC07_inmux02_bram_cbit_6 -(7 8) Column buffer control bit: MEMT_colbuf_cntl_1 -(7 9) Column buffer control bit: MEMT_colbuf_cntl_0 -(8 0) routing sp4_h_l_36 sp4_h_r_1 -(8 0) routing sp4_h_l_40 sp4_h_r_1 -(8 0) routing sp4_v_b_1 sp4_h_r_1 -(8 0) routing sp4_v_b_7 sp4_h_r_1 -(8 1) routing sp4_h_l_36 sp4_v_b_1 -(8 1) routing sp4_h_l_42 sp4_v_b_1 -(8 1) routing sp4_h_r_1 sp4_v_b_1 -(8 1) routing sp4_v_t_47 sp4_v_b_1 -(8 10) routing sp4_h_r_11 sp4_h_l_42 -(8 10) routing sp4_h_r_7 sp4_h_l_42 -(8 10) routing sp4_v_t_36 sp4_h_l_42 -(8 10) routing sp4_v_t_42 sp4_h_l_42 -(8 11) routing sp4_h_l_42 sp4_v_t_42 -(8 11) routing sp4_h_r_1 sp4_v_t_42 -(8 11) routing sp4_h_r_7 sp4_v_t_42 -(8 11) routing sp4_v_b_4 sp4_v_t_42 -(8 12) routing sp4_h_l_39 sp4_h_r_10 -(8 12) routing sp4_h_l_47 sp4_h_r_10 -(8 12) routing sp4_v_b_10 sp4_h_r_10 -(8 12) routing sp4_v_b_4 sp4_h_r_10 -(8 13) routing sp4_h_l_41 sp4_v_b_10 -(8 13) routing sp4_h_l_47 sp4_v_b_10 -(8 13) routing sp4_h_r_10 sp4_v_b_10 -(8 13) routing sp4_v_t_42 sp4_v_b_10 -(8 14) routing sp4_h_r_10 sp4_h_l_47 -(8 14) routing sp4_h_r_2 sp4_h_l_47 -(8 14) routing sp4_v_t_41 sp4_h_l_47 -(8 14) routing sp4_v_t_47 sp4_h_l_47 -(8 15) routing sp4_h_l_47 sp4_v_t_47 -(8 15) routing sp4_h_r_10 sp4_v_t_47 -(8 15) routing sp4_h_r_4 sp4_v_t_47 -(8 15) routing sp4_v_b_7 sp4_v_t_47 -(8 2) routing sp4_h_r_1 sp4_h_l_36 -(8 2) routing sp4_h_r_5 sp4_h_l_36 -(8 2) routing sp4_v_t_36 sp4_h_l_36 -(8 2) routing sp4_v_t_42 sp4_h_l_36 -(8 3) routing sp4_h_l_36 sp4_v_t_36 -(8 3) routing sp4_h_r_1 sp4_v_t_36 -(8 3) routing sp4_h_r_7 sp4_v_t_36 -(8 3) routing sp4_v_b_10 sp4_v_t_36 -(8 4) routing sp4_h_l_41 sp4_h_r_4 -(8 4) routing sp4_h_l_45 sp4_h_r_4 -(8 4) routing sp4_v_b_10 sp4_h_r_4 -(8 4) routing sp4_v_b_4 sp4_h_r_4 -(8 5) routing sp4_h_l_41 sp4_v_b_4 -(8 5) routing sp4_h_l_47 sp4_v_b_4 -(8 5) routing sp4_h_r_4 sp4_v_b_4 -(8 5) routing sp4_v_t_36 sp4_v_b_4 -(8 6) routing sp4_h_r_4 sp4_h_l_41 -(8 6) routing sp4_h_r_8 sp4_h_l_41 -(8 6) routing sp4_v_t_41 sp4_h_l_41 -(8 6) routing sp4_v_t_47 sp4_h_l_41 -(8 7) routing sp4_h_l_41 sp4_v_t_41 -(8 7) routing sp4_h_r_10 sp4_v_t_41 -(8 7) routing sp4_h_r_4 sp4_v_t_41 -(8 7) routing sp4_v_b_1 sp4_v_t_41 -(8 8) routing sp4_h_l_42 sp4_h_r_7 -(8 8) routing sp4_h_l_46 sp4_h_r_7 -(8 8) routing sp4_v_b_1 sp4_h_r_7 -(8 8) routing sp4_v_b_7 sp4_h_r_7 -(8 9) routing sp4_h_l_36 sp4_v_b_7 -(8 9) routing sp4_h_l_42 sp4_v_b_7 -(8 9) routing sp4_h_r_7 sp4_v_b_7 -(8 9) routing sp4_v_t_41 sp4_v_b_7 -(9 0) routing sp4_h_l_47 sp4_h_r_1 -(9 0) routing sp4_v_b_1 sp4_h_r_1 -(9 0) routing sp4_v_b_7 sp4_h_r_1 -(9 0) routing sp4_v_t_36 sp4_h_r_1 -(9 1) routing sp4_h_l_36 sp4_v_b_1 -(9 1) routing sp4_h_l_42 sp4_v_b_1 -(9 1) routing sp4_v_t_36 sp4_v_b_1 -(9 1) routing sp4_v_t_40 sp4_v_b_1 -(9 10) routing sp4_h_r_4 sp4_h_l_42 -(9 10) routing sp4_v_b_7 sp4_h_l_42 -(9 10) routing sp4_v_t_36 sp4_h_l_42 -(9 10) routing sp4_v_t_42 sp4_h_l_42 -(9 11) routing sp4_h_r_1 sp4_v_t_42 -(9 11) routing sp4_h_r_7 sp4_v_t_42 -(9 11) routing sp4_v_b_11 sp4_v_t_42 -(9 11) routing sp4_v_b_7 sp4_v_t_42 -(9 12) routing sp4_h_l_42 sp4_h_r_10 -(9 12) routing sp4_v_b_10 sp4_h_r_10 -(9 12) routing sp4_v_b_4 sp4_h_r_10 -(9 12) routing sp4_v_t_47 sp4_h_r_10 -(9 13) routing sp4_h_l_41 sp4_v_b_10 -(9 13) routing sp4_h_l_47 sp4_v_b_10 -(9 13) routing sp4_v_t_39 sp4_v_b_10 -(9 13) routing sp4_v_t_47 sp4_v_b_10 -(9 14) routing sp4_h_r_7 sp4_h_l_47 -(9 14) routing sp4_v_b_10 sp4_h_l_47 -(9 14) routing sp4_v_t_41 sp4_h_l_47 -(9 14) routing sp4_v_t_47 sp4_h_l_47 -(9 15) routing sp4_h_r_10 sp4_v_t_47 -(9 15) routing sp4_h_r_4 sp4_v_t_47 -(9 15) routing sp4_v_b_10 sp4_v_t_47 -(9 15) routing sp4_v_b_2 sp4_v_t_47 -(9 2) routing sp4_h_r_10 sp4_h_l_36 -(9 2) routing sp4_v_b_1 sp4_h_l_36 -(9 2) routing sp4_v_t_36 sp4_h_l_36 -(9 2) routing sp4_v_t_42 sp4_h_l_36 -(9 3) routing sp4_h_r_1 sp4_v_t_36 -(9 3) routing sp4_h_r_7 sp4_v_t_36 -(9 3) routing sp4_v_b_1 sp4_v_t_36 -(9 3) routing sp4_v_b_5 sp4_v_t_36 -(9 4) routing sp4_h_l_36 sp4_h_r_4 -(9 4) routing sp4_v_b_10 sp4_h_r_4 -(9 4) routing sp4_v_b_4 sp4_h_r_4 -(9 4) routing sp4_v_t_41 sp4_h_r_4 -(9 5) routing sp4_h_l_41 sp4_v_b_4 -(9 5) routing sp4_h_l_47 sp4_v_b_4 -(9 5) routing sp4_v_t_41 sp4_v_b_4 -(9 5) routing sp4_v_t_45 sp4_v_b_4 -(9 6) routing sp4_h_r_1 sp4_h_l_41 -(9 6) routing sp4_v_b_4 sp4_h_l_41 -(9 6) routing sp4_v_t_41 sp4_h_l_41 -(9 6) routing sp4_v_t_47 sp4_h_l_41 -(9 7) routing sp4_h_r_10 sp4_v_t_41 -(9 7) routing sp4_h_r_4 sp4_v_t_41 -(9 7) routing sp4_v_b_4 sp4_v_t_41 -(9 7) routing sp4_v_b_8 sp4_v_t_41 -(9 8) routing sp4_h_l_41 sp4_h_r_7 -(9 8) routing sp4_v_b_1 sp4_h_r_7 -(9 8) routing sp4_v_b_7 sp4_h_r_7 -(9 8) routing sp4_v_t_42 sp4_h_r_7 -(9 9) routing sp4_h_l_36 sp4_v_b_7 -(9 9) routing sp4_h_l_42 sp4_v_b_7 -(9 9) routing sp4_v_t_42 sp4_v_b_7 -(9 9) routing sp4_v_t_46 sp4_v_b_7 diff --git a/icefuzz/database.py b/icefuzz/database.py index a0caca6..ee94c03 100644 --- a/icefuzz/database.py +++ b/icefuzz/database.py @@ -148,7 +148,7 @@ with open("database_ramt.txt", "w") as f: for entry in read_database("bitdata_ramt.txt", "ramt"): print("\t".join(entry), file=f) -for device_class in ["5k", "8k"]: +for device_class in ["8k"]: with open("database_ramb_%s.txt" % (device_class, ), "w") as f: for entry in read_database("bitdata_ramb_%s.txt" % (device_class, ), "ramb_" + device_class): print("\t".join(entry), file=f) @@ -163,4 +163,4 @@ for dsp_idx in range(4): print("\t".join(entry), file=f) with open("database_ipcon_5k.txt", "w") as f: for entry in read_database("bitdata_ipcon_5k.txt", "ipcon"): - print("\t".join(entry), file=f) \ No newline at end of file + print("\t".join(entry), file=f) diff --git a/icefuzz/export.py b/icefuzz/export.py index 0aae954..4a2444a 100644 --- a/icefuzz/export.py +++ b/icefuzz/export.py @@ -5,7 +5,7 @@ device_class = os.getenv("ICEDEVICE") with open("../icebox/iceboxdb.py", "w") as f: files = [ "database_io", "database_logic", "database_ramb", "database_ramt", "database_ipcon_5k"] - for device_class in ["5k", "8k"]: + for device_class in ["8k"]: files.append("database_ramb_" + device_class) files.append("database_ramt_" + device_class) for i in range(4): -- cgit v1.2.3 From 7e587c9b6b62057f7e9258ac93c7fec77e994fa1 Mon Sep 17 00:00:00 2001 From: David Shah Date: Sat, 13 Jan 2018 17:31:09 +0000 Subject: Add 5k UWG30 ieren data to db --- icebox/icebox.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/icebox/icebox.py b/icebox/icebox.py index e19e489..198b5f2 100644 --- a/icebox/icebox.py +++ b/icebox/icebox.py @@ -2347,7 +2347,11 @@ ieren_db = { ( 7, 0, 1, 7, 0, 0), ( 5, 0, 0, 5, 0, 1), ( 6, 0, 0, 6, 0, 1), - ( 7, 0, 0, 7, 0, 1) + ( 7, 0, 0, 7, 0, 1), + (12, 31, 0, 12, 31, 1), + (12, 0, 0, 12, 0, 1), + (13, 0, 0, 13, 0, 1), + (12, 0, 1, 12, 0, 0) ] } -- cgit v1.2.3 From 4b16c3735c0c183837994a4b4b07296f0bbba57c Mon Sep 17 00:00:00 2001 From: David Shah Date: Sat, 13 Jan 2018 18:51:27 +0000 Subject: =?UTF-8?q?I=C2=B3C=20IO=20reverse=20engineered=20and=20documented?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- docs/ultraplus.html | 13 +++++++++++++ icefuzz/tests/sb_io_i3c.pcf | 8 ++++++++ icefuzz/tests/sb_io_i3c.v | 35 +++++++++++++++++++++++++++++++++++ 3 files changed, 56 insertions(+) create mode 100644 icefuzz/tests/sb_io_i3c.pcf create mode 100644 icefuzz/tests/sb_io_i3c.v diff --git a/docs/ultraplus.html b/docs/ultraplus.html index b5dda62..11e249d 100644 --- a/docs/ultraplus.html +++ b/docs/ultraplus.html @@ -290,6 +290,19 @@ can be used as an open-drain IO using the standard IO cell.

+

I3C capable IO

+

The UltraPlus devices have two IO pins designed for the new MIPI I3C standard (pins 23 and 25 in the SG48 package), +compared to normal IO pins they have two switchable pullups each. One of these pullups, the weak pullup, is fixed at 100k and the +other can be set to 3.3k, 6.8k or 10k using the mechanism above. The pullup control signals do not +connect directly to the IO tile, but instead connect through an IPConnect tile.

+ +

The connections are listed below:

+ + + + +
SignalPin 23
(19, 31, 0)		Pin 25
(19, 31, 1)
PU_ENB(25, 27, lutff_6/in_0)(25, 27, lutff_7/in_0)
WEAK_PU_ENB(25, 27, lutff_4/in_0)(25, 27, lutff_5/in_0)
+

Hard IP

The UltraPlus devices contain three types of Hard IP: I2C (SB_I2C), SPI (SB_SPI), and LED PWM generation diff --git a/icefuzz/tests/sb_io_i3c.pcf b/icefuzz/tests/sb_io_i3c.pcf new file mode 100644 index 0000000..cb3cd30 --- /dev/null +++ b/icefuzz/tests/sb_io_i3c.pcf @@ -0,0 +1,8 @@ +set_io pin_23 23 +set_io pin_25 25 + +set_io pin_23_puen 2 +set_io pin_23_wkpuen 3 + +set_io pin_25_puen 4 +set_io pin_25_wkpuen 6 diff --git a/icefuzz/tests/sb_io_i3c.v b/icefuzz/tests/sb_io_i3c.v new file mode 100644 index 0000000..5237283 --- /dev/null +++ b/icefuzz/tests/sb_io_i3c.v @@ -0,0 +1,35 @@ + +module top ( + inout pin_23, + inout pin_25, + input pin_23_puen, + input pin_23_wkpuen, + input pin_25_puen, + input pin_25_wkpuen); + + (* PULLUP_RESISTOR = "3P3K" *) + SB_IO_I3C #( + .PIN_TYPE(6'b000001), + .PULLUP(1'b1), + .WEAK_PULLUP(1'b1), + + .NEG_TRIGGER(1'b0) + ) IO_PIN_0 ( + .PACKAGE_PIN(pin_23), + .PU_ENB(pin_23_puen), + .WEAK_PU_ENB(pin_23_wkpuen) + ) ; + + (* PULLUP_RESISTOR = "3P3K" *) + SB_IO_I3C #( + .PIN_TYPE(6'b000001), + .PULLUP(1'b1), + .WEAK_PULLUP(1'b1), + + .NEG_TRIGGER(1'b0) + ) IO_PIN_1 ( + .PACKAGE_PIN(pin_25), + .PU_ENB(pin_25_puen), + .WEAK_PU_ENB(pin_25_wkpuen) + ); +endmodule -- cgit v1.2.3 From 99857b1505fa6c651ad9cd4177d8fc68d3e3851c Mon Sep 17 00:00:00 2001 From: David Shah Date: Sun, 14 Jan 2018 10:45:35 +0000 Subject: Add example for 5k UWG30 package --- examples/up5k_rgb/Makefile.uwg30 | 36 ++++++++++++++++++++++++++++++++++++ examples/up5k_rgb/rgb_uwg30.pcf | 3 +++ 2 files changed, 39 insertions(+) create mode 100644 examples/up5k_rgb/Makefile.uwg30 create mode 100644 examples/up5k_rgb/rgb_uwg30.pcf diff --git a/examples/up5k_rgb/Makefile.uwg30 b/examples/up5k_rgb/Makefile.uwg30 new file mode 100644 index 0000000..b3755ff --- /dev/null +++ b/examples/up5k_rgb/Makefile.uwg30 @@ -0,0 +1,36 @@ +PROJ = rgb +PIN_DEF = rgb_uwg30.pcf +DEVICE = up5k + +ARACHNE = arachne-pnr +ARACHNE_ARGS = +ICEPACK = icepack +ICETIME = icetime +ICEPROG = iceprog + +all: $(PROJ).bin + +%.blif: %.v + yosys -p 'synth_ice40 -top top -blif $@' $< + +%.asc: $(PIN_DEF) %.blif + $(ARACHNE) $(ARACHNE_ARGS) -d $(subst up,,$(subst hx,,$(subst lp,,$(DEVICE)))) -o $@ -p $^ -P uwg30 + +%.bin: %.asc + $(ICEPACK) $< $@ + +%.rpt: %.asc + $(ICETIME) -d $(DEVICE) -mtr $@ $< + +prog: $(PROJ).bin + $(ICEPROG) -S $< + +sudo-prog: $(PROJ).bin + @echo 'Executing prog as root!!!' + sudo $(ICEPROG) -S $< + +clean: + rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin + +.SECONDARY: +.PHONY: all prog clean diff --git a/examples/up5k_rgb/rgb_uwg30.pcf b/examples/up5k_rgb/rgb_uwg30.pcf new file mode 100644 index 0000000..475cfd5 --- /dev/null +++ b/examples/up5k_rgb/rgb_uwg30.pcf @@ -0,0 +1,3 @@ +set_io RGB0 A5 +set_io RGB1 B5 +set_io RGB2 C5 -- cgit v1.2.3