From d983e72e8ec328eecf2ef9ab521198746f0c1c2a Mon Sep 17 00:00:00 2001 From: Claire Wolf Date: Mon, 20 Apr 2020 13:18:10 +0200 Subject: Update index.html Signed-off-by: Claire Wolf --- docs/index.html | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/docs/index.html b/docs/index.html index 3ca1721..fc50ea8 100644 --- a/docs/index.html +++ b/docs/index.html @@ -30,7 +30,7 @@

What is Project IceStorm?

-Project IceStorm aims at reverse engineering and documenting the bitstream +Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files. The IceStorm flow (Yosys, It has a very minimalistic architecture with a very regular structure. There are not many -different kinds of tiles or special function units. This makes it both ideal for -reverse engineering and as a reference platform for general purpose FPGA tool development. +different kinds of tiles or special function units. This makes it both ideal for creating +bitstream documentations and as a reference platform for general purpose FPGA tool development.

@@ -64,8 +64,8 @@ Breakout Board featuring an HX8K chip.)

What is the Status of the Project?

-We are pretty confident that we have the 1K and 8K devices completely reverse -engineered. For example, it seems we can create correct functional Verilog +We are pretty confident that we have the 1K and 8K devices completely +documented. For example, it seems we can create correct functional Verilog models for all bitstreams generated by Lattice iCEcube2 for the iCE40 HX1K-TQ144 and the iCE40 HX8K-CT256 using our icebox_vlog tool.

@@ -557,12 +557,14 @@ Links to related projects. Contact me at clifford@clifford.at if you have an int
  • IceStorm Learner’s Documentation -

    Other FPGA reverse engineering projects

    +

    Other FPGA bitstream documentation projects

    -- cgit v1.2.3