From 3c490702694f66b5ceba31dc50538bd14f8019f4 Mon Sep 17 00:00:00 2001 From: David Shah Date: Sat, 25 Nov 2017 10:20:54 +0000 Subject: Add note about glitch filter --- docs/ultraplus.html | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/docs/ultraplus.html b/docs/ultraplus.html index e01d038..694b82d 100644 --- a/docs/ultraplus.html +++ b/docs/ultraplus.html @@ -285,7 +285,8 @@ can be used as an open-drain IO using the standard IO cell.

Hard IP

The UltraPlus devices contain three types of Hard IP: I2C (SB_I2C), SPI (SB_SPI), and LED PWM generation -(SB_LEDDA_IP). The connections and configurations for each of these blocks are documented below.

+(SB_LEDDA_IP). The connections and configurations for each of these blocks are documented below. Names in italics are parameters rather than actual bits, +where multiple bits are used to enable an IP they are labeled as _ENABLE_0, _ENABLE_1, etc.

@@ -410,6 +411,15 @@ can be used as an open-drain IO using the standard IO cell.

SignalI2C
(0, 31, 0)		I2C
(25, 31, 0)

-

The I2C "glitch filter" is a seperate module from the I2C interface IP and needs to be reverse engineered seperately. +

The I2C "glitch filter" (referred to as SB_FILTER_50NS) is a seperate module from the I2C interface IP, with connections as shown below: + + + + + + + + +
SignalSB_FILTER_50NS
(25, 31, 2)		SB_FILTER_50NS
(25, 31, 3)
FILTERIN(25, 27, lutff_1/in_0)(25, 27, lutff_0/in_0)
FILTEROUT(25, 27, slf_op_2)(25, 27, slf_op_1)
ENABLE_0(25, 30, CBIT_2)(25, 30, CBIT_5)
ENABLE_1(25, 30, CBIT_3)(25, 30, CBIT_6)
ENABLE_2(25, 30, CBIT_4)(25, 30, CBIT_7)
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