From 39337b7bf9f66fdeec471c5718f1bb1e7548654e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 12 Nov 2015 00:47:26 +0100 Subject: Webpage updates --- docs/index.html | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/docs/index.html b/docs/index.html index 54dc489..6e344fb 100644 --- a/docs/index.html +++ b/docs/index.html @@ -14,10 +14,11 @@

What is Project IceStorm?

-Project IceStorm aims at documenting the bitstream format of Lattice iCE40 -FPGAs and providing simple tools for analyzing and creating bitstream files. -At the moment the focus of the project is on the HX1K-TQ144 and HX8K-CT256 -devices, but most of the information is device-independent. +Project IceStorm aims at reverse engineering and documenting the bitstream +format of Lattice iCE40 FPGAs and providing simple tools for analyzing and +creating bitstream files. At the moment the focus of the project is on the +HX1K-TQ144 and HX8K-CT256 devices, but most of the information is +device-independent.

Why the Lattice iCE40?

@@ -37,8 +38,15 @@ for all kinds of projects.

What is the Status of the Project?

-We have enough bits mapped that we can create a functional Verilog model for almost all -bitstreams generated by Lattice iCEcube2 for the iCE40 HX1K-TQ144 and the iCE40 HX8K-CT256. +We have enough bits mapped that we can create a functional Verilog model for +almost all bitstreams generated by Lattice iCEcube2 for the iCE40 HX1K-TQ144 +and the iCE40 HX8K-CT256, and can create bitstreams for this parts using our +own tool-chain. +

+ +

+The next milestones for the project are timing analysis and support for more +parts from the iCE40 family.

What is the Status of the Fully Open Source iCE40 Flow?

@@ -355,6 +363,7 @@ Links to related projects. Contact me at clifford@clifford.at if you have an int
  • J1a SwapForth built with IceStorm
  • ICEd = an Arduino Style Board, with ICE FPGA
  • A Spanish FPGA Tutorial using IceStorm +
  • CAT Board
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