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* Remove seperate 5k RAM DB and share with 8k insteadDavid Shah2018-01-162-2849/+9
| | | | | This should ensure that the 5k RAM routing entries are now complete, fixing #115
* Add pinout for 5k UWG30 packageDavid Shah2018-01-161-0/+23
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* HFOSC trimming infoDavid Shah2018-01-161-1/+12
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* New UltraPlus corner tracing algorithmDavid Shah2018-01-161-87/+86
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* Misc routing tweaksDavid Shah2018-01-161-3/+7
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* Figure out missing SPI config bits, and add to chipdbDavid Shah2018-01-161-0/+8
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* Chipdb fix for hard IPDavid Shah2017-11-261-4/+4
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* Add UltraPlus IP to chipdbDavid Shah2017-11-242-3/+212
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* Begin I2C/SPI IP reverse engineeringDavid Shah2017-11-231-0/+8
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* Fix whitespace and a couple of typosDavid Shah2017-11-201-3/+3
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* Add all cf_bits and pullup strength notesDavid Shah2017-11-181-0/+12
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* Add missing 5k BRAM bitsDavid Shah2017-11-171-7/+338
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* Make 5k db as a default targetDavid Shah2017-11-171-1/+2
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* Remove non-existing routing resources (5k)David Shah2017-11-171-2/+3
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* Add support for UltraPlus SPRAMDavid Shah2017-11-172-1/+254
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* Add UltraPlus LED driver support and demoDavid Shah2017-11-172-11/+39
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* UltraPlus Internal Oscillator supportDavid Shah2017-11-172-1/+34
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* UltraPlus DSPs workingDavid Shah2017-11-172-1/+8
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* Add new tile types and MAC16s to chipdbDavid Shah2017-11-172-4/+138
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* Tidy up some of the icebox changesDavid Shah2017-11-171-44/+53
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* Fix 5k corner routing, and reverse engineer SPRAMDavid Shah2017-11-171-20/+93
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* Start UltraPlus DSP documentationDavid Shah2017-11-172-2/+3
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* Trace DSP routingDavid Shah2017-11-174-349/+6531
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* Fix 5k gbin configurationDavid Shah2017-11-061-2/+2
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* Add more 5k RAM bits to dbDavid Shah2017-11-051-4/+86
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* Fix 5k padin_glb_netwk bitsDavid Shah2017-11-051-8/+8
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* Fix global network 1 padin bitDavid Shah2017-11-011-2/+2
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* Work on 5k global buffer padsDavid Shah2017-11-011-8/+10
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* Add missing up5k global buffer padsDavid Shah2017-10-311-1/+4
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* Working up5k PLL supportDavid Shah2017-10-311-63/+61
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* Fix loading 5k asc filesDavid Shah2017-10-311-1/+1
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* Add new 5k IO config bits to databaseDavid Shah2017-10-291-3/+21
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* Share glb_netwk data between 5k and 8k partsDavid Shah2017-10-292-78/+101
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* Fix global network data for up5kDavid Shah2017-10-251-9/+9
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* Fix colbuf db for up5kDavid Shah2017-10-251-5/+7
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* Add ColBufCtrl bits to database for 5k partsDavid Shah2017-10-251-100/+72
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* Add CarryInSet bit to DBDavid Shah2017-10-241-0/+3
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* Fix IeRen database for up5kDavid Shah2017-10-231-97/+40
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* Swap IEREN for pin 26 to get example working, other inputs still need fixingDavid Shah2017-10-212-2/+73
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* Fix RAM tile location in icebox.pyDavid Shah2017-10-211-1/+1
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* Fix icebox to generate a working chipdbDavid Shah2017-10-211-4/+4
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* Bring chip data in icebox in line with icepack - and icecubeDavid Shah2017-10-211-50/+50
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* Modify icebox.py so it generates a 5k chipdbDavid Shah2017-10-202-30/+390
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* Add (attempt at) IeRen mapping for 5kDavid Shah2017-10-201-0/+98
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* Add LP384 support to icebox_htmlDarrell Harmon2017-10-121-3/+31
| | | | Unsure about what IO tiles should be enabled, so all are enabled.
* Merge pull request #97 from rlutz/hlc-fixesClifford Wolf2017-09-146-1/+2403
|\ | | | | Fixes to high-level configuration converters
| * icebox: Put .hlc converters under ISC licenseRoland Lutz2017-09-026-1/+2403
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| | * icebox: Fix parsing of IO block special wiresRoland Lutz2017-08-271-5/+5
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| | * icebox: Fix parsing of PLL directiveRoland Lutz2017-08-271-1/+4
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| | * icebox: Give useful error messages for .hlc parsing errorsRoland Lutz2017-08-271-12/+18
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