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| * Add UltraPlus I³C IO to chipdbDavid Shah2018-02-091-1/+10
| * Add RGB driver outputs to chipdbDavid Shah2018-02-091-0/+4
* | Fix compiler warning (comparison between signed and unsigned int) in icetimeClifford Wolf2018-02-091-1/+1
* | Merge pull request #122 from daveshah1/iceprog-up2Clifford Wolf2018-02-091-3/+3
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| * Add out-of-the-box FT232H support (for Upduino 2, etc)David Shah2018-02-091-3/+3
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* Remove up5k_mac16 "example" and add README to up5k_rgb and icebreakerClifford Wolf2018-02-066-123/+4
* Add icebreaker example projectClifford Wolf2018-02-064-0/+153
* Merge pull request #119 from daveshah1/up5k_improveClifford Wolf2018-01-3012-3503/+18362
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| * Tidy upDavid Shah2018-01-303-1154/+0
| * Misc UltraPlus fixesDavid Shah2018-01-301-29/+35
| * Updated 5k timing data, icetime regression fixDavid Shah2018-01-296-12479/+13778
| * DSP related fixesDavid Shah2018-01-282-269/+2
| * Working DSP timing analysisDavid Shah2018-01-262-3/+33
| * Work on timing analysis of DSPsDavid Shah2018-01-261-8/+196
| * Parse extra cells in icetimeDavid Shah2018-01-231-1/+50
| * More DSP timing fuzzing, start adding new tiles to icetimeDavid Shah2018-01-223-2/+3710
| * Seperate different DSP configs in timing dataDavid Shah2018-01-2211-2532/+13532
* | Merge pull request #118 from daveshah1/up5k_fix_timingClifford Wolf2018-01-202-143/+88
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| * Fix 5k timing dataDavid Shah2018-01-202-143/+88
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* Merge pull request #116 from daveshah1/up5k_misc_fixesClifford Wolf2018-01-1614-10109/+270
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| * Add example for 5k UWG30 packageDavid Shah2018-01-162-0/+39
| * I³C IO reverse engineered and documentedDavid Shah2018-01-163-0/+56
| * Add 5k UWG30 ieren data to dbDavid Shah2018-01-161-1/+5
| * Remove seperate 5k RAM DB and share with 8k insteadDavid Shah2018-01-167-10016/+13
| * Add pinout for 5k UWG30 packageDavid Shah2018-01-161-0/+23
| * Add SPI enable bits to docsDavid Shah2018-01-161-0/+4
| * HFOSC trimming infoDavid Shah2018-01-162-1/+20
| * New UltraPlus corner tracing algorithmDavid Shah2018-01-161-87/+86
| * Misc routing tweaksDavid Shah2018-01-161-3/+7
| * Figure out missing SPI config bits, and add to chipdbDavid Shah2018-01-163-2/+18
* | Add "iceprog -e"Clifford Wolf2018-01-021-20/+42
* | Merge pull request #113 from cr1901/nosleepClifford Wolf2017-12-311-20/+65
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| * | Enable writing nosleep config bit into output bitstream.William D. Jones2017-12-311-11/+30
| * | Add nosleep field to FpgaConfig- read_bits recognizes the option.William D. Jones2017-12-311-9/+35
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* | Merge pull request #112 from mithro/patch-2Clifford Wolf2017-12-091-0/+13
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| * | Creating COPYING file.Tim Ansell2017-12-081-0/+13
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* | Merge pull request #110 from daveshah1/up5k_ipClifford Wolf2017-11-2820-14/+5004
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| * Whitespace fixesDavid Shah2017-11-283-9/+36
| * Add uncommitted changes and tidy up some filesDavid Shah2017-11-283-2/+253
| * Chipdb fix for hard IPDavid Shah2017-11-261-4/+4
| * Add note about glitch filterDavid Shah2017-11-251-2/+12
| * Add UltraPlus IP to chipdbDavid Shah2017-11-242-3/+212
| * Initial 5k support in icetime (no support for new cells yet)David Shah2017-11-243-7/+28
| * Preparations for 5k icetimeDavid Shah2017-11-243-2/+3627
| * Documented I2C/SPI/LEDDA_IPDavid Shah2017-11-242-2/+196
| * All 5k IP tracedDavid Shah2017-11-244-3/+129
| * Work on UltraPlus IP tracingDavid Shah2017-11-243-0/+366
| * Begin I2C/SPI IP reverse engineeringDavid Shah2017-11-235-0/+161
* | Merge pull request #109 from daveshah1/up5kClifford Wolf2017-11-2144-121/+24909
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| * Tidy up 5k examplesDavid Shah2017-11-206-35/+18
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