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-rw-r--r--icefuzz/.gitignore1
-rw-r--r--icefuzz/Makefile22
-rw-r--r--icefuzz/cached_io.txt2
-rw-r--r--icefuzz/cached_ramb_8k.txt3
-rw-r--r--icefuzz/cached_ramt.txt3
-rw-r--r--icefuzz/database.py9
-rw-r--r--icefuzz/icecube.sh1
-rw-r--r--icefuzz/timings.py437
-rw-r--r--icefuzz/timings_1k.txt528
-rw-r--r--icefuzz/timings_8k.txt528
-rw-r--r--icefuzz/tmedges.ys20
-rw-r--r--icefuzz/tmedges_1k.txt612
-rw-r--r--icefuzz/tmedges_8k.txt618
13 files changed, 2776 insertions, 8 deletions
diff --git a/icefuzz/.gitignore b/icefuzz/.gitignore
index 4406a27..e32cfc1 100644
--- a/icefuzz/.gitignore
+++ b/icefuzz/.gitignore
@@ -4,5 +4,6 @@
*.tmp/
*.txt
*.vsb
+*.sdf
/work_*/
__pycache__
diff --git a/icefuzz/Makefile b/icefuzz/Makefile
index 030eb35..0233eb4 100644
--- a/icefuzz/Makefile
+++ b/icefuzz/Makefile
@@ -36,6 +36,24 @@ endif
diff -U0 cached_ramb_8k.txt bitdata_ramb_8k.txt || cp -v bitdata_ramb_8k.txt cached_ramb_8k.txt
diff -U0 cached_ramt_8k.txt bitdata_ramt_8k.txt || cp -v bitdata_ramt_8k.txt cached_ramt_8k.txt
+timings:
+ifeq ($(EIGTHK),_8k)
+ cp tmedges_8k.txt tmedges.tmp
+ for f in work_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done
+ sort -u tmedges.tmp > tmedges_8k.txt && rm -f tmedges.tmp
+ python3 timings.py -t timings_8k.txt work_*/*.sdf > timings_8k.new
+ mv timings_8k.new timings_8k.txt
+else
+ cp tmedges_1k.txt tmedges.tmp
+ for f in work_*/*.vsb; do echo $$f; yosys -q -f verilog -s tmedges.ys $$f; done
+ sort -u tmedges.tmp > tmedges_1k.txt && rm -f tmedges.tmp
+ python3 timings.py -t timings_1k.txt work_*/*.sdf > timings_1k.new
+ mv timings_1k.new timings_1k.txt
+endif
+
+timings_html:
+ python3 timings.py -h tmedges_1k.txt -t timings_1k.txt -l "HX1K with default temp/volt settings" > timings_1k.html
+
data_cached.txt: cached_io.txt cached_logic.txt cached_ramb$(EIGTHK).txt cached_ramt$(EIGTHK).txt
gawk '{ print "io", $$0; }' cached_io.txt > data_cached.new
gawk '{ print "logic", $$0; }' cached_logic.txt >> data_cached.new
@@ -64,11 +82,11 @@ define data_template
data_$(1).txt: make_$(1).py ../icepack/icepack
ifeq ($(EIGTHK),_8k)
ICE8KPINS=1 python3 make_$(1).py
- ICEDEV=hx8k-ct256 $(MAKE) -C work_$(1)
+ +ICEDEV=hx8k-ct256 $(MAKE) -C work_$(1)
python3 extract.py -8 work_$(1)/*.glb > $$@
else
python3 make_$(1).py
- $(MAKE) -C work_$(1)
+ +$(MAKE) -C work_$(1)
python3 extract.py work_$(1)/*.glb > $$@
endif
endef
diff --git a/icefuzz/cached_io.txt b/icefuzz/cached_io.txt
index 257e8d0..6033a28 100644
--- a/icefuzz/cached_io.txt
+++ b/icefuzz/cached_io.txt
@@ -12,6 +12,7 @@
(0 13) Enable bit of Mux _out_links/OutMux0_3 => wire_io_cluster/io_1/D_IN_1 span4_vert_6
(0 14) Enable bit of Mux _out_links/OutMux7_3 => wire_io_cluster/io_1/D_IN_1 span4_horz_r_7
(0 14) Enable bit of Mux _out_links/OutMux7_3 => wire_io_cluster/io_1/D_IN_1 span4_vert_b_7
+(0 15) Enable bit of Mux _out_links/OutMux5_3 => wire_io_cluster/io_1/D_IN_1 span4_horz_46
(0 15) Enable bit of Mux _out_links/OutMux5_3 => wire_io_cluster/io_1/D_IN_1 span4_vert_46
(0 2) Enable bit of Mux _out_links/OutMux7_0 => wire_io_cluster/io_0/D_IN_0 span4_horz_r_4
(0 2) Enable bit of Mux _out_links/OutMux7_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_b_4
@@ -52,6 +53,7 @@
(1 4) Enable bit of Mux _out_links/OutMux3_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_26
(1 4) Enable bit of Mux _out_links/OutMux3_1 => wire_io_cluster/io_0/D_IN_1 span4_vert_26
(1 5) Enable bit of Mux _out_links/OutMux1_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_10
+(1 5) Enable bit of Mux _out_links/OutMux1_1 => wire_io_cluster/io_0/D_IN_1 span4_vert_10
(1 6) Enable bit of Mux _out_links/OutMux8_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_r_9
(1 6) Enable bit of Mux _out_links/OutMux8_1 => wire_io_cluster/io_0/D_IN_1 span4_vert_b_9
(1 7) Enable bit of Mux _out_links/OutMux6_1 => wire_io_cluster/io_0/D_IN_1 span4_horz_r_1
diff --git a/icefuzz/cached_ramb_8k.txt b/icefuzz/cached_ramb_8k.txt
index 843ce53..b19db9a 100644
--- a/icefuzz/cached_ramb_8k.txt
+++ b/icefuzz/cached_ramb_8k.txt
@@ -57,6 +57,7 @@
(0 8) routing glb_netwk_7 <X> glb2local_1
(0 9) routing glb_netwk_1 <X> glb2local_1
(0 9) routing glb_netwk_3 <X> glb2local_1
+(0 9) routing glb_netwk_5 <X> glb2local_1
(0 9) routing glb_netwk_7 <X> glb2local_1
(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_0 glb2local_2
(1 10) Enable bit of Mux _local_links/global_mux_2 => glb_netwk_1 glb2local_2
@@ -128,9 +129,11 @@
(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_2 glb2local_1
(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_3 glb2local_1
(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_4 glb2local_1
+(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_5 glb2local_1
(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_6 glb2local_1
(1 8) Enable bit of Mux _local_links/global_mux_1 => glb_netwk_7 glb2local_1
(1 9) routing glb_netwk_4 <X> glb2local_1
+(1 9) routing glb_netwk_5 <X> glb2local_1
(1 9) routing glb_netwk_6 <X> glb2local_1
(1 9) routing glb_netwk_7 <X> glb2local_1
(10 0) routing sp4_h_l_40 <X> sp4_h_r_1
diff --git a/icefuzz/cached_ramt.txt b/icefuzz/cached_ramt.txt
index c51dafa..84c2126 100644
--- a/icefuzz/cached_ramt.txt
+++ b/icefuzz/cached_ramt.txt
@@ -35,6 +35,7 @@
(0 3) routing glb_netwk_7 <X> wire_bram/ram/RCLK
(0 3) routing lc_trk_g1_1 <X> wire_bram/ram/RCLK
(0 3) routing lc_trk_g3_1 <X> wire_bram/ram/RCLK
+(0 4) routing glb_netwk_5 <X> wire_bram/ram/RCLKE
(0 4) routing glb_netwk_7 <X> wire_bram/ram/RCLKE
(0 4) routing lc_trk_g2_2 <X> wire_bram/ram/RCLKE
(0 4) routing lc_trk_g3_3 <X> wire_bram/ram/RCLKE
@@ -82,6 +83,7 @@
(1 13) routing glb_netwk_5 <X> glb2local_3
(1 13) routing glb_netwk_6 <X> glb2local_3
(1 13) routing glb_netwk_7 <X> glb2local_3
+(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_0 wire_bram/ram/RE
(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_2 wire_bram/ram/RE
(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_4 wire_bram/ram/RE
(1 14) Enable bit of Mux _global_links/set_rst_mux => glb_netwk_6 wire_bram/ram/RE
@@ -100,6 +102,7 @@
(1 3) Enable bit of Mux _span_links/cross_mux_horz_5 => sp12_h_r_10 sp4_h_r_17
(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_1 wire_bram/ram/RCLKE
(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_3 wire_bram/ram/RCLKE
+(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_5 wire_bram/ram/RCLKE
(1 4) Enable bit of Mux _global_links/ce_mux => glb_netwk_7 wire_bram/ram/RCLKE
(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g0_2 wire_bram/ram/RCLKE
(1 4) Enable bit of Mux _global_links/ce_mux => lc_trk_g1_3 wire_bram/ram/RCLKE
diff --git a/icefuzz/database.py b/icefuzz/database.py
index 7720ce2..9f0ebc9 100644
--- a/icefuzz/database.py
+++ b/icefuzz/database.py
@@ -2,12 +2,9 @@
import re, sys, os
-def cmp_bits(a, b):
+def sort_bits_key(a):
if a[0] == "!": a = a[1:]
- if b[0] == "!": b = b[1:]
- a = re.sub(r"\d+", lambda m: "%02d" % int(m.group(0)), a)
- b = re.sub(r"\d+", lambda m: "%02d" % int(m.group(0)), b)
- return cmp(a, b)
+ return re.sub(r"\d+", lambda m: "%02d" % int(m.group(0)), a)
def read_database(filename, tile_type):
raw_db = list()
@@ -107,7 +104,7 @@ def read_database(filename, tile_type):
database = list()
for func in sorted(func_to_bits):
bits = func_to_bits[func]
- entry = (",".join(sorted(bits, cmp_bits)),) + func
+ entry = (",".join(sorted(bits, key=sort_bits_key)),) + func
database.append(entry)
return database
diff --git a/icefuzz/icecube.sh b/icefuzz/icecube.sh
index 54421a4..f3dabc6 100644
--- a/icefuzz/icecube.sh
+++ b/icefuzz/icecube.sh
@@ -189,5 +189,6 @@ cp "$1.tmp"/outputs/bitmap/top_bitmap.bin "$1.bin"
cp "$1.tmp"/outputs/bitmap/top_bitmap_glb.txt "$1.glb"
cp "$1.tmp"/outputs/placer/top_sbt.pcf "$1.psb"
cp "$1.tmp"/outputs/netlist/top_sbt.v "$1.vsb"
+cp "$1.tmp"/outputs/netlist/top_sbt.sdf "$1.sdf"
$scriptdir/../icepack/iceunpack "$1.bin" "$1.txt"
diff --git a/icefuzz/timings.py b/icefuzz/timings.py
new file mode 100644
index 0000000..75215d5
--- /dev/null
+++ b/icefuzz/timings.py
@@ -0,0 +1,437 @@
+#!/usr/bin/env python3
+
+import getopt, sys, re
+
+ignore_cells = set([
+ "ADTTRIBUF", "CascadeBuf", "DL", "GIOBUG", "LUT_MUX", "MUX4",
+ "PLL40_2_FEEDBACK_PATH_DELAY", "PLL40_2_FEEDBACK_PATH_EXTERNAL",
+ "PLL40_2_FEEDBACK_PATH_PHASE_AND_DELAY", "PLL40_2_FEEDBACK_PATH_SIMPLE",
+ "PLL40_2F_FEEDBACK_PATH_DELAY", "PLL40_2F_FEEDBACK_PATH_EXTERNAL",
+ "PLL40_2F_FEEDBACK_PATH_PHASE_AND_DELAY", "PLL40_2F_FEEDBACK_PATH_SIMPLE",
+ "PLL40_FEEDBACK_PATH_DELAY", "PLL40_FEEDBACK_PATH_EXTERNAL",
+ "PLL40_FEEDBACK_PATH_PHASE_AND_DELAY", "PLL40_FEEDBACK_PATH_SIMPLE",
+ "PRE_IO_PIN_TYPE", "sync_clk_enable", "TRIBUF"
+])
+
+database = dict()
+sdf_inputs = list()
+txt_inputs = list()
+output_mode = "txt"
+label = "unknown"
+edgefile = None
+
+def usage():
+ print("""
+Usage: python3 timings.py [options] [sdf_file..]
+
+ -t filename
+ read TXT file
+
+ -l label
+ label for HTML file title
+
+ -h edgefile
+ output HTML, use specified edge file
+
+ -s
+ output SDF (not TXT) format
+""")
+ sys.exit(0)
+
+
+try:
+ opts, args = getopt.getopt(sys.argv[1:], "t:l:h:s")
+except:
+ usage()
+
+for o, a in opts:
+ if o == "-t":
+ txt_inputs.append(a)
+ elif o == "-l":
+ label = a
+ elif o == "-h":
+ output_mode = "html"
+ edgefile = a
+ elif o == "-s":
+ output_mode = "sdf"
+ else:
+ usage()
+
+sdf_inputs += args
+
+
+convert = lambda text: int(text) if text.isdigit() else text.lower()
+alphanum_key = lambda key: [ convert(c) for c in re.split('([0-9]+)', key) ]
+alphanum_key_list = lambda l: [len(l)] + [ alphanum_key(s) for s in l ]
+
+
+def skip_whitespace(text, cursor):
+ while cursor < len(text) and text[cursor] in [" ", "\t", "\r", "\n"]:
+ cursor += 1
+ return cursor
+
+
+def parse_sdf(text, cursor):
+ cursor = skip_whitespace(text, cursor)
+
+ if cursor < len(text) and text[cursor] == "(":
+ expr = []
+ cursor += 1
+ while cursor < len(text) and text[cursor] != ")":
+ child, cursor = parse_sdf(text, cursor)
+ expr.append(child)
+ cursor = skip_whitespace(text, cursor)
+ return expr, cursor+1
+
+ if cursor < len(text) and text[cursor] == '"':
+ expr = '"'
+ cursor += 1
+ while cursor < len(text) and text[cursor] != '"':
+ expr += text[cursor]
+ cursor += 1
+ return expr + '"', cursor+1
+
+ expr = ""
+ while cursor < len(text) and text[cursor] not in [" ", "\t", "\r", "\n", "(", ")"]:
+ expr += text[cursor]
+ cursor += 1
+ return expr, cursor
+
+
+def sdf_to_string(expr):
+ if type(expr) is list:
+ tokens = []
+ tokens.append("(")
+ first_child = True
+ for child in expr:
+ if not first_child:
+ tokens.append(" ")
+ tokens.append(sdf_to_string(child))
+ first_child = False
+ tokens.append(")")
+ return "".join(tokens)
+ else:
+ return expr
+
+
+def dump_sdf(expr, indent=""):
+ if type(expr) is list:
+ if len(expr) > 0 and expr[0] in ["IOPATH", "SETUP", "HOLD", "CELLTYPE", "INSTANCE", "SDFVERSION",
+ "DESIGN", "DATE", "VENDOR", "DIVIDER", "TIMESCALE", "RECOVERY", "REMOVAL"]:
+ print(indent + sdf_to_string(expr))
+ else:
+ print("%s(%s" % (indent, expr[0] if len(expr) > 0 else ""))
+ for child in expr[1:]:
+ dump_sdf(child, indent + " ")
+ print("%s)" % indent)
+ else:
+ print("%s%s" % (indent, expr))
+
+
+def generalize_instances(expr):
+ if type(expr) is list:
+ if len(expr) == 2 and expr[0] == "INSTANCE":
+ expr[1] = "*"
+ for child in expr:
+ generalize_instances(child)
+
+
+def list_to_tuple(expr):
+ if type(expr) is list:
+ tup = []
+ for child in expr:
+ tup.append(list_to_tuple(child))
+ return tuple(tup)
+ return expr
+
+
+def uniquify_cells(expr):
+ cache = set()
+ filtered_expr = []
+
+ for child in expr:
+ t = list_to_tuple(child)
+ if t not in cache:
+ filtered_expr.append(child)
+ cache.add(t)
+
+ return filtered_expr
+
+
+def rewrite_celltype(celltype):
+ if celltype.startswith("PRE_IO_PIN_TYPE_"):
+ celltype = "PRE_IO_PIN_TYPE"
+
+ if celltype.startswith("Span4Mux"):
+ if celltype == "Span4Mux":
+ celltype = "Span4Mux_v4"
+ elif celltype == "Span4Mux_v":
+ celltype = "Span4Mux_v4"
+ elif celltype == "Span4Mux_h":
+ celltype = "Span4Mux_h4"
+ else:
+ match = re.match("Span4Mux_s(.*)_(h|v)", celltype)
+ if match:
+ celltype = "Span4Mux_%c%d" % (match.group(2), int(match.group(1)))
+
+ if celltype.startswith("Span12Mux"):
+ if celltype == "Span12Mux":
+ celltype = "Span12Mux_v12"
+ elif celltype == "Span12Mux_v":
+ celltype = "Span12Mux_v12"
+ elif celltype == "Span12Mux_h":
+ celltype = "Span12Mux_h12"
+ else:
+ match = re.match("Span12Mux_s(.*)_(h|v)", celltype)
+ if match:
+ celltype = "Span12Mux_%c%d" % (match.group(2), int(match.group(1)))
+
+ return celltype
+
+
+def add_entry(celltype, entry):
+ entry = sdf_to_string(entry)
+ entry = entry.replace("(posedge ", "posedge:")
+ entry = entry.replace("(negedge ", "negedge:")
+ entry = entry.replace("(", "")
+ entry = entry.replace(")", "")
+ entry = entry.split()
+ if celltype.count("FEEDBACK") == 0 and entry[0] == "IOPATH" and entry[2].startswith("PLLOUT"):
+ entry[3] = "*:*:*"
+ entry[4] = "*:*:*"
+ database[celltype].add(tuple(entry))
+
+
+###########################################
+# Parse SDF input files
+
+for filename in sdf_inputs:
+ print("### reading SDF file %s" % filename, file=sys.stderr)
+
+ intext = []
+ with open(filename, "r") as f:
+ for line in f:
+ line = re.sub("//.*", "", line)
+ intext.append(line)
+
+ sdfdata, _ = parse_sdf("".join(intext), 0)
+ generalize_instances(sdfdata)
+ sdfdata = uniquify_cells(sdfdata)
+
+ for cell in sdfdata:
+ if cell[0] != "CELL":
+ continue
+
+ celltype = None
+
+ for stmt in cell:
+ if stmt[0] == "CELLTYPE":
+ celltype = rewrite_celltype(stmt[1][1:-1])
+ database.setdefault(celltype, set())
+
+ if stmt[0] == "DELAY":
+ assert stmt[1][0] == "ABSOLUTE"
+ for entry in stmt[1][1:]:
+ assert entry[0] == "IOPATH"
+ add_entry(celltype, entry)
+
+ if stmt[0] == "TIMINGCHECK":
+ for entry in stmt[1:]:
+ add_entry(celltype, entry)
+
+
+###########################################
+# Parse TXT input files
+
+for filename in txt_inputs:
+ print("### reading TXT file %s" % filename, file=sys.stderr)
+ with open(filename, "r") as f:
+ celltype = None
+ for line in f:
+ line = line.split()
+ if len(line) > 1:
+ if line[0] == "CELL":
+ celltype = rewrite_celltype(line[1])
+ database.setdefault(celltype, set())
+ else:
+ add_entry(celltype, line)
+
+
+###########################################
+# Filter database
+
+for celltype in ignore_cells:
+ del database[celltype]
+
+
+###########################################
+# Create SDF output
+
+if output_mode == "sdf":
+ print("(DELAYFILE")
+ print(" (SDFVERSION \"3.0\")")
+ print(" (TIMESCALE 1ps)")
+
+ def format_entry(entry):
+ text = []
+ for i in range(len(entry)):
+ if i > 2:
+ text.append("(%s)" % entry[i])
+ elif entry[i].startswith("posedge:"):
+ text.append("(posedge %s)" % entry[i].replace("posedge:", ""))
+ elif entry[i].startswith("negedge:"):
+ text.append("(negedge %s)" % entry[i].replace("negedge:", ""))
+ else:
+ text.append(entry[i])
+ return " ".join(text)
+
+ for celltype in sorted(database, key=alphanum_key):
+ print(" (CELL")
+ print(" (CELLTYPE \"%s\")" % celltype)
+ print(" (INSTANCE *)")
+
+ delay_abs_entries = list()
+ timingcheck_entries = list()
+ for entry in sorted(database[celltype], key=alphanum_key_list):
+ if entry[0] == "IOPATH":
+ delay_abs_entries.append(entry)
+ else:
+ timingcheck_entries.append(entry)
+
+ if len(delay_abs_entries) != 0:
+ print(" (DELAY")
+ print(" (ABSOLUTE")
+ for entry in delay_abs_entries:
+ print(" (%s)" % format_entry(entry))
+ print(" )")
+ print(" )")
+
+ if len(timingcheck_entries) != 0:
+ print(" (TIMINGCHECK")
+ for entry in timingcheck_entries:
+ print(" (%s)" % format_entry(entry))
+ print(" )")
+
+ print(" )")
+
+ print(")")
+
+
+###########################################
+# Create TXT output
+
+if output_mode == "txt":
+ for celltype in sorted(database, key=alphanum_key):
+ print("CELL %s" % celltype)
+ entries_lens = list()
+ for entry in database[celltype]:
+ for i in range(len(entry)):
+ if i < len(entries_lens):
+ entries_lens[i] = max(entries_lens[i], len(entry[i]))
+ else:
+ entries_lens.append(len(entry[i]))
+ for entry in sorted(database[celltype], key=alphanum_key_list):
+ for i in range(len(entry)):
+ print("%s%-*s" % (" " if i != 0 else "", entries_lens[i] if i != len(entry)-1 else 0, entry[i]), end="")
+ print()
+ print()
+
+
+###########################################
+# Create HTML output
+
+if output_mode == "html":
+ print("<h1>IceStorm Timing Model: %s</h1>" % label)
+
+ edge_celltypes = set()
+ source_by_sink_desc = dict()
+ sink_by_source_desc = dict()
+
+ with open(edgefile, "r") as f:
+ for line in f:
+ source, sink = line.split()
+ source_cell, source_port = source.split(".")
+ sink_cell, sink_port = sink.split(".")
+
+ source_cell = rewrite_celltype(source_cell)
+ sink_cell = rewrite_celltype(sink_cell)
+
+ assert source_cell not in ignore_cells
+ assert sink_cell not in ignore_cells
+
+ if source_cell in ["GND", "VCC"]:
+ continue
+
+ source_by_sink_desc.setdefault(sink_cell, set())
+ sink_by_source_desc.setdefault(source_cell, set())
+
+ source_by_sink_desc[sink_cell].add((sink_port, source_cell, source_port))
+ sink_by_source_desc[source_cell].add((source_port, sink_cell, sink_port))
+
+ edge_celltypes.add(source_cell)
+ edge_celltypes.add(sink_cell)
+
+ print("<div style=\"-webkit-column-count: 3; -moz-column-count: 3; column-count: 3;\"><ul style=\"margin:0\">")
+ for celltype in sorted(database, key=alphanum_key):
+ if celltype not in edge_celltypes:
+ print("### ignoring unused cell type %s" % celltype, file=sys.stderr)
+ else:
+ print("<li><a href=\"#%s\">%s</a></li>" % (celltype, celltype))
+ print("</ul></div>")
+
+ for celltype in sorted(database, key=alphanum_key):
+ if celltype not in edge_celltypes:
+ continue
+
+ print("<p><hr></p>")
+ print("<h2><a name=\"%s\">%s</a></h2>" % (celltype, celltype))
+
+ if celltype in source_by_sink_desc:
+ print("<h3>Sources driving this cell type:</h3>")
+ print("<table width=\"600\" border>")
+ print("<tr><th>Input Port</th><th>Source Cell</th><th>Source Port</th></tr>")
+ for entry in sorted(source_by_sink_desc[celltype], key=alphanum_key_list):
+ print("<tr><td>%s</td><td><a href=\"#%s\">%s</a></td><td>%s</td></tr>" % (entry[0], entry[1], entry[1], entry[2]))
+ print("</table>")
+
+ if celltype in sink_by_source_desc:
+ print("<h3>Sinks driven by this cell type:</h3>")
+ print("<table width=\"600\" border>")
+ print("<tr><th>Output Port</th><th>Sink Cell</th><th>Sink Port</th></tr>")
+ for entry in sorted(sink_by_source_desc[celltype], key=alphanum_key_list):
+ print("<tr><td>%s</td><td><a href=\"#%s\">%s</a></td><td>%s</td></tr>" % (entry[0], entry[1], entry[1], entry[2]))
+ print("</table>")
+
+ delay_abs_entries = list()
+ timingcheck_entries = list()
+ for entry in sorted(database[celltype], key=alphanum_key_list):
+ if entry[0] == "IOPATH":
+ delay_abs_entries.append(entry)
+ else:
+ timingcheck_entries.append(entry)
+
+ if len(delay_abs_entries) > 0:
+ print("<h3>Propagation Delays:</h3>")
+ print("<table width=\"800\" border>")
+ print("<tr><th rowspan=\"2\">Input Port</th><th rowspan=\"2\">Output Port</th>")
+ print("<th colspan=\"3\">Low-High Transition</th><th colspan=\"3\">High-Low Transition</th></tr>")
+ print("<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>")
+ for entry in delay_abs_entries:
+ print("<tr><td>%s</td><td>%s</td>" % (entry[1].replace(":", " "), entry[2].replace(":", " ")), end="")
+ print("<td>%s</td><td>%s</td><td>%s</td>" % tuple(entry[3].split(":")), end="")
+ print("<td>%s</td><td>%s</td><td>%s</td>" % tuple(entry[4].split(":")), end="")
+ print("</tr>")
+ print("</table>")
+
+ if len(timingcheck_entries) > 0:
+ print("<h3>Timing Checks:</h3>")
+ print("<table width=\"800\" border>")
+ print("<tr><th rowspan=\"2\">Check Type</th><th rowspan=\"2\">Input Port</th>")
+ print("<th rowspan=\"2\">Output Port</th><th colspan=\"3\">Timing</th></tr>")
+ print("<tr><th>Min</th><th>Typ</th><th>Max</th></tr>")
+ for entry in timingcheck_entries:
+ print("<tr><td>%s</td><td>%s</td><td>%s</td>" % (entry[0], entry[1].replace(":", " "), entry[2].replace(":", " ")), end="")
+ print("<td>%s</td><td>%s</td><td>%s</td>" % tuple(entry[3].split(":")), end="")
+ print("</tr>")
+ print("</table>")
+
diff --git a/icefuzz/timings_1k.txt b/icefuzz/timings_1k.txt
new file mode 100644
index 0000000..11b3b39
--- /dev/null
+++ b/icefuzz/timings_1k.txt
@@ -0,0 +1,528 @@
+CELL CascadeMux
+IOPATH I O 0:0:0 0:0:0
+
+CELL CEMux
+IOPATH I O 562.692:731:888.975 516.892:671.5:816.617
+
+CELL ClkMux
+IOPATH I O 287.889:374:454.825 215.917:280.5:341.118
+
+CELL gio2CtrlBuf
+IOPATH I O 0:0:0 0:0:0
+
+CELL Glb2LocalMux
+IOPATH I O 418.748:544:661.563 333.689:433.5:527.183
+
+CELL GlobalMux
+IOPATH I O 143.944:187:227.412 71.9722:93.5:113.706
+
+CELL ICE_CARRY_IN_MUX
+IOPATH carryinitin carryinitout 183.202:238:289.434 163.573:212.5:258.423
+
+CELL ICE_GB
+IOPATH USERSIGNALTOGLOBALBUFFER GLOBALBUFFEROUTPUT 575.778:748:909.649 523.434:680:826.954
+
+CELL InMux
+IOPATH I O 242.088:314.5:382.466 202.831:263.5:320.445
+
+CELL INV
+IOPATH I O 0:0:0 0:0:0
+
+CELL IO_PAD
+IOPATH DIN PACKAGEPIN 2291.5:2291.5:2291.5 2353.2:2353.2:2353.2
+IOPATH OE PACKAGEPIN 1902:1902:1902 1990:1990:1990
+IOPATH OE PACKAGEPIN 1973:1973:1973 1942:1942:1942
+IOPATH OE PACKAGEPIN 2291.5:2291.5:2291.5 2353.2:2353.2:2353.2
+IOPATH PACKAGEPIN DOUT 590:590:590 540:540:540
+
+CELL IoInMux
+IOPATH I O 242.088:314.5:382.466 202.831:263.5:320.445
+
+CELL IoSpan4Mux
+IOPATH I O 268.26:348.5:423.814 300.975:391:475.498
+
+CELL LocalMux
+IOPATH I O 307.518:399.5:485.835 287.889:374:454.825
+
+CELL LogicCell40
+HOLD negedge:ce posedge:clk 0:0:0
+HOLD negedge:in0 posedge:clk 0:0:0
+HOLD negedge:in1 posedge:clk 0:0:0
+HOLD negedge:in2 posedge:clk 0:0:0
+HOLD negedge:in3 posedge:clk 0:0:0
+HOLD negedge:sr posedge:clk -184.184:-239.275:-290.984
+HOLD posedge:ce posedge:clk 0:0:0
+HOLD posedge:in0 posedge:clk 0:0:0
+HOLD posedge:in1 posedge:clk 0:0:0
+HOLD posedge:in2 posedge:clk 0:0:0
+HOLD posedge:in3 posedge:clk 0:0:0
+HOLD posedge:sr posedge:clk -167.106:-217.09:-264.005
+RECOVERY negedge:sr posedge:clk 148.983:193.545:235.372
+RECOVERY posedge:sr posedge:clk 0:0:0
+REMOVAL negedge:sr posedge:clk 0:0:0
+REMOVAL posedge:sr posedge:clk 0:0:0
+SETUP negedge:ce posedge:clk 0:0:0
+SETUP negedge:in0 posedge:clk 372.947:484.5:589.205
+SETUP negedge:in1 posedge:clk 353.318:459:558.194
+SETUP negedge:in2 posedge:clk 300.975:391:475.498
+SETUP negedge:in3 posedge:clk 202.831:263.5:320.445
+SETUP negedge:sr posedge:clk 130.859:170:206.738
+SETUP posedge:ce posedge:clk 0:0:0
+SETUP posedge:in0 posedge:clk 438.376:569.5:692.574
+SETUP posedge:in1 posedge:clk 372.947:484.5:589.205
+SETUP posedge:in2 posedge:clk 346.775:450.5:547.857
+SETUP posedge:in3 posedge:clk 255.174:331.5:403.14
+SETUP posedge:sr posedge:clk 189.745:246.5:299.771
+IOPATH carryin carryout 117.773:153:186.065 98.144:127.5:155.054
+IOPATH in0 lcout 418.748:544:661.563 359.861:467.5:568.531
+IOPATH in0 ltout 340.232:442:537.52 359.861:467.5:568.531
+IOPATH in1 carryout 242.088:314.5:382.466 229.003:297.5:361.792
+IOPATH in1 lcout 372.947:484.5:589.205 353.318:459:558.194
+IOPATH in1 ltout 300.975:391:475.498 353.318:459:558.194
+IOPATH in2 carryout 215.917:280.5:341.118 124.316:161.5:196.402
+IOPATH in2 lcout 353.318:459:558.194 327.147:425:516.846
+IOPATH in2 ltout 287.889:374:454.825 320.604:416.5:506.509
+IOPATH in3 lcout 294.432:382.5:465.161 268.26:348.5:423.814
+IOPATH in3 ltout 248.631:323:392.803 255.174:331.5:403.14
+IOPATH posedge:clk lcout 503.806:654.5:795.943 503.806:654.5:795.943
+IOPATH sr lcout 0:0:0 558.989:726.189:883.125
+IOPATH sr lcout 558.963:726.155:883.083 0:0:0
+
+CELL Odrv4
+IOPATH I O 327.147:425:516.846 346.775:450.5:547.857
+
+CELL Odrv12
+IOPATH I O 458.005:595:723.585 503.806:654.5:795.943
+
+CELL PLL40
+IOPATH PLLIN PLLOUTCORE *:*:* *:*:*
+IOPATH PLLIN PLLOUTGLOBAL *:*:* *:*:*
+
+CELL PLL40_2
+IOPATH PLLIN PLLOUTCOREA *:*:* *:*:*
+IOPATH PLLIN PLLOUTCOREB *:*:* *:*:*
+IOPATH PLLIN PLLOUTGLOBALA *:*:* *:*:*
+IOPATH PLLIN PLLOUTGLOBALB *:*:* *:*:*
+
+CELL PLL40_2F
+IOPATH PLLIN PLLOUTCOREA *:*:* *:*:*
+IOPATH PLLIN PLLOUTCOREB *:*:* *:*:*
+IOPATH PLLIN PLLOUTGLOBALA *:*:* *:*:*
+IOPATH PLLIN PLLOUTGLOBALB *:*:* *:*:*
+
+CELL PRE_IO
+HOLD negedge:CLOCKENABLE posedge:INPUTCLK 0:0:0
+HOLD negedge:CLOCKENABLE posedge:OUTPUTCLK 0:0:0
+HOLD negedge:DOUT0 posedge:OUTPUTCLK 0:0:0
+HOLD negedge:DOUT1 negedge:OUTPUTCLK 0:0:0
+HOLD negedge:OUTPUTENABLE posedge:OUTPUTCLK 0:0:0
+HOLD negedge:PADIN negedge:INPUTCLK 0:0:0
+HOLD negedge:PADIN posedge:INPUTCLK 0:0:0
+HOLD posedge:CLOCKENABLE posedge:INPUTCLK 0:0:0
+HOLD posedge:CLOCKENABLE posedge:OUTPUTCLK 0:0:0
+HOLD posedge:DOUT0 posedge:OUTPUTCLK 0:0:0
+HOLD posedge:DOUT1 negedge:OUTPUTCLK 0:0:0
+HOLD posedge:OUTPUTENABLE posedge:OUTPUTCLK 0:0:0
+HOLD posedge:PADIN negedge:INPUTCLK 0:0:0
+HOLD posedge:PADIN posedge:INPUTCLK 0:0:0
+SETUP negedge:CLOCKENABLE posedge:INPUTCLK 65.4293:85:103.369
+SETUP negedge:CLOCKENABLE posedge:OUTPUTCLK 65.4293:85:103.369
+SETUP negedge:DOUT0 posedge:OUTPUTCLK 65.4293:85:103.369
+SETUP negedge:DOUT1 negedge:OUTPUTCLK 65.4293:85:103.369
+SETUP negedge:OUTPUTENABLE posedge:OUTPUTCLK 65.4293:85:103.369
+SETUP negedge:PADIN negedge:INPUTCLK 1527.97:1985:2413.98
+SETUP negedge:PADIN posedge:INPUTCLK 1527.97:1985:2413.98
+SETUP posedge:CLOCKENABLE posedge:INPUTCLK 71.9722:93.5:113.706
+SETUP posedge:CLOCKENABLE posedge:OUTPUTCLK 71.9722:93.5:113.706
+SETUP posedge:DOUT0 posedge:OUTPUTCLK 71.9722:93.5:113.706
+SETUP posedge:DOUT1 negedge:OUTPUTCLK 71.9722:93.5:113.706
+SETUP posedge:OUTPUTENABLE posedge:OUTPUTCLK 71.9722:93.5:113.706
+SETUP posedge:PADIN negedge:INPUTCLK 1534.51:1993.5:2424.32
+SETUP posedge:PADIN posedge:INPUTCLK 1534.51:1993.5:2424.32
+IOPATH DOUT0 PADOUT 1871.28:2431:2956.36 2087.19:2711.5:3297.48
+IOPATH LATCHINPUTVALUE DIN0 320.604:416.5:506.509 346.775:450.5:547.857
+IOPATH negedge:INPUTCLK DIN1 130.859:170:206.738 130.859:170:206.738
+IOPATH negedge:OUTPUTCLK PADOUT 104.687:136:165.391 130.859:170:206.738
+IOPATH OUTPUTENABLE PADOEN 163.573:212.5:258.423 196.288:255:310.108
+IOPATH PADIN DIN0 575.778:748:909.649 431.833:561:682.237
+IOPATH posedge:INPUTCLK DIN0 130.859:170:206.738 130.859:170:206.738
+IOPATH posedge:OUTPUTCLK PADOEN 104.687:136:165.391 130.859:170:206.738
+IOPATH posedge:OUTPUTCLK PADOUT 104.687:136:165.391 130.859:170:206.738
+
+CELL PRE_IO_GBUF
+IOPATH PADSIGNALTOGLOBALBUFFER GLOBALBUFFEROUTPUT 1313.95:1706.97:2075.86 1170.01:1519.97:1848.45
+
+CELL SB_PLL40_2F_CORE
+IOPATH REFERENCECLK PLLOUTCOREA *:*:* *:*:*
+IOPATH REFERENCECLK PLLOUTCOREB *:*:* *:*:*
+IOPATH REFERENCECLK PLLOUTGLOBALA *:*:* *:*:*
+IOPATH REFERENCECLK PLLOUTGLOBALB *:*:* *:*:*
+
+CELL SB_PLL40_CORE
+IOPATH REFERENCECLK PLLOUTCORE *:*:* *:*:*
+IOPATH REFERENCECLK PLLOUTGLOBAL *:*:* *:*:*
+
+CELL SB_RAM40_4K
+HOLD negedge:MASK[0] posedge:WCLK 0:0:0
+HOLD negedge:MASK[1] posedge:WCLK 0:0:0
+HOLD negedge:MASK[2] posedge:WCLK 0:0:0
+HOLD negedge:MASK[3] posedge:WCLK 0:0:0
+HOLD negedge:MASK[4] posedge:WCLK 0:0:0
+HOLD negedge:MASK[5] posedge:WCLK 0:0:0
+HOLD negedge:MASK[6] posedge:WCLK 0:0:0
+HOLD negedge:MASK[7] posedge:WCLK 0:0:0
+HOLD negedge:MASK[8] posedge:WCLK 0:0:0
+HOLD negedge:MASK[9] posedge:WCLK 0:0:0
+HOLD negedge:MASK[10] posedge:WCLK 0:0:0
+HOLD negedge:MASK[11] posedge:WCLK 0:0:0
+HOLD negedge:MASK[12] posedge:WCLK 0:0:0
+HOLD negedge:MASK[13] posedge:WCLK 0:0:0
+HOLD negedge:MASK[14] posedge:WCLK 0:0:0
+HOLD negedge:MASK[15] posedge:WCLK 0:0:0
+HOLD negedge:RADDR[0] posedge:RCLK 52.3434:68:82.6954
+HOLD negedge:RADDR[1] posedge:RCLK 52.3434:68:82.6954
+HOLD negedge:RADDR[2] posedge:RCLK 52.3434:68:82.6954
+HOLD negedge:RADDR[3] posedge:RCLK 52.3434:68:82.6954
+HOLD negedge:RADDR[4] posedge:RCLK 52.3434:68:82.6954
+HOLD negedge:RADDR[5] posedge:RCLK 52.3434:68:82.6954
+HOLD negedge:RADDR[6] posedge:RCLK 52.3434:68:82.6954
+HOLD negedge:RADDR[7] posedge:RCLK 52.3434:68:82.6954
+HOLD negedge:RADDR[8] posedge:RCLK 52.3434:68:82.6954
+HOLD negedge:RADDR[9] posedge:RCLK 52.3434:68:82.6954
+HOLD negedge:RADDR[10] posedge:RCLK 52.3434:68:82.6954
+HOLD negedge:RCLKE posedge:RCLK 49.072:63.75:77.5269
+HOLD negedge:RE posedge:RCLK 78.5152:102:124.043
+HOLD negedge:WADDR[0] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WADDR[1] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WADDR[2] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WADDR[3] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WADDR[4] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WADDR[5] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WADDR[6] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WADDR[7] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WADDR[8] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WADDR[9] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WADDR[10] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WCLKE posedge:WCLK 25.5174:33.15:40.314
+HOLD negedge:WDATA[0] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[1] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[2] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[3] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[4] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[5] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[6] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[7] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[8] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[9] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[10] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[11] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[12] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[13] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[14] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[15] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WE posedge:WCLK 45.8005:59.5:72.3585
+HOLD posedge:MASK[0] posedge:WCLK 0:0:0
+HOLD posedge:MASK[1] posedge:WCLK 0:0:0
+HOLD posedge:MASK[2] posedge:WCLK 0:0:0
+HOLD posedge:MASK[3] posedge:WCLK 0:0:0
+HOLD posedge:MASK[4] posedge:WCLK 0:0:0
+HOLD posedge:MASK[5] posedge:WCLK 0:0:0
+HOLD posedge:MASK[6] posedge:WCLK 0:0:0
+HOLD posedge:MASK[7] posedge:WCLK 0:0:0
+HOLD posedge:MASK[8] posedge:WCLK 0:0:0
+HOLD posedge:MASK[9] posedge:WCLK 0:0:0
+HOLD posedge:MASK[10] posedge:WCLK 0:0:0
+HOLD posedge:MASK[11] posedge:WCLK 0:0:0
+HOLD posedge:MASK[12] posedge:WCLK 0:0:0
+HOLD posedge:MASK[13] posedge:WCLK 0:0:0
+HOLD posedge:MASK[14] posedge:WCLK 0:0:0
+HOLD posedge:MASK[15] posedge:WCLK 0:0:0
+HOLD posedge:RADDR[0] posedge:RCLK 52.3434:68:82.6954
+HOLD posedge:RADDR[1] posedge:RCLK 52.3434:68:82.6954
+HOLD posedge:RADDR[2] posedge:RCLK 52.3434:68:82.6954
+HOLD posedge:RADDR[3] posedge:RCLK 52.3434:68:82.6954
+HOLD posedge:RADDR[4] posedge:RCLK 52.3434:68:82.6954
+HOLD posedge:RADDR[5] posedge:RCLK 52.3434:68:82.6954
+HOLD posedge:RADDR[6] posedge:RCLK 52.3434:68:82.6954
+HOLD posedge:RADDR[7] posedge:RCLK 52.3434:68:82.6954
+HOLD posedge:RADDR[8] posedge:RCLK 52.3434:68:82.6954
+HOLD posedge:RADDR[9] posedge:RCLK 52.3434:68:82.6954
+HOLD posedge:RADDR[10] posedge:RCLK 52.3434:68:82.6954
+HOLD posedge:RCLKE posedge:RCLK 49.072:63.75:77.5269
+HOLD posedge:RE posedge:RCLK 78.5152:102:124.043
+HOLD posedge:WADDR[0] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WADDR[1] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WADDR[2] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WADDR[3] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WADDR[4] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WADDR[5] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WADDR[6] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WADDR[7] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WADDR[8] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WADDR[9] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WADDR[10] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WCLKE posedge:WCLK 25.5174:33.15:40.314
+HOLD posedge:WDATA[0] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[1] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[2] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[3] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[4] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[5] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[6] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[7] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[8] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[9] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[10] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[11] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[12] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[13] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[14] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[15] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WE posedge:WCLK 45.8005:59.5:72.3585
+SETUP negedge:MASK[0] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[1] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[2] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[3] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[4] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[5] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[6] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[7] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[8] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[9] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[10] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[11] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[12] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[13] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[14] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[15] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:RADDR[0] posedge:RCLK 189.745:246.5:299.771
+SETUP negedge:RADDR[1] posedge:RCLK 189.745:246.5:299.771
+SETUP negedge:RADDR[2] posedge:RCLK 189.745:246.5:299.771
+SETUP negedge:RADDR[3] posedge:RCLK 189.745:246.5:299.771
+SETUP negedge:RADDR[4] posedge:RCLK 189.745:246.5:299.771
+SETUP negedge:RADDR[5] posedge:RCLK 189.745:246.5:299.771
+SETUP negedge:RADDR[6] posedge:RCLK 189.745:246.5:299.771
+SETUP negedge:RADDR[7] posedge:RCLK 189.745:246.5:299.771
+SETUP negedge:RADDR[8] posedge:RCLK 189.745:246.5:299.771
+SETUP negedge:RADDR[9] posedge:RCLK 189.745:246.5:299.771
+SETUP negedge:RADDR[10] posedge:RCLK 189.745:246.5:299.771
+SETUP negedge:RCLKE posedge:RCLK 248.631:323:392.803
+SETUP negedge:RE posedge:RCLK 91.601:119:144.717
+SETUP negedge:WADDR[0] posedge:WCLK 209.374:272:330.781
+SETUP negedge:WADDR[1] posedge:WCLK 209.374:272:330.781
+SETUP negedge:WADDR[2] posedge:WCLK 209.374:272:330.781
+SETUP negedge:WADDR[3] posedge:WCLK 209.374:272:330.781
+SETUP negedge:WADDR[4] posedge:WCLK 209.374:272:330.781
+SETUP negedge:WADDR[5] posedge:WCLK 209.374:272:330.781
+SETUP negedge:WADDR[6] posedge:WCLK 209.374:272:330.781
+SETUP negedge:WADDR[7] posedge:WCLK 209.374:272:330.781
+SETUP negedge:WADDR[8] posedge:WCLK 209.374:272:330.781
+SETUP negedge:WADDR[9] posedge:WCLK 209.374:272:330.781
+SETUP negedge:WADDR[10] posedge:WCLK 209.374:272:330.781
+SETUP negedge:WCLKE posedge:WCLK 248.631:323:392.803
+SETUP negedge:WDATA[0] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[1] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[2] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[3] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[4] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[5] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[6] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[7] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[8] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[9] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[10] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[11] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[12] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[13] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[14] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[15] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WE posedge:WCLK 124.316:161.5:196.402
+SETUP posedge:MASK[0] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[1] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[2] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[3] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[4] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[5] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[6] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[7] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[8] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[9] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[10] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[11] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[12] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[13] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[14] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[15] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:RADDR[0] posedge:RCLK 189.745:246.5:299.771
+SETUP posedge:RADDR[1] posedge:RCLK 189.745:246.5:299.771
+SETUP posedge:RADDR[2] posedge:RCLK 189.745:246.5:299.771
+SETUP posedge:RADDR[3] posedge:RCLK 189.745:246.5:299.771
+SETUP posedge:RADDR[4] posedge:RCLK 189.745:246.5:299.771
+SETUP posedge:RADDR[5] posedge:RCLK 189.745:246.5:299.771
+SETUP posedge:RADDR[6] posedge:RCLK 189.745:246.5:299.771
+SETUP posedge:RADDR[7] posedge:RCLK 189.745:246.5:299.771
+SETUP posedge:RADDR[8] posedge:RCLK 189.745:246.5:299.771
+SETUP posedge:RADDR[9] posedge:RCLK 189.745:246.5:299.771
+SETUP posedge:RADDR[10] posedge:RCLK 189.745:246.5:299.771
+SETUP posedge:RCLKE posedge:RCLK 248.631:323:392.803
+SETUP posedge:RE posedge:RCLK 91.601:119:144.717
+SETUP posedge:WADDR[0] posedge:WCLK 209.374:272:330.781
+SETUP posedge:WADDR[1] posedge:WCLK 209.374:272:330.781
+SETUP posedge:WADDR[2] posedge:WCLK 209.374:272:330.781
+SETUP posedge:WADDR[3] posedge:WCLK 209.374:272:330.781
+SETUP posedge:WADDR[4] posedge:WCLK 209.374:272:330.781
+SETUP posedge:WADDR[5] posedge:WCLK 209.374:272:330.781
+SETUP posedge:WADDR[6] posedge:WCLK 209.374:272:330.781
+SETUP posedge:WADDR[7] posedge:WCLK 209.374:272:330.781
+SETUP posedge:WADDR[8] posedge:WCLK 209.374:272:330.781
+SETUP posedge:WADDR[9] posedge:WCLK 209.374:272:330.781
+SETUP posedge:WADDR[10] posedge:WCLK 209.374:272:330.781
+SETUP posedge:WCLKE posedge:WCLK 248.631:323:392.803
+SETUP posedge:WDATA[0] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[1] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[2] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[3] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[4] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[5] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[6] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[7] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[8] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[9] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[10] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[11] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[12] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[13] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[14] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[15] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WE posedge:WCLK 124.316:161.5:196.402
+IOPATH posedge:RCLK RDATA[0] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[1] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[2] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[3] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[4] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[5] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[6] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[7] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[8] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[9] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[10] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[11] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[12] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[13] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[14] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[15] 2002.14:2601:3163.1 2002.14:2601:3163.1
+
+CELL Sp12to4
+IOPATH I O 399.119:518.5:630.552 418.748:544:661.563
+
+CELL Span4Mux_h0
+IOPATH I O 137.402:178.5:217.075 130.859:170:206.738
+
+CELL Span4Mux_h1
+IOPATH I O 163.573:212.5:258.423 157.03:204:248.086
+
+CELL Span4Mux_h2
+IOPATH I O 189.745:246.5:299.771 189.745:246.5:299.771
+
+CELL Span4Mux_h3
+IOPATH I O 215.917:280.5:341.118 215.917:280.5:341.118
+
+CELL Span4Mux_h4
+IOPATH I O 281.346:365.5:444.488 294.432:382.5:465.161
+
+CELL Span4Mux_v0
+IOPATH I O 189.745:246.5:299.771 176.659:229.5:279.097
+
+CELL Span4Mux_v1
+IOPATH I O 189.745:246.5:299.771 183.202:238:289.434
+
+CELL Span4Mux_v2
+IOPATH I O 235.546:306:372.129 235.546:306:372.129
+
+CELL Span4Mux_v3
+IOPATH I O 294.432:382.5:465.161 314.061:408:496.172
+
+CELL Span4Mux_v4
+IOPATH I O 327.147:425:516.846 346.775:450.5:547.857
+
+CELL Span12Mux_h0
+IOPATH I O 130.859:170:206.738 137.402:178.5:217.075
+
+CELL Span12Mux_h1
+IOPATH I O 124.316:161.5:196.402 124.316:161.5:196.402
+
+CELL Span12Mux_h2
+IOPATH I O 150.487:195.5:237.749 157.03:204:248.086
+
+CELL Span12Mux_h3
+IOPATH I O 157.03:204:248.086 170.116:221:268.76
+
+CELL Span12Mux_h4
+IOPATH I O 183.202:238:289.434 202.831:263.5:320.445
+
+CELL Span12Mux_h5
+IOPATH I O 215.917:280.5:341.118 242.088:314.5:382.466
+
+CELL Span12Mux_h6
+IOPATH I O 235.546:306:372.129 261.717:340:413.477
+
+CELL Span12Mux_h7
+IOPATH I O 268.26:348.5:423.814 300.975:391:475.498
+
+CELL Span12Mux_h8
+IOPATH I O 320.604:416.5:506.509 359.861:467.5:568.531
+
+CELL Span12Mux_h9
+IOPATH I O 366.404:476:578.868 405.662:527:640.889
+
+CELL Span12Mux_h10
+IOPATH I O 399.119:518.5:630.552 438.376:569.5:692.574
+
+CELL Span12Mux_h11
+IOPATH I O 438.376:569.5:692.574 490.72:637.5:775.269
+
+CELL Span12Mux_h12
+IOPATH I O 458.005:595:723.585 503.806:654.5:795.943
+
+CELL Span12Mux_v0
+IOPATH I O 91.601:119:144.717 98.144:127.5:155.054
+
+CELL Span12Mux_v1
+IOPATH I O 98.144:127.5:155.054 98.144:127.5:155.054
+
+CELL Span12Mux_v2
+IOPATH I O 130.859:170:206.738 143.944:187:227.412
+
+CELL Span12Mux_v3
+IOPATH I O 137.402:178.5:217.075 157.03:204:248.086
+
+CELL Span12Mux_v4
+IOPATH I O 170.116:221:268.76 196.288:255:310.108
+
+CELL Span12Mux_v5
+IOPATH I O 222.46:289:351.455 248.631:323:392.803
+
+CELL Span12Mux_v6
+IOPATH I O 242.088:314.5:382.466 268.26:348.5:423.814
+
+CELL Span12Mux_v7
+IOPATH I O 261.717:340:413.477 294.432:382.5:465.161
+
+CELL Span12Mux_v8
+IOPATH I O 333.689:433.5:527.183 366.404:476:578.868
+
+CELL Span12Mux_v9
+IOPATH I O 353.318:459:558.194 392.576:510:620.215
+
+CELL Span12Mux_v10
+IOPATH I O 366.404:476:578.868 405.662:527:640.889
+
+CELL Span12Mux_v11
+IOPATH I O 386.033:501.5:609.878 425.29:552.5:671.9
+
+CELL Span12Mux_v12
+IOPATH I O 458.005:595:723.585 503.806:654.5:795.943
+
+CELL SRMux
+IOPATH I O 431.833:561:682.237 333.689:433.5:527.183
+
diff --git a/icefuzz/timings_8k.txt b/icefuzz/timings_8k.txt
new file mode 100644
index 0000000..4a60b63
--- /dev/null
+++ b/icefuzz/timings_8k.txt
@@ -0,0 +1,528 @@
+CELL CascadeMux
+IOPATH I O 0:0:0 0:0:0
+
+CELL CEMux
+IOPATH I O 562.692:731:888.975 516.892:671.5:816.617
+
+CELL ClkMux
+IOPATH I O 287.889:374:454.825 215.917:280.5:341.118
+
+CELL gio2CtrlBuf
+IOPATH I O 0:0:0 0:0:0
+
+CELL Glb2LocalMux
+IOPATH I O 418.748:544:661.563 333.689:433.5:527.183
+
+CELL GlobalMux
+IOPATH I O 143.944:187:227.412 71.9722:93.5:113.706
+
+CELL ICE_CARRY_IN_MUX
+IOPATH carryinitin carryinitout 183.202:238:289.434 163.573:212.5:258.423
+
+CELL ICE_GB
+IOPATH USERSIGNALTOGLOBALBUFFER GLOBALBUFFEROUTPUT 575.778:748:909.649 523.434:680:826.954
+
+CELL InMux
+IOPATH I O 242.088:314.5:382.466 202.831:263.5:320.445
+
+CELL INV
+IOPATH I O 0:0:0 0:0:0
+
+CELL IO_PAD
+IOPATH DIN PACKAGEPIN 2291.5:2291.5:2291.5 2353.2:2353.2:2353.2
+IOPATH OE PACKAGEPIN 1902:1902:1902 1990:1990:1990
+IOPATH OE PACKAGEPIN 1973:1973:1973 1942:1942:1942
+IOPATH OE PACKAGEPIN 2291.5:2291.5:2291.5 2353.2:2353.2:2353.2
+IOPATH PACKAGEPIN DOUT 590:590:590 540:540:540
+
+CELL IoInMux
+IOPATH I O 242.088:314.5:382.466 202.831:263.5:320.445
+
+CELL IoSpan4Mux
+IOPATH I O 268.26:348.5:423.814 300.975:391:475.498
+
+CELL LocalMux
+IOPATH I O 307.518:399.5:485.835 287.889:374:454.825
+
+CELL LogicCell40
+HOLD negedge:ce posedge:clk 0:0:0
+HOLD negedge:in0 posedge:clk 0:0:0
+HOLD negedge:in1 posedge:clk 0:0:0
+HOLD negedge:in2 posedge:clk 0:0:0
+HOLD negedge:in3 posedge:clk 0:0:0
+HOLD negedge:sr posedge:clk -184.184:-239.275:-290.984
+HOLD posedge:ce posedge:clk 0:0:0
+HOLD posedge:in0 posedge:clk 0:0:0
+HOLD posedge:in1 posedge:clk 0:0:0
+HOLD posedge:in2 posedge:clk 0:0:0
+HOLD posedge:in3 posedge:clk 0:0:0
+HOLD posedge:sr posedge:clk -167.106:-217.09:-264.005
+RECOVERY negedge:sr posedge:clk 148.983:193.545:235.372
+RECOVERY posedge:sr posedge:clk 0:0:0
+REMOVAL negedge:sr posedge:clk 0:0:0
+REMOVAL posedge:sr posedge:clk 0:0:0
+SETUP negedge:ce posedge:clk 0:0:0
+SETUP negedge:in0 posedge:clk 372.947:484.5:589.205
+SETUP negedge:in1 posedge:clk 353.318:459:558.194
+SETUP negedge:in2 posedge:clk 300.975:391:475.498
+SETUP negedge:in3 posedge:clk 202.831:263.5:320.445
+SETUP negedge:sr posedge:clk 130.859:170:206.738
+SETUP posedge:ce posedge:clk 0:0:0
+SETUP posedge:in0 posedge:clk 438.376:569.5:692.574
+SETUP posedge:in1 posedge:clk 372.947:484.5:589.205
+SETUP posedge:in2 posedge:clk 346.775:450.5:547.857
+SETUP posedge:in3 posedge:clk 255.174:331.5:403.14
+SETUP posedge:sr posedge:clk 189.745:246.5:299.771
+IOPATH carryin carryout 117.773:153:186.065 98.144:127.5:155.054
+IOPATH in0 lcout 418.748:544:661.563 359.861:467.5:568.531
+IOPATH in0 ltout 340.232:442:537.52 359.861:467.5:568.531
+IOPATH in1 carryout 242.088:314.5:382.466 229.003:297.5:361.792
+IOPATH in1 lcout 372.947:484.5:589.205 353.318:459:558.194
+IOPATH in1 ltout 300.975:391:475.498 353.318:459:558.194
+IOPATH in2 carryout 215.917:280.5:341.118 124.316:161.5:196.402
+IOPATH in2 lcout 353.318:459:558.194 327.147:425:516.846
+IOPATH in2 ltout 287.889:374:454.825 320.604:416.5:506.509
+IOPATH in3 lcout 294.432:382.5:465.161 268.26:348.5:423.814
+IOPATH in3 ltout 248.631:323:392.803 255.174:331.5:403.14
+IOPATH posedge:clk lcout 503.806:654.5:795.943 503.806:654.5:795.943
+IOPATH sr lcout 0:0:0 558.989:726.189:883.125
+IOPATH sr lcout 558.963:726.155:883.083 0:0:0
+
+CELL Odrv4
+IOPATH I O 327.147:425:516.846 346.775:450.5:547.857
+
+CELL Odrv12
+IOPATH I O 458.005:595:723.585 503.806:654.5:795.943
+
+CELL PLL40
+IOPATH PLLIN PLLOUTCORE *:*:* *:*:*
+IOPATH PLLIN PLLOUTGLOBAL *:*:* *:*:*
+
+CELL PLL40_2
+IOPATH PLLIN PLLOUTCOREA *:*:* *:*:*
+IOPATH PLLIN PLLOUTCOREB *:*:* *:*:*
+IOPATH PLLIN PLLOUTGLOBALA *:*:* *:*:*
+IOPATH PLLIN PLLOUTGLOBALB *:*:* *:*:*
+
+CELL PLL40_2F
+IOPATH PLLIN PLLOUTCOREA *:*:* *:*:*
+IOPATH PLLIN PLLOUTCOREB *:*:* *:*:*
+IOPATH PLLIN PLLOUTGLOBALA *:*:* *:*:*
+IOPATH PLLIN PLLOUTGLOBALB *:*:* *:*:*
+
+CELL PRE_IO
+HOLD negedge:CLOCKENABLE posedge:INPUTCLK 0:0:0
+HOLD negedge:CLOCKENABLE posedge:OUTPUTCLK 0:0:0
+HOLD negedge:DOUT0 posedge:OUTPUTCLK 0:0:0
+HOLD negedge:DOUT1 negedge:OUTPUTCLK 0:0:0
+HOLD negedge:OUTPUTENABLE posedge:OUTPUTCLK 0:0:0
+HOLD negedge:PADIN negedge:INPUTCLK 0:0:0
+HOLD negedge:PADIN posedge:INPUTCLK 0:0:0
+HOLD posedge:CLOCKENABLE posedge:INPUTCLK 0:0:0
+HOLD posedge:CLOCKENABLE posedge:OUTPUTCLK 0:0:0
+HOLD posedge:DOUT0 posedge:OUTPUTCLK 0:0:0
+HOLD posedge:DOUT1 negedge:OUTPUTCLK 0:0:0
+HOLD posedge:OUTPUTENABLE posedge:OUTPUTCLK 0:0:0
+HOLD posedge:PADIN negedge:INPUTCLK 0:0:0
+HOLD posedge:PADIN posedge:INPUTCLK 0:0:0
+SETUP negedge:CLOCKENABLE posedge:INPUTCLK 65.4293:85:103.369
+SETUP negedge:CLOCKENABLE posedge:OUTPUTCLK 65.4293:85:103.369
+SETUP negedge:DOUT0 posedge:OUTPUTCLK 65.4293:85:103.369
+SETUP negedge:DOUT1 negedge:OUTPUTCLK 65.4293:85:103.369
+SETUP negedge:OUTPUTENABLE posedge:OUTPUTCLK 65.4293:85:103.369
+SETUP negedge:PADIN negedge:INPUTCLK 1758.87:2284.97:2778.77
+SETUP negedge:PADIN posedge:INPUTCLK 1758.87:2284.97:2778.77
+SETUP posedge:CLOCKENABLE posedge:INPUTCLK 71.9722:93.5:113.706
+SETUP posedge:CLOCKENABLE posedge:OUTPUTCLK 71.9722:93.5:113.706
+SETUP posedge:DOUT0 posedge:OUTPUTCLK 71.9722:93.5:113.706
+SETUP posedge:DOUT1 negedge:OUTPUTCLK 71.9722:93.5:113.706
+SETUP posedge:OUTPUTENABLE posedge:OUTPUTCLK 71.9722:93.5:113.706
+SETUP posedge:PADIN negedge:INPUTCLK 1765.41:2293.47:2789.11
+SETUP posedge:PADIN posedge:INPUTCLK 1765.41:2293.47:2789.11
+IOPATH DOUT0 PADOUT 1871.28:2431:2956.36 2087.19:2711.5:3297.48
+IOPATH LATCHINPUTVALUE DIN0 320.604:416.5:506.509 346.775:450.5:547.857
+IOPATH negedge:INPUTCLK DIN1 130.859:170:206.738 130.859:170:206.738
+IOPATH negedge:OUTPUTCLK PADOUT 104.687:136:165.391 130.859:170:206.738
+IOPATH OUTPUTENABLE PADOEN 163.573:212.5:258.423 196.288:255:310.108
+IOPATH PADIN DIN0 575.778:748:909.649 431.833:561:682.237
+IOPATH posedge:INPUTCLK DIN0 130.859:170:206.738 130.859:170:206.738
+IOPATH posedge:OUTPUTCLK PADOEN 104.687:136:165.391 130.859:170:206.738
+IOPATH posedge:OUTPUTCLK PADOUT 104.687:136:165.391 130.859:170:206.738
+
+CELL PRE_IO_GBUF
+IOPATH PADSIGNALTOGLOBALBUFFER GLOBALBUFFEROUTPUT 1737.34:2257:2744.76 1593.4:2070:2517.35
+
+CELL SB_PLL40_2F_CORE
+IOPATH REFERENCECLK PLLOUTCOREA *:*:* *:*:*
+IOPATH REFERENCECLK PLLOUTCOREB *:*:* *:*:*
+IOPATH REFERENCECLK PLLOUTGLOBALA *:*:* *:*:*
+IOPATH REFERENCECLK PLLOUTGLOBALB *:*:* *:*:*
+
+CELL SB_PLL40_CORE
+IOPATH REFERENCECLK PLLOUTCORE *:*:* *:*:*
+IOPATH REFERENCECLK PLLOUTGLOBAL *:*:* *:*:*
+
+CELL SB_RAM40_4K
+HOLD negedge:MASK[0] posedge:WCLK 0:0:0
+HOLD negedge:MASK[1] posedge:WCLK 0:0:0
+HOLD negedge:MASK[2] posedge:WCLK 0:0:0
+HOLD negedge:MASK[3] posedge:WCLK 0:0:0
+HOLD negedge:MASK[4] posedge:WCLK 0:0:0
+HOLD negedge:MASK[5] posedge:WCLK 0:0:0
+HOLD negedge:MASK[6] posedge:WCLK 0:0:0
+HOLD negedge:MASK[7] posedge:WCLK 0:0:0
+HOLD negedge:MASK[8] posedge:WCLK 0:0:0
+HOLD negedge:MASK[9] posedge:WCLK 0:0:0
+HOLD negedge:MASK[10] posedge:WCLK 0:0:0
+HOLD negedge:MASK[11] posedge:WCLK 0:0:0
+HOLD negedge:MASK[12] posedge:WCLK 0:0:0
+HOLD negedge:MASK[13] posedge:WCLK 0:0:0
+HOLD negedge:MASK[14] posedge:WCLK 0:0:0
+HOLD negedge:MASK[15] posedge:WCLK 0:0:0
+HOLD negedge:RADDR[0] posedge:RCLK 52.3434:68:82.6954
+HOLD negedge:RADDR[1] posedge:RCLK 52.3434:68:82.6954
+HOLD negedge:RADDR[2] posedge:RCLK 52.3434:68:82.6954
+HOLD negedge:RADDR[3] posedge:RCLK 52.3434:68:82.6954
+HOLD negedge:RADDR[4] posedge:RCLK 52.3434:68:82.6954
+HOLD negedge:RADDR[5] posedge:RCLK 52.3434:68:82.6954
+HOLD negedge:RADDR[6] posedge:RCLK 52.3434:68:82.6954
+HOLD negedge:RADDR[7] posedge:RCLK 52.3434:68:82.6954
+HOLD negedge:RADDR[8] posedge:RCLK 52.3434:68:82.6954
+HOLD negedge:RADDR[9] posedge:RCLK 52.3434:68:82.6954
+HOLD negedge:RADDR[10] posedge:RCLK 52.3434:68:82.6954
+HOLD negedge:RCLKE posedge:RCLK 49.072:63.75:77.5269
+HOLD negedge:RE posedge:RCLK 78.5152:102:124.043
+HOLD negedge:WADDR[0] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WADDR[1] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WADDR[2] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WADDR[3] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WADDR[4] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WADDR[5] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WADDR[6] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WADDR[7] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WADDR[8] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WADDR[9] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WADDR[10] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WCLKE posedge:WCLK 25.5174:33.15:40.314
+HOLD negedge:WDATA[0] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[1] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[2] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[3] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[4] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[5] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[6] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[7] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[8] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[9] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[10] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[11] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[12] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[13] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[14] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WDATA[15] posedge:WCLK 32.7147:42.5:51.6846
+HOLD negedge:WE posedge:WCLK 45.8005:59.5:72.3585
+HOLD posedge:MASK[0] posedge:WCLK 0:0:0
+HOLD posedge:MASK[1] posedge:WCLK 0:0:0
+HOLD posedge:MASK[2] posedge:WCLK 0:0:0
+HOLD posedge:MASK[3] posedge:WCLK 0:0:0
+HOLD posedge:MASK[4] posedge:WCLK 0:0:0
+HOLD posedge:MASK[5] posedge:WCLK 0:0:0
+HOLD posedge:MASK[6] posedge:WCLK 0:0:0
+HOLD posedge:MASK[7] posedge:WCLK 0:0:0
+HOLD posedge:MASK[8] posedge:WCLK 0:0:0
+HOLD posedge:MASK[9] posedge:WCLK 0:0:0
+HOLD posedge:MASK[10] posedge:WCLK 0:0:0
+HOLD posedge:MASK[11] posedge:WCLK 0:0:0
+HOLD posedge:MASK[12] posedge:WCLK 0:0:0
+HOLD posedge:MASK[13] posedge:WCLK 0:0:0
+HOLD posedge:MASK[14] posedge:WCLK 0:0:0
+HOLD posedge:MASK[15] posedge:WCLK 0:0:0
+HOLD posedge:RADDR[0] posedge:RCLK 52.3434:68:82.6954
+HOLD posedge:RADDR[1] posedge:RCLK 52.3434:68:82.6954
+HOLD posedge:RADDR[2] posedge:RCLK 52.3434:68:82.6954
+HOLD posedge:RADDR[3] posedge:RCLK 52.3434:68:82.6954
+HOLD posedge:RADDR[4] posedge:RCLK 52.3434:68:82.6954
+HOLD posedge:RADDR[5] posedge:RCLK 52.3434:68:82.6954
+HOLD posedge:RADDR[6] posedge:RCLK 52.3434:68:82.6954
+HOLD posedge:RADDR[7] posedge:RCLK 52.3434:68:82.6954
+HOLD posedge:RADDR[8] posedge:RCLK 52.3434:68:82.6954
+HOLD posedge:RADDR[9] posedge:RCLK 52.3434:68:82.6954
+HOLD posedge:RADDR[10] posedge:RCLK 52.3434:68:82.6954
+HOLD posedge:RCLKE posedge:RCLK 49.072:63.75:77.5269
+HOLD posedge:RE posedge:RCLK 78.5152:102:124.043
+HOLD posedge:WADDR[0] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WADDR[1] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WADDR[2] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WADDR[3] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WADDR[4] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WADDR[5] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WADDR[6] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WADDR[7] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WADDR[8] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WADDR[9] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WADDR[10] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WCLKE posedge:WCLK 25.5174:33.15:40.314
+HOLD posedge:WDATA[0] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[1] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[2] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[3] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[4] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[5] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[6] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[7] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[8] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[9] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[10] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[11] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[12] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[13] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[14] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WDATA[15] posedge:WCLK 32.7147:42.5:51.6846
+HOLD posedge:WE posedge:WCLK 45.8005:59.5:72.3585
+SETUP negedge:MASK[0] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[1] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[2] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[3] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[4] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[5] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[6] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[7] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[8] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[9] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[10] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[11] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[12] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[13] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[14] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:MASK[15] posedge:WCLK 255.174:331.5:403.14
+SETUP negedge:RADDR[0] posedge:RCLK 189.745:246.5:299.771
+SETUP negedge:RADDR[1] posedge:RCLK 189.745:246.5:299.771
+SETUP negedge:RADDR[2] posedge:RCLK 189.745:246.5:299.771
+SETUP negedge:RADDR[3] posedge:RCLK 189.745:246.5:299.771
+SETUP negedge:RADDR[4] posedge:RCLK 189.745:246.5:299.771
+SETUP negedge:RADDR[5] posedge:RCLK 189.745:246.5:299.771
+SETUP negedge:RADDR[6] posedge:RCLK 189.745:246.5:299.771
+SETUP negedge:RADDR[7] posedge:RCLK 189.745:246.5:299.771
+SETUP negedge:RADDR[8] posedge:RCLK 189.745:246.5:299.771
+SETUP negedge:RADDR[9] posedge:RCLK 189.745:246.5:299.771
+SETUP negedge:RADDR[10] posedge:RCLK 189.745:246.5:299.771
+SETUP negedge:RCLKE posedge:RCLK 248.631:323:392.803
+SETUP negedge:RE posedge:RCLK 91.601:119:144.717
+SETUP negedge:WADDR[0] posedge:WCLK 209.374:272:330.781
+SETUP negedge:WADDR[1] posedge:WCLK 209.374:272:330.781
+SETUP negedge:WADDR[2] posedge:WCLK 209.374:272:330.781
+SETUP negedge:WADDR[3] posedge:WCLK 209.374:272:330.781
+SETUP negedge:WADDR[4] posedge:WCLK 209.374:272:330.781
+SETUP negedge:WADDR[5] posedge:WCLK 209.374:272:330.781
+SETUP negedge:WADDR[6] posedge:WCLK 209.374:272:330.781
+SETUP negedge:WADDR[7] posedge:WCLK 209.374:272:330.781
+SETUP negedge:WADDR[8] posedge:WCLK 209.374:272:330.781
+SETUP negedge:WADDR[9] posedge:WCLK 209.374:272:330.781
+SETUP negedge:WADDR[10] posedge:WCLK 209.374:272:330.781
+SETUP negedge:WCLKE posedge:WCLK 248.631:323:392.803
+SETUP negedge:WDATA[0] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[1] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[2] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[3] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[4] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[5] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[6] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[7] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[8] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[9] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[10] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[11] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[12] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[13] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[14] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WDATA[15] posedge:WCLK 150.487:195.5:237.749
+SETUP negedge:WE posedge:WCLK 124.316:161.5:196.402
+SETUP posedge:MASK[0] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[1] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[2] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[3] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[4] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[5] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[6] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[7] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[8] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[9] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[10] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[11] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[12] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[13] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[14] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:MASK[15] posedge:WCLK 255.174:331.5:403.14
+SETUP posedge:RADDR[0] posedge:RCLK 189.745:246.5:299.771
+SETUP posedge:RADDR[1] posedge:RCLK 189.745:246.5:299.771
+SETUP posedge:RADDR[2] posedge:RCLK 189.745:246.5:299.771
+SETUP posedge:RADDR[3] posedge:RCLK 189.745:246.5:299.771
+SETUP posedge:RADDR[4] posedge:RCLK 189.745:246.5:299.771
+SETUP posedge:RADDR[5] posedge:RCLK 189.745:246.5:299.771
+SETUP posedge:RADDR[6] posedge:RCLK 189.745:246.5:299.771
+SETUP posedge:RADDR[7] posedge:RCLK 189.745:246.5:299.771
+SETUP posedge:RADDR[8] posedge:RCLK 189.745:246.5:299.771
+SETUP posedge:RADDR[9] posedge:RCLK 189.745:246.5:299.771
+SETUP posedge:RADDR[10] posedge:RCLK 189.745:246.5:299.771
+SETUP posedge:RCLKE posedge:RCLK 248.631:323:392.803
+SETUP posedge:RE posedge:RCLK 91.601:119:144.717
+SETUP posedge:WADDR[0] posedge:WCLK 209.374:272:330.781
+SETUP posedge:WADDR[1] posedge:WCLK 209.374:272:330.781
+SETUP posedge:WADDR[2] posedge:WCLK 209.374:272:330.781
+SETUP posedge:WADDR[3] posedge:WCLK 209.374:272:330.781
+SETUP posedge:WADDR[4] posedge:WCLK 209.374:272:330.781
+SETUP posedge:WADDR[5] posedge:WCLK 209.374:272:330.781
+SETUP posedge:WADDR[6] posedge:WCLK 209.374:272:330.781
+SETUP posedge:WADDR[7] posedge:WCLK 209.374:272:330.781
+SETUP posedge:WADDR[8] posedge:WCLK 209.374:272:330.781
+SETUP posedge:WADDR[9] posedge:WCLK 209.374:272:330.781
+SETUP posedge:WADDR[10] posedge:WCLK 209.374:272:330.781
+SETUP posedge:WCLKE posedge:WCLK 248.631:323:392.803
+SETUP posedge:WDATA[0] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[1] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[2] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[3] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[4] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[5] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[6] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[7] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[8] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[9] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[10] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[11] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[12] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[13] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[14] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WDATA[15] posedge:WCLK 150.487:195.5:237.749
+SETUP posedge:WE posedge:WCLK 124.316:161.5:196.402
+IOPATH posedge:RCLK RDATA[0] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[1] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[2] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[3] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[4] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[5] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[6] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[7] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[8] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[9] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[10] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[11] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[12] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[13] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[14] 2002.14:2601:3163.1 2002.14:2601:3163.1
+IOPATH posedge:RCLK RDATA[15] 2002.14:2601:3163.1 2002.14:2601:3163.1
+
+CELL Sp12to4
+IOPATH I O 399.119:518.5:630.552 418.748:544:661.563
+
+CELL Span4Mux_h0
+IOPATH I O 137.402:178.5:217.075 130.859:170:206.738
+
+CELL Span4Mux_h1
+IOPATH I O 163.573:212.5:258.423 157.03:204:248.086
+
+CELL Span4Mux_h2
+IOPATH I O 189.745:246.5:299.771 189.745:246.5:299.771
+
+CELL Span4Mux_h3
+IOPATH I O 215.917:280.5:341.118 215.917:280.5:341.118
+
+CELL Span4Mux_h4
+IOPATH I O 281.346:365.5:444.488 294.432:382.5:465.161
+
+CELL Span4Mux_v0
+IOPATH I O 189.745:246.5:299.771 176.659:229.5:279.097
+
+CELL Span4Mux_v1
+IOPATH I O 189.745:246.5:299.771 183.202:238:289.434
+
+CELL Span4Mux_v2
+IOPATH I O 235.546:306:372.129 235.546:306:372.129
+
+CELL Span4Mux_v3
+IOPATH I O 294.432:382.5:465.161 314.061:408:496.172
+
+CELL Span4Mux_v4
+IOPATH I O 327.147:425:516.846 346.775:450.5:547.857
+
+CELL Span12Mux_h0
+IOPATH I O 130.859:170:206.738 137.402:178.5:217.075
+
+CELL Span12Mux_h1
+IOPATH I O 124.316:161.5:196.402 124.316:161.5:196.402
+
+CELL Span12Mux_h2
+IOPATH I O 150.487:195.5:237.749 157.03:204:248.086
+
+CELL Span12Mux_h3
+IOPATH I O 157.03:204:248.086 170.116:221:268.76
+
+CELL Span12Mux_h4
+IOPATH I O 183.202:238:289.434 202.831:263.5:320.445
+
+CELL Span12Mux_h5
+IOPATH I O 215.917:280.5:341.118 242.088:314.5:382.466
+
+CELL Span12Mux_h6
+IOPATH I O 235.546:306:372.129 261.717:340:413.477
+
+CELL Span12Mux_h7
+IOPATH I O 268.26:348.5:423.814 300.975:391:475.498
+
+CELL Span12Mux_h8
+IOPATH I O 320.604:416.5:506.509 359.861:467.5:568.531
+
+CELL Span12Mux_h9
+IOPATH I O 366.404:476:578.868 405.662:527:640.889
+
+CELL Span12Mux_h10
+IOPATH I O 399.119:518.5:630.552 438.376:569.5:692.574
+
+CELL Span12Mux_h11
+IOPATH I O 438.376:569.5:692.574 490.72:637.5:775.269
+
+CELL Span12Mux_h12
+IOPATH I O 458.005:595:723.585 503.806:654.5:795.943
+
+CELL Span12Mux_v0
+IOPATH I O 91.601:119:144.717 98.144:127.5:155.054
+
+CELL Span12Mux_v1
+IOPATH I O 98.144:127.5:155.054 98.144:127.5:155.054
+
+CELL Span12Mux_v2
+IOPATH I O 130.859:170:206.738 143.944:187:227.412
+
+CELL Span12Mux_v3
+IOPATH I O 137.402:178.5:217.075 157.03:204:248.086
+
+CELL Span12Mux_v4
+IOPATH I O 170.116:221:268.76 196.288:255:310.108
+
+CELL Span12Mux_v5
+IOPATH I O 222.46:289:351.455 248.631:323:392.803
+
+CELL Span12Mux_v6
+IOPATH I O 242.088:314.5:382.466 268.26:348.5:423.814
+
+CELL Span12Mux_v7
+IOPATH I O 261.717:340:413.477 294.432:382.5:465.161
+
+CELL Span12Mux_v8
+IOPATH I O 333.689:433.5:527.183 366.404:476:578.868
+
+CELL Span12Mux_v9
+IOPATH I O 353.318:459:558.194 392.576:510:620.215
+
+CELL Span12Mux_v10
+IOPATH I O 366.404:476:578.868 405.662:527:640.889
+
+CELL Span12Mux_v11
+IOPATH I O 386.033:501.5:609.878 425.29:552.5:671.9
+
+CELL Span12Mux_v12
+IOPATH I O 458.005:595:723.585 503.806:654.5:795.943
+
+CELL SRMux
+IOPATH I O 431.833:561:682.237 333.689:433.5:527.183
+
diff --git a/icefuzz/tmedges.ys b/icefuzz/tmedges.ys
new file mode 100644
index 0000000..ab25f2d
--- /dev/null
+++ b/icefuzz/tmedges.ys
@@ -0,0 +1,20 @@
+hierarchy -generate LogicCell40 i:in* i:*in i:clk i:ce i:sr o:*out
+hierarchy -generate ICE_GB i:USERSIGNALTOGLOBALBUFFER o:GLOBALBUFFEROUTPUT
+hierarchy -generate PRE_IO_GBUF i:PADSIGNALTOGLOBALBUFFER o:GLOBALBUFFEROUTPUT
+hierarchy -generate VCC o:*
+hierarchy -generate GND o:*
+hierarchy -generate IO_PAD i:OE i:DIN o:DOUT io:PACKAGEPIN
+hierarchy -generate PRE_IO o:PADOEN o:PADOUT i:PADIN i:CLOCKENABLE o:DIN0 o:DIN1 \
+ i:DOUT0 i:DOUT1 i:INPUTCLK i:LATCHINPUTVALUE i:OUTPUTCLK i:OUTPUTENABLE
+hierarchy -generate *PLL40* i:PACKAGEPIN i:BYPASS i:DYNAMICDELAY i:EXTFEEDBACK i:LATCHINPUTVALUE \
+ o:LOCK o:PLLOUT* i:REFERENCECLK i:RESETB i:SCLK i:SDI o:SDO i:PLLIN
+hierarchy -generate SB_RAM40_4K o:RDATA i:RADDR i:WADDR i:MASK i:WDATA i:RCLKE i:RCLK i:RE i:WCLKE i:WCLK i:WE
+hierarchy -generate ICE_CARRY_IN_MUX i:*in o:*out
+hierarchy -generate *Mux* i:I o:O
+hierarchy -generate Odrv* i:I o:O
+hierarchy -generate Sp12to4 i:I o:O
+hierarchy -generate INV i:I o:O
+hierarchy -generate gio2CtrlBuf i:I o:O
+
+hierarchy -check
+tee -a tmedges.tmp edgetypes
diff --git a/icefuzz/tmedges_1k.txt b/icefuzz/tmedges_1k.txt
new file mode 100644
index 0000000..2794758
--- /dev/null
+++ b/icefuzz/tmedges_1k.txt
@@ -0,0 +1,612 @@
+CEMux.O LogicCell40.ce
+CEMux.O PRE_IO.CLOCKENABLE
+CEMux.O SB_RAM40_4K.RCLKE
+CEMux.O SB_RAM40_4K.WCLKE
+CascadeMux.O LogicCell40.in2
+CascadeMux.O SB_RAM40_4K.RADDR[0]
+CascadeMux.O SB_RAM40_4K.RADDR[10]
+CascadeMux.O SB_RAM40_4K.RADDR[1]
+CascadeMux.O SB_RAM40_4K.RADDR[2]
+CascadeMux.O SB_RAM40_4K.RADDR[3]
+CascadeMux.O SB_RAM40_4K.RADDR[4]
+CascadeMux.O SB_RAM40_4K.RADDR[5]
+CascadeMux.O SB_RAM40_4K.RADDR[6]
+CascadeMux.O SB_RAM40_4K.RADDR[7]
+CascadeMux.O SB_RAM40_4K.RADDR[8]
+CascadeMux.O SB_RAM40_4K.RADDR[9]
+CascadeMux.O SB_RAM40_4K.WADDR[0]
+CascadeMux.O SB_RAM40_4K.WADDR[10]
+CascadeMux.O SB_RAM40_4K.WADDR[1]
+CascadeMux.O SB_RAM40_4K.WADDR[2]
+CascadeMux.O SB_RAM40_4K.WADDR[3]
+CascadeMux.O SB_RAM40_4K.WADDR[4]
+CascadeMux.O SB_RAM40_4K.WADDR[5]
+CascadeMux.O SB_RAM40_4K.WADDR[6]
+CascadeMux.O SB_RAM40_4K.WADDR[7]
+CascadeMux.O SB_RAM40_4K.WADDR[8]
+CascadeMux.O SB_RAM40_4K.WADDR[9]
+ClkMux.O INV.I
+ClkMux.O LogicCell40.clk
+ClkMux.O PRE_IO.INPUTCLK
+ClkMux.O PRE_IO.OUTPUTCLK
+ClkMux.O SB_RAM40_4K.RCLK
+ClkMux.O SB_RAM40_4K.WCLK
+GND.Y LogicCell40.carryin
+GND.Y LogicCell40.clk
+GND.Y LogicCell40.in0
+GND.Y LogicCell40.in1
+GND.Y LogicCell40.in2
+GND.Y LogicCell40.in3
+GND.Y LogicCell40.sr
+GND.Y PRE_IO.DOUT0
+Glb2LocalMux.O LocalMux.I
+GlobalMux.O CEMux.I
+GlobalMux.O ClkMux.I
+GlobalMux.O Glb2LocalMux.I
+GlobalMux.O SRMux.I
+ICE_CARRY_IN_MUX.carryinitout InMux.I
+ICE_CARRY_IN_MUX.carryinitout LogicCell40.carryin
+ICE_GB.GLOBALBUFFEROUTPUT gio2CtrlBuf.I
+INV.O LogicCell40.clk
+INV.O SB_RAM40_4K.RCLK
+INV.O SB_RAM40_4K.WCLK
+IO_PAD.DOUT PLL40.PLLIN
+IO_PAD.DOUT PLL40_2.PLLIN
+IO_PAD.DOUT PLL40_2F.PLLIN
+IO_PAD.DOUT PRE_IO.PADIN
+IO_PAD.DOUT PRE_IO_GBUF.PADSIGNALTOGLOBALBUFFER
+IO_PAD.PACKAGEPIN IO_PAD.PACKAGEPIN
+InMux.O CascadeMux.I
+InMux.O LogicCell40.in0
+InMux.O LogicCell40.in1
+InMux.O LogicCell40.in3
+InMux.O SB_RAM40_4K.MASK[0]
+InMux.O SB_RAM40_4K.MASK[10]
+InMux.O SB_RAM40_4K.MASK[11]
+InMux.O SB_RAM40_4K.MASK[12]
+InMux.O SB_RAM40_4K.MASK[13]
+InMux.O SB_RAM40_4K.MASK[14]
+InMux.O SB_RAM40_4K.MASK[15]
+InMux.O SB_RAM40_4K.MASK[1]
+InMux.O SB_RAM40_4K.MASK[2]
+InMux.O SB_RAM40_4K.MASK[3]
+InMux.O SB_RAM40_4K.MASK[4]
+InMux.O SB_RAM40_4K.MASK[5]
+InMux.O SB_RAM40_4K.MASK[6]
+InMux.O SB_RAM40_4K.MASK[7]
+InMux.O SB_RAM40_4K.MASK[8]
+InMux.O SB_RAM40_4K.MASK[9]
+InMux.O SB_RAM40_4K.WDATA[0]
+InMux.O SB_RAM40_4K.WDATA[10]
+InMux.O SB_RAM40_4K.WDATA[11]
+InMux.O SB_RAM40_4K.WDATA[12]
+InMux.O SB_RAM40_4K.WDATA[13]
+InMux.O SB_RAM40_4K.WDATA[14]
+InMux.O SB_RAM40_4K.WDATA[15]
+InMux.O SB_RAM40_4K.WDATA[1]
+InMux.O SB_RAM40_4K.WDATA[2]
+InMux.O SB_RAM40_4K.WDATA[3]
+InMux.O SB_RAM40_4K.WDATA[4]
+InMux.O SB_RAM40_4K.WDATA[5]
+InMux.O SB_RAM40_4K.WDATA[6]
+InMux.O SB_RAM40_4K.WDATA[7]
+InMux.O SB_RAM40_4K.WDATA[8]
+InMux.O SB_RAM40_4K.WDATA[9]
+IoInMux.O ICE_GB.USERSIGNALTOGLOBALBUFFER
+IoInMux.O PLL40.BYPASS
+IoInMux.O PLL40.DYNAMICDELAY[0]
+IoInMux.O PLL40.DYNAMICDELAY[1]
+IoInMux.O PLL40.DYNAMICDELAY[2]
+IoInMux.O PLL40.DYNAMICDELAY[3]
+IoInMux.O PLL40.DYNAMICDELAY[4]
+IoInMux.O PLL40.DYNAMICDELAY[5]
+IoInMux.O PLL40.DYNAMICDELAY[6]
+IoInMux.O PLL40.DYNAMICDELAY[7]
+IoInMux.O PLL40.EXTFEEDBACK
+IoInMux.O PLL40.LATCHINPUTVALUE
+IoInMux.O PLL40.RESETB
+IoInMux.O PLL40.SCLK
+IoInMux.O PLL40.SDI
+IoInMux.O PLL40_2.BYPASS
+IoInMux.O PLL40_2.DYNAMICDELAY[0]
+IoInMux.O PLL40_2.DYNAMICDELAY[1]
+IoInMux.O PLL40_2.DYNAMICDELAY[2]
+IoInMux.O PLL40_2.DYNAMICDELAY[3]
+IoInMux.O PLL40_2.DYNAMICDELAY[4]
+IoInMux.O PLL40_2.DYNAMICDELAY[5]
+IoInMux.O PLL40_2.DYNAMICDELAY[6]
+IoInMux.O PLL40_2.DYNAMICDELAY[7]
+IoInMux.O PLL40_2.EXTFEEDBACK
+IoInMux.O PLL40_2.LATCHINPUTVALUE
+IoInMux.O PLL40_2.RESETB
+IoInMux.O PLL40_2.SCLK
+IoInMux.O PLL40_2.SDI
+IoInMux.O PLL40_2F.BYPASS
+IoInMux.O PLL40_2F.DYNAMICDELAY[0]
+IoInMux.O PLL40_2F.DYNAMICDELAY[1]
+IoInMux.O PLL40_2F.DYNAMICDELAY[2]
+IoInMux.O PLL40_2F.DYNAMICDELAY[3]
+IoInMux.O PLL40_2F.DYNAMICDELAY[4]
+IoInMux.O PLL40_2F.DYNAMICDELAY[5]
+IoInMux.O PLL40_2F.DYNAMICDELAY[6]
+IoInMux.O PLL40_2F.DYNAMICDELAY[7]
+IoInMux.O PLL40_2F.EXTFEEDBACK
+IoInMux.O PLL40_2F.LATCHINPUTVALUE
+IoInMux.O PLL40_2F.RESETB
+IoInMux.O PLL40_2F.SCLK
+IoInMux.O PLL40_2F.SDI
+IoInMux.O PRE_IO.DOUT0
+IoInMux.O PRE_IO.DOUT1
+IoInMux.O PRE_IO.LATCHINPUTVALUE
+IoInMux.O PRE_IO.OUTPUTENABLE
+IoInMux.O SB_PLL40_2F_CORE.BYPASS
+IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[0]
+IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[1]
+IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[2]
+IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[3]
+IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[4]
+IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[5]
+IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[6]
+IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[7]
+IoInMux.O SB_PLL40_2F_CORE.EXTFEEDBACK
+IoInMux.O SB_PLL40_2F_CORE.LATCHINPUTVALUE
+IoInMux.O SB_PLL40_2F_CORE.REFERENCECLK
+IoInMux.O SB_PLL40_2F_CORE.RESETB
+IoInMux.O SB_PLL40_2F_CORE.SCLK
+IoInMux.O SB_PLL40_2F_CORE.SDI
+IoInMux.O SB_PLL40_CORE.BYPASS
+IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[0]
+IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[1]
+IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[2]
+IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[3]
+IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[4]
+IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[5]
+IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[6]
+IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[7]
+IoInMux.O SB_PLL40_CORE.EXTFEEDBACK
+IoInMux.O SB_PLL40_CORE.LATCHINPUTVALUE
+IoInMux.O SB_PLL40_CORE.REFERENCECLK
+IoInMux.O SB_PLL40_CORE.RESETB
+IoInMux.O SB_PLL40_CORE.SCLK
+IoInMux.O SB_PLL40_CORE.SDI
+IoSpan4Mux.O IoSpan4Mux.I
+IoSpan4Mux.O LocalMux.I
+IoSpan4Mux.O Span4Mux_h.I
+IoSpan4Mux.O Span4Mux_s0_h.I
+IoSpan4Mux.O Span4Mux_s0_v.I
+IoSpan4Mux.O Span4Mux_s1_h.I
+IoSpan4Mux.O Span4Mux_s1_v.I
+IoSpan4Mux.O Span4Mux_s2_h.I
+IoSpan4Mux.O Span4Mux_s2_v.I
+IoSpan4Mux.O Span4Mux_s3_h.I
+IoSpan4Mux.O Span4Mux_s3_v.I
+IoSpan4Mux.O Span4Mux_v.I
+LocalMux.O CEMux.I
+LocalMux.O ClkMux.I
+LocalMux.O InMux.I
+LocalMux.O IoInMux.I
+LocalMux.O SRMux.I
+LogicCell40.carryout ICE_CARRY_IN_MUX.carryinitin
+LogicCell40.carryout InMux.I
+LogicCell40.carryout LogicCell40.carryin
+LogicCell40.lcout LocalMux.I
+LogicCell40.lcout Odrv12.I
+LogicCell40.lcout Odrv4.I
+LogicCell40.ltout CascadeMux.I
+Odrv12.O LocalMux.I
+Odrv12.O Sp12to4.I
+Odrv12.O Span12Mux_s0_h.I
+Odrv12.O Span12Mux_s0_v.I
+Odrv12.O Span12Mux_s10_h.I
+Odrv12.O Span12Mux_s10_v.I
+Odrv12.O Span12Mux_s11_h.I
+Odrv12.O Span12Mux_s11_v.I
+Odrv12.O Span12Mux_s1_h.I
+Odrv12.O Span12Mux_s1_v.I
+Odrv12.O Span12Mux_s2_h.I
+Odrv12.O Span12Mux_s2_v.I
+Odrv12.O Span12Mux_s3_h.I
+Odrv12.O Span12Mux_s3_v.I
+Odrv12.O Span12Mux_s4_h.I
+Odrv12.O Span12Mux_s4_v.I
+Odrv12.O Span12Mux_s5_h.I
+Odrv12.O Span12Mux_s5_v.I
+Odrv12.O Span12Mux_s6_h.I
+Odrv12.O Span12Mux_s6_v.I
+Odrv12.O Span12Mux_s7_h.I
+Odrv12.O Span12Mux_s7_v.I
+Odrv12.O Span12Mux_s8_h.I
+Odrv12.O Span12Mux_s8_v.I
+Odrv12.O Span12Mux_s9_h.I
+Odrv12.O Span12Mux_s9_v.I
+Odrv12.O Span12Mux_v.I
+Odrv4.O IoSpan4Mux.I
+Odrv4.O LocalMux.I
+Odrv4.O Span4Mux_h.I
+Odrv4.O Span4Mux_s0_h.I
+Odrv4.O Span4Mux_s0_v.I
+Odrv4.O Span4Mux_s1_h.I
+Odrv4.O Span4Mux_s1_v.I
+Odrv4.O Span4Mux_s2_h.I
+Odrv4.O Span4Mux_s2_v.I
+Odrv4.O Span4Mux_s3_h.I
+Odrv4.O Span4Mux_s3_v.I
+Odrv4.O Span4Mux_v.I
+PLL40.LOCK LocalMux.I
+PLL40.PLLOUTCORE LocalMux.I
+PLL40.PLLOUTCORE Odrv12.I
+PLL40.PLLOUTCORE Odrv4.I
+PLL40.PLLOUTGLOBAL GlobalMux.I
+PLL40.SDO LocalMux.I
+PLL40_2.LOCK LocalMux.I
+PLL40_2.PLLOUTCOREA LocalMux.I
+PLL40_2.PLLOUTCOREA Odrv12.I
+PLL40_2.PLLOUTCOREA Odrv4.I
+PLL40_2.PLLOUTCOREB LocalMux.I
+PLL40_2.PLLOUTCOREB Odrv12.I
+PLL40_2.PLLOUTCOREB Odrv4.I
+PLL40_2.PLLOUTGLOBALA GlobalMux.I
+PLL40_2.PLLOUTGLOBALB GlobalMux.I
+PLL40_2.SDO LocalMux.I
+PLL40_2F.LOCK LocalMux.I
+PLL40_2F.PLLOUTCOREA LocalMux.I
+PLL40_2F.PLLOUTCOREA Odrv12.I
+PLL40_2F.PLLOUTCOREA Odrv4.I
+PLL40_2F.PLLOUTCOREB LocalMux.I
+PLL40_2F.PLLOUTCOREB Odrv12.I
+PLL40_2F.PLLOUTCOREB Odrv4.I
+PLL40_2F.PLLOUTGLOBALA GlobalMux.I
+PLL40_2F.PLLOUTGLOBALB GlobalMux.I
+PLL40_2F.SDO LocalMux.I
+PRE_IO.DIN0 LocalMux.I
+PRE_IO.DIN0 Odrv12.I
+PRE_IO.DIN0 Odrv4.I
+PRE_IO.DIN1 LocalMux.I
+PRE_IO.DIN1 Odrv12.I
+PRE_IO.DIN1 Odrv4.I
+PRE_IO.PADOEN IO_PAD.OE
+PRE_IO.PADOUT IO_PAD.DIN
+PRE_IO_GBUF.GLOBALBUFFEROUTPUT gio2CtrlBuf.I
+SB_PLL40_2F_CORE.LOCK LocalMux.I
+SB_PLL40_2F_CORE.PLLOUTCOREA LocalMux.I
+SB_PLL40_2F_CORE.PLLOUTCOREA Odrv12.I
+SB_PLL40_2F_CORE.PLLOUTCOREA Odrv4.I
+SB_PLL40_2F_CORE.PLLOUTCOREB LocalMux.I
+SB_PLL40_2F_CORE.PLLOUTCOREB Odrv12.I
+SB_PLL40_2F_CORE.PLLOUTCOREB Odrv4.I
+SB_PLL40_2F_CORE.PLLOUTGLOBALA GlobalMux.I
+SB_PLL40_2F_CORE.PLLOUTGLOBALB GlobalMux.I
+SB_PLL40_2F_CORE.SDO LocalMux.I
+SB_PLL40_CORE.LOCK LocalMux.I
+SB_PLL40_CORE.PLLOUTCORE LocalMux.I
+SB_PLL40_CORE.PLLOUTCORE Odrv12.I
+SB_PLL40_CORE.PLLOUTCORE Odrv4.I
+SB_PLL40_CORE.PLLOUTGLOBAL GlobalMux.I
+SB_PLL40_CORE.SDO LocalMux.I
+SB_RAM40_4K.RDATA[0] LocalMux.I
+SB_RAM40_4K.RDATA[0] Odrv12.I
+SB_RAM40_4K.RDATA[0] Odrv4.I
+SB_RAM40_4K.RDATA[10] LocalMux.I
+SB_RAM40_4K.RDATA[10] Odrv12.I
+SB_RAM40_4K.RDATA[10] Odrv4.I
+SB_RAM40_4K.RDATA[11] LocalMux.I
+SB_RAM40_4K.RDATA[11] Odrv12.I
+SB_RAM40_4K.RDATA[11] Odrv4.I
+SB_RAM40_4K.RDATA[12] LocalMux.I
+SB_RAM40_4K.RDATA[12] Odrv12.I
+SB_RAM40_4K.RDATA[12] Odrv4.I
+SB_RAM40_4K.RDATA[13] LocalMux.I
+SB_RAM40_4K.RDATA[13] Odrv12.I
+SB_RAM40_4K.RDATA[13] Odrv4.I
+SB_RAM40_4K.RDATA[14] LocalMux.I
+SB_RAM40_4K.RDATA[14] Odrv12.I
+SB_RAM40_4K.RDATA[14] Odrv4.I
+SB_RAM40_4K.RDATA[15] LocalMux.I
+SB_RAM40_4K.RDATA[15] Odrv12.I
+SB_RAM40_4K.RDATA[15] Odrv4.I
+SB_RAM40_4K.RDATA[1] LocalMux.I
+SB_RAM40_4K.RDATA[1] Odrv12.I
+SB_RAM40_4K.RDATA[1] Odrv4.I
+SB_RAM40_4K.RDATA[2] LocalMux.I
+SB_RAM40_4K.RDATA[2] Odrv12.I
+SB_RAM40_4K.RDATA[2] Odrv4.I
+SB_RAM40_4K.RDATA[3] LocalMux.I
+SB_RAM40_4K.RDATA[3] Odrv12.I
+SB_RAM40_4K.RDATA[3] Odrv4.I
+SB_RAM40_4K.RDATA[4] LocalMux.I
+SB_RAM40_4K.RDATA[4] Odrv12.I
+SB_RAM40_4K.RDATA[4] Odrv4.I
+SB_RAM40_4K.RDATA[5] LocalMux.I
+SB_RAM40_4K.RDATA[5] Odrv12.I
+SB_RAM40_4K.RDATA[5] Odrv4.I
+SB_RAM40_4K.RDATA[6] LocalMux.I
+SB_RAM40_4K.RDATA[6] Odrv12.I
+SB_RAM40_4K.RDATA[6] Odrv4.I
+SB_RAM40_4K.RDATA[7] LocalMux.I
+SB_RAM40_4K.RDATA[7] Odrv12.I
+SB_RAM40_4K.RDATA[7] Odrv4.I
+SB_RAM40_4K.RDATA[8] LocalMux.I
+SB_RAM40_4K.RDATA[8] Odrv12.I
+SB_RAM40_4K.RDATA[8] Odrv4.I
+SB_RAM40_4K.RDATA[9] LocalMux.I
+SB_RAM40_4K.RDATA[9] Odrv12.I
+SB_RAM40_4K.RDATA[9] Odrv4.I
+SRMux.O LogicCell40.sr
+SRMux.O SB_RAM40_4K.RE
+SRMux.O SB_RAM40_4K.WE
+Sp12to4.O IoSpan4Mux.I
+Sp12to4.O LocalMux.I
+Sp12to4.O Span4Mux_h.I
+Sp12to4.O Span4Mux_s0_h.I
+Sp12to4.O Span4Mux_s0_v.I
+Sp12to4.O Span4Mux_s1_h.I
+Sp12to4.O Span4Mux_s1_v.I
+Sp12to4.O Span4Mux_s2_h.I
+Sp12to4.O Span4Mux_s2_v.I
+Sp12to4.O Span4Mux_s3_h.I
+Sp12to4.O Span4Mux_s3_v.I
+Sp12to4.O Span4Mux_v.I
+Span12Mux_s0_h.O LocalMux.I
+Span12Mux_s0_h.O Sp12to4.I
+Span12Mux_s0_h.O Span12Mux_s11_h.I
+Span12Mux_s0_h.O Span12Mux_s1_v.I
+Span12Mux_s0_v.O LocalMux.I
+Span12Mux_s0_v.O Sp12to4.I
+Span12Mux_s0_v.O Span12Mux_v.I
+Span12Mux_s10_h.O LocalMux.I
+Span12Mux_s10_h.O Sp12to4.I
+Span12Mux_s10_h.O Span12Mux_s2_v.I
+Span12Mux_s10_h.O Span12Mux_s5_v.I
+Span12Mux_s10_h.O Span12Mux_v.I
+Span12Mux_s10_v.O LocalMux.I
+Span12Mux_s10_v.O Sp12to4.I
+Span12Mux_s10_v.O Span12Mux_s10_h.I
+Span12Mux_s10_v.O Span12Mux_s5_v.I
+Span12Mux_s10_v.O Span12Mux_s8_h.I
+Span12Mux_s11_h.O LocalMux.I
+Span12Mux_s11_h.O Sp12to4.I
+Span12Mux_s11_h.O Span12Mux_s0_h.I
+Span12Mux_s11_v.O LocalMux.I
+Span12Mux_s11_v.O Sp12to4.I
+Span12Mux_s11_v.O Span12Mux_s4_v.I
+Span12Mux_s11_v.O Span12Mux_s8_h.I
+Span12Mux_s11_v.O Span12Mux_s9_h.I
+Span12Mux_s1_h.O LocalMux.I
+Span12Mux_s1_h.O Sp12to4.I
+Span12Mux_s1_h.O Span12Mux_s10_h.I
+Span12Mux_s1_v.O LocalMux.I
+Span12Mux_s1_v.O Sp12to4.I
+Span12Mux_s1_v.O Span12Mux_v.I
+Span12Mux_s2_h.O LocalMux.I
+Span12Mux_s2_h.O Sp12to4.I
+Span12Mux_s2_h.O Span12Mux_s0_v.I
+Span12Mux_s2_h.O Span12Mux_s10_v.I
+Span12Mux_s2_h.O Span12Mux_s11_v.I
+Span12Mux_s2_h.O Span12Mux_s1_v.I
+Span12Mux_s2_h.O Span12Mux_s2_v.I
+Span12Mux_s2_h.O Span12Mux_s4_v.I
+Span12Mux_s2_h.O Span12Mux_s6_v.I
+Span12Mux_s2_h.O Span12Mux_s8_v.I
+Span12Mux_s2_h.O Span12Mux_s9_h.I
+Span12Mux_s2_h.O Span12Mux_s9_v.I
+Span12Mux_s2_v.O LocalMux.I
+Span12Mux_s2_v.O Sp12to4.I
+Span12Mux_s2_v.O Span12Mux_s9_h.I
+Span12Mux_s3_h.O LocalMux.I
+Span12Mux_s3_h.O Sp12to4.I
+Span12Mux_s3_h.O Span12Mux_s10_v.I
+Span12Mux_s3_h.O Span12Mux_s11_v.I
+Span12Mux_s3_h.O Span12Mux_s1_v.I
+Span12Mux_s3_h.O Span12Mux_s2_v.I
+Span12Mux_s3_h.O Span12Mux_s4_v.I
+Span12Mux_s3_h.O Span12Mux_s6_v.I
+Span12Mux_s3_h.O Span12Mux_s7_v.I
+Span12Mux_s3_h.O Span12Mux_s8_h.I
+Span12Mux_s3_h.O Span12Mux_s8_v.I
+Span12Mux_s3_h.O Span12Mux_s9_v.I
+Span12Mux_s3_h.O Span12Mux_v.I
+Span12Mux_s3_v.O LocalMux.I
+Span12Mux_s3_v.O Sp12to4.I
+Span12Mux_s3_v.O Span12Mux_s8_h.I
+Span12Mux_s3_v.O Span12Mux_v.I
+Span12Mux_s4_h.O LocalMux.I
+Span12Mux_s4_h.O Sp12to4.I
+Span12Mux_s4_h.O Span12Mux_s2_v.I
+Span12Mux_s4_h.O Span12Mux_s3_v.I
+Span12Mux_s4_h.O Span12Mux_s4_v.I
+Span12Mux_s4_h.O Span12Mux_s6_v.I
+Span12Mux_s4_h.O Span12Mux_s7_h.I
+Span12Mux_s4_h.O Span12Mux_s7_v.I
+Span12Mux_s4_h.O Span12Mux_s8_v.I
+Span12Mux_s4_v.O LocalMux.I
+Span12Mux_s4_v.O Sp12to4.I
+Span12Mux_s4_v.O Span12Mux_s10_h.I
+Span12Mux_s4_v.O Span12Mux_s11_v.I
+Span12Mux_s4_v.O Span12Mux_s2_h.I
+Span12Mux_s4_v.O Span12Mux_s8_h.I
+Span12Mux_s5_h.O LocalMux.I
+Span12Mux_s5_h.O Sp12to4.I
+Span12Mux_s5_h.O Span12Mux_s10_v.I
+Span12Mux_s5_h.O Span12Mux_s11_v.I
+Span12Mux_s5_h.O Span12Mux_s6_h.I
+Span12Mux_s5_h.O Span12Mux_s7_v.I
+Span12Mux_s5_h.O Span12Mux_s8_v.I
+Span12Mux_s5_h.O Span12Mux_s9_v.I
+Span12Mux_s5_h.O Span12Mux_v.I
+Span12Mux_s5_v.O LocalMux.I
+Span12Mux_s5_v.O Sp12to4.I
+Span12Mux_s5_v.O Span12Mux_s10_h.I
+Span12Mux_s5_v.O Span12Mux_s10_v.I
+Span12Mux_s5_v.O Span12Mux_s5_h.I
+Span12Mux_s5_v.O Span12Mux_s8_h.I
+Span12Mux_s6_h.O LocalMux.I
+Span12Mux_s6_h.O Sp12to4.I
+Span12Mux_s6_h.O Span12Mux_s0_v.I
+Span12Mux_s6_h.O Span12Mux_s11_v.I
+Span12Mux_s6_h.O Span12Mux_s3_v.I
+Span12Mux_s6_h.O Span12Mux_s5_h.I
+Span12Mux_s6_h.O Span12Mux_s5_v.I
+Span12Mux_s6_h.O Span12Mux_s7_v.I
+Span12Mux_s6_h.O Span12Mux_s8_v.I
+Span12Mux_s6_h.O Span12Mux_s9_v.I
+Span12Mux_s6_h.O Span12Mux_v.I
+Span12Mux_s6_v.O LocalMux.I
+Span12Mux_s6_v.O Sp12to4.I
+Span12Mux_s6_v.O Span12Mux_s5_h.I
+Span12Mux_s6_v.O Span12Mux_s8_h.I
+Span12Mux_s6_v.O Span12Mux_s9_v.I
+Span12Mux_s7_h.O LocalMux.I
+Span12Mux_s7_h.O Sp12to4.I
+Span12Mux_s7_h.O Span12Mux_s10_v.I
+Span12Mux_s7_h.O Span12Mux_s1_v.I
+Span12Mux_s7_h.O Span12Mux_s4_h.I
+Span12Mux_s7_h.O Span12Mux_s8_v.I
+Span12Mux_s7_h.O Span12Mux_s9_v.I
+Span12Mux_s7_h.O Span12Mux_v.I
+Span12Mux_s7_v.O LocalMux.I
+Span12Mux_s7_v.O Sp12to4.I
+Span12Mux_s7_v.O Span12Mux_s10_h.I
+Span12Mux_s7_v.O Span12Mux_s11_h.I
+Span12Mux_s7_v.O Span12Mux_s6_h.I
+Span12Mux_s7_v.O Span12Mux_s7_h.I
+Span12Mux_s7_v.O Span12Mux_s8_h.I
+Span12Mux_s7_v.O Span12Mux_s8_v.I
+Span12Mux_s8_h.O LocalMux.I
+Span12Mux_s8_h.O Sp12to4.I
+Span12Mux_s8_h.O Span12Mux_s10_v.I
+Span12Mux_s8_h.O Span12Mux_s11_v.I
+Span12Mux_s8_h.O Span12Mux_s2_v.I
+Span12Mux_s8_h.O Span12Mux_s3_h.I
+Span12Mux_s8_h.O Span12Mux_s3_v.I
+Span12Mux_s8_h.O Span12Mux_s4_v.I
+Span12Mux_s8_h.O Span12Mux_s6_v.I
+Span12Mux_s8_h.O Span12Mux_s7_v.I
+Span12Mux_s8_h.O Span12Mux_s8_v.I
+Span12Mux_s8_h.O Span12Mux_s9_v.I
+Span12Mux_s8_h.O Span12Mux_v.I
+Span12Mux_s8_v.O LocalMux.I
+Span12Mux_s8_v.O Sp12to4.I
+Span12Mux_s8_v.O Span12Mux_s10_h.I
+Span12Mux_s8_v.O Span12Mux_s2_h.I
+Span12Mux_s8_v.O Span12Mux_s7_v.I
+Span12Mux_s8_v.O Span12Mux_s8_h.I
+Span12Mux_s9_h.O LocalMux.I
+Span12Mux_s9_h.O Sp12to4.I
+Span12Mux_s9_h.O Span12Mux_s0_v.I
+Span12Mux_s9_h.O Span12Mux_s10_v.I
+Span12Mux_s9_h.O Span12Mux_s1_v.I
+Span12Mux_s9_h.O Span12Mux_s2_h.I
+Span12Mux_s9_h.O Span12Mux_s2_v.I
+Span12Mux_s9_h.O Span12Mux_s4_v.I
+Span12Mux_s9_h.O Span12Mux_v.I
+Span12Mux_s9_v.O LocalMux.I
+Span12Mux_s9_v.O Sp12to4.I
+Span12Mux_s9_v.O Span12Mux_s6_v.I
+Span12Mux_s9_v.O Span12Mux_s7_h.I
+Span12Mux_v.O LocalMux.I
+Span12Mux_v.O Sp12to4.I
+Span12Mux_v.O Span12Mux_s0_h.I
+Span12Mux_v.O Span12Mux_s0_v.I
+Span12Mux_v.O Span12Mux_s10_h.I
+Span12Mux_v.O Span12Mux_s11_h.I
+Span12Mux_v.O Span12Mux_s1_h.I
+Span12Mux_v.O Span12Mux_s1_v.I
+Span12Mux_v.O Span12Mux_s2_h.I
+Span12Mux_v.O Span12Mux_s2_v.I
+Span12Mux_v.O Span12Mux_s3_h.I
+Span12Mux_v.O Span12Mux_s3_v.I
+Span12Mux_v.O Span12Mux_s4_h.I
+Span12Mux_v.O Span12Mux_s5_h.I
+Span12Mux_v.O Span12Mux_s6_h.I
+Span12Mux_v.O Span12Mux_s7_h.I
+Span12Mux_v.O Span12Mux_s8_h.I
+Span12Mux_v.O Span12Mux_s9_h.I
+Span4Mux_h.O LocalMux.I
+Span4Mux_h.O Span4Mux_h.I
+Span4Mux_h.O Span4Mux_s0_h.I
+Span4Mux_h.O Span4Mux_s0_v.I
+Span4Mux_h.O Span4Mux_s1_h.I
+Span4Mux_h.O Span4Mux_s1_v.I
+Span4Mux_h.O Span4Mux_s2_h.I
+Span4Mux_h.O Span4Mux_s2_v.I
+Span4Mux_h.O Span4Mux_s3_h.I
+Span4Mux_h.O Span4Mux_s3_v.I
+Span4Mux_h.O Span4Mux_v.I
+Span4Mux_s0_h.O IoSpan4Mux.I
+Span4Mux_s0_h.O LocalMux.I
+Span4Mux_s0_h.O Span4Mux_h.I
+Span4Mux_s0_h.O Span4Mux_s0_v.I
+Span4Mux_s0_h.O Span4Mux_s1_v.I
+Span4Mux_s0_h.O Span4Mux_s2_v.I
+Span4Mux_s0_h.O Span4Mux_s3_v.I
+Span4Mux_s0_h.O Span4Mux_v.I
+Span4Mux_s0_v.O IoSpan4Mux.I
+Span4Mux_s0_v.O LocalMux.I
+Span4Mux_s0_v.O Span4Mux_h.I
+Span4Mux_s0_v.O Span4Mux_s0_h.I
+Span4Mux_s0_v.O Span4Mux_s1_h.I
+Span4Mux_s0_v.O Span4Mux_s2_h.I
+Span4Mux_s0_v.O Span4Mux_s3_h.I
+Span4Mux_s0_v.O Span4Mux_v.I
+Span4Mux_s1_h.O IoSpan4Mux.I
+Span4Mux_s1_h.O LocalMux.I
+Span4Mux_s1_h.O Span4Mux_h.I
+Span4Mux_s1_h.O Span4Mux_s0_v.I
+Span4Mux_s1_h.O Span4Mux_s1_v.I
+Span4Mux_s1_h.O Span4Mux_s2_v.I
+Span4Mux_s1_h.O Span4Mux_s3_v.I
+Span4Mux_s1_h.O Span4Mux_v.I
+Span4Mux_s1_v.O IoSpan4Mux.I
+Span4Mux_s1_v.O LocalMux.I
+Span4Mux_s1_v.O Span4Mux_h.I
+Span4Mux_s1_v.O Span4Mux_s0_h.I
+Span4Mux_s1_v.O Span4Mux_s1_h.I
+Span4Mux_s1_v.O Span4Mux_s2_h.I
+Span4Mux_s1_v.O Span4Mux_s3_h.I
+Span4Mux_s1_v.O Span4Mux_v.I
+Span4Mux_s2_h.O IoSpan4Mux.I
+Span4Mux_s2_h.O LocalMux.I
+Span4Mux_s2_h.O Span4Mux_h.I
+Span4Mux_s2_h.O Span4Mux_s0_v.I
+Span4Mux_s2_h.O Span4Mux_s1_v.I
+Span4Mux_s2_h.O Span4Mux_s2_v.I
+Span4Mux_s2_h.O Span4Mux_s3_v.I
+Span4Mux_s2_h.O Span4Mux_v.I
+Span4Mux_s2_v.O IoSpan4Mux.I
+Span4Mux_s2_v.O LocalMux.I
+Span4Mux_s2_v.O Span4Mux_h.I
+Span4Mux_s2_v.O Span4Mux_s0_h.I
+Span4Mux_s2_v.O Span4Mux_s1_h.I
+Span4Mux_s2_v.O Span4Mux_s2_h.I
+Span4Mux_s2_v.O Span4Mux_s3_h.I
+Span4Mux_s2_v.O Span4Mux_v.I
+Span4Mux_s3_h.O IoSpan4Mux.I
+Span4Mux_s3_h.O LocalMux.I
+Span4Mux_s3_h.O Span4Mux_h.I
+Span4Mux_s3_h.O Span4Mux_s0_v.I
+Span4Mux_s3_h.O Span4Mux_s1_v.I
+Span4Mux_s3_h.O Span4Mux_s2_v.I
+Span4Mux_s3_h.O Span4Mux_s3_v.I
+Span4Mux_s3_h.O Span4Mux_v.I
+Span4Mux_s3_v.O IoSpan4Mux.I
+Span4Mux_s3_v.O LocalMux.I
+Span4Mux_s3_v.O Span4Mux_h.I
+Span4Mux_s3_v.O Span4Mux_s0_h.I
+Span4Mux_s3_v.O Span4Mux_s1_h.I
+Span4Mux_s3_v.O Span4Mux_s2_h.I
+Span4Mux_s3_v.O Span4Mux_s3_h.I
+Span4Mux_s3_v.O Span4Mux_v.I
+Span4Mux_v.O LocalMux.I
+Span4Mux_v.O Span4Mux_h.I
+Span4Mux_v.O Span4Mux_s0_h.I
+Span4Mux_v.O Span4Mux_s0_v.I
+Span4Mux_v.O Span4Mux_s1_h.I
+Span4Mux_v.O Span4Mux_s1_v.I
+Span4Mux_v.O Span4Mux_s2_h.I
+Span4Mux_v.O Span4Mux_s2_v.I
+Span4Mux_v.O Span4Mux_s3_h.I
+Span4Mux_v.O Span4Mux_s3_v.I
+Span4Mux_v.O Span4Mux_v.I
+VCC.Y IO_PAD.OE
+VCC.Y PRE_IO.CLOCKENABLE
+gio2CtrlBuf.O GlobalMux.I
diff --git a/icefuzz/tmedges_8k.txt b/icefuzz/tmedges_8k.txt
new file mode 100644
index 0000000..076886c
--- /dev/null
+++ b/icefuzz/tmedges_8k.txt
@@ -0,0 +1,618 @@
+CEMux.O LogicCell40.ce
+CEMux.O PRE_IO.CLOCKENABLE
+CEMux.O SB_RAM40_4K.RCLKE
+CEMux.O SB_RAM40_4K.WCLKE
+CascadeMux.O LogicCell40.in2
+CascadeMux.O SB_RAM40_4K.RADDR[0]
+CascadeMux.O SB_RAM40_4K.RADDR[10]
+CascadeMux.O SB_RAM40_4K.RADDR[1]
+CascadeMux.O SB_RAM40_4K.RADDR[2]
+CascadeMux.O SB_RAM40_4K.RADDR[3]
+CascadeMux.O SB_RAM40_4K.RADDR[4]
+CascadeMux.O SB_RAM40_4K.RADDR[5]
+CascadeMux.O SB_RAM40_4K.RADDR[6]
+CascadeMux.O SB_RAM40_4K.RADDR[7]
+CascadeMux.O SB_RAM40_4K.RADDR[8]
+CascadeMux.O SB_RAM40_4K.RADDR[9]
+CascadeMux.O SB_RAM40_4K.WADDR[0]
+CascadeMux.O SB_RAM40_4K.WADDR[10]
+CascadeMux.O SB_RAM40_4K.WADDR[1]
+CascadeMux.O SB_RAM40_4K.WADDR[2]
+CascadeMux.O SB_RAM40_4K.WADDR[3]
+CascadeMux.O SB_RAM40_4K.WADDR[4]
+CascadeMux.O SB_RAM40_4K.WADDR[5]
+CascadeMux.O SB_RAM40_4K.WADDR[6]
+CascadeMux.O SB_RAM40_4K.WADDR[7]
+CascadeMux.O SB_RAM40_4K.WADDR[8]
+CascadeMux.O SB_RAM40_4K.WADDR[9]
+ClkMux.O INV.I
+ClkMux.O LogicCell40.clk
+ClkMux.O PRE_IO.INPUTCLK
+ClkMux.O PRE_IO.OUTPUTCLK
+ClkMux.O SB_RAM40_4K.RCLK
+ClkMux.O SB_RAM40_4K.WCLK
+GND.Y LogicCell40.carryin
+GND.Y LogicCell40.clk
+GND.Y LogicCell40.in0
+GND.Y LogicCell40.in1
+GND.Y LogicCell40.in2
+GND.Y LogicCell40.in3
+GND.Y LogicCell40.sr
+GND.Y PRE_IO.DOUT0
+Glb2LocalMux.O LocalMux.I
+GlobalMux.O CEMux.I
+GlobalMux.O ClkMux.I
+GlobalMux.O Glb2LocalMux.I
+GlobalMux.O SRMux.I
+ICE_CARRY_IN_MUX.carryinitout InMux.I
+ICE_CARRY_IN_MUX.carryinitout LogicCell40.carryin
+ICE_GB.GLOBALBUFFEROUTPUT gio2CtrlBuf.I
+INV.O LogicCell40.clk
+INV.O SB_RAM40_4K.RCLK
+INV.O SB_RAM40_4K.WCLK
+IO_PAD.DOUT PLL40.PLLIN
+IO_PAD.DOUT PLL40_2.PLLIN
+IO_PAD.DOUT PLL40_2F.PLLIN
+IO_PAD.DOUT PRE_IO.PADIN
+IO_PAD.DOUT PRE_IO_GBUF.PADSIGNALTOGLOBALBUFFER
+IO_PAD.PACKAGEPIN IO_PAD.PACKAGEPIN
+InMux.O CascadeMux.I
+InMux.O LogicCell40.in0
+InMux.O LogicCell40.in1
+InMux.O LogicCell40.in3
+InMux.O SB_RAM40_4K.MASK[0]
+InMux.O SB_RAM40_4K.MASK[10]
+InMux.O SB_RAM40_4K.MASK[11]
+InMux.O SB_RAM40_4K.MASK[12]
+InMux.O SB_RAM40_4K.MASK[13]
+InMux.O SB_RAM40_4K.MASK[14]
+InMux.O SB_RAM40_4K.MASK[15]
+InMux.O SB_RAM40_4K.MASK[1]
+InMux.O SB_RAM40_4K.MASK[2]
+InMux.O SB_RAM40_4K.MASK[3]
+InMux.O SB_RAM40_4K.MASK[4]
+InMux.O SB_RAM40_4K.MASK[5]
+InMux.O SB_RAM40_4K.MASK[6]
+InMux.O SB_RAM40_4K.MASK[7]
+InMux.O SB_RAM40_4K.MASK[8]
+InMux.O SB_RAM40_4K.MASK[9]
+InMux.O SB_RAM40_4K.WDATA[0]
+InMux.O SB_RAM40_4K.WDATA[10]
+InMux.O SB_RAM40_4K.WDATA[11]
+InMux.O SB_RAM40_4K.WDATA[12]
+InMux.O SB_RAM40_4K.WDATA[13]
+InMux.O SB_RAM40_4K.WDATA[14]
+InMux.O SB_RAM40_4K.WDATA[15]
+InMux.O SB_RAM40_4K.WDATA[1]
+InMux.O SB_RAM40_4K.WDATA[2]
+InMux.O SB_RAM40_4K.WDATA[3]
+InMux.O SB_RAM40_4K.WDATA[4]
+InMux.O SB_RAM40_4K.WDATA[5]
+InMux.O SB_RAM40_4K.WDATA[6]
+InMux.O SB_RAM40_4K.WDATA[7]
+InMux.O SB_RAM40_4K.WDATA[8]
+InMux.O SB_RAM40_4K.WDATA[9]
+IoInMux.O ICE_GB.USERSIGNALTOGLOBALBUFFER
+IoInMux.O PLL40.BYPASS
+IoInMux.O PLL40.DYNAMICDELAY[0]
+IoInMux.O PLL40.DYNAMICDELAY[1]
+IoInMux.O PLL40.DYNAMICDELAY[2]
+IoInMux.O PLL40.DYNAMICDELAY[3]
+IoInMux.O PLL40.DYNAMICDELAY[4]
+IoInMux.O PLL40.DYNAMICDELAY[5]
+IoInMux.O PLL40.DYNAMICDELAY[6]
+IoInMux.O PLL40.DYNAMICDELAY[7]
+IoInMux.O PLL40.EXTFEEDBACK
+IoInMux.O PLL40.LATCHINPUTVALUE
+IoInMux.O PLL40.RESETB
+IoInMux.O PLL40.SCLK
+IoInMux.O PLL40.SDI
+IoInMux.O PLL40_2.BYPASS
+IoInMux.O PLL40_2.DYNAMICDELAY[0]
+IoInMux.O PLL40_2.DYNAMICDELAY[1]
+IoInMux.O PLL40_2.DYNAMICDELAY[2]
+IoInMux.O PLL40_2.DYNAMICDELAY[3]
+IoInMux.O PLL40_2.DYNAMICDELAY[4]
+IoInMux.O PLL40_2.DYNAMICDELAY[5]
+IoInMux.O PLL40_2.DYNAMICDELAY[6]
+IoInMux.O PLL40_2.DYNAMICDELAY[7]
+IoInMux.O PLL40_2.EXTFEEDBACK
+IoInMux.O PLL40_2.LATCHINPUTVALUE
+IoInMux.O PLL40_2.RESETB
+IoInMux.O PLL40_2.SCLK
+IoInMux.O PLL40_2.SDI
+IoInMux.O PLL40_2F.BYPASS
+IoInMux.O PLL40_2F.DYNAMICDELAY[0]
+IoInMux.O PLL40_2F.DYNAMICDELAY[1]
+IoInMux.O PLL40_2F.DYNAMICDELAY[2]
+IoInMux.O PLL40_2F.DYNAMICDELAY[3]
+IoInMux.O PLL40_2F.DYNAMICDELAY[4]
+IoInMux.O PLL40_2F.DYNAMICDELAY[5]
+IoInMux.O PLL40_2F.DYNAMICDELAY[6]
+IoInMux.O PLL40_2F.DYNAMICDELAY[7]
+IoInMux.O PLL40_2F.EXTFEEDBACK
+IoInMux.O PLL40_2F.LATCHINPUTVALUE
+IoInMux.O PLL40_2F.RESETB
+IoInMux.O PLL40_2F.SCLK
+IoInMux.O PLL40_2F.SDI
+IoInMux.O PRE_IO.DOUT0
+IoInMux.O PRE_IO.DOUT1
+IoInMux.O PRE_IO.LATCHINPUTVALUE
+IoInMux.O PRE_IO.OUTPUTENABLE
+IoInMux.O SB_PLL40_2F_CORE.BYPASS
+IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[0]
+IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[1]
+IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[2]
+IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[3]
+IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[4]
+IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[5]
+IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[6]
+IoInMux.O SB_PLL40_2F_CORE.DYNAMICDELAY[7]
+IoInMux.O SB_PLL40_2F_CORE.EXTFEEDBACK
+IoInMux.O SB_PLL40_2F_CORE.LATCHINPUTVALUE
+IoInMux.O SB_PLL40_2F_CORE.REFERENCECLK
+IoInMux.O SB_PLL40_2F_CORE.RESETB
+IoInMux.O SB_PLL40_2F_CORE.SCLK
+IoInMux.O SB_PLL40_2F_CORE.SDI
+IoInMux.O SB_PLL40_CORE.BYPASS
+IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[0]
+IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[1]
+IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[2]
+IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[3]
+IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[4]
+IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[5]
+IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[6]
+IoInMux.O SB_PLL40_CORE.DYNAMICDELAY[7]
+IoInMux.O SB_PLL40_CORE.EXTFEEDBACK
+IoInMux.O SB_PLL40_CORE.LATCHINPUTVALUE
+IoInMux.O SB_PLL40_CORE.REFERENCECLK
+IoInMux.O SB_PLL40_CORE.RESETB
+IoInMux.O SB_PLL40_CORE.SCLK
+IoInMux.O SB_PLL40_CORE.SDI
+IoSpan4Mux.O IoSpan4Mux.I
+IoSpan4Mux.O LocalMux.I
+IoSpan4Mux.O Span4Mux_h.I
+IoSpan4Mux.O Span4Mux_s0_h.I
+IoSpan4Mux.O Span4Mux_s0_v.I
+IoSpan4Mux.O Span4Mux_s1_h.I
+IoSpan4Mux.O Span4Mux_s1_v.I
+IoSpan4Mux.O Span4Mux_s2_h.I
+IoSpan4Mux.O Span4Mux_s2_v.I
+IoSpan4Mux.O Span4Mux_s3_h.I
+IoSpan4Mux.O Span4Mux_s3_v.I
+IoSpan4Mux.O Span4Mux_v.I
+LocalMux.O CEMux.I
+LocalMux.O ClkMux.I
+LocalMux.O InMux.I
+LocalMux.O IoInMux.I
+LocalMux.O SRMux.I
+LogicCell40.carryout ICE_CARRY_IN_MUX.carryinitin
+LogicCell40.carryout InMux.I
+LogicCell40.carryout LogicCell40.carryin
+LogicCell40.lcout LocalMux.I
+LogicCell40.lcout Odrv12.I
+LogicCell40.lcout Odrv4.I
+LogicCell40.ltout CascadeMux.I
+Odrv12.O LocalMux.I
+Odrv12.O Sp12to4.I
+Odrv12.O Span12Mux_h.I
+Odrv12.O Span12Mux_s0_h.I
+Odrv12.O Span12Mux_s0_v.I
+Odrv12.O Span12Mux_s10_h.I
+Odrv12.O Span12Mux_s10_v.I
+Odrv12.O Span12Mux_s11_h.I
+Odrv12.O Span12Mux_s11_v.I
+Odrv12.O Span12Mux_s1_h.I
+Odrv12.O Span12Mux_s1_v.I
+Odrv12.O Span12Mux_s2_h.I
+Odrv12.O Span12Mux_s2_v.I
+Odrv12.O Span12Mux_s3_h.I
+Odrv12.O Span12Mux_s3_v.I
+Odrv12.O Span12Mux_s4_h.I
+Odrv12.O Span12Mux_s4_v.I
+Odrv12.O Span12Mux_s5_h.I
+Odrv12.O Span12Mux_s5_v.I
+Odrv12.O Span12Mux_s6_h.I
+Odrv12.O Span12Mux_s6_v.I
+Odrv12.O Span12Mux_s7_h.I
+Odrv12.O Span12Mux_s7_v.I
+Odrv12.O Span12Mux_s8_h.I
+Odrv12.O Span12Mux_s8_v.I
+Odrv12.O Span12Mux_s9_h.I
+Odrv12.O Span12Mux_s9_v.I
+Odrv12.O Span12Mux_v.I
+Odrv4.O IoSpan4Mux.I
+Odrv4.O LocalMux.I
+Odrv4.O Span4Mux_h.I
+Odrv4.O Span4Mux_s0_h.I
+Odrv4.O Span4Mux_s0_v.I
+Odrv4.O Span4Mux_s1_h.I
+Odrv4.O Span4Mux_s1_v.I
+Odrv4.O Span4Mux_s2_h.I
+Odrv4.O Span4Mux_s2_v.I
+Odrv4.O Span4Mux_s3_h.I
+Odrv4.O Span4Mux_s3_v.I
+Odrv4.O Span4Mux_v.I
+PLL40.LOCK LocalMux.I
+PLL40.PLLOUTCORE Odrv12.I
+PLL40.PLLOUTGLOBAL GlobalMux.I
+PLL40.SDO LocalMux.I
+PLL40_2.LOCK LocalMux.I
+PLL40_2.PLLOUTCOREA Odrv12.I
+PLL40_2.PLLOUTCOREB Odrv12.I
+PLL40_2.PLLOUTGLOBALA GlobalMux.I
+PLL40_2.PLLOUTGLOBALB GlobalMux.I
+PLL40_2.SDO LocalMux.I
+PLL40_2F.LOCK LocalMux.I
+PLL40_2F.PLLOUTCOREA Odrv12.I
+PLL40_2F.PLLOUTCOREB Odrv12.I
+PLL40_2F.PLLOUTGLOBALA GlobalMux.I
+PLL40_2F.PLLOUTGLOBALB GlobalMux.I
+PLL40_2F.SDO LocalMux.I
+PRE_IO.DIN0 LocalMux.I
+PRE_IO.DIN0 Odrv12.I
+PRE_IO.DIN0 Odrv4.I
+PRE_IO.DIN1 LocalMux.I
+PRE_IO.DIN1 Odrv12.I
+PRE_IO.DIN1 Odrv4.I
+PRE_IO.PADOEN IO_PAD.OE
+PRE_IO.PADOUT IO_PAD.DIN
+PRE_IO_GBUF.GLOBALBUFFEROUTPUT gio2CtrlBuf.I
+SB_PLL40_2F_CORE.LOCK LocalMux.I
+SB_PLL40_2F_CORE.PLLOUTCOREA Odrv12.I
+SB_PLL40_2F_CORE.PLLOUTCOREB Odrv12.I
+SB_PLL40_2F_CORE.PLLOUTGLOBALA GlobalMux.I
+SB_PLL40_2F_CORE.PLLOUTGLOBALB GlobalMux.I
+SB_PLL40_2F_CORE.SDO LocalMux.I
+SB_PLL40_CORE.LOCK LocalMux.I
+SB_PLL40_CORE.PLLOUTCORE Odrv12.I
+SB_PLL40_CORE.PLLOUTGLOBAL GlobalMux.I
+SB_PLL40_CORE.SDO LocalMux.I
+SB_RAM40_4K.RDATA[0] LocalMux.I
+SB_RAM40_4K.RDATA[0] Odrv12.I
+SB_RAM40_4K.RDATA[0] Odrv4.I
+SB_RAM40_4K.RDATA[10] LocalMux.I
+SB_RAM40_4K.RDATA[10] Odrv12.I
+SB_RAM40_4K.RDATA[10] Odrv4.I
+SB_RAM40_4K.RDATA[11] LocalMux.I
+SB_RAM40_4K.RDATA[11] Odrv12.I
+SB_RAM40_4K.RDATA[11] Odrv4.I
+SB_RAM40_4K.RDATA[12] LocalMux.I
+SB_RAM40_4K.RDATA[12] Odrv12.I
+SB_RAM40_4K.RDATA[12] Odrv4.I
+SB_RAM40_4K.RDATA[13] LocalMux.I
+SB_RAM40_4K.RDATA[13] Odrv12.I
+SB_RAM40_4K.RDATA[13] Odrv4.I
+SB_RAM40_4K.RDATA[14] LocalMux.I
+SB_RAM40_4K.RDATA[14] Odrv12.I
+SB_RAM40_4K.RDATA[14] Odrv4.I
+SB_RAM40_4K.RDATA[15] LocalMux.I
+SB_RAM40_4K.RDATA[15] Odrv12.I
+SB_RAM40_4K.RDATA[15] Odrv4.I
+SB_RAM40_4K.RDATA[1] LocalMux.I
+SB_RAM40_4K.RDATA[1] Odrv12.I
+SB_RAM40_4K.RDATA[1] Odrv4.I
+SB_RAM40_4K.RDATA[2] LocalMux.I
+SB_RAM40_4K.RDATA[2] Odrv12.I
+SB_RAM40_4K.RDATA[2] Odrv4.I
+SB_RAM40_4K.RDATA[3] LocalMux.I
+SB_RAM40_4K.RDATA[3] Odrv12.I
+SB_RAM40_4K.RDATA[3] Odrv4.I
+SB_RAM40_4K.RDATA[4] LocalMux.I
+SB_RAM40_4K.RDATA[4] Odrv12.I
+SB_RAM40_4K.RDATA[4] Odrv4.I
+SB_RAM40_4K.RDATA[5] LocalMux.I
+SB_RAM40_4K.RDATA[5] Odrv12.I
+SB_RAM40_4K.RDATA[5] Odrv4.I
+SB_RAM40_4K.RDATA[6] LocalMux.I
+SB_RAM40_4K.RDATA[6] Odrv12.I
+SB_RAM40_4K.RDATA[6] Odrv4.I
+SB_RAM40_4K.RDATA[7] LocalMux.I
+SB_RAM40_4K.RDATA[7] Odrv12.I
+SB_RAM40_4K.RDATA[7] Odrv4.I
+SB_RAM40_4K.RDATA[8] LocalMux.I
+SB_RAM40_4K.RDATA[8] Odrv12.I
+SB_RAM40_4K.RDATA[8] Odrv4.I
+SB_RAM40_4K.RDATA[9] LocalMux.I
+SB_RAM40_4K.RDATA[9] Odrv12.I
+SB_RAM40_4K.RDATA[9] Odrv4.I
+SRMux.O LogicCell40.sr
+SRMux.O SB_RAM40_4K.RE
+SRMux.O SB_RAM40_4K.WE
+Sp12to4.O IoSpan4Mux.I
+Sp12to4.O LocalMux.I
+Sp12to4.O Span4Mux_h.I
+Sp12to4.O Span4Mux_s0_h.I
+Sp12to4.O Span4Mux_s0_v.I
+Sp12to4.O Span4Mux_s1_h.I
+Sp12to4.O Span4Mux_s1_v.I
+Sp12to4.O Span4Mux_s2_h.I
+Sp12to4.O Span4Mux_s2_v.I
+Sp12to4.O Span4Mux_s3_h.I
+Sp12to4.O Span4Mux_s3_v.I
+Sp12to4.O Span4Mux_v.I
+Span12Mux_h.O LocalMux.I
+Span12Mux_h.O Sp12to4.I
+Span12Mux_h.O Span12Mux_h.I
+Span12Mux_h.O Span12Mux_s0_h.I
+Span12Mux_h.O Span12Mux_s0_v.I
+Span12Mux_h.O Span12Mux_s10_h.I
+Span12Mux_h.O Span12Mux_s10_v.I
+Span12Mux_h.O Span12Mux_s11_h.I
+Span12Mux_h.O Span12Mux_s11_v.I
+Span12Mux_h.O Span12Mux_s1_h.I
+Span12Mux_h.O Span12Mux_s1_v.I
+Span12Mux_h.O Span12Mux_s2_h.I
+Span12Mux_h.O Span12Mux_s2_v.I
+Span12Mux_h.O Span12Mux_s3_h.I
+Span12Mux_h.O Span12Mux_s3_v.I
+Span12Mux_h.O Span12Mux_s4_h.I
+Span12Mux_h.O Span12Mux_s4_v.I
+Span12Mux_h.O Span12Mux_s5_h.I
+Span12Mux_h.O Span12Mux_s5_v.I
+Span12Mux_h.O Span12Mux_s6_h.I
+Span12Mux_h.O Span12Mux_s6_v.I
+Span12Mux_h.O Span12Mux_s7_h.I
+Span12Mux_h.O Span12Mux_s7_v.I
+Span12Mux_h.O Span12Mux_s8_h.I
+Span12Mux_h.O Span12Mux_s8_v.I
+Span12Mux_h.O Span12Mux_s9_h.I
+Span12Mux_h.O Span12Mux_s9_v.I
+Span12Mux_h.O Span12Mux_v.I
+Span12Mux_s0_h.O LocalMux.I
+Span12Mux_s0_h.O Sp12to4.I
+Span12Mux_s0_h.O Span12Mux_h.I
+Span12Mux_s0_h.O Span12Mux_v.I
+Span12Mux_s0_v.O LocalMux.I
+Span12Mux_s0_v.O Sp12to4.I
+Span12Mux_s0_v.O Span12Mux_h.I
+Span12Mux_s0_v.O Span12Mux_v.I
+Span12Mux_s10_h.O LocalMux.I
+Span12Mux_s10_h.O Sp12to4.I
+Span12Mux_s10_h.O Span12Mux_h.I
+Span12Mux_s10_h.O Span12Mux_s10_v.I
+Span12Mux_s10_h.O Span12Mux_s11_v.I
+Span12Mux_s10_h.O Span12Mux_s4_v.I
+Span12Mux_s10_h.O Span12Mux_s6_v.I
+Span12Mux_s10_h.O Span12Mux_s8_v.I
+Span12Mux_s10_h.O Span12Mux_s9_v.I
+Span12Mux_s10_h.O Span12Mux_v.I
+Span12Mux_s10_v.O LocalMux.I
+Span12Mux_s10_v.O Sp12to4.I
+Span12Mux_s10_v.O Span12Mux_h.I
+Span12Mux_s10_v.O Span12Mux_s10_h.I
+Span12Mux_s10_v.O Span12Mux_s7_h.I
+Span12Mux_s10_v.O Span12Mux_s8_h.I
+Span12Mux_s10_v.O Span12Mux_s9_h.I
+Span12Mux_s10_v.O Span12Mux_v.I
+Span12Mux_s11_h.O LocalMux.I
+Span12Mux_s11_h.O Sp12to4.I
+Span12Mux_s11_h.O Span12Mux_h.I
+Span12Mux_s11_h.O Span12Mux_s10_v.I
+Span12Mux_s11_h.O Span12Mux_s11_v.I
+Span12Mux_s11_h.O Span12Mux_s9_v.I
+Span12Mux_s11_h.O Span12Mux_v.I
+Span12Mux_s11_v.O LocalMux.I
+Span12Mux_s11_v.O Sp12to4.I
+Span12Mux_s11_v.O Span12Mux_h.I
+Span12Mux_s11_v.O Span12Mux_s8_h.I
+Span12Mux_s11_v.O Span12Mux_s9_h.I
+Span12Mux_s11_v.O Span12Mux_v.I
+Span12Mux_s1_h.O LocalMux.I
+Span12Mux_s1_h.O Sp12to4.I
+Span12Mux_s1_h.O Span12Mux_h.I
+Span12Mux_s1_h.O Span12Mux_s3_v.I
+Span12Mux_s1_h.O Span12Mux_s6_v.I
+Span12Mux_s1_h.O Span12Mux_s9_v.I
+Span12Mux_s1_h.O Span12Mux_v.I
+Span12Mux_s1_v.O LocalMux.I
+Span12Mux_s1_v.O Sp12to4.I
+Span12Mux_s1_v.O Span12Mux_v.I
+Span12Mux_s2_h.O LocalMux.I
+Span12Mux_s2_h.O Sp12to4.I
+Span12Mux_s2_h.O Span12Mux_h.I
+Span12Mux_s2_h.O Span12Mux_s11_v.I
+Span12Mux_s2_h.O Span12Mux_s3_v.I
+Span12Mux_s2_h.O Span12Mux_s9_v.I
+Span12Mux_s2_h.O Span12Mux_v.I
+Span12Mux_s2_v.O LocalMux.I
+Span12Mux_s2_v.O Sp12to4.I
+Span12Mux_s2_v.O Span12Mux_h.I
+Span12Mux_s2_v.O Span12Mux_s2_h.I
+Span12Mux_s2_v.O Span12Mux_s5_h.I
+Span12Mux_s2_v.O Span12Mux_v.I
+Span12Mux_s3_h.O LocalMux.I
+Span12Mux_s3_h.O Sp12to4.I
+Span12Mux_s3_h.O Span12Mux_h.I
+Span12Mux_s3_h.O Span12Mux_s7_v.I
+Span12Mux_s3_h.O Span12Mux_v.I
+Span12Mux_s3_v.O LocalMux.I
+Span12Mux_s3_v.O Sp12to4.I
+Span12Mux_s3_v.O Span12Mux_h.I
+Span12Mux_s3_v.O Span12Mux_v.I
+Span12Mux_s4_h.O LocalMux.I
+Span12Mux_s4_h.O Sp12to4.I
+Span12Mux_s4_h.O Span12Mux_h.I
+Span12Mux_s4_v.O LocalMux.I
+Span12Mux_s4_v.O Sp12to4.I
+Span12Mux_s4_v.O Span12Mux_h.I
+Span12Mux_s4_v.O Span12Mux_v.I
+Span12Mux_s5_h.O LocalMux.I
+Span12Mux_s5_h.O Sp12to4.I
+Span12Mux_s5_h.O Span12Mux_h.I
+Span12Mux_s5_h.O Span12Mux_v.I
+Span12Mux_s5_v.O LocalMux.I
+Span12Mux_s5_v.O Sp12to4.I
+Span12Mux_s5_v.O Span12Mux_h.I
+Span12Mux_s5_v.O Span12Mux_v.I
+Span12Mux_s6_h.O LocalMux.I
+Span12Mux_s6_h.O Sp12to4.I
+Span12Mux_s6_h.O Span12Mux_h.I
+Span12Mux_s6_h.O Span12Mux_s10_v.I
+Span12Mux_s6_h.O Span12Mux_s11_v.I
+Span12Mux_s6_h.O Span12Mux_s6_v.I
+Span12Mux_s6_h.O Span12Mux_v.I
+Span12Mux_s6_v.O LocalMux.I
+Span12Mux_s6_v.O Sp12to4.I
+Span12Mux_s6_v.O Span12Mux_h.I
+Span12Mux_s6_v.O Span12Mux_s10_h.I
+Span12Mux_s6_v.O Span12Mux_s5_h.I
+Span12Mux_s6_v.O Span12Mux_s7_h.I
+Span12Mux_s6_v.O Span12Mux_s8_h.I
+Span12Mux_s6_v.O Span12Mux_s9_h.I
+Span12Mux_s6_v.O Span12Mux_v.I
+Span12Mux_s7_h.O LocalMux.I
+Span12Mux_s7_h.O Sp12to4.I
+Span12Mux_s7_h.O Span12Mux_h.I
+Span12Mux_s7_h.O Span12Mux_s10_v.I
+Span12Mux_s7_h.O Span12Mux_s11_v.I
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generated by cgit v1.2.3 (git 2.25.1) at 2025-08-10 00:51:25 +0000