diff options
Diffstat (limited to 'examples/icestick')
| -rw-r--r-- | examples/icestick/Makefile | 2 | ||||
| -rw-r--r-- | examples/icestick/example.v | 2 | ||||
| -rw-r--r-- | examples/icestick/icestick.pcf | 22 | ||||
| -rw-r--r-- | examples/icestick/rs232demo.v | 48 |
4 files changed, 37 insertions, 37 deletions
diff --git a/examples/icestick/Makefile b/examples/icestick/Makefile index f40c8a3..9294608 100644 --- a/examples/icestick/Makefile +++ b/examples/icestick/Makefile @@ -1,4 +1,6 @@ PROJ = example +# PROJ = rs232demo + PIN_DEF = icestick.pcf DEVICE = hx1k diff --git a/examples/icestick/example.v b/examples/icestick/example.v index a934400..3eb7007 100644 --- a/examples/icestick/example.v +++ b/examples/icestick/example.v @@ -13,7 +13,7 @@ module top ( reg [BITS+LOG2DELAY-1:0] counter = 0; reg [BITS-1:0] outcnt; - always@(posedge clk) begin + always @(posedge clk) begin counter <= counter + 1; outcnt <= counter >> LOG2DELAY; end diff --git a/examples/icestick/icestick.pcf b/examples/icestick/icestick.pcf index 23067be..8bf462e 100644 --- a/examples/icestick/icestick.pcf +++ b/examples/icestick/icestick.pcf @@ -1,11 +1,11 @@ -# full iCEstick pinout:
-# http://www.pighixxx.com/test/portfolio-items/icestick/
-
-set_io --warn-no-port RX 9
-set_io --warn-no-port TX 8
-set_io LED1 99
-set_io LED2 98
-set_io LED3 97
-set_io LED4 96
-set_io LED5 95
-set_io clk 21
+# full iCEstick pinout: +# http://www.pighixxx.com/test/portfolio-items/icestick/ + +set_io --warn-no-port RX 9 +set_io --warn-no-port TX 8 +set_io LED1 99 +set_io LED2 98 +set_io LED3 97 +set_io LED4 96 +set_io LED5 95 +set_io clk 21 diff --git a/examples/icestick/rs232demo.v b/examples/icestick/rs232demo.v index fc7a770..f9e7546 100644 --- a/examples/icestick/rs232demo.v +++ b/examples/icestick/rs232demo.v @@ -12,46 +12,44 @@ module top ( parameter integer CLOCK_FREQ_HZ = 12000000; localparam integer HALF_PERIOD = CLOCK_FREQ_HZ / (2 * BAUD_RATE); - reg [9:0] buffer; + reg [7:0] buffer; reg buffer_valid; reg [$clog2(3*HALF_PERIOD):0] cycle_cnt; reg [3:0] bit_cnt = 0; - reg [0:0] state = 0; + reg recv = 0; always @(posedge clk) begin buffer_valid <= 0; - case (state) - 0: begin - if (!RX) begin - cycle_cnt <= HALF_PERIOD; - bit_cnt <= 0; - state <= 1; - end + if (!recv) begin + if (!RX) begin + cycle_cnt <= HALF_PERIOD; + bit_cnt <= 0; + recv <= 1; end - 1: begin - if (cycle_cnt == 2*HALF_PERIOD) begin - cycle_cnt <= 0; - buffer[bit_cnt] <= RX; - bit_cnt <= bit_cnt + 1; - if (bit_cnt == 9) begin - buffer_valid <= 1; - state <= 0; - end + end else begin + if (cycle_cnt == 2*HALF_PERIOD) begin + cycle_cnt <= 0; + bit_cnt <= bit_cnt + 1; + if (bit_cnt == 9) begin + buffer_valid <= 1; + recv <= 0; end else begin - cycle_cnt <= cycle_cnt + 1; + buffer <= {RX, buffer[7:1]}; end + end else begin + cycle_cnt <= cycle_cnt + 1; end - endcase + end end always @(posedge clk) begin if (buffer_valid) begin - if (buffer[8:1] == "1") LED1 <= !LED1; - if (buffer[8:1] == "2") LED2 <= !LED2; - if (buffer[8:1] == "3") LED3 <= !LED3; - if (buffer[8:1] == "4") LED4 <= !LED4; - if (buffer[8:1] == "5") LED5 <= !LED5; + if (buffer == "1") LED1 <= !LED1; + if (buffer == "2") LED2 <= !LED2; + if (buffer == "3") LED3 <= !LED3; + if (buffer == "4") LED4 <= !LED4; + if (buffer == "5") LED5 <= !LED5; end end |