2 files changed, 6 insertions, 5 deletions
diff --git a/docs/index.html b/docs/index.html
index ebf424d..be02756 100644
--- a/docs/index.html
+++ b/docs/index.html
@@ -515,6 +515,7 @@ Links to related projects. Contact me at clifford@clifford.at if you have an int
 <li><a href="http://opencores.org/project,ecowlogic-pico">eCow-Logic pico-ITX Lattice ICE40 board</a>
 <li><a href="https://www.nandland.com/blog/go-board-introduction.html">Nandland Go Board</a>
 <li><a href="https://folknologylabs.wordpress.com/2016/08/17/the-lull-before-the-storm/">myStorm board (iCE40 + STM32)</a>
+<li><a href="https://github.com/tvelliott/dsp_ice">DSP iCE board (another iCE40 + STM32 board)</a>
 </ul>
 
 <h3>Lectures and Tutorials</h3>
diff --git a/docs/io_tile.html b/docs/io_tile.html
index c683ff7..82cf65b 100644
--- a/docs/io_tile.html
+++ b/docs/io_tile.html
@@ -47,9 +47,9 @@ to <span style="font-family:monospace">span12_horz_23</span>.
 </p>
 
 <p>
-A top/bottom io cell has 16 connections named <span style="font-family:monospace">span4_vert_l_0</span> to <span style="font-family:monospace">span4_vert_l_15</span> on its top edge and
-16 connections named <span style="font-family:monospace">span4_vert_r_0</span> to <span style="font-family:monospace">span4_vert_r_15</span> on its bottom edge. The nets <span style="font-family:monospace">span4_vert_l_0</span>
-to <span style="font-family:monospace">span4_vert_l_11</span> are connected to <span style="font-family:monospace">span4_vert_r_4</span> to <span style="font-family:monospace">span4_vert_r_15</span>. The span-4 and span-12 wires
+A top/bottom io cell has 16 connections named <span style="font-family:monospace">span4_horz_l_0</span> to <span style="font-family:monospace">span4_horz_l_15</span> on its left edge and
+16 connections named <span style="font-family:monospace">span4_horz_r_0</span> to <span style="font-family:monospace">span4_horz_r_15</span> on its right edge. The nets <span style="font-family:monospace">span4_horz_l_0</span>
+to <span style="font-family:monospace">span4_horz_l_11</span> are connected to <span style="font-family:monospace">span4_horz_r_4</span> to <span style="font-family:monospace">span4_horz_r_15</span>. The span-4 and span-12 wires
 of the adjacent logic cell are connected to the nets <span style="font-family:monospace">span4_vert_0</span> to <span style="font-family:monospace">span4_vert_47</span> and <span style="font-family:monospace">span12_vert_0</span>
 to <span style="font-family:monospace">span12_vert_23</span>.
 </p>
@@ -489,9 +489,9 @@ of the 1k chip:
 <tr><td>1 0</td><td><span style="font-family:monospace">fabout</span></td><td rowspan="1"><span style="font-family:monospace">BYPASS</span></td></tr>
 <tr><td>2 0</td><td><span style="font-family:monospace">fabout</span></td><td rowspan="1"><span style="font-family:monospace">RESETB</span></td></tr>
 <tr><td>5 0</td><td><span style="font-family:monospace">fabout</span></td><td rowspan="1"><span style="font-family:monospace">LATCHINPUTVALUE</span></td></tr>
-<tr><td>12 1</td><td><span style="font-family:monospace">neigh_op_bnl_1</span></td><td rowspan="1"><span style="font-family:monospace">SDO</span></td></tr>
+<tr><td>12 1</td><td><span style="font-family:monospace">neigh_op_bnr_3</span></td><td rowspan="1"><span style="font-family:monospace">SDO</span></td></tr>
 <tr><td>4 0</td><td><span style="font-family:monospace">fabout</span></td><td rowspan="1"><span style="font-family:monospace">SDI</span></td></tr>
-<tr><td>5 0</td><td><span style="font-family:monospace">fabout</span></td><td rowspan="1"><span style="font-family:monospace">SCLK</span></td></tr>
+<tr><td>3 0</td><td><span style="font-family:monospace">fabout</span></td><td rowspan="1"><span style="font-family:monospace">SCLK</span></td></tr>
 </table>
 
 <p>