diff options
-rwxr-xr-x | icebox/icebox_hlc2asc.py | 8 | ||||
-rwxr-xr-x | icebox/icebox_vlog.py | 4 |
2 files changed, 7 insertions, 5 deletions
diff --git a/icebox/icebox_hlc2asc.py b/icebox/icebox_hlc2asc.py index c26b173..c9b2a04 100755 --- a/icebox/icebox_hlc2asc.py +++ b/icebox/icebox_hlc2asc.py @@ -293,7 +293,7 @@ def revert_to_fabout(x, y, net): for i, xy in enumerate(GLB_NETWK_INTERNAL_TILES): if net == 'glb_netwk_%d' % i and (x, y) == xy: return 'fabout' - raise ParseError("{} is a global netowrk, but not at an expectd location {} {}".format(net, x, y)) + raise ParseError("{} is a global network, but not at an expected location {} {}".format(net, x, y)) return net @@ -956,7 +956,7 @@ class IOTile(Tile): if fields == ['io_1'] and self.blocks[1] is None: self.blocks[1] = IOBlock(self, 1) return self.blocks[1] - raise ParseError("Unepxected new block in {}".format(type(self).__name__)) + raise ParseError("Unexpected new block in {}".format(type(self).__name__)) class IOBlock: def __init__(self, tile, index): @@ -1006,7 +1006,9 @@ class IOBlock: self.enable_input = True elif fields == ['disable_pull_up'] and not self.disable_pull_up: self.disable_pull_up = True - elif fields[0] == 'GLOBAL_BUFFER_OUTPUT' and fields[1] == '->' \ + elif fields[0] in ('GLOBAL_BUFFER_OUTPUT', + 'io_%d/GLOBAL_BUFFER_OUTPUT' % self.index) \ + and fields[1] == '->' \ and fields[2].startswith('glb_netwk_'): if GLB_NETWK_EXTERNAL_BLOCKS[int(fields[2][10:])] \ != (self.tile.x, self.tile.y, self.index): diff --git a/icebox/icebox_vlog.py b/icebox/icebox_vlog.py index 9f5b602..0080f34 100755 --- a/icebox/icebox_vlog.py +++ b/icebox/icebox_vlog.py @@ -842,9 +842,9 @@ for lut in luts_queue: else: always_stmts.append("/* FF %2d %2d %2d */ assign %s = %s;" % (lut[0], lut[1], lut[2], net_out, net_lout)) if not "1" in lut_bits: - const_assigns.append([net_out, "1'b0"]) + const_assigns.append([net_lout, "/* LUT %2d %2d %2d */ 1'b0" % (lut[0], lut[1], lut[2])]) elif not "0" in lut_bits: - const_assigns.append([net_out, "1'b1"]) + const_assigns.append([net_lout, "/* LUT %2d %2d %2d */ 1'b1" % (lut[0], lut[1], lut[2])]) else: def make_lut_expr(bits, sigs): if not sigs: |