/*
* This file is part of the flashrom project.
*
* Copyright (C) 2007, 2008 Carl-Daniel Hailfinger
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __SPI_H__
#define __SPI_H__ 1
/*
* Contains the generic SPI headers
*/
/* Read Electronic ID */
#define JEDEC_RDID 0x9f
#define JEDEC_RDID_OUTSIZE 0x01
/* INSIZE may be 0x04 for some chips*/
#define JEDEC_RDID_INSIZE 0x03
/* Some Atmel AT25F* models have bit 3 as don't care bit in commands */
#define AT25F_RDID 0x15 /* 0x15 or 0x1d */
#define AT25F_RDID_OUTSIZE 0x01
#define AT25F_RDID_INSIZE 0x02
/* Read Electronic Manufacturer Signature */
#define JEDEC_REMS 0x90
#define JEDEC_REMS_OUTSIZE 0x04
#define JEDEC_REMS_INSIZE 0x02
/* Read Serial Flash Discoverable Parameters (SFDP) */
#define JEDEC_SFDP 0x5a
#define JEDEC_SFDP_OUTSIZE 0x05 /* 8b op, 24b addr, 8b dummy */
/* JEDEC_SFDP_INSIZE : any length */
/* Read Electronic Signature */
#define JEDEC_RES 0xab
#define JEDEC_RES_OUTSIZE 0x04
/* INSIZE may be 0x02 for some chips*/
#define JEDEC_RES_INSIZE 0x01
/* Write Enable */
#define JEDEC_WREN 0x06
#define JEDEC_WREN_OUTSIZE 0x01
#define JEDEC_WREN_INSIZE 0x00
/* Write Disable */
#define JEDEC_WRDI 0x04
#define JEDEC_WRDI_OUTSIZE 0x01
#define JEDEC_WRDI_INSIZE 0x00
/* Chip Erase 0x60 is supported by Macronix/SST chips. */
#define JEDEC_CE_60 0x60
#define JEDEC_CE_60_OUTSIZE 0x01
#define JEDEC_CE_60_INSIZE 0x00
/* Chip Erase 0x62 is supported by Atmel AT25F chips. */
#define JEDEC_CE_62 0x62
#define JEDEC_CE_62_OUTSIZE 0x01
#define JEDEC_CE_62_INSIZE 0x00
/* Chip Erase 0xc7 is supported by SST/ST/EON/Macronix chips. */
#define JEDEC_CE_C7 0xc7
#define JEDEC_CE_C7_OUTSIZE 0x01
#define JEDEC_CE_C7_INSIZE 0x00
/* Block Erase 0x50 is supported by Atmel AT26DF chips. */
#define JEDEC_BE_50 0x50
#define JEDEC_BE_50_OUTSIZE 0x04
#define JEDEC_BE_50_INSIZE 0x00
/* Block Erase 0x52 is supported by SST and old Atmel chips. */
#define JEDEC_BE_52 0x52
#define JEDEC_BE_52_OUTSIZE 0x04
#define JEDEC_BE_52_INSIZE 0x00
/* Block Erase 0x81 is supported by Atmel AT26DF chips. */
#define JEDEC_BE_81 0x81
#define JEDEC_BE_81_OUTSIZE 0x04
#define JEDEC_BE_81_INSIZE 0x00
/* Block Erase 0xd8 is supported by EON/Macronix chips. */
#define JEDEC_BE_D8 0xd8
#define JEDEC_BE_D8_OUTSIZE 0x04
#define JEDEC_BE_D8_INSIZE 0x00
/* Block Erase 0xd7 is supported by PMC chips. */
#define JEDEC_BE_D7 0xd7
#define JEDEC_BE_D7_OUTSIZE 0x04
#define JEDEC_BE_D7_INSIZE 0x00
/* Sector Erase 0x20 is supported by Macronix/SST chips. */
#define JEDEC_SE 0x20
#define JEDEC_SE_OUTSIZE 0x04
#define JEDEC_SE_INSIZE 0x00
/* Read Status Register */
#define JEDEC_RDSR 0x05
#define JEDEC_RDSR_OUTSIZE 0x01
#define JEDEC_RDSR_INSIZE 0x01
/* Status Register Bits */
#define SPI_SR_WIP (0x01 << 0)
#define SPI_SR_WEL (0x01 << 1)
#define SPI_SR_AAI (0x01 << 6)
/* Write Status Enable */
#define JEDEC_EWSR 0x50
#define JEDEC_EWSR_OUTSIZE 0x01
#define JEDEC_EWSR_INSIZE 0x00
/* Write Status Register */
#define JEDEC_WRSR 0x01
#define JEDEC_WRSR_OUTSIZE 0x02
#define JEDEC_WRSR_INSIZE 0x00
/* Read the memory */
#define JEDEC_READ 0x03
#define JEDEC_READ_OUTSIZE 0x04
/* JEDEC_READ_INSIZE : any length */
/* Write memory byte */
#define JEDEC_BYTE_PROGRAM 0x02
#define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05
#define JEDEC_BYTE_PROGRAM_INSIZE 0x00
/* Write AAI word (SST25VF080B) */
#define JEDEC_AAI_WORD_PROGRAM 0xad
#define JEDEC_AAI_WORD_PROGRAM_OUTSIZE 0x06
#define JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE 0x03
#define JEDEC_AAI_WORD_PROGRAM_INSIZE 0x00
/* Error codes */
#define SPI_GENERIC_ERROR -1
#define SPI_INVALID_OPCODE -2
#define SPI_INVALID_ADDRESS -3
#define SPI_INVALID_LENGTH -4
#define SPI_FLASHROM_BUG -5
#define SPI_PROGRAMMER_ERROR -6
#endif /* !__SPI_H__ */
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.. program:: ghdl
.. _USING:Synthesis:
Synthesis
#########
.. WARNING::
This is experimental and work in progress! If you find crashes or unsupported features, please :ref:`report them <reporting_bugs>`!
Since ``v0.37``, GHDL features a built-in (experimental) synthesis kernel with two backends: ``synth`` and ``yosys-plugin``. Currently, synthesis is supported as a front-end of other synthesis and technology mapping tools.
Hence, the netlists generated by GHDL are not optimised.
.. NOTE::
Due to GHDL's modular architecture (see :ref:`INT:Overview`), the synthesis kernel shares the VHDL parsing front-end with the simulation back-ends. Hence, available options for synthesis are the same as for analysis and/or simulation elaboration (see :ref:`GHDL:options`).
.. index:: synthesis command
.. _Synth:command:
Synthesis [``--synth``]
=======================
.. HINT::
This command is useful for checking that a design can be synthesized, before actually running a complete synthesis
tool. In fact, because this is expected to be much faster, it can be used as a frequent check.
.. TIP::
Since GHDL's front-end supports multiple versions of the standard, but the synthesised netlists are generated using
a subset of VHDL 1993, GHDL's synthesis features can be used as a preprocessor with tools that do support older
versions of the standard, but which don't provide the most recent features.
.. option:: --synth <[options] primary_unit [secondary_unit]>
Elaborates for synthesis the design whose top unit is indicated by ``primary_unit [secondary_unit]``.
.. ATTENTION::
All the units must have been analyzed; that is, the artifacts of previously executed :option:`-a` calls must exist.
.. option:: --synth <[options] files... -e primary_unit [secondary_unit]>
Analyses and elaborates for synthesis the files present on the command line only.
Elaboration starts from the top unit indicated by ``primary_unit [secondary_unit]``.
Currently, the output is a generic netlist using a (very simple) subset of VHDL 1993.
See :ghdlsharp:`1174` for on-going discussion about other output formats.
.. TIP::
Files can be provided in any order.
.. _Synth:plugin:
Yosys plugin
============
`ghdl-yosys-plugin <https://github.com/ghdl/ghdl-yosys-plugin>`_ is a module to use GHDL as a VHDL front-end for `Yosys
Open Synthesis Suite <http://www.clifford.at/yosys/>`_, a framework for optimised synthesis and technology mapping.
Artifacts generated by Yosys can be used in multiple open source and vendor tools to achieve P&R, formal verification,
etc. A relevant feature of combining GHDL and Yosys is that mixed-language (VHDL-Verilog) synthesis with open source
tools is possible.
The command line syntax for this plugin is the same as for :option:`--synth`, except that the command name (``--synth``)
is neither required nor supported. Instead, ``yosys``, ``yosys -m ghdl`` or ``yosys -m path/to/ghdl.so`` need to be used,
depending of how is the plugin built. See `README <https://github.com/ghdl/ghdl-yosys-plugin>`_ for building and installation
guidelines.
.. HINT::
ghdl-yosys-plugin is a thin layer that converts the internal representation of :option:`--synth` to Yosys' C API. Hence, it is suggested to check the designs with :option:`--synth` before running synthesis with Yosys.
|