/* * Radio tuning for RTL8225 on RTL8185 * * Copyright 2007 Michael Wu * Copyright 2007 Andrea Merello * * Modified slightly for iPXE, June 2009 by Joshua Oreman * * Based on the r8180 driver, which is: * Copyright 2005 Andrea Merello , et al. * * Thanks to Realtek for their support! * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #include #include #include #include "rtl818x.h" FILE_LICENCE(GPL2_ONLY); #define RTL8225_ANAPARAM_ON 0xa0000b59 #define RTL8225_ANAPARAM2_ON 0x860dec11 #define RTL8225_ANAPARAM_OFF 0xa00beb59 #define RTL8225_ANAPARAM2_OFF 0x840dec11 #define min(a,b) (((a)<(b))?(a):(b)) #define ARRAY_SIZE(a) (int)(sizeof(a)/sizeof((a)[0])) static inline void rtl8225_write_phy_ofdm(struct net80211_device *dev, u8 addr, u8 data) { rtl818x_write_phy(dev, addr, data); } static inline void rtl8225_write_phy_cck(struct net80211_device *dev, u8 addr, u8 data) { rtl818x_write_phy(dev, addr, data | 0x10000); } static void rtl8225_write(struct net80211_device *dev, u8 addr, u16 data) { struct rtl818x_priv *priv = dev->priv; u16 reg80, reg84, reg82; u32 bangdata; int i; bangdata = (data << 4) | (addr & 0xf); reg80 = rtl818x_ioread16(priv, &priv->map->RFPinsOutput) & 0xfff3; reg82 = rtl818x_ioread16(priv, &priv->map->RFPinsEnable); rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, reg82 | 0x7); reg84 = rtl818x_ioread16(priv, &priv->map->RFPinsSelect); rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, reg84 | 0x7 | 0x400); rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); udelay(10); rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80 | (1 << 2)); rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); udelay(2); rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80); rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); udelay(10); for (i = 15; i >= 0; i--) { u16 reg = ( reg80 | ( ( bangdata >> i ) & 1 ) ); if (i & 1) rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg); rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg | (1 << 1)); rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg | (1 << 1)); if (!(i & 1)) rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg); } rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80 | (1 << 2)); rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); udelay(10); rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80 | (1 << 2)); rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, reg84 | 0x400); rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF); } static u16 rtl8225_read(struct net80211_device *dev, u8 addr) { struct rtl818x_priv *priv = dev->priv; u16 reg80, reg82, reg84, out; int i; reg80 = rtl818x_ioread16(priv, &priv->map->RFPinsOutput); reg82 = rtl818x_ioread16(priv, &priv->map->RFPinsEnable); reg84 = rtl818x_ioread16(priv, &priv->map->RFPinsSelect) | 0x400; reg80 &= ~0xF; rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, reg82 | 0x000F); rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, reg84 | 0x000F); rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80 | (1 << 2)); rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); udelay(4); rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80); rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); udelay(5); for (i = 4; i >= 0; i--) { u16 reg = reg80 | ((addr >> i) & 1); if (!(i & 1)) { rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg); rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); udelay(1); } rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg | (1 << 1)); rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); udelay(2); rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg | (1 << 1)); rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); udelay(2); if (i & 1) { rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg); rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); udelay(1); } } rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x000E); rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x040E); rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80 | (1 << 3) | (1 << 1)); rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); udelay(2); rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80 | (1 << 3)); rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); udelay(2); rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80 | (1 << 3)); rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); udelay(2); out = 0; for (i = 11; i >= 0; i--) { rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80 | (1 << 3)); rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); udelay(1); rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80 | (1 << 3) | (1 << 1)); rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); udelay(2); rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80 | (1 << 3) | (1 << 1)); rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); udelay(2); rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80 | (1 << 3) | (1 << 1)); rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); udelay(2); if (rtl818x_ioread16(priv, &priv->map->RFPinsInput) & (1 << 1)) out |= 1 << i; rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80 | (1 << 3)); rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); udelay(2); } rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg80 | (1 << 3) | (1 << 2)); rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); udelay(2); rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, reg82); rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, reg84); rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x03A0); return out; } static const u16 rtl8
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generated by cgit v1.2.3 (git 2.25.1) at 2025-07-23 14:44:53 +0000
, 5, 0x00); rtl8225_write_phy_ofdm(dev, 6, 0x40); rtl8225_write_phy_ofdm(dev, 7, 0x00); rtl8225_write_phy_ofdm(dev, 8, 0x40); mdelay(1); } static const u16 rtl8225z2_rxgain[] = { 0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0008, 0x0009, 0x000a, 0x000b, 0x0102, 0x0103, 0x0104, 0x0105, 0x0140, 0x0141, 0x0142, 0x0143, 0x0144, 0x0145, 0x0180, 0x0181, 0x0182, 0x0183, 0x0184, 0x0185, 0x0188, 0x0189, 0x018a, 0x018b, 0x0243, 0x0244, 0x0245, 0x0280, 0x0281, 0x0282, 0x0283, 0x0284, 0x0285, 0x0288, 0x0289, 0x028a, 0x028b, 0x028c, 0x0342, 0x0343, 0x0344, 0x0345, 0x0380, 0x0381, 0x0382, 0x0383, 0x0384, 0x0385, 0x0388, 0x0389, 0x038a, 0x038b, 0x038c, 0x038d, 0x0390, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0398, 0x0399, 0x039a, 0x039b, 0x039c, 0x039d, 0x03a0, 0x03a1, 0x03a2, 0x03a3, 0x03a4, 0x03a5, 0x03a8, 0x03a9, 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3, 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb }; static void rtl8225z2_rf_init(struct net80211_device *dev) { struct rtl818x_priv *priv = dev->priv; int i; rtl818x_set_anaparam(priv, RTL8225_ANAPARAM_ON); /* host_pci_init */ rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480); rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF); rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x0488); rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0); rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); mdelay(200); /* FIXME: ehh?? */ rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0xFF & ~(1 << 6)); rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x00088008); /* TODO: check if we need really to change BRSR to do RF config */ rtl818x_ioread16(priv, &priv->map->BRSR); rtl818x_iowrite16(priv, &priv->map->BRSR, 0xFFFF); rtl818x_iowrite32(priv, &priv->map->RF_PARA, 0x00100044); rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); rtl818x_iowrite8(priv, &priv->map->CONFIG3, 0x44); rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF); rtl8225_write(dev, 0x0, 0x0B7); mdelay(1); rtl8225_write(dev, 0x1, 0xEE0); mdelay(1); rtl8225_write(dev, 0x2, 0x44D); mdelay(1); rtl8225_write(dev, 0x3, 0x441); mdelay(1); rtl8225_write(dev, 0x4, 0x8C3); mdelay(1); rtl8225_write(dev, 0x5, 0xC72); mdelay(1); rtl8225_write(dev, 0x6, 0x0E6); mdelay(1); rtl8225_write(dev, 0x7, 0x82A); mdelay(1); rtl8225_write(dev, 0x8, 0x03F); mdelay(1); rtl8225_write(dev, 0x9, 0x335); mdelay(1); rtl8225_write(dev, 0xa, 0x9D4); mdelay(1); rtl8225_write(dev, 0xb, 0x7BB); mdelay(1); rtl8225_write(dev, 0xc, 0x850); mdelay(1); rtl8225_write(dev, 0xd, 0xCDF); mdelay(1); rtl8225_write(dev, 0xe, 0x02B); mdelay(1); rtl8225_write(dev, 0xf, 0x114); mdelay(100); if (!(rtl8225_read(dev, 6) & (1 << 7))) { rtl8225_write(dev, 0x02, 0x0C4D); mdelay(200); rtl8225_write(dev, 0x02, 0x044D); mdelay(100); /* TODO: readd calibration failure message when the calibration check works */ } rtl8225_write(dev, 0x0, 0x1B7); rtl8225_write(dev, 0x3, 0x002); rtl8225_write(dev, 0x5, 0x004); for (i = 0; i < ARRAY_SIZE(rtl8225z2_rxgain); i++) { rtl8225_write(dev, 0x1, i + 1); rtl8225_write(dev, 0x2, rtl8225z2_rxgain[i]); } rtl8225_write(dev, 0x0, 0x0B7); mdelay(100); rtl8225_write(dev, 0x2, 0xC4D); mdelay(200); rtl8225_write(dev, 0x2, 0x44D); mdelay(100); rtl8225_write(dev, 0x00, 0x2BF); rtl8225_write(dev, 0xFF, 0xFFFF); rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF); for (i = 0; i < ARRAY_SIZE(rtl8225_agc); i++) { rtl8225_write_phy_ofdm(dev, 0xB, rtl8225_agc[i]); mdelay(1); rtl8225_write_phy_ofdm(dev, 0xA, 0x80 + i); mdelay(1); } mdelay(1); rtl8225_write_phy_ofdm(dev, 0x00, 0x01); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x01, 0x02); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x02, 0x62); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x03, 0x00); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x04, 0x00); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x05, 0x00); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x06, 0x40); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x07, 0x00); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x08, 0x40); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x09, 0xfe); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x0a, 0x09); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x18, 0xef); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x0b, 0x80); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x0c, 0x01); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x0d, 0x43); rtl8225_write_phy_ofdm(dev, 0x0e, 0xd3); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x0f, 0x38); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x10, 0x84); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x11, 0x06); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x12, 0x20); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x13, 0x20); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x14, 0x00); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x15, 0x40); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x16, 0x00); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x17, 0x40); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x18, 0xef); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x19, 0x19); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x1a, 0x20); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x1b, 0x11); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x1c, 0x04); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x1d, 0xc5); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x1e, 0xb3); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x1f, 0x75); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x20, 0x1f); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x21, 0x27); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x22, 0x16); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x23, 0x80); mdelay(1); /* FIXME: not needed? */ rtl8225_write_phy_ofdm(dev, 0x24, 0x46); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x25, 0x20); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x26, 0x90); mdelay(1); rtl8225_write_phy_ofdm(dev, 0x27, 0x88); mdelay(1); rtl8225_write_phy_cck(dev, 0x00, 0x98); mdelay(1); rtl8225_write_phy_cck(dev, 0x03, 0x20); mdelay(1); rtl8225_write_phy_cck(dev, 0x04, 0x7e); mdelay(1); rtl8225_write_phy_cck(dev, 0x05, 0x12); mdelay(1); rtl8225_write_phy_cck(dev, 0x06, 0xfc); mdelay(1); rtl8225_write_phy_cck(dev, 0x07, 0x78); mdelay(1); rtl8225_write_phy_cck(dev, 0x08, 0x2e); mdelay(1); rtl8225_write_phy_cck(dev, 0x10, 0x93); mdelay(1); rtl8225_write_phy_cck(dev, 0x11, 0x88); mdelay(1); rtl8225_write_phy_cck(dev, 0x12, 0x47); mdelay(1); rtl8225_write_phy_cck(dev, 0x13, 0xd0); rtl8225_write_phy_cck(dev, 0x19, 0x00); rtl8225_write_phy_cck(dev, 0x1a, 0xa0); rtl8225_write_phy_cck(dev, 0x1b, 0x08); rtl8225_write_phy_cck(dev, 0x40, 0x86); rtl8225_write_phy_cck(dev, 0x41, 0x8a); mdelay(1); rtl8225_write_phy_cck(dev, 0x42, 0x15); mdelay(1); rtl8225_write_phy_cck(dev, 0x43, 0x18); mdelay(1); rtl8225_write_phy_cck(dev, 0x44, 0x36); mdelay(1); rtl8225_write_phy_cck(dev, 0x45, 0x35); mdelay(1); rtl8225_write_phy_cck(dev, 0x46, 0x2e); mdelay(1); rtl8225_write_phy_cck(dev, 0x47, 0x25); mdelay(1); rtl8225_write_phy_cck(dev, 0x48, 0x1c); mdelay(1); rtl8225_write_phy_cck(dev, 0x49, 0x12); mdelay(1); rtl8225_write_phy_cck(dev, 0x4a, 0x09); mdelay(1); rtl8225_write_phy_cck(dev, 0x4b, 0x04); mdelay(1); rtl8225_write_phy_cck(dev, 0x4c, 0x05); mdelay(1); rtl818x_iowrite8(priv, (u8 *)priv->map + 0x5B, 0x0D); mdelay(1); rtl8225z2_rf_set_tx_power(dev, 1); /* RX antenna default to A */ rtl8225_write_phy_cck(dev, 0x10, 0x9b); mdelay(1); /* B: 0xDB */ rtl8225_write_phy_ofdm(dev, 0x26, 0x90); mdelay(1); /* B: 0x10 */ rtl818x_iowrite8(priv, &priv->map->TX_ANTENNA, 0x03); /* B: 0x00 */ mdelay(1); rtl818x_iowrite32(priv, (u32 *)((u8 *)priv->map + 0x94), 0x15c00002); rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF); } static void rtl8225x_rf_init(struct net80211_device *dev) { struct rtl818x_priv *priv = dev->priv; u16 reg8, reg9; rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480); rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x0488); rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF); rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); mdelay(100); rtl8225_write(dev, 0, 0x1B7); reg8 = rtl8225_read(dev, 8); reg9 = rtl8225_read(dev, 9); rtl8225_write(dev, 0, 0x0B7); if (reg8 != 0x588 || reg9 != 0x700) { priv->rf_flag = 0; rtl8225_rf_init(dev); } else { priv->rf_flag = 1; rtl8225z2_rf_init(dev); } } static void rtl8225_rf_stop(struct net80211_device *dev) { struct rtl818x_priv *priv = dev->priv; u8 reg; rtl8225_write(dev, 0x4, 0x1f); mdelay(1); rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | RTL818X_CONFIG3_ANAPARAM_WRITE); rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, RTL8225_ANAPARAM2_OFF); rtl818x_iowrite32(priv, &priv->map->ANAPARAM, RTL8225_ANAPARAM_OFF); rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE); rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); } static void rtl8225_rf_set_channel(struct net80211_device *dev, struct net80211_channel *channelp) { struct rtl818x_priv *priv = dev->priv; int chan = channelp->channel_nr; if (priv->rf_flag) rtl8225z2_rf_set_tx_power(dev, chan); else rtl8225_rf_set_tx_power(dev, chan); rtl8225_write(dev, 0x7, rtl8225_chan[chan - 1]); mdelay(10); } static void rtl8225_rf_conf_erp(struct net80211_device *dev) { struct rtl818x_priv *priv = dev->priv; if (dev->phy_flags & NET80211_PHY_USE_SHORT_SLOT) { rtl818x_iowrite8(priv, &priv->map->SLOT, 0x9); rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22); rtl818x_iowrite8(priv, &priv->map->DIFS, 0x14); rtl818x_iowrite8(priv, &priv->map->EIFS, 81); rtl818x_iowrite8(priv, &priv->map->CW_VAL, 0x73); } else { rtl818x_iowrite8(priv, &priv->map->SLOT, 0x14); rtl818x_iowrite8(priv, &priv->map->SIFS, 0x44); rtl818x_iowrite8(priv, &priv->map->DIFS, 0x24); rtl818x_iowrite8(priv, &priv->map->EIFS, 81); rtl818x_iowrite8(priv, &priv->map->CW_VAL, 0xa5); } } struct rtl818x_rf_ops rtl8225_ops __rtl818x_rf_driver = { .name = "rtl8225", .id = 9, .init = rtl8225x_rf_init, .stop = rtl8225_rf_stop, .set_chan = rtl8225_rf_set_channel, .conf_erp = rtl8225_rf_conf_erp, };