-- Lists data type. -- Copyright (C) 2002, 2003, 2004, 2005 Tristan Gingold -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see . with Tables; package body Lists is type List_Record is record First : Chunk_Index_Type; Last : Chunk_Index_Type; Chunk_Idx : Nat32; Nbr : Natural; end record; package Listt is new Tables (Table_Component_Type => List_Record, Table_Index_Type => List_Type, Table_Low_Bound => 2, Table_Initial => 128); package Chunkt is new Tables (Table_Component_Type => Chunk_Type, Table_Index_Type => Chunk_Index_Type, Table_Low_Bound => 1, Table_Initial => 128); Chunk_Free_List : Chunk_Index_Type := No_Chunk_Index; procedure Free_Chunk (Idx : Chunk_Index_Type) is begin Chunkt.Table (Idx).Next := Chunk_Free_List; Chunk_Free_List := Idx; end Free_Chunk; function Get_Free_Chunk return Chunk_Index_Type is Res : Chunk_Index_Type; begin if Chunk_Free_List /= No_Chunk_Index then Res := Chunk_Free_List; Chunk_Free_List := Chunkt.Table (Res).Next; return Res; else return Chunkt.Allocate; end if; end Get_Free_Chunk; function Get_Nbr_Elements (List: List_Type) return Natural is begin return Listt.Table (List).Nbr; end Get_Nbr_Elements; function Is_Empty (List : List_Type) return Boolean is begin return Listt.Table (List).Nbr = 0; end Is_Empty; procedure Append_Element (List: List_Type; Element: El_Type) is L : List_Record renames Listt.Table (List); C : Chunk_Index_Type; begin L.Chunk_Idx := L.Chunk_Idx + 1; if L.Chunk_Idx < Chunk_Len then Chunkt.Table (L.Last).Els (L.Chunk_Idx) := Element; else C := Get_Free_Chunk; Chunkt.Table (C).Next := No_Chunk_Index; Chunkt.Table (C).Els (0) := Element; L.Chunk_Idx := 0; if L.Nbr = 0 then L.First := C; else Chunkt.Table (L.Last).Next := C; end if; L.Last := C; end if; L.Nbr := L.Nbr + 1; end Append_Element; function Get_First_Element (List: List_Type) return El_Type is L : List_Record renames Listt.Table (List); begin pragma Assert (L.Nbr > 0); return Chunkt.Table (L.First).Els (0); end Get_First_Element; -- Add (append) an element only if it was not already present in the list. procedure Add_Element (List: List_Type; El: El_Type) is It : Iterator; begin It := Iterate (List); while Is_Valid (It) loop if Get_Element (It) = El then return; end if; Next (It); end loop; Append_Element (List, El); end Add_Element; -- Chain of unused lists. List_Free_Chain : List_Type := Null_List; function Create_List return List_Type is Res : List_Type; begin if List_Free_Chain = Null_List then Listt.Increment_Last; Res := Listt.Last; else Res := List_Free_Chain; List_Free_Chain := List_Type (Listt.Table (Res).Chunk_Idx); end if; Listt.Table (Res) := List_Record'(First => No_Chunk_Index, Last => No_Chunk_Index, Chunk_Idx => Chunk_Len, Nbr => 0); return Res; end Create_List; procedure Destroy_List (List : in out List_Type) is C, Next_C : Chunk_Index_Type; begin if List = Null_List then return; end if; C := Listt.Table (List).First; while C /= No_Chunk_Index loop Next_C := Chunkt.Table (C).Next; Free_Chunk (C); C := Next_C; end loop; Listt.Table (List).Chunk_Idx := Nat32 (List_Free_Chain); List_Free_Chain := List; List := Null_List; end Destroy_List; procedure Finalize is begin Listt.Free; Chunkt.Free; end Finalize; procedure Initialize is begin Listt.Init; Chunkt.Init; List_Free_Chain := Null_List; Chunk_Free_List := No_Chunk_Index; end Initialize; function Iterate (List : List_Valid_Type) return Iterator is L : List_Record renames Listt.Table (List); begin return Iterator'(Chunk => L.First, Chunk_Idx => 0, Remain => Int32 (L.Nbr)); end Iterate; function Iterate_Safe (List : List_Type) return Iterator is begin if List = Null_List then return Iterator'(Chunk => No_Chunk_Index, Chunk_Idx => 0, Remain => 0); end if; return Iterate (List); end Iterate_Safe; function Is_Valid (It : Iterator) return Boolean is begin return It.Remain > 0; end Is_Valid; procedure Next (It : in out Iterator) is begin It.Chunk_Idx := It.Chunk_Idx + 1; if It.Chunk_Idx = Chunk_Len then It.Chunk := Chunkt.Table (It.Chunk).Next; It.Chunk_Idx := 0; end if; It.Remain := It.Remain - 1; end Next; function Get_Element (It : Iterator) return El_Type is begin return Chunkt.Table (It.Chunk).Els (It.Chunk_Idx); end Get_Element; procedure Set_Element (It : Iterator; El : El_Type) is begin Chunkt.Table (It.Chunk).Els (It.Chunk_Idx) := El; end Set_Element; end Lists; '>108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 
```
yosys -- Yosys Open SYnthesis Suite

Copyright (C) 2012 - 2018  Clifford Wolf <clifford@clifford.at>

Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.

THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
```


yosys – Yosys Open SYnthesis Suite
===================================

This is a framework for RTL synthesis tools. It currently has
extensive Verilog-2005 support and provides a basic set of
synthesis algorithms for various application domains.

Yosys can be adapted to perform any synthesis job by combining
the existing passes (algorithms) using synthesis scripts and
adding additional passes as needed by extending the yosys C++
code base.

Yosys is free software licensed under the ISC license (a GPL
compatible license that is similar in terms to the MIT license
or the 2-clause BSD license).


Web Site and Other Resources
============================

More information and documentation can be found on the Yosys web site:
- http://www.clifford.at/yosys/

The "Documentation" page on the web site contains links to more resources,
including a manual that even describes some of the Yosys internals:
- http://www.clifford.at/yosys/documentation.html

The file `CodingReadme` in this directory contains additional information
for people interested in using the Yosys C++ APIs.

Users interested in formal verification might want to use the formal verification
front-end for Yosys, SymbiYosys:
- https://symbiyosys.readthedocs.io/en/latest/
- https://github.com/YosysHQ/SymbiYosys


Setup
======

You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is
recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make.
TCL, readline and libffi are optional (see ``ENABLE_*`` settings in Makefile).
Xdot (graphviz) is used by the ``show`` command in yosys to display schematics.

For example on Ubuntu Linux 16.04 LTS the following commands will install all
prerequisites for building yosys:

	$ sudo apt-get install build-essential clang bison flex \
		libreadline-dev gawk tcl-dev libffi-dev git \
		graphviz xdot pkg-config python3

Similarily, on Mac OS X MacPorts or Homebrew can be used to install dependencies:

	$ brew tap Homebrew/bundle && brew bundle
	$ sudo port install bison flex readline gawk libffi \
		git graphviz pkgconfig python36

On FreeBSD use the following command to install all prerequisites:

	# pkg install bison flex readline gawk libffi\
		git graphviz pkgconfig python3 python36 tcl-wrapper

On FreeBSD system use gmake instead of make. To run tests use:
    % MAKE=gmake CC=cc gmake test

For Cygwin use the following command to install all prerequisites, or select these additional packages:

	setup-x86_64.exe -q --packages=bison,flex,gcc-core,gcc-g++,git,libffi-devel,libreadline-devel,make,pkg-config,python3,tcl-devel

There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well
as a source distribution for Visual Studio. Visit the Yosys download page for
more information: http://www.clifford.at/yosys/download.html

To configure the build system to use a specific compiler, use one of

	$ make config-clang
	$ make config-gcc

For other compilers and build configurations it might be
necessary to make some changes to the config section of the
Makefile.

	$ vi Makefile            # ..or..
	$ vi Makefile.conf

To build Yosys simply type 'make' in this directory.

	$ make
	$ sudo make install

Note that this also downloads, builds and installs ABC (using yosys-abc
as executable name).

Tests are located in the tests subdirectory and can be executed using the test target. Note that you need gawk as well as a recent version of iverilog (i.e. build from git). Then, execute tests via:

	$ make test

Getting Started
===============

Yosys can be used with the interactive command shell, with
synthesis scripts or with command line arguments. Let's perform
a simple synthesis job using the interactive command shell:

	$ ./yosys
	yosys>

the command ``help`` can be used to print a list of all available
commands and ``help <command>`` to print details on the specified command:

	yosys> help help

reading the design using the Verilog frontend:

	yosys> read_verilog tests/simple/fiedler-cooley.v

writing the design to the console in Yosys's internal format:

	yosys> write_ilang

elaborate design hierarchy:

	yosys> hierarchy

convert processes (``always`` blocks) to netlist elements and perform
some simple optimizations:

	yosys> proc; opt

display design netlist using ``xdot``:

	yosys> show

the same thing using ``gv`` as postscript viewer:

	yosys> show -format ps -viewer gv

translating netlist to gate logic and perform some simple optimizations:

	yosys> techmap; opt

write design netlist to a new Verilog file:

	yosys> write_verilog synth.v

a similar synthesis can be performed using yosys command line options only:

	$ ./yosys -o synth.v -p hierarchy -p proc -p opt \
	                     -p techmap -p opt tests/simple/fiedler-cooley.v

or using a simple synthesis script:

	$ cat synth.ys
	read_verilog tests/simple/fiedler-cooley.v
	hierarchy; proc; opt; techmap; opt
	write_verilog synth.v

	$ ./yosys synth.ys

It is also possible to only have the synthesis commands but not the read/write
commands in the synthesis script:

	$ cat synth.ys
	hierarchy; proc; opt; techmap; opt

	$ ./yosys -o synth.v tests/simple/fiedler-cooley.v synth.ys

The following very basic synthesis script should work well with all designs:

	# check design hierarchy
	hierarchy

	# translate processes (always blocks)
	proc; opt

	# detect and optimize FSM encodings
	fsm; opt

	# implement memories (arrays)
	memory; opt

	# convert to gate logic
	techmap; opt

If ABC is enabled in the Yosys build configuration and a cell library is given
in the liberty file ``mycells.lib``, the following synthesis script will
synthesize for the given cell library:

	# the high-level stuff
	hierarchy; proc; fsm; opt; memory; opt

	# mapping to internal cell library
	techmap; opt

	# mapping flip-flops to mycells.lib
	dfflibmap -liberty mycells.lib

	# mapping logic to mycells.lib
	abc -liberty mycells.lib

	# cleanup
	clean

If you do not have a liberty file but want to test this synthesis script,
you can use the file ``examples/cmos/cmos_cells.lib`` from the yosys sources.

Liberty file downloads for and information about free and open ASIC standard
cell libraries can be found here:

- http://www.vlsitechnology.org/html/libraries.html
- http://www.vlsitechnology.org/synopsys/vsclib013.lib

The command ``synth`` provides a good default synthesis script (see
``help synth``).  If possible a synthesis script should borrow from ``synth``.
For example:

	# the high-level stuff
	hierarchy
	synth -run coarse

	# mapping to internal cells
	techmap; opt -fast
	dfflibmap -liberty mycells.lib
	abc -liberty mycells.lib
	clean

Yosys is under construction. A more detailed documentation will follow.


Unsupported Verilog-2005 Features
=================================

The following Verilog-2005 features are not supported by
Yosys and there are currently no plans to add support
for them:

- Non-synthesizable language features as defined in
	IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002

- The ``tri``, ``triand``, ``trior``, ``wand`` and ``wor`` net types

- The ``config`` keyword and library map files

- The ``disable``, ``primitive`` and ``specify`` statements

- Latched logic (is synthesized as logic with feedback loops)


Verilog Attributes and non-standard features
============================================

- The ``full_case`` attribute on case statements is supported
  (also the non-standard ``// synopsys full_case`` directive)

- The ``parallel_case`` attribute on case statements is supported
  (also the non-standard ``// synopsys parallel_case`` directive)

- The ``// synopsys translate_off`` and ``// synopsys translate_on``
  directives are also supported (but the use of ``` `ifdef .. `endif ```
  is strongly recommended instead).

- The ``nomem2reg`` attribute on modules or arrays prohibits the
  automatic early conversion of arrays to separate registers. This
  is potentially dangerous. Usually the front-end has good reasons
  for converting an array to a list of registers. Prohibiting this
  step will likely result in incorrect synthesis results.

- The ``mem2reg`` attribute on modules or arrays forces the early
  conversion of arrays to separate registers.

- The ``nomeminit`` attribute on modules or arrays prohibits the
  creation of initialized memories. This effectively puts ``mem2reg``
  on all memories that are written to in an ``initial`` block and