From f7f0f0a48f49e0328401c1f60575f07c92c0c15f Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Thu, 15 Aug 2019 09:59:45 +0200 Subject: add synthesis support for logic operators on numeric types (#893) * add logic operators on unsigned * handle signed too * handle unary not --- testsuite/synth/psl01/hello.vhdl | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'testsuite') diff --git a/testsuite/synth/psl01/hello.vhdl b/testsuite/synth/psl01/hello.vhdl index 6f5e40735..6676b883a 100644 --- a/testsuite/synth/psl01/hello.vhdl +++ b/testsuite/synth/psl01/hello.vhdl @@ -22,8 +22,8 @@ begin end process; cnt <= val; - --psl default clock is clk; + --psl default clock is rising_edge(clk); --psl restrict {rst; (not rst)[*]}; - --psl assert always val /= 5 or rst = '1'; - --psl assume always val < 50; + --psl assert always val /= 5 abort rst; + --psl assume always val < 10; end behav; -- cgit v1.2.3