From f2c863f7e030796cb325885654ffe3e945f35198 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Mon, 10 Oct 2022 18:20:39 +0200 Subject: testsuite/gna: add a test for #2212 --- testsuite/gna/issue2212/minimal.vhdl | 22 ++++++++++++++++++++++ testsuite/gna/issue2212/testsuite.sh | 11 +++++++++++ 2 files changed, 33 insertions(+) create mode 100644 testsuite/gna/issue2212/minimal.vhdl create mode 100755 testsuite/gna/issue2212/testsuite.sh (limited to 'testsuite') diff --git a/testsuite/gna/issue2212/minimal.vhdl b/testsuite/gna/issue2212/minimal.vhdl new file mode 100644 index 000000000..82f034123 --- /dev/null +++ b/testsuite/gna/issue2212/minimal.vhdl @@ -0,0 +1,22 @@ +library IEEE; + use IEEE.std_logic_1164.all; + use IEEE.numeric_std.all; + +entity minimal is + port( + duty_cycle: in std_logic_vector(7 downto 0) + ); +end entity minimal; + +architecture rtl of minimal is + +begin + + DECIDE_STATE: process(all) is +--DECIDE_STATE: process(duty_cycle) is -- uncomment to run + variable duty : boolean; + begin + duty := true when signed(duty_cycle) > 0 else false; + end process; + +end architecture rtl; diff --git a/testsuite/gna/issue2212/testsuite.sh b/testsuite/gna/issue2212/testsuite.sh new file mode 100755 index 000000000..2865dbca5 --- /dev/null +++ b/testsuite/gna/issue2212/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze minimal.vhdl +elab_simulate minimal + +clean + +echo "Test successful" -- cgit v1.2.3