From ef0dbc726749df434036b23480b89f01cbe67d44 Mon Sep 17 00:00:00 2001
From: Patrick Lehmann <Patrick.Lehmann@plc2.de>
Date: Sat, 19 Jun 2021 03:20:59 +0200
Subject: Added handling of Parenthesis.

---
 testsuite/pyunit/SimpleEntity.vhdl | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'testsuite')

diff --git a/testsuite/pyunit/SimpleEntity.vhdl b/testsuite/pyunit/SimpleEntity.vhdl
index 90d68fd83..931599086 100644
--- a/testsuite/pyunit/SimpleEntity.vhdl
+++ b/testsuite/pyunit/SimpleEntity.vhdl
@@ -4,7 +4,7 @@ use     ieee.numeric_std.all;
 
 entity entity_1 is
 	generic (
-		FREQ : real     := 100.0;
+		FREQ : real     := (100.0 * 1024.0 * 1024.0);
 		BITS : positive := 8
 	);
 	port (
@@ -17,7 +17,7 @@ end entity entity_1;
 architecture behav of entity_1 is
 	signal Reset_n : std_logic;
 begin
-	Reset_n <= not Reset;
+	Reset_n <= (not Reset);
 
 	process(Clock)
 	begin
-- 
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