From ca39821dc013a877a8dbdfabbc3b861eb4d4d2e3 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 26 Jul 2021 00:13:11 +0200 Subject: Adjusted to renaming in pyVHDLModel. --- testsuite/pyunit/dom/Literals.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'testsuite') diff --git a/testsuite/pyunit/dom/Literals.py b/testsuite/pyunit/dom/Literals.py index 418a1b76d..febfd4294 100644 --- a/testsuite/pyunit/dom/Literals.py +++ b/testsuite/pyunit/dom/Literals.py @@ -34,7 +34,7 @@ from pathlib import Path from textwrap import dedent from unittest import TestCase -from pyVHDLModel.VHDLModel import Expression +from pyVHDLModel.SyntaxModel import Expression from pyGHDL.dom.DesignUnit import Package -- cgit v1.2.3 From 20b636decb9c502891fbf5f9a15cf8e7126904a5 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 28 Jul 2021 09:00:03 +0200 Subject: Handle instantiations 1/2. --- testsuite/pyunit/Current.vhdl | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) (limited to 'testsuite') diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index eae346375..3c518cce4 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -85,7 +85,7 @@ architecture behav of entity_1 is package inner_pack is end package; begin - process(Clock) + proc: process(Clock) begin if rising_edge(Clock) then if Reset = '1' then @@ -95,6 +95,36 @@ begin end if; end if; end process; + + a <= b; + + + inst1: entity work.counter1(rtl) + generic map ( + BITS => 8 + ) + port map ( + clk => Clock + ); + + inst2: component counter2 + port map ( + clk => Clock + ); + + inst3: configuration counter3 + port map ( + clk => Clock + ); + + blk: block + begin + inst4: entity work.counter4(rtl) + port map ( + clk => Clock + ); + end block; + end architecture behav; package package_1 is -- cgit v1.2.3 From 21a1a3b2ce0be2d9ada1c2d112d225f5d773f71a Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 29 Jul 2021 23:33:51 +0200 Subject: Added generate statements. --- testsuite/pyunit/Current.vhdl | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'testsuite') diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index 3c518cce4..d364a2b2e 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -81,7 +81,7 @@ architecture behav of entity_1 is disconnect address_bus : resolved_word after 3 ns; disconnect others : resolved_word after 2 ns; - default clock is rising_edge(clk); +-- default clock is rising_edge(clk); package inner_pack is end package; begin @@ -125,6 +125,19 @@ begin ); end block; + genIf: if True generate + constant G0 : boolean := False; + begin + + elsif False generate + constant G1 : boolean := False; + begin + + else generate + constant G2 : boolean := False; + begin + + end generate; end architecture behav; package package_1 is -- cgit v1.2.3 From 3f31acc7304b03996f045f39b9e1130a4ffdc330 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 11 Aug 2021 02:55:48 +0200 Subject: Improved pretty-printing for hierarchy. --- testsuite/pyunit/Current.vhdl | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) (limited to 'testsuite') diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index d364a2b2e..f11ab764a 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -128,15 +128,33 @@ begin genIf: if True generate constant G0 : boolean := False; begin - + inst: IfDummy; elsif False generate constant G1 : boolean := False; begin - + inst: ElsifDummy; else generate constant G2 : boolean := False; begin + inst: ElseDummy; + end generate; + + genFor: for I in 0 to 3 generate + constant G3 : boolean := False; + begin + inst: ForDummy; + end generate; + + genCase: case selector generate + when 0 => + constant G4 : boolean := False; + begin + inst: Case0Dummy; + when others => + constant G5 : boolean := False; + begin + inst: OthersDummy; end generate; end architecture behav; -- cgit v1.2.3 From 3abbfe34b529af865d6549bb3e6ed47ea1ab1e37 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 11 Aug 2021 03:34:54 +0200 Subject: Improved handling of generate statements and pretty-printing of hierarchy. --- testsuite/pyunit/Current.vhdl | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'testsuite') diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index f11ab764a..c0c66b0e9 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -128,33 +128,33 @@ begin genIf: if True generate constant G0 : boolean := False; begin - inst: IfDummy; + inst: component IfDummy; elsif False generate constant G1 : boolean := False; begin - inst: ElsifDummy; + inst: component ElsifDummy; else generate constant G2 : boolean := False; begin - inst: ElseDummy; + inst: component ElseDummy; end generate; genFor: for I in 0 to 3 generate constant G3 : boolean := False; begin - inst: ForDummy; + inst: component ForDummy; end generate; genCase: case selector generate when 0 => constant G4 : boolean := False; begin - inst: Case0Dummy; + inst: component Case0Dummy; when others => constant G5 : boolean := False; begin - inst: OthersDummy; + inst: component OthersDummy; end generate; end architecture behav; -- cgit v1.2.3 From b34f3e885407693a2839771fd469af4ce2b40978 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 11 Aug 2021 11:48:00 +0200 Subject: Improvements for case generate statements. --- testsuite/pyunit/Current.vhdl | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'testsuite') diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index c0c66b0e9..1f1e6c51c 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -151,8 +151,23 @@ begin begin inst: component Case0Dummy; - when others => + when 1 | 2 => constant G5 : boolean := False; + begin + inst: component Case12Dummy; + + when 3 to 4 => + constant G6 : boolean := False; + begin + inst: component Case34Dummy; + + when 5 to 6 | 8 to 9 => + constant G7 : boolean := False; + begin + inst: component Case5689Dummy; + + when others => + constant G8 : boolean := False; begin inst: component OthersDummy; end generate; -- cgit v1.2.3 From bc09bbf10599436e1efdb0432886b2bb8b4bf890 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 11 Aug 2021 15:49:39 +0200 Subject: Support for concurrent procedure call. --- testsuite/pyunit/Current.vhdl | 3 +++ 1 file changed, 3 insertions(+) (limited to 'testsuite') diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index 1f1e6c51c..a63a3c75f 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -171,6 +171,9 @@ begin begin inst: component OthersDummy; end generate; + + call: OtherDummy; + ende: std.env.stop; end architecture behav; package package_1 is -- cgit v1.2.3 From 357cb9746c53e3f32fc9c2f28686c25e388918c3 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 12 Aug 2021 13:06:11 +0200 Subject: Preparations for sequential statements. --- testsuite/pyunit/Current.vhdl | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'testsuite') diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index a63a3c75f..f97d831b9 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -94,6 +94,26 @@ begin Q <= std_logic_vector(unsigned(Q) + 1); end if; end if; + + for i in 7 downto 0 loop + loop + while true loop + next; + next when true; + end loop; + exit; + exit when true; + end loop; + return; + end loop; + + case foo_bar is + when 0 => + when 1 | 2 => + when 3 to 4 => + when 5 to 6 | 8 to 9 => + when others => + end case; end process; a <= b; -- cgit v1.2.3 From c4326161ce97d3286e8dffe31d0c168e05f3f9ea Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 13 Aug 2021 22:21:04 +0200 Subject: Improved handling of ranges (e.g. via attribute names). --- testsuite/pyunit/dom/Sanity.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'testsuite') diff --git a/testsuite/pyunit/dom/Sanity.py b/testsuite/pyunit/dom/Sanity.py index adf838646..cc321acc7 100644 --- a/testsuite/pyunit/dom/Sanity.py +++ b/testsuite/pyunit/dom/Sanity.py @@ -53,5 +53,9 @@ design = Design() def test_AllVHDLSources(file): check_call([sys_executable, _GHDL_ROOT / "pyGHDL/cli/dom.py", "pretty", "-f", file], stderr=STDOUT) -# document = Document(Path(file)) -# design.Documents.append(document) + # try: + # lib = design.GetLibrary("sanity") + # document = Document(Path(file)) + # design.AddDocument(document, lib) + # except DOMException as ex: + # print(ex) -- cgit v1.2.3 From 2daa121cd8d40175a82c887b514208ff7f0a50da Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sat, 14 Aug 2021 21:59:17 +0200 Subject: Extended testcase. --- testsuite/pyunit/Current.vhdl | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'testsuite') diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index f97d831b9..f755b95a8 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -189,7 +189,15 @@ begin when others => constant G8 : boolean := False; begin - inst: component OthersDummy; + blkOthers: block + constant G9 : boolean := False; + begin + ifOthers: if false generate + constant G10 : boolean := False; + begin + inst: component OthersDummy; + end generate; + end block; end generate; call: OtherDummy; -- cgit v1.2.3 From c74c26bbb6b58e0cf7fba78e382f0949240b7721 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 16 Aug 2021 17:43:29 +0200 Subject: Handle if-statements. --- testsuite/pyunit/Current.vhdl | 2 ++ 1 file changed, 2 insertions(+) (limited to 'testsuite') diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index f755b95a8..cd6537519 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -90,6 +90,8 @@ begin if rising_edge(Clock) then if Reset = '1' then Q <= (others => '0'); + elsif Load = '1' then + Q <= D after 10 ns; else Q <= std_logic_vector(unsigned(Q) + 1); end if; -- cgit v1.2.3 From 3f0308a5f807269aa5691fa1c704c0e9147d45f1 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 16 Aug 2021 23:47:04 +0200 Subject: Handle contexts. --- testsuite/pyunit/Current.vhdl | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'testsuite') diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index cd6537519..a835eae40 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -219,6 +219,9 @@ package package_1 is attribute fixed of ghdl, gtkwave [x, y] : constant is true; component comp is + generic ( + BITS : positive := 2 + ); port ( clk : std ); @@ -248,3 +251,10 @@ end package body; vunit vu (component_1) { } + +context ctx is + library osvvm; + library axi4_lite, axi4_stream; + use osvvm.alert.all; + use osvvm.alert.alertid, osvvm.alert.priority; +end context; -- cgit v1.2.3 From 597bc9928352ba187bdb0a707332a5f7a0a28e1a Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 16 Aug 2021 23:56:16 +0200 Subject: Handle context references. --- testsuite/pyunit/Current.vhdl | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) (limited to 'testsuite') diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index a835eae40..240c11d5f 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -206,6 +206,16 @@ begin ende: std.env.stop; end architecture behav; +context ctx is + library osvvm; + library axi4_lite, axi4_stream; + use osvvm.alert.all; + use osvvm.alert.alertid, osvvm.alert.priority; +end context; + + +context work.ctx; + package package_1 is generic ( BITS : positive @@ -251,10 +261,3 @@ end package body; vunit vu (component_1) { } - -context ctx is - library osvvm; - library axi4_lite, axi4_stream; - use osvvm.alert.all; - use osvvm.alert.alertid, osvvm.alert.priority; -end context; -- cgit v1.2.3 From c34b020a8c1b6aa5083a637e3e9062c7a71b309a Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 17 Aug 2021 10:16:59 +0200 Subject: Some updates. --- testsuite/pyunit/Current.vhdl | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'testsuite') diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index 240c11d5f..a397e8700 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -111,9 +111,13 @@ begin case foo_bar is when 0 => + report "hello" & " " & "world"; when 1 | 2 => + report "vhdl" severity note; when 3 to 4 => + assert true nor false report "nothing"; when 5 to 6 | 8 to 9 => + assert true nor false report "nothing" severity warning or error; when others => end case; end process; -- cgit v1.2.3 From 2488e55caba1c369785a93ab2578c4a1e0c40c65 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 17 Aug 2021 10:44:34 +0200 Subject: Read condition, message and severity from asserts and reports. --- testsuite/pyunit/Current.vhdl | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'testsuite') diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index a397e8700..69f324f37 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -120,6 +120,11 @@ begin assert true nor false report "nothing" severity warning or error; when others => end case; + + report "hello" & " " & "world"; + report "vhdl" severity note; + assert true nor false report "nothing"; + assert true nor false report "nothing" severity warning; end process; a <= b; -- cgit v1.2.3 From d0dc820554320ad076854481f5cb0957edd3cda5 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 17 Aug 2021 12:17:51 +0200 Subject: Implemented handling of wait statements. --- testsuite/pyunit/Current.vhdl | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'testsuite') diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index 69f324f37..1f802af47 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -121,10 +121,14 @@ begin when others => end case; - report "hello" & " " & "world"; - report "vhdl" severity note; - assert true nor false report "nothing"; - assert true nor false report "nothing" severity warning; + wait; + wait on a, b; + wait until rising_edge(clock); + wait on clock until rising_edge(clock); + wait for 10 ns; + wait on c for 50 ns; + wait until rising_edge(clock) for 100 ns; + wait on sel until rising_edge(clock) for 100 ns; end process; a <= b; -- cgit v1.2.3 From 8c0f8e0ad95c53beac983546550222117c6a639c Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 17 Aug 2021 20:14:13 +0200 Subject: Handle associations. --- testsuite/pyunit/Current.vhdl | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) (limited to 'testsuite') diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index 1f802af47..81887ae7f 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -136,20 +136,29 @@ begin inst1: entity work.counter1(rtl) generic map ( - BITS => 8 + BITS1 => 8 ) port map ( - clk => Clock + clk1 => Clock ); inst2: component counter2 + generic map ( + BITS2 => 8, + value2 + ) port map ( - clk => Clock + clk2 => Clock, + enable2 ); inst3: configuration counter3 + generic map ( + BITS3 => 8 + ) port map ( - clk => Clock + clk3 => Clock, + control(0) => battery and emergency ); blk: block @@ -215,7 +224,8 @@ begin end block; end generate; - call: OtherDummy; + call: CallDummy; + called: CalledDummy(25); ende: std.env.stop; end architecture behav; -- cgit v1.2.3 From 324d56b5ab4b1cdd1c43f412d4139a38dcb90eb9 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 18 Aug 2021 08:19:44 +0200 Subject: Handle open in map aspects. --- testsuite/pyunit/Current.vhdl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'testsuite') diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index 81887ae7f..b4906e211 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -165,7 +165,8 @@ begin begin inst4: entity work.counter4(rtl) port map ( - clk => Clock + clk => Clock, + value => open ); end block; -- cgit v1.2.3 From 8b98e2883b40b00922c9944c2470211ee055a9a5 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 23 Aug 2021 09:02:47 +0200 Subject: Fixes due to a bug in pyVHDLModel. Name Context was used twice. --- testsuite/pyunit/dom/Literals.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'testsuite') diff --git a/testsuite/pyunit/dom/Literals.py b/testsuite/pyunit/dom/Literals.py index febfd4294..debd401e3 100644 --- a/testsuite/pyunit/dom/Literals.py +++ b/testsuite/pyunit/dom/Literals.py @@ -34,7 +34,7 @@ from pathlib import Path from textwrap import dedent from unittest import TestCase -from pyVHDLModel.SyntaxModel import Expression +from pyVHDLModel.SyntaxModel import ExpressionUnion from pyGHDL.dom.DesignUnit import Package @@ -60,7 +60,7 @@ class Literals(TestCase): """ ) - def parse(self, filename: Path, code: str) -> Expression: + def parse(self, filename: Path, code: str) -> ExpressionUnion: sourceCode = self._packageTemplate.format(code=code) document = Document(filename, sourceCode) @@ -69,7 +69,7 @@ class Literals(TestCase): # Traverse already to default value expression package: Package = document.Packages[0] item: Constant = package.DeclaredItems[0] - default: Expression = item.DefaultExpression + default: ExpressionUnion = item.DefaultExpression return default @@ -82,7 +82,7 @@ class Literals(TestCase): expected = (0, 1, 1024, 1048576) # Parse in-memory - default: Expression = self.parse(_filename, constantDeclartion) + default: ExpressionUnion = self.parse(_filename, constantDeclartion) self.assertIsInstance(default, IntegerLiteral) self.assertEqual(expected[0], default.Value) -- cgit v1.2.3