From d85a1a9dcc4ebe3bafc746ea27ba38c5c7f78681 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 25 Jun 2020 07:48:01 +0200
Subject: testsuite/gna: add tests for #641

---
 testsuite/gna/issue641/ent.vhdl     | 52 +++++++++++++++++++++++++++++++++++++
 testsuite/gna/issue641/repro1.vhdl  | 22 ++++++++++++++++
 testsuite/gna/issue641/repro2.vhdl  | 21 +++++++++++++++
 testsuite/gna/issue641/testsuite.sh | 14 ++++++++++
 4 files changed, 109 insertions(+)
 create mode 100644 testsuite/gna/issue641/ent.vhdl
 create mode 100644 testsuite/gna/issue641/repro1.vhdl
 create mode 100644 testsuite/gna/issue641/repro2.vhdl
 create mode 100755 testsuite/gna/issue641/testsuite.sh

(limited to 'testsuite')

diff --git a/testsuite/gna/issue641/ent.vhdl b/testsuite/gna/issue641/ent.vhdl
new file mode 100644
index 000000000..27e8bf732
--- /dev/null
+++ b/testsuite/gna/issue641/ent.vhdl
@@ -0,0 +1,52 @@
+-- Helper package
+library ieee;
+use     ieee.std_logic_1164.all;
+
+package p is
+	type BusRecord is record
+		Address : std_logic_vector;
+		Data    : std_logic_vector;
+	end record;
+end package;
+
+-- DUT
+library ieee;
+use     ieee.std_logic_1164.all;
+use     work.p.all;
+
+entity e is
+	port (
+		Axi : inout BusRecord
+	);
+end entity;
+
+architecture a of e is
+	alias  AxiData is Axi.Data;
+
+	signal Address : std_logic_vector(Axi.Address'range);
+	signal Data1   : AxiData'subtype;    -- line 27: declaration of signal "data1" with unconstrained array subtype "std_logic_vector" is not allowed
+	signal Data2   : Axi.Data'subtype;   -- line 28: prefix must denote an object; a type mark must be a simple or expanded name
+begin
+
+end architecture;
+
+-- Top Level
+library ieee;
+use     ieee.std_logic_1164.all;
+use     work.p.all;
+
+entity test is
+end entity;
+
+architecture tb of test is
+	signal AxiBus : BusRecord(
+		Address(7 downto 0),
+		Data(31 downto 0)
+	);
+begin
+	DUT: entity work.e
+		port map (
+			Axi => AxiBus
+		);
+end architecture;
+
diff --git a/testsuite/gna/issue641/repro1.vhdl b/testsuite/gna/issue641/repro1.vhdl
new file mode 100644
index 000000000..7807666b7
--- /dev/null
+++ b/testsuite/gna/issue641/repro1.vhdl
@@ -0,0 +1,22 @@
+entity repro1b is
+  port (b : bit_vector);
+end entity;
+
+architecture a of repro1b is
+  signal c : b'subtype;
+begin
+  c <= b;
+  assert c'left = 7;
+  assert c'right = 0;
+end architecture;
+
+entity repro1 is
+end entity;
+
+architecture tb of repro1 is
+  signal s : bit_vector(7 downto 0);
+begin
+  DUT: entity work.repro1b
+    port map (b => s);
+end architecture;
+
diff --git a/testsuite/gna/issue641/repro2.vhdl b/testsuite/gna/issue641/repro2.vhdl
new file mode 100644
index 000000000..055672a15
--- /dev/null
+++ b/testsuite/gna/issue641/repro2.vhdl
@@ -0,0 +1,21 @@
+entity repro2b is
+  port (b : bit_vector);
+end entity;
+
+architecture a of repro2b is
+  signal c, d : b'subtype;
+begin
+  c <= b;
+  d <= b;
+end architecture;
+
+entity repro2 is
+end entity;
+
+architecture tb of repro2 is
+  signal s : bit_vector(7 downto 0);
+begin
+  DUT: entity work.repro2b
+    port map (b => s);
+end architecture;
+
diff --git a/testsuite/gna/issue641/testsuite.sh b/testsuite/gna/issue641/testsuite.sh
new file mode 100755
index 000000000..e18661f1f
--- /dev/null
+++ b/testsuite/gna/issue641/testsuite.sh
@@ -0,0 +1,14 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze ent.vhdl
+elab_simulate test
+
+analyze repro1.vhdl
+elab_simulate repro1
+
+clean
+
+echo "Test successful"
-- 
cgit v1.2.3