From d11ad2282157564dad9e53eccf9f2ec8a05bbda7 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 1 Dec 2019 08:57:39 +0100
Subject: testcase: complete test for #1044.

---
 testsuite/synth/issue1044/ent.vhdl | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'testsuite')

diff --git a/testsuite/synth/issue1044/ent.vhdl b/testsuite/synth/issue1044/ent.vhdl
index fc98054d0..5c0fb6471 100644
--- a/testsuite/synth/issue1044/ent.vhdl
+++ b/testsuite/synth/issue1044/ent.vhdl
@@ -13,6 +13,9 @@ end;
 architecture a of ent is
    constant fmul : real := val * 5.0;
    constant fneg : real := -val;
+   constant fid : real := +val;
+   constant fabs : real := abs val;
+   constant fexp : real := val ** 2;
 begin
 	lt  <= '1' when VAL  < 1.5 else '0';
 end;
-- 
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