From b709733aa8df0671ff77bc57636702f8a6e00800 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 30 Apr 2018 04:48:10 +0200
Subject: Add testcase for #563

---
 testsuite/gna/issue563/counter.vhdl    | 33 +++++++++++++++++++++++
 testsuite/gna/issue563/repro.vhdl      | 49 ++++++++++++++++++++++++++++++++++
 testsuite/gna/issue563/repro2.vhdl     |  5 ++++
 testsuite/gna/issue563/tb_counter.vhdl | 49 ++++++++++++++++++++++++++++++++++
 testsuite/gna/issue563/testsuite.sh    | 13 +++++++++
 5 files changed, 149 insertions(+)
 create mode 100644 testsuite/gna/issue563/counter.vhdl
 create mode 100644 testsuite/gna/issue563/repro.vhdl
 create mode 100644 testsuite/gna/issue563/repro2.vhdl
 create mode 100644 testsuite/gna/issue563/tb_counter.vhdl
 create mode 100755 testsuite/gna/issue563/testsuite.sh

(limited to 'testsuite')

diff --git a/testsuite/gna/issue563/counter.vhdl b/testsuite/gna/issue563/counter.vhdl
new file mode 100644
index 000000000..63c428f96
--- /dev/null
+++ b/testsuite/gna/issue563/counter.vhdl
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity counter is
+  port (
+    key0: in std_logic;
+    key3: in std_logic;
+    counter_out: out std_logic_vector(3 downto 0)
+  );
+end counter;
+
+architecture arch_counter of counter is
+  signal c: std_logic_vector(0 to 3) := (others => '0');
+begin
+  process(key0, key3)
+  begin
+    if (rising_edge(key0)) then
+      c <= std_logic_vector(unsigned(c) + 1);
+      if (unsigned(c) = 9) then
+        c <= "0000";
+      end if;
+    end if;
+    if (rising_edge(key3)) then
+      c <= std_logic_vector(unsigned(c) - 1);
+      if (unsigned(c) = "1111") then
+        c <= "1000";
+      end if;
+    end if;
+  end process;
+
+  counter_out <= c;
+end arch_counter ; -- arch_counter
diff --git a/testsuite/gna/issue563/repro.vhdl b/testsuite/gna/issue563/repro.vhdl
new file mode 100644
index 000000000..e5a0a15de
--- /dev/null
+++ b/testsuite/gna/issue563/repro.vhdl
@@ -0,0 +1,49 @@
+-- library ieee;
+-- library vunit_lib;
+-- context vunit_lib.vunit_context; 
+-- use ieee.std_logic_1164.all;
+-- use ieee.numeric_std.all;
+
+entity tb_counter is
+  -- generic (runner_cfg : string);
+end tb_counter;
+
+architecture arch_tb_counter of tb_counter is
+  -- component counter is
+  --   port (
+  --     key0: in std_logic;
+  --     key3: in std_logic;
+  --     counter_out: out std_logic_vector(3 downto 0)
+  --   );
+  -- end component;
+ --  signal key0, key3: std_logic;
+ --  signal counter_out: std_logic_vector(3 downto 0);
+
+  -- function trigger_rising() return std_logic_vector is
+  --   begin
+  --     key0 <= '0';
+  --     wait for 1 ns;
+  --     key0 <= '1';
+  --     wait for 1 ns;
+  --   end;
+    
+begin
+  -- uut: counter port map(
+  --   key0 => key0,
+  --   key3 => key3,
+  --   counter_out => counter_out
+  -- );
+
+  main: process
+  begin
+    -- test_runner_setup(runner, runner_cfg);
+    -- for j in 0 to 8 loop
+    -- trigger_rising();
+    -- check_match( counter_out, (std_logic_vector(to_unsigned(j + 1, 4))) );
+    -- end loop;
+    check_match(counter_out, ())))
+    -- test_runner_cleanup(runner); -- Simulation ends here
+  end process;
+
+end arch_tb_counter  ; -- arch_tb_counter 
+
diff --git a/testsuite/gna/issue563/repro2.vhdl b/testsuite/gna/issue563/repro2.vhdl
new file mode 100644
index 000000000..760cc24bc
--- /dev/null
+++ b/testsuite/gna/issue563/repro2.vhdl
@@ -0,0 +1,5 @@
+library ieee;
+context ieee.ieee_std_context;
+
+entity repro2 is
+end repro2; 
diff --git a/testsuite/gna/issue563/tb_counter.vhdl b/testsuite/gna/issue563/tb_counter.vhdl
new file mode 100644
index 000000000..86dc3f0a2
--- /dev/null
+++ b/testsuite/gna/issue563/tb_counter.vhdl
@@ -0,0 +1,49 @@
+library ieee;
+--library vunit_lib;
+--context vunit_lib.vunit_context; 
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity tb_counter is
+  generic (runner_cfg : string);
+end tb_counter;
+
+architecture arch_tb_counter of tb_counter is
+  component counter is
+    port (
+      key0: in std_logic;
+      key3: in std_logic;
+      counter_out: out std_logic_vector(3 downto 0)
+    );
+  end component;
+  signal key0, key3: std_logic;
+  signal counter_out: std_logic_vector(3 downto 0);
+
+  function trigger_rising() return std_logic_vector is
+    begin
+      key0 <= '0';
+      wait for 1 ns;
+      key0 <= '1';
+      wait for 1 ns;
+    end;
+    
+begin
+  uut: counter port map(
+    key0 => key0,
+    key3 => key3,
+    counter_out => counter_out
+  );
+
+  main: process
+  begin
+    test_runner_setup(runner, runner_cfg);
+    for j in 0 to 8 loop
+      trigger_rising();
+      check_match(counter_out, (std_logic_vector(to_unsigned(j + 1, 4))));
+    end loop;
+    check_match(counter_out, ())))
+    test_runner_cleanup(runner); -- Simulation ends here
+  end process;
+
+end arch_tb_counter  ; -- arch_tb_counter 
diff --git a/testsuite/gna/issue563/testsuite.sh b/testsuite/gna/issue563/testsuite.sh
new file mode 100755
index 000000000..6fd09901e
--- /dev/null
+++ b/testsuite/gna/issue563/testsuite.sh
@@ -0,0 +1,13 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze_failure repro.vhdl
+
+analyze_failure repro2.vhdl
+
+analyze counter.vhdl
+analyze_failure tb_counter.vhdl
+clean
+
+echo "Test successful"
-- 
cgit v1.2.3