From ae3e6932f7cecfce0dce4777644fc29040886651 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Thu, 9 Sep 2021 18:05:10 +0200 Subject: testsuite/gna: add a test for #1129 close #1129 --- testsuite/gna/issue1129/repro.vhdl | 36 ++++++++++++++++++++++++++++++++++++ testsuite/gna/issue1129/test.vhdl | 36 ++++++++++++++++++++++++++++++++++++ testsuite/gna/issue1129/testsuite.sh | 16 ++++++++++++++++ 3 files changed, 88 insertions(+) create mode 100644 testsuite/gna/issue1129/repro.vhdl create mode 100644 testsuite/gna/issue1129/test.vhdl create mode 100755 testsuite/gna/issue1129/testsuite.sh (limited to 'testsuite') diff --git a/testsuite/gna/issue1129/repro.vhdl b/testsuite/gna/issue1129/repro.vhdl new file mode 100644 index 000000000..46c707632 --- /dev/null +++ b/testsuite/gna/issue1129/repro.vhdl @@ -0,0 +1,36 @@ +entity ent is + generic( + BITS : positive); + port( + input : in bit_vector(BITS - 1 downto 0)); +end entity; + +architecture rtl of ent is +begin +end architecture; + + + +entity test is +end entity; + +architecture rtl of test is + constant MAX : positive := 7; + signal input : natural; + + function to_bv (l : natural; v : natural) return bit_vector + is + variable res : bit_vector (l - 1 downto 0); + begin + if v /= 0 then + res (0) := '1'; + end if; + return res; + end to_bv; +begin + ent : entity work.ent + generic map( + BITS => MAX) + port map( + input => to_bv(MAX, input)); +end architecture; diff --git a/testsuite/gna/issue1129/test.vhdl b/testsuite/gna/issue1129/test.vhdl new file mode 100644 index 000000000..7bcaeea54 --- /dev/null +++ b/testsuite/gna/issue1129/test.vhdl @@ -0,0 +1,36 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ent is + generic( + BITS : positive); + port( + input : in unsigned(BITS - 1 downto 0)); +end entity; + +architecture rtl of ent is +begin +end architecture; + + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity test is +end entity; + +architecture rtl of test is + constant MAX : positive := 7; + signal input : u_unsigned(MAX - 1 downto 0); +-- constant CONST : unsigned := to_unsigned(MAX, input); +begin + ent : entity work.ent + generic map( + BITS => MAX) + port map( + input => to_unsigned(MAX, input)); + --input => CONST); +end architecture; diff --git a/testsuite/gna/issue1129/testsuite.sh b/testsuite/gna/issue1129/testsuite.sh new file mode 100755 index 000000000..e47d5820e --- /dev/null +++ b/testsuite/gna/issue1129/testsuite.sh @@ -0,0 +1,16 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze repro.vhdl +elab_simulate test + +clean + +analyze test.vhdl +elab_simulate test + +clean + +echo "Test successful" -- cgit v1.2.3