From a7fc811243abef3bd4428c3368e7ae5b105322a0 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 13 Jan 2020 18:55:13 +0100
Subject: testsuite/synth: add test for previous commit.

---
 testsuite/synth/uassoc01/tb_uassoc02.vhdl | 23 ++++++++++++++++++
 testsuite/synth/uassoc01/testsuite.sh     |  2 +-
 testsuite/synth/uassoc01/uassoc02.vhdl    | 39 +++++++++++++++++++++++++++++++
 3 files changed, 63 insertions(+), 1 deletion(-)
 create mode 100644 testsuite/synth/uassoc01/tb_uassoc02.vhdl
 create mode 100644 testsuite/synth/uassoc01/uassoc02.vhdl

(limited to 'testsuite')

diff --git a/testsuite/synth/uassoc01/tb_uassoc02.vhdl b/testsuite/synth/uassoc01/tb_uassoc02.vhdl
new file mode 100644
index 000000000..5f4bec664
--- /dev/null
+++ b/testsuite/synth/uassoc01/tb_uassoc02.vhdl
@@ -0,0 +1,23 @@
+entity tb_uassoc02 is
+end tb_uassoc02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_uassoc02 is
+  signal i1 : std_logic_vector(3 downto 0);
+  signal i2 : std_logic_vector(7 downto 0);
+  signal o  : std_logic_vector(3 downto 0);
+begin
+  dut: entity work.uassoc02
+    port map (i1, i2, o);
+
+  process
+  begin
+    i1 <= "1100";
+    i2 <= b"1010_1010";
+    wait for 1 ns;
+    assert o = "0110" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/uassoc01/testsuite.sh b/testsuite/synth/uassoc01/testsuite.sh
index bcbdf419d..f9e7f9e51 100755
--- a/testsuite/synth/uassoc01/testsuite.sh
+++ b/testsuite/synth/uassoc01/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in uassoc01; do
+for t in uassoc01 uassoc02; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean
diff --git a/testsuite/synth/uassoc01/uassoc02.vhdl b/testsuite/synth/uassoc01/uassoc02.vhdl
new file mode 100644
index 000000000..b8c085cd9
--- /dev/null
+++ b/testsuite/synth/uassoc01/uassoc02.vhdl
@@ -0,0 +1,39 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity uassoc02_sub is
+  port (i : std_logic_vector;
+        o : out std_logic_vector);
+end uassoc02_sub;
+
+architecture behav of uassoc02_sub is
+begin
+  o <= not i;
+end behav;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity uassoc02 is
+  port (i1 : std_logic_vector(3 downto 0);
+        i2 : std_logic_vector(7 downto 0);
+        o : out std_logic_vector(3 downto 0));
+end uassoc02;
+
+architecture rtl of uassoc02 is
+  component uassoc02_sub is
+    port (i : std_logic_vector;
+          o : out std_logic_vector);
+  end component;
+
+  signal o1: std_logic_vector(3 downto 0);
+  signal o2: std_logic_vector(7 downto 0);
+begin
+  dut1: uassoc02_sub
+    port map (i => i1, o => o1);
+
+  dut2: uassoc02_sub
+    port map (i => i2, o => o2);
+
+  o <= o1 xor o2 (3 downto 0);
+end rtl;
-- 
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